Detection circuit based on band-gap reference voltage and band-gap reference voltage circuit

Abstract

The invention discloses a band-gap reference voltage-based detection circuit and a band-gap reference voltage circuit, and the detection circuit comprises a voltage limiting starting control unit which is connected between a power supply voltage and a reference potential, is connected with a control end of a first MOS tube in a band-gap reference voltage generation circuit, and is used for starting the first MOS tube when the power supply voltage is electrified to a first voltage threshold value; performing mirror image copying on the current flowing through the first MOS tube to generate a first current; and the voltage margin control unit is connected with the voltage-limiting starting control unit and the first output node, and is used for generating a band-gap reference establishment signal BGS based on the first current and the band-gap reference voltage VBG when the power supply voltage is electrified to a second voltage threshold value. Through the arrangement of the detection circuit, whether the band-gap reference voltage is established or not can be judged without introducing the reference voltage into the band-gap reference voltage circuit, the high-level band-gap reference establishment signal is output after the power supply voltage is powered on to the second voltage threshold value, and the band-gap reference circuit can be suitable for the condition that the power supply voltage is powered on slowly.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a detection circuit based on a bandgap reference voltage and a bandgap reference voltage circuit. Background Art

[0002] Bandgap (BG) is a measure of voltage and current in the chip. Bandgap reference voltage V BG The accuracy directly determines whether the ruler is accurate, so the bandgap reference voltage V BG Whether it has been established correctly and provides an accurate bandgap reference establishment completion signal to the subsequent circuit to indicate the bandgap reference voltage V BG It is very important to have stable establishment.

[0003] The prior art generally generates a target bandgap reference voltage using a reference current generated by a reference voltage source, and determines whether the target bandgap reference voltage is stably established by detecting whether the reference current is stably established. However, when the reference voltage source is powered on slowly, the reference current may be established but the target bandgap reference voltage is not stably established, resulting in an inaccurate signal of the bandgap reference establishment completion, thereby affecting the operation of the subsequent circuit and even damaging the subsequent circuit.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a detection circuit based on a bandgap reference voltage and a bandgap reference voltage circuit. Summary of the invention

[0005] The object of the present invention is to provide a detection circuit based on a bandgap reference voltage and a bandgap reference voltage circuit, which can generate an accurate bandgap reference establishment completion signal when the power supply voltage is slowly powered on.

[0006] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0007] A detection circuit based on a bandgap reference voltage is applied to a bandgap reference voltage circuit, wherein the bandgap reference voltage circuit comprises a bandgap reference voltage generating circuit and a start-up circuit, wherein the bandgap reference voltage generating circuit is used to generate a bandgap reference voltage V at a first output node. BG , the detection circuit comprises:

[0008] A voltage-limited startup control unit is connected between the power supply voltage and the reference potential, and is connected to the control end of the first MOS tube in the bandgap reference voltage generating circuit, and is used to mirror-copy the current flowing through the first MOS tube to generate a first current when the power supply voltage is powered up to a first voltage threshold;

[0009] A voltage margin control unit is connected to the voltage limit start control unit and the first output node, and is used for, when the power supply voltage is powered up to the second voltage threshold, based on the first current and the bandgap reference voltage V BG A bandgap reference setup signal BG_S is generated at the second output node, and the second voltage threshold is greater than the first voltage threshold.

[0010] In one or more embodiments of the present invention, the voltage-limited startup control unit includes a voltage-limited unit and a first current copy unit; wherein,

[0011] The voltage limiting unit includes a second MOS tube, a voltage limiting device or a plurality of voltage limiting devices arranged in series, wherein a first end of the second MOS tube is connected to a power supply voltage, a control end of the second MOS tube is connected to a control end of the first MOS tube, and a second end of the second MOS tube is connected to the voltage limiting device;

[0012] The first current replication unit is connected to the voltage limiting device and is used to generate a first current.

[0013] In one or more embodiments of the present invention, the first current replication unit includes a fourth MOS tube and a fifth MOS tube; wherein,

[0014] The second end of the fourth MOS tube is short-circuited with the control end, the second end of the fourth MOS tube is connected to the voltage limiting device, and the first end of the fourth MOS tube is connected to the reference potential;

[0015] The control end of the fifth MOS tube is connected to the control end of the fourth MOS tube, the first end of the fifth MOS tube is connected to the reference potential, and the second end of the fifth MOS tube is connected to the voltage margin control unit.

[0016] In one or more embodiments of the present invention, the first voltage threshold is V DS,M2 +V TH,M3 +V TH,M4 , where V DS,M2 is the drain-source voltage of the second MOS tube, V TH,M3 is the conduction voltage of the third MOS tube, V TH,M4 is the turn-on threshold voltage of the fourth MOS tube.

[0017] In one or more embodiments of the present invention, the voltage margin control unit includes a second current copy unit, an eighth MOS tube and a pull-down resistor; wherein,

[0018] The second current copy unit is connected to the voltage-limited startup control unit and the power supply voltage, and the second current copy unit is used to copy the first current and generate a mirror current;

[0019] The first end of the eighth MOS tube is connected to the second current replication unit, the control end of the eighth MOS tube is connected to the first output node, and the second end of the eighth MOS tube is connected to the second output node;

[0020] A first end of the pull-down resistor is connected to the second output node, and a second end of the pull-down resistor is connected to a reference potential.

[0021] In one or more embodiments of the present invention, the second current copy unit includes a sixth MOS transistor and a seventh MOS transistor;

[0022] The control end of the sixth MOS tube is short-circuited with the second end, and the control end of the sixth MOS tube is connected to the voltage-limited startup control unit, and the first end of the sixth MOS tube is connected to the power supply voltage;

[0023] The first end of the seventh MOS tube is connected to the power supply voltage, the control end of the seventh MOS tube is connected to the control end of the sixth MOS tube, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube.

[0024] In one or more embodiments of the present invention, the second voltage threshold is V BG +V DS,M7 +V TH,M8 , where V DS,M7 is the drain-source voltage of the seventh MOS tube, V TH,M8 is the turn-on threshold voltage of the eighth MOS tube.

[0025] In one or more embodiments of the present invention, the voltage margin control unit further includes a signal shaping unit including a trigger, a first inverter and a second inverter;

[0026] The input end of the trigger is connected to the second output node and receives the bandgap reference establishment signal BG_S, and the output end of the trigger is connected to the input end of the first inverter and generates a first logic level signal;

[0027] The output terminal of the first inverter is connected to the input terminal of the second inverter and generates a second logic level signal, and the output terminal of the second inverter generates an output signal BG_OK.

[0028] In one or more embodiments of the present invention, the voltage margin control unit further includes a current compensation unit;

[0029] The current compensation unit is connected to the second current copy unit and the output end of the first inverter in the signal shaping unit, and the current compensation unit is connected to the power supply voltage. The current compensation unit is used to generate a compensation current based on the second logic level signal.

[0030] In one or more embodiments of the present invention, the current compensation unit includes a ninth MOS tube and a tenth MOS tube; wherein,

[0031] The first end of the ninth MOS tube is connected to the power supply voltage, the control end of the ninth MOS tube is connected to the second current copy unit, and the second end of the ninth MOS tube is connected to the first end of the tenth MOS tube;

[0032] The control end of the tenth MOS tube is connected to the output end of the first inverter, and the second end of the tenth MOS tube is connected to the first end of the eighth MOS tube.

[0033] In one or more embodiments of the present invention, the signal shaping unit further includes an RC delay unit; the RC delay unit is connected between the output end of the trigger and the reference potential, and is used to perform delay processing on the first logic level signal.

[0034] In one or more embodiments of the present invention, the detection circuit further includes a power-on protection unit;

[0035] The power-on protection unit is connected between the second output node and the reference potential and is connected to the startup circuit, and is used for pulling down the voltage on the second output node to the first level after the startup circuit is powered on.

[0036] In one or more embodiments of the present invention, the power-on protection unit includes an eleventh MOS tube, a first end of the eleventh MOS tube is connected to a reference potential, a control end of the eleventh MOS tube is connected to a startup circuit, and a second end of the eleventh MOS tube is connected to a second output node.

[0037] Another specific embodiment of the present invention provides a technical solution as follows:

[0038] A bandgap reference voltage circuit, the bandgap reference voltage circuit comprising:

[0039] The bandgap reference voltage generating circuit is connected between the power supply voltage and the reference potential and is used to generate a bandgap reference voltage V at the first output node. BG ;

[0040] A startup circuit, connected between the power supply voltage and the reference potential, and connected to the first output node and the control end of the first MOS transistor in the bandgap reference voltage generating circuit, for starting the bandgap reference voltage generating circuit;

[0041] A detection circuit, the detection circuit comprising:

[0042] A voltage-limited startup control unit is connected between the power supply voltage and the reference potential, and is connected to the control end of the first MOS tube in the bandgap reference voltage generating circuit, and is used to mirror-copy the current flowing through the first MOS tube to generate a first current when the power supply voltage is powered up to a first voltage threshold;

[0043] A voltage margin control unit is connected to the voltage limit start control unit and the first output node, and is used for, when the power supply voltage is powered up to the second voltage threshold, based on the first current and the bandgap reference voltage V BG A bandgap reference setup signal BG_S is generated at the second output node, and the second voltage threshold is greater than the first voltage threshold.

[0044] In one or more embodiments of the present invention, the startup circuit includes a pull-up resistor, a control tube and a current mirror unit, the first end of the pull-up resistor is connected to the power supply voltage, the second end is connected to the second end of the control tube and the current mirror unit, the control end of the control tube is connected to the first output node, the first end is connected to the reference potential, and the current mirror unit is connected to the control end of the first MOS tube and the detection circuit.

[0045] Compared with the prior art, the detection circuit based on the bandgap reference voltage and the bandgap reference voltage circuit of the present invention can determine whether the bandgap reference voltage is established without introducing a reference voltage in the bandgap reference voltage circuit through the setting of the detection circuit, and output a high-level bandgap reference establishment signal after the power supply voltage is powered up to the second voltage threshold;

[0046] The present invention has high reliability, and limits the power supply voltage margin through a voltage-limited startup control unit, and avoids the subsequent circuit from mistakenly generating a bandgap reference establishment signal based on a lower bandgap reference signal and the power supply voltage when the power supply voltage is slowly powered on;

[0047] The voltage margin control unit limits the power supply voltage margin again, further ensuring the bandgap reference voltage V BG After the establishment is completed, it can also accurately generate a low-level output signal when the power supply voltage is powered down to protect the subsequent circuit;

[0048] The present invention has strong versatility and is applicable to different power supply voltage power-on and power-off rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 The figure is a schematic diagram of a detection circuit based on a bandgap reference voltage and a bandgap reference voltage circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0052] The term "coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purpose, such as connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0053] The present invention discloses a detection circuit based on a bandgap reference voltage, which is applied to a bandgap reference voltage circuit, wherein the bandgap reference circuit includes a bandgap reference voltage generating circuit and a start-up circuit. The detection circuit includes:

[0054] A voltage-limited startup control unit is connected between the power supply voltage and the reference potential, and is connected to the control end of the first MOS tube in the bandgap reference voltage generating circuit, and is used to mirror-copy the current flowing through the first MOS tube to generate a first current when the power supply voltage is powered up to a first voltage threshold;

[0055] A voltage margin control unit is connected to the voltage limit start control unit and the first output node, and is used for, when the power supply voltage is powered up to the second voltage threshold, based on the first current and the bandgap reference voltage V BG A bandgap reference setup signal BG_S is generated at the second output node, and the second voltage threshold is greater than the first voltage threshold.

[0056] The present invention also discloses a bandgap reference voltage circuit, comprising:

[0057] The bandgap reference voltage generating circuit is connected between the power supply voltage and the reference potential and is used to generate a bandgap reference voltage V at the first output node. BG ;

[0058] A startup circuit, connected between the power supply voltage and the reference potential, and connected to the first output node and the control end of the first MOS transistor in the bandgap reference voltage generating circuit, for starting the bandgap reference voltage generating circuit;

[0059] The detection circuit is used to generate a bandgap reference establishment signal BG_S.

[0060] The present invention is further described below in conjunction with specific embodiments.

[0061] like Figure 1 As shown, the bandgap reference voltage generating circuit 10 in this embodiment includes an operational amplifier AMP, a first MOS transistor M1, a first branch and a second branch.

[0062] The first end of the first MOS tube M1 is connected to the power supply voltage VDD, the second end of the first MOS tube M1 is connected to the first output node, the first branch includes a first bipolar transistor Q1 and a plurality of first matching resistors R1, the second branch includes a second bipolar transistor Q2 and a plurality of second matching resistors R2a, R2b, the first input end and the second input end of the operational amplifier AMP are respectively connected to the first branch and the second branch, the output end of the operational amplifier AMP is connected to the control end of the first MOS tube M1, and the first output node is used to output a bandgap reference voltage V BG .

[0063] The base and collector of the first bipolar transistor Q1 are short-circuited, and the collector is connected to the first matching resistor R1, and the emitter of the first bipolar transistor Q1 is connected to the reference potential GND; the base and collector of the second bipolar transistor Q2 are short-circuited, and the collector is connected to the second matching resistor R2b, and the emitter of the second bipolar transistor Q2 is connected to the reference potential GND.

[0064] The reference potential GND in this embodiment is the ground potential, the first end of the MOS tube involved in this embodiment is the source, the second end is the drain, and the control end is the gate. In this embodiment, the first MOS tube M1 is a PMOS tube.

[0065] The bandgap reference voltage generating circuit 10 generates a bandgap reference voltage V BG The principle is already in the prior art and will not be described in detail in the present invention.

[0066] The startup circuit 20 includes a pull-up resistor R3, a control transistor MN1 and a current mirror unit 21. The first end of the pull-up resistor R3 is connected to the power supply voltage VDD, the second end of the pull-up resistor R3 is connected to the second end of the control transistor MN1 and the current mirror unit 21, and the control end of the control transistor MN1 is connected to the first output node to receive the bandgap reference voltage V BGThe first end of the control tube MN1 is connected to the reference potential GND, the current mirror unit 21 is connected to the control end of the first MOS tube M1, and the start-up circuit 20 is used to start the bandgap reference voltage generating circuit 10.

[0067] Further, the current mirror unit 21 includes a twelfth MOS transistor MN2 and a thirteenth MOS transistor MN3. The first end of the twelfth MOS transistor MN2 is connected to the reference potential GND, the second end of the twelfth MOS transistor MN2 is short-circuited with its own control end, and the second end of the twelfth MOS transistor MN2 is connected to the second end of the pull-up resistor R3. The first end of the thirteenth MOS transistor MN3 is connected to the reference potential GND, the second end of the thirteenth MOS transistor MN3 is connected to the control end of the first MOS transistor M1 in the bandgap reference voltage generating circuit 10, and the control end of the thirteenth MOS transistor MN3 is connected to the control end of the twelfth MOS transistor MN2. In this embodiment, the control transistor MN1, the twelfth MOS transistor MN2 and the thirteenth MOS transistor MN3 are NMOS transistors.

[0068] like Figure 1 As shown, the detection circuit 30 based on the bandgap reference voltage in this embodiment includes:

[0069] The voltage-limited startup control unit 31 is connected between the power supply voltage VDD and the reference potential GND, and is connected to the control end of the first MOS transistor M1 in the bandgap reference voltage generating circuit 10, and is used to mirror the current flowing through the first MOS transistor M1 to generate the first current Ib when the power supply voltage VDD is powered up to the first voltage threshold;

[0070] The voltage margin control unit 32 is connected to the voltage limit start control unit 31 and the first output node A, and is used to generate a voltage margin control signal based on the first current Ib and the bandgap reference voltage V when the power supply voltage VDD is powered up to the second voltage threshold. BG The bandgap reference setup signal BG_S is generated at the second output node A. The second voltage threshold is greater than the first voltage threshold.

[0071] The voltage-limited startup control unit in this embodiment includes a voltage-limited unit 311 and a first current copying unit 312 .

[0072] The voltage limiting unit 311 includes a second MOS tube M2, a voltage limiting device or a plurality of voltage limiting devices arranged in series. The first end of the second MOS tube M2 is connected to the power supply voltage VDD, the control end of the second MOS tube M2 is connected to the control end of the first MOS tube M1, and the second end of the second MOS tube M2 is connected to the voltage limiting device. In this embodiment, the second MOS tube M2 is a PMOS tube.

[0073] Furthermore, if Figure 1As shown, the voltage limiting device in this embodiment includes a third MOS tube M3, a first end of the third MOS tube M3 is connected to the second end of the second MOS tube M2, a control end of the third MOS tube M3 is short-circuited with its own second end, and a second end of the third MOS tube M3 is connected to the first current copy unit 312. In this embodiment, the third MOS tube M3 is a PMOS tube.

[0074] It is understandable that, in other optional embodiments, the voltage limiting device in the voltage limiting unit 311 may be set to be multiple, and the multiple voltage limiting devices are connected in series. That is, multiple control ends are connected in sequence to the third MOS tubes M3 whose second ends are short-circuited, and the first end of the first-stage third MOS tube is connected to the second end of the second MOS tube M2, the first end of the next-stage third MOS tube is connected to the second end of the previous-stage third MOS tube, and the second end of the last-stage third MOS tube is connected to the first current copy unit 312.

[0075] The first current copy unit 312 is connected to the voltage limiting device and is used to generate the first current Ib. Specifically, the current copy unit 312 includes a fourth MOS transistor M4 and a fifth MOS transistor M5. The fourth MOS transistor M4 and the fifth MOS transistor M5 are NMOS transistors.

[0076] The second end of the fourth MOS tube M4 is short-circuited with its own control end, and the second end of the fourth MOS tube M4 is connected to the voltage limiting device, and the first end of the fourth MOS tube M4 is connected to the reference potential GND.

[0077] The second end of the fifth MOS tube M5 is connected to the control end of the sixth MOS tube M6 in the voltage margin control unit 32, the control end of the fifth MOS tube M5 is connected to the control end of the fourth MOS tube M4, and the first end of the fifth MOS tube M5 is connected to the reference potential GND. It can be understood that the fourth MOS tube M4 and the fifth MOS tube M5 constitute a group of current mirrors.

[0078] Based on the connection structure of the voltage-limited startup control unit 31, it can be seen that the first voltage threshold is V DS,M2 +V TH,M3 +V TH,M4 , where V DS,M2 is the drain-source voltage of the second MOS tube, V TH,M3 is the conduction threshold voltage of the third MOS tube, V TH,M4 is the conduction threshold voltage of the fourth MOS tube. Further, if the number of voltage limiting devices is n, the first voltage threshold is V SD,M2 +nV TH,M3 +V TH,M4 .

[0079] After the power supply voltage VDD is powered up to the first voltage threshold, the current copy unit 312 in the voltage-limited startup control unit 31 is started, and the second MOS transistor M2 and the first MOS transistor M1 also form a set of current mirrors. At this time, the second MOS transistor M2 copies the current in the first MOS transistor M1, and the current in the fourth MOS transistor M4 in the current copy unit 312 is equal to the current in the second MOS transistor M2, and the current in the fifth MOS transistor M6 is the first current Ib.

[0080] like Figure 1 As shown, the voltage margin control unit 32 in this embodiment includes a second current copy unit 321, an eighth MOS transistor M8 and a pull-down resistor R4.

[0081] The second current copy unit 321 is connected to the voltage-limited startup control unit 31 and the power supply voltage VDD, and is used to copy the first current Ib and generate a mirror current Is;

[0082] A first end of the eighth MOS tube M8 is connected to the second current copy unit 321 , a control end of the eighth MOS tube M8 is connected to the first output node A, and a second end of the eighth MOS tube is connected to the second output node A; in this embodiment, the eighth MOS tube M8 is a PMOS tube.

[0083] The first end of the pull-down resistor R4 is connected to the second output node A, and the second end of the pull-down resistor R4 is connected to the reference potential GND. The pull-down resistor R4 is used to generate a bandgap reference establishment signal BG_S based on the mirror current Is after the eighth MOS transistor M8 is turned on.

[0084] like Figure 1 As shown, the second current copy unit 321 in this embodiment includes a sixth MOS transistor M6 and a seventh MOS transistor M7.

[0085] The control end of the sixth MOS tube M6 is short-circuited with its own second end, and the control end of the sixth MOS tube M6 is connected to the second end of the fifth MOS tube M5 in the voltage-limited startup control unit 31 , and the first end of the sixth MOS tube M6 is connected to the power supply voltage VDD.

[0086] The first end of the seventh MOS tube M7 is connected to the power supply voltage VDD, the control end of the seventh MOS tube M7 is connected to the control end of the sixth MOS tube M6, and the second end of the seventh MOS tube M7 is connected to the first end of the eighth MOS tube M8. In this embodiment, the sixth MOS tube M6 and the seventh MOS tube M7 are PMOS tubes.

[0087] From the circuit structure of the second current copy unit 321, the eighth MOS tube M8 and the pull-down resistor R4, it can be seen that the second voltage threshold is V BG +V DS,M7 +V TH,M8, where V DS,M7 is the drain-source voltage of the seventh MOS tube M7, V TH,M8 is the turn-on threshold voltage of the eighth MOS tube M8.

[0088] like Figure 1 As shown, in this embodiment, the voltage margin control unit 32 further includes a second capacitor C2, a first end of the second capacitor C2 is connected to the second output node A, and a second end of the second capacitor C2 is connected to the reference potential GND. The setting of the second capacitor C2 further ensures the power-on time of the power supply voltage VDD, that is, ensures the bandgap reference voltage V BG The establishment time.

[0089] like Figure 1 As shown, in this embodiment, the voltage margin control unit 32 further includes a signal shaping unit, which is connected to the second output node A and is used to shape the bandgap reference establishment signal BG_S and generate an output signal BG_OK.

[0090] The signal shaping unit in this embodiment includes a trigger I1, a first inverter I2, and a second inverter I3. The signal shaping unit 322 in this embodiment is connected between the power supply voltage VDD and the reference potential GND, that is, the trigger I1, the first inverter I2, and the second inverter I3 work between the power supply voltage VDD and the reference potential GND.

[0091] The input end of the trigger I1 is connected to the second output node A and receives the bandgap reference establishment signal BG_S. The output end of the trigger I1 is connected to the input end of the first inverter I2 and generates a first logic level signal. The trigger I1 in this embodiment is a co-inverting Schmitt trigger, that is, when the bandgap reference establishment signal BG_S is greater than the set flip threshold of the trigger, the first logic level signal generated by the trigger I1 is a high level, and vice versa, when the bandgap reference establishment signal BG_S is less than the set flip threshold of the trigger, the first logic level signal generated by the trigger I1 is a low level.

[0092] The output terminal of the first inverter I2 is connected to the input terminal of the second inverter I3 and generates a second logic level signal, and the output terminal of the second inverter I3 generates an output signal BG_OK. It can be understood that the second logic level signal is inverted with the first logic level signal, and the output signal BG_OK is inverted with the second logic level signal.

[0093] like Figure 1 As shown, in this embodiment, the voltage margin control unit 32 further includes a current compensation unit 323, which is connected to the second current copy unit 321 and the output end of the first inverter I2 in the signal shaping unit, and is used to generate a compensation current Ic based on the second logic level signal.

[0094] Specifically, the current compensation unit 323 includes a ninth MOS tube M9 and a tenth MOS tube M10. The first end of the ninth MOS tube M9 is connected to the power supply voltage VDD, the control end of the ninth MOS tube M9 is connected to the control end of the seventh MOS tube M7 in the second current copy unit 321, the second end of the ninth MOS tube M9 is connected to the first end of the tenth MOS tube M10; the control end of the tenth MOS tube M10 is connected to the output end of the first inverter I2, and the second end of the tenth MOS tube M10 is connected to the first end of the eighth MOS tube M8. The ninth MOS tube M9 and the tenth MOS tube M10 are PMOS tubes.

[0095] It can be understood that after the trigger I1 is flipped, when the second logic level signal is at a low level, the tenth MOS tube M10 is turned on, the ninth MOS tube M9 and the seventh MOS tube M7 can be regarded as a group of current mirrors, then the ninth MOS tube M9 copies the current in the seventh MOS tube M7 to generate the compensation current Ic, then after the eighth MOS tube M8 is turned on, the current in the eighth MOS tube M8 is the sum of the mirror current Is and the compensation current Ic.

[0096] like Figure 1 As shown, optionally, the signal shaping unit 323 in this embodiment further includes an RC delay unit 323 for delaying the first logic level signal. The RC delay unit is connected between the output end of the trigger and the reference potential GND.

[0097] The RC delay unit 323 includes a third resistor R5 and a first capacitor C1, the first end of the third resistor R5 is connected to the output end of the trigger I1, the second end of the third resistor R5 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the reference potential GND, and the first end of the first capacitor C1 is connected to the input end of the first inverter I2.

[0098] like Figure 1 As shown, the detection circuit in this embodiment further includes a power-on protection unit 33. The power-on protection unit 33 is connected between the second output node A and the reference potential GND, and is connected to the current mirror unit 21 in the startup circuit 20, and is used to pull down the potential of the second output node A to the first level after the startup circuit 20 is powered on, that is, to pull down the bandgap reference establishment signal BG_S to the first level. The first level in this embodiment is a low level.

[0099] Specifically, the power-on protection unit 33 includes an eleventh MOS transistor M11, a first end of the eleventh MOS transistor M11 is connected to the reference potential GND, a second end of the eleventh MOS transistor M11 is connected to the second output node A, and a control end of the eleventh MOS transistor M11 is connected to a control end of the thirteenth MOS transistor MN3 in the current mirror unit 21. The eleventh MOS transistor M11 is an NMOS transistor.

[0100] The working principle of the bandgap reference voltage circuit in this embodiment is as follows:

[0101] The present invention is applicable to the slow power-up of the power supply voltage VDD. When the power supply voltage VDD does not start to power up, the bandgap reference voltage generating circuit 10, the start-up circuit 20, and the detection circuit 30 are in a non-operating state;

[0102] When the power supply voltage VDD starts to power on and is at a lower voltage value, the startup circuit 20 starts to work: the bandgap reference voltage V BG The control tube MN1 is in the off state, and the thirteenth MOS tube MN3 is turned on, so the control terminal PGATE voltage of the first MOS tube M1 is pulled down. At this time, the bandgap reference voltage V BG The control terminal voltage of the thirteenth MOS transistor MN3 is nearly equal to the power supply voltage VDD, and the control terminal voltage of the thirteenth MOS transistor MN3 is pulled up to the power supply voltage VDD by the pull-up resistor R3, so the eleventh MOS transistor M11 is turned on, and the eleventh MOS transistor M11 pulls down the potential of the second output node A, that is, the bandgap reference establishment signal BG_S is at a low level, and the output signal BG_OK is at a low level, thereby avoiding the generation of an erroneous bandgap reference establishment signal BG_S when the power supply voltage VDD starts to power on.

[0103] The power supply voltage VDD continues to increase to about 0.6V and is less than the first voltage threshold (V SD,M2 +V TH,M3 +V TH,M4 ), the control tube MN1 is turned on, the voltage of the control terminal PGATE of the first MOS tube M1 is pulled down, and the voltage of the second terminal of the pull-up resistor R3 is pulled down, thereby turning off the twelfth MOS tube MN2, the thirteenth MOS tube MN3 and the eleventh MOS tube M11. At this time, the start-up circuit 20 is turned off, and the bandgap reference voltage generating circuit 10 relies on its internal loop regulation, and the bandgap reference voltage V BG Since the power supply voltage VDD does not rise to the first voltage threshold at this time, the voltage limit start control unit 31 is not started, so the first current Ib is 0, the mirror current Is is also 0, the potential of the second output node A is low, the bandgap reference establishment signal BG_S is low, and the output signal BG_OK is low.

[0104] The power supply voltage VDD continues to be powered up to a value greater than the first voltage threshold (V SD,M2 +V TH,M3 +V TH,M4 ), the power supply voltage VDD at this time can generally make the bandgap reference voltage V BGThe voltage-limited startup control unit 31 is established near the stable value, and the first current Ib gradually increases. At this time, the eighth MOS tube M8 is turned off, the potential of the second output node A is low, the bandgap reference establishment signal BG_S is low level, and the output signal BG_OK is low level. The voltage-limited startup control unit 31 realizes the power supply voltage margin control and improves the accuracy of the bandgap reference establishment signal BG_S and the output signal BG_OK.

[0105] The power supply voltage VDD continues to be powered up to a value greater than the second voltage threshold (V BG +V SD,M7 +V TH,M8 ), the eighth MOS tube M8 is turned on, the mirror current Is is generated in the seventh MOS tube M7, the voltage of the second output node A (i.e., the bandgap reference establishment signal BG_S) is pulled high, and when the voltage of the second output node A is greater than the flip threshold set by the trigger, the trigger I1 flips and generates a high-level first logic level signal, and the first logic level signal generates a high-level output signal BG_OK after passing through the first inverter I2 and the second inverter I3, indicating that the power supply voltage VDD is sufficient to establish the bandgap reference voltage VBG to 1.2V.

[0106] During the VDD establishment process, the voltage of the second output node A is equal to the mirror current Is×R4, where the mirror current Is is the current I in the seventh MOS tube M7. DS,M7 When the voltage of the second output node A (bandgap reference establishment signal BG_S) is not high enough, the Schmitt trigger may flip, and the PMOS and NMOS tubes inside the Schmitt trigger are turned on, forming a current path between the power supply voltage VDD and the ground potential GND, and generating leakage current.

[0107] Therefore, this embodiment proposes a current compensation unit 322. When the voltage of the second output node A is greater than the flip threshold set by the trigger, the trigger I1 is flipped and triggered, the first logic level signal is high, and the second logic level signal is low. At this time, the current compensation unit 322 generates a compensation current Ic, and the voltage of the second output node A is equal to (Is+Ic)×R4. The voltage of the second output node A is close to the power supply voltage VDD, and the Schmitt trigger can be flipped normally while avoiding leakage current generated by the Schmitt trigger.

[0108] During the power-down process of the power supply voltage VDD, when the power supply voltage VDD is less than the second voltage threshold (V BG +V SD,M7 +V TH,M8), the eighth MOS tube M8 is turned off, the pull-down resistor R4 pulls down the voltage of the second output node A, the bandgap reference establishment signal BG_S is low level, the trigger I1 triggers the flip, the first logic level signal changes from high level to low level, the second logic level signal changes from low level to high level, the output signal BG_OK changes to low level, and the subsequent circuit triggers protection.

[0109] The present invention is also applicable to the fast power-up of the power supply voltage VDD. Based on the RC delay unit 323 proposed in this embodiment, when the power supply voltage VDD is fast powered up to the second voltage threshold, the RC delay unit 323 can filter out high-frequency noise, control the first inverter I2 to delay receiving the first logic level signal, avoid generating an erroneous output signal BG_OK, and improve the anti-interference ability and reliability of the system.

[0110] The detection circuit in this embodiment includes four states:

[0111] In the first state (the bandgap reference voltage establishes the start-up state), the start-up circuit 20 works, and the current in the first MOS tube M1 and the bandgap reference voltage V BG Gradually increases, the eleventh MOS transistor M11 in the detection circuit 30 is turned on, pulling down the voltage on the second output node A, the bandgap reference establishment signal BG_S is low level (0), and the output signal BG_OK output by the signal shaping unit is low level (0).

[0112] In the second state (the bandgap reference voltage establishes the primary state), the startup circuit 20 does not work, the eleventh MOS transistor M11 is turned off, and the bandgap reference voltage V BG During the establishment process, as the power supply voltage VDD gradually increases but is less than the first voltage threshold, the bandgap reference voltage V BG The current in the first MOS tube M1 gradually increases, the second MOS tube M2 is turned off, the current in the second MOS tube M2 and the current copy unit is 0, the bandgap reference establishment signal BG_S is low level (0), and the output signal BG_OK is low level (0).

[0113] The third state (bandgap reference voltage establishes the secondary state), as the power supply voltage VDD and the bandgap reference voltage V BGThe current in the first MOS tube M1 gradually increases, the power supply voltage VDD is greater than the first voltage threshold but less than the second voltage threshold, the second MOS tube M2 is turned on, the second MOS tube M2, the current copy unit and the seventh MOS tube M7 copy the current in the first MOS tube M1 step by step and generate the first current Ib, the eighth MOS tube M8 is turned off, the current in the eighth MOS tube M8 is 0, the voltage on the pull-down resistor R4 is 0, that is, the voltage on the second output node A is 0, the bandgap reference establishment signal BG_S is low level (0), and the output signal BG_OK output by the signal shaping unit is low level (0).

[0114] In the fourth state (the state after the bandgap reference voltage is established), the power supply voltage VDD is greater than the second voltage threshold, and the bandgap reference voltage V BG After the establishment is completed, the eighth MOS tube M8 is turned on, and the voltage on the pull-down resistor R4 (i.e., the voltage of the second output node A) gradually increases. When the voltage on the pull-down resistor R4 exceeds the flip threshold voltage of the Schmitt trigger, the bandgap reference establishment signal BG_S is high level (1), and the output signal BG_OK output by the signal shaping unit is high level (1).

[0115] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0116] The present invention can determine whether the bandgap reference voltage is established by setting the detection circuit without introducing a reference voltage in the bandgap reference voltage circuit. BG After establishment, the bandgap reference establishment signal that outputs a high level can be applied to the situation where the power supply voltage is powered on slowly.

[0117] The power supply voltage margin is limited by the voltage-limited startup control unit to avoid the subsequent circuit from mistakenly generating a bandgap reference establishment signal based on a lower bandgap reference signal and the power supply voltage when the power supply voltage is slowly powered on;

[0118] The voltage margin control unit limits the power supply voltage margin again, further ensuring the bandgap reference voltage V BG When the establishment is completed, a low-level bandgap reference establishment signal can be accurately generated when the power supply voltage is powered down to protect the subsequent circuits;

[0119] The present invention is applicable to different power supply voltage power-on and power-off rates, and the solution is simple in method, low in cost, high in reliability and strong in versatility.

[0120] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0121] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A detection circuit based on a bandgap reference voltage, applied to a bandgap reference voltage circuit, the bandgap reference voltage circuit comprising a bandgap reference voltage generating circuit and a start-up circuit, the bandgap reference voltage generating circuit being used to generate a bandgap reference voltage V at a first output node BG , characterized in that, The detection circuit comprises: A voltage-limited startup control unit is connected between the power supply voltage and the reference potential, and is connected to the control end of the first MOS tube in the bandgap reference voltage generating circuit, and is used to mirror-copy the current flowing through the first MOS tube to generate a first current when the power supply voltage is powered up to a first voltage threshold; A voltage margin control unit is connected to the voltage limit start control unit and the first output node, and is used for, when the power supply voltage is powered up to the second voltage threshold, based on the first current and the bandgap reference voltage V BG A bandgap reference setup signal BG_S is generated at the second output node, and the second voltage threshold is greater than the first voltage threshold.

2. The detection circuit based on the bandgap reference voltage according to claim 1, characterized in that: The voltage-limited startup control unit includes a voltage-limited unit and a first current copy unit; wherein, The voltage limiting unit includes a second MOS tube, a voltage limiting device or a plurality of voltage limiting devices arranged in series, wherein a first end of the second MOS tube is connected to a power supply voltage, a control end of the second MOS tube is connected to a control end of the first MOS tube, and a second end of the second MOS tube is connected to the voltage limiting device; The first current replication unit is connected to the voltage limiting device and is used to generate a first current.

3. The detection circuit based on the bandgap reference voltage according to claim 2, characterized in that: The first current copy unit includes a fourth MOS tube and a fifth MOS tube; wherein, The second end of the fourth MOS tube is short-circuited with the control end, the second end of the fourth MOS tube is connected to the voltage limiting device, and the first end of the fourth MOS tube is connected to the reference potential; The control end of the fifth MOS tube is connected to the control end of the fourth MOS tube, the first end of the fifth MOS tube is connected to the reference potential, and the second end of the fifth MOS tube is connected to the voltage margin control unit.

4. The detection circuit based on the bandgap reference voltage according to claim 3, characterized in that: The first voltage threshold is V DS,M2 +V TH,M3 +V TH,M4 , where V DS,M2 is the drain-source voltage of the second MOS tube, V TH,M3 is the conduction voltage of the third MOS tube, V TH,M4 is the turn-on threshold voltage of the fourth MOS tube.

5. The detection circuit based on bandgap reference voltage according to claim 1, characterized in that: The voltage margin control unit includes a second current copy unit, an eighth MOS tube and a pull-down resistor; wherein, The second current copy unit is connected to the voltage-limited startup control unit and the power supply voltage, and the second current copy unit is used to copy the first current and generate a mirror current; The first end of the eighth MOS tube is connected to the second current replication unit, the control end of the eighth MOS tube is connected to the first output node, and the second end of the eighth MOS tube is connected to the second output node; A first end of the pull-down resistor is connected to the second output node, and a second end of the pull-down resistor is connected to a reference potential.

6. The detection circuit based on bandgap reference voltage according to claim 5, characterized in that: The second current copy unit includes a sixth MOS tube and a seventh MOS tube; The control end of the sixth MOS tube is short-circuited with the second end, and the control end of the sixth MOS tube is connected to the voltage-limited startup control unit, and the first end of the sixth MOS tube is connected to the power supply voltage; The first end of the seventh MOS tube is connected to the power supply voltage, the control end of the seventh MOS tube is connected to the control end of the sixth MOS tube, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube.

7. The detection circuit based on bandgap reference voltage according to claim 6, characterized in that: The second voltage threshold is V BG +V DS,M7 +V TH,M8 , where V DS,M7 is the drain-source voltage of the seventh MOS tube, V TH,M8 is the turn-on threshold voltage of the eighth MOS tube.

8. The detection circuit based on bandgap reference voltage according to claim 5, characterized in that: The voltage margin control unit further includes a signal shaping unit, including a trigger, a first inverter and a second inverter; The input end of the trigger is connected to the second output node and receives the bandgap reference establishment signal BG_S, and the output end of the trigger is connected to the input end of the first inverter and generates a first logic level signal; The output terminal of the first inverter is connected to the input terminal of the second inverter and generates a second logic level signal, and the output terminal of the second inverter generates an output signal BG_OK.

9. The detection circuit based on bandgap reference voltage according to claim 8, characterized in that: The voltage margin control unit also includes a current compensation unit; The current compensation unit is connected to the second current copy unit and the output end of the first inverter in the signal shaping unit, and the current compensation unit is connected to the power supply voltage. The current compensation unit is used to generate a compensation current based on the second logic level signal.

10. The detection circuit based on bandgap reference voltage according to claim 9, characterized in that: The current compensation unit includes a ninth MOS tube and a tenth MOS tube; wherein, The first end of the ninth MOS tube is connected to the power supply voltage, the control end of the ninth MOS tube is connected to the second current copy unit, and the second end of the ninth MOS tube is connected to the first end of the tenth MOS tube; The control end of the tenth MOS tube is connected to the output end of the first inverter, and the second end of the tenth MOS tube is connected to the first end of the eighth MOS tube.

11. The detection circuit based on bandgap reference voltage according to claim 8, characterized in that: The signal shaping unit also includes an RC delay unit; The RC delay unit is connected between the output end of the trigger and the reference potential, and is used for delaying the first logic level signal.

12. The detection circuit based on bandgap reference voltage according to claim 1, characterized in that: The detection circuit also includes a power-on protection unit; The power-on protection unit is connected between the second output node and the reference potential and is connected to the startup circuit, and is used for pulling down the voltage on the second output node to the first level after the startup circuit is powered on.

13. The detection circuit based on bandgap reference voltage according to claim 12, characterized in that: The power-on protection unit includes an eleventh MOS tube, a first end of the eleventh MOS tube is connected to a reference potential, a control end of the eleventh MOS tube is connected to a start-up circuit, and a second end of the eleventh MOS tube is connected to a second output node.

14. A bandgap reference voltage circuit, characterized in that: The bandgap reference voltage circuit comprises: The bandgap reference voltage generating circuit is connected between the power supply voltage and the reference potential and is used to generate a bandgap reference voltage V at the first output node. BG ; A startup circuit, connected between the power supply voltage and the reference potential, and connected to the first output node and the control end of the first MOS transistor in the bandgap reference voltage generating circuit, for starting the bandgap reference voltage generating circuit; A detection circuit, the detection circuit comprising: A voltage-limited startup control unit is connected between the power supply voltage and the reference potential, and is connected to the control end of the first MOS tube in the bandgap reference voltage generating circuit, and is used to mirror-copy the current flowing through the first MOS tube to generate a first current when the power supply voltage is powered up to a first voltage threshold; A voltage margin control unit is connected to the voltage limit start control unit and the first output node, and is used for, when the power supply voltage is powered up to the second voltage threshold, based on the first current and the bandgap reference voltage V BG A bandgap reference setup signal BG_S is generated at the second output node, and the second voltage threshold is greater than the first voltage threshold.

15. The bandgap reference voltage circuit according to claim 14, characterized in that: The startup circuit includes a pull-up resistor, a control tube and a current mirror unit, wherein the first end of the pull-up resistor is connected to the power supply voltage, the second end is connected to the second end of the control tube and the current mirror unit, the control end of the control tube is connected to the first output node, the first end is connected to the reference potential, and the current mirror unit is connected to the control end of the first MOS tube and the detection circuit.

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