Detection circuit based on bandgap reference voltage and bandgap reference voltage circuit

Abstract

The present invention discloses a detection circuit based on a bandgap reference voltage and a bandgap reference voltage circuit. The detection circuit includes: a voltage-limited startup control unit connected between a power supply voltage and a reference potential, and connected to a control end of a first MOS transistor in a bandgap reference voltage generating circuit, and used for mirroring a current flowing through the first MOS transistor to generate a first current when the power supply voltage is powered up to a first voltage threshold; a voltage margin control unit connected to the voltage-limited startup control unit and a first output node, and used for generating a first current based on the first current and the bandgap reference voltage V when the power supply voltage is powered up to a second voltage threshold. BG Generate a bandgap reference establishment signal BG_S. The present invention, through the setting of the detection circuit, can determine whether the bandgap reference voltage is established without introducing a reference voltage in the bandgap reference voltage circuit. After the power supply voltage is powered up to the second voltage threshold, a high-level bandgap reference establishment signal is output, which is applicable to the situation where the power supply voltage is powered up slowly.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a detection circuit based on a bandgap reference voltage and a bandgap reference voltage circuit. Background Art

[0002] Bandgap (BG) is a scale for voltage and current in a chip. Whether it is accurate directly determines whether the ruler is accurate, so the bandgap reference voltage is judged Whether it has been established correctly and provides an accurate bandgap reference establishment completion signal to the subsequent circuit to indicate the bandgap reference voltage It is very important that it is already stably established.

[0003] Existing technologies typically use a reference current generated by a reference voltage source to generate a target bandgap reference voltage. The stability of the target bandgap reference voltage is determined by detecting whether the reference current is stable. However, when the reference voltage source is slowly powered on, it can happen that the reference current is established but the target bandgap reference voltage is not. This results in an inaccurate signal indicating the bandgap reference is established, which can affect the operation of subsequent circuits and even damage them.

[0004] Therefore, in order to solve the above technical problems, it is necessary to provide a detection circuit based on a bandgap reference voltage and a bandgap reference voltage circuit. Summary of the Invention

[0005] The object of the present invention is to provide a detection circuit based on a bandgap reference voltage and a bandgap reference voltage circuit, which can generate an accurate bandgap reference establishment completion signal when the power supply voltage is slowly powered on.

[0006] In order to achieve the above object, a specific embodiment of the present invention provides the following technical solutions:

[0007] A detection circuit based on a bandgap reference voltage is applied to a bandgap reference voltage circuit, wherein the bandgap reference voltage circuit includes a bandgap reference voltage generating circuit and a start-up circuit, wherein the bandgap reference voltage generating circuit is used to generate a bandgap reference voltage at a first output node. , the detection circuit includes:

[0008] a voltage-limited startup control unit, connected between the power supply voltage and the reference potential, and connected to the control terminal of the first MOS transistor in the bandgap reference voltage generating circuit, and configured to mirror the current flowing through the first MOS transistor to generate a first current when the power supply voltage is powered up to a first voltage threshold;

[0009] A voltage margin control unit is connected to the voltage limit start control unit and the first output node, and is used to generate a voltage margin control unit based on the first current and the bandgap reference voltage when the power supply voltage is powered up to the second voltage threshold. A bandgap reference setup signal BG_S is generated at the second output node, and the second voltage threshold is greater than the first voltage threshold.

[0010] In one or more embodiments of the present invention, the voltage-limited startup control unit includes a voltage-limiting unit and a first current copying unit; wherein,

[0011] The voltage limiting unit includes a second MOS transistor, a voltage limiting device or multiple voltage limiting devices arranged in series, a first end of the second MOS transistor is connected to the power supply voltage, a control end of the second MOS transistor is connected to the control end of the first MOS transistor, and a second end of the second MOS transistor is connected to the voltage limiting device;

[0012] The first current replication unit is connected to the voltage limiting device and is configured to generate a first current.

[0013] In one or more embodiments of the present invention, the first current copy unit includes a fourth MOS transistor and a fifth MOS transistor; wherein,

[0014] The second end of the fourth MOS transistor is short-circuited with the control end, the second end of the fourth MOS transistor is connected to the voltage limiting device, and the first end of the fourth MOS transistor is connected to the reference potential;

[0015] The control end of the fifth MOS tube is connected to the control end of the fourth MOS tube, the first end of the fifth MOS tube is connected to the reference potential, and the second end of the fifth MOS tube is connected to the voltage margin control unit.

[0016] In one or more embodiments of the present invention, the first voltage threshold is ,in, is the drain-source voltage of the second MOS tube, is the conduction threshold voltage of the third MOS tube, is the turn-on threshold voltage of the fourth MOS tube.

[0017] In one or more embodiments of the present invention, the voltage margin control unit includes a second current copy unit, an eighth MOS transistor and a pull-down resistor; wherein,

[0018] The second current copy unit is connected to the voltage-limited startup control unit and the power supply voltage, and the second current copy unit is used to copy the first current and generate a mirror current;

[0019] The first end of the eighth MOS transistor is connected to the second current replication unit, the control end of the eighth MOS transistor is connected to the first output node, and the second end of the eighth MOS transistor is connected to the second output node;

[0020] A first end of the pull-down resistor is connected to the second output node, and a second end of the pull-down resistor is connected to a reference potential.

[0021] In one or more embodiments of the present invention, the second current copy unit includes a sixth MOS transistor and a seventh MOS transistor;

[0022] The control end of the sixth MOS tube is short-circuited with the second end, the control end of the sixth MOS tube is connected to the voltage-limited startup control unit, and the first end of the sixth MOS tube is connected to the power supply voltage;

[0023] The first end of the seventh MOS tube is connected to the power supply voltage, the control end of the seventh MOS tube is connected to the control end of the sixth MOS tube, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube.

[0024] In one or more embodiments of the present invention, the second voltage threshold is ,in, is the drain-source voltage of the seventh MOS tube, is the turn-on threshold voltage of the eighth MOS tube.

[0025] In one or more embodiments of the present invention, the voltage margin control unit further includes a signal shaping unit including a trigger, a first inverter, and a second inverter;

[0026] The input terminal of the trigger is connected to the second output node and receives the bandgap reference establishment signal BG_S, and the output terminal of the trigger is connected to the input terminal of the first inverter and generates a first logic level signal;

[0027] The output terminal of the first inverter is connected to the input terminal of the second inverter and generates a second logic level signal, and the output terminal of the second inverter generates an output signal BG_OK.

[0028] In one or more embodiments of the present invention, the voltage margin control unit further includes a current compensation unit;

[0029] The current compensation unit is connected to the second current copy unit and the output end of the first inverter in the signal shaping unit, and is connected to the power supply voltage. The current compensation unit is used to generate a compensation current based on the second logic level signal.

[0030] In one or more embodiments of the present invention, the current compensation unit includes a ninth MOS transistor and a tenth MOS transistor; wherein,

[0031] The first end of the ninth MOS transistor is connected to the power supply voltage, the control end of the ninth MOS transistor is connected to the second current replication unit, and the second end of the ninth MOS transistor is connected to the first end of the tenth MOS transistor;

[0032] The control end of the tenth MOS transistor is connected to the output end of the first inverter, and the second end of the tenth MOS transistor is connected to the first end of the eighth MOS transistor.

[0033] In one or more embodiments of the present invention, the signal shaping unit further includes an RC delay unit; the RC delay unit is connected between the output terminal of the trigger and the reference potential, and is used to perform delay processing on the first logic level signal.

[0034] In one or more embodiments of the present invention, the detection circuit further includes a power-on protection unit;

[0035] The power-on protection unit is connected between the second output node and the reference potential and is connected to the startup circuit, and is used to pull down the voltage on the second output node to the first level after the startup circuit is powered on.

[0036] In one or more embodiments of the present invention, the power-on protection unit includes an eleventh MOS transistor, a first end of the eleventh MOS transistor is connected to the reference potential, a control end of the eleventh MOS transistor is connected to the startup circuit, and a second end of the eleventh MOS transistor is connected to the second output node.

[0037] Another specific embodiment of the present invention provides a technical solution as follows:

[0038] A bandgap reference voltage circuit, comprising:

[0039] A bandgap reference voltage generating circuit is connected between the power supply voltage and the reference potential and is used to generate a bandgap reference voltage at the first output node. ;

[0040] A startup circuit is connected between the power supply voltage and the reference potential, and is connected to the first output node and the control terminal of the first MOS transistor in the bandgap reference voltage generating circuit, for starting the bandgap reference voltage generating circuit;

[0041] A detection circuit, the detection circuit comprising:

[0042] a voltage-limited startup control unit, connected between the power supply voltage and the reference potential, and connected to the control terminal of the first MOS transistor in the bandgap reference voltage generating circuit, and configured to mirror the current flowing through the first MOS transistor to generate a first current when the power supply voltage is powered up to a first voltage threshold;

[0043] A voltage margin control unit is connected to the voltage limit start control unit and the first output node, and is used to generate a voltage margin control unit based on the first current and the bandgap reference voltage when the power supply voltage is powered up to the second voltage threshold. A bandgap reference setup signal BG_S is generated at the second output node, and the second voltage threshold is greater than the first voltage threshold.

[0044] In one or more embodiments of the present invention, the startup circuit includes a pull-up resistor, a control tube and a current mirror unit, the first end of the pull-up resistor is connected to the power supply voltage, the second end is connected to the second end of the control tube and the current mirror unit, the control end of the control tube is connected to the first output node, and the first end is connected to the reference potential, and the current mirror unit is connected to the control end of the first MOS tube and the detection circuit.

[0045] Compared with the prior art, the detection circuit based on the bandgap reference voltage and the bandgap reference voltage circuit of the present invention can determine whether the bandgap reference voltage is established without introducing a reference voltage through the setting of the detection circuit, and output a high-level bandgap reference establishment signal after the power supply voltage is powered up to the second voltage threshold;

[0046] The present invention has high reliability and limits the power supply voltage margin through a voltage-limited startup control unit. When the power supply voltage is slowly powered on, it prevents the subsequent circuit from mistakenly generating a bandgap reference establishment signal based on a lower bandgap reference signal and the power supply voltage.

[0047] The voltage margin control unit limits the power supply voltage margin again, further ensuring the bandgap reference voltage After the establishment is completed, it can also accurately generate a low-level output signal when the power supply voltage is powered off to protect the subsequent circuit;

[0048] The present invention has strong versatility and is applicable to different power supply voltage and power-on and power-off rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 FIG. 1 is a schematic diagram of a detection circuit based on a bandgap reference voltage and a bandgap reference voltage circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0052] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices to achieve the same or similar functional purpose, such as a connection through circuits or components such as switches and follower circuits. Furthermore, in the present invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0053] The present invention discloses a detection circuit based on a bandgap reference voltage, which is applied to a bandgap reference voltage circuit, wherein the bandgap reference circuit includes a bandgap reference voltage generating circuit and a start-up circuit. The detection circuit includes:

[0054] a voltage-limited startup control unit, connected between the power supply voltage and the reference potential, and connected to the control terminal of the first MOS transistor in the bandgap reference voltage generating circuit, and configured to mirror the current flowing through the first MOS transistor to generate a first current when the power supply voltage is powered up to a first voltage threshold;

[0055] A voltage margin control unit is connected to the voltage limit start control unit and the first output node, and is used to generate a voltage margin control unit based on the first current and the bandgap reference voltage when the power supply voltage is powered up to the second voltage threshold. A bandgap reference setup signal BG_S is generated at the second output node, and the second voltage threshold is greater than the first voltage threshold.

[0056] The present invention also discloses a bandgap reference voltage circuit, comprising:

[0057] A bandgap reference voltage generating circuit is connected between the power supply voltage and the reference potential and is used to generate a bandgap reference voltage at the first output node. ;

[0058] A startup circuit is connected between the power supply voltage and the reference potential, and is connected to the first output node and the control terminal of the first MOS transistor in the bandgap reference voltage generating circuit, for starting the bandgap reference voltage generating circuit;

[0059] The detection circuit is used to generate a bandgap reference establishment signal BG_S.

[0060] The present invention will be further described below with reference to specific embodiments.

[0061] like Figure 1 As shown, the bandgap reference voltage generating circuit 10 in this embodiment includes an operational amplifier AMP, a first MOS transistor M1 , a first branch and a second branch.

[0062] A first end of the first MOS transistor M1 is connected to a power supply voltage VDD, a second end of the first MOS transistor M1 is connected to a first output node, a first branch includes a first bipolar transistor Q1 and a plurality of first matching resistors R1, a second branch includes a second bipolar transistor Q2 and a plurality of second matching resistors R2a and R2b, a first input end and a second input end of the operational amplifier AMP are connected to the first branch and the second branch respectively, an output end of the operational amplifier AMP is connected to a control end of the first MOS transistor M1, and a first output node is used to output a bandgap reference voltage .

[0063] The base and collector of the first bipolar transistor Q1 are short-circuited, and the collector is connected to the first matching resistor R1, and the emitter of the first bipolar transistor Q1 is connected to the reference potential GND; the base and collector of the second bipolar transistor Q2 are short-circuited, and the collector is connected to the second matching resistor R2b, and the emitter of the second bipolar transistor Q2 is connected to the reference potential GND.

[0064] The reference potential GND in this embodiment is the ground potential, the first terminal of the MOS transistor involved in this embodiment is the source, the second terminal is the drain, and the control terminal is the gate. In this embodiment, the first MOS transistor M1 is a PMOS transistor.

[0065] The bandgap reference voltage generating circuit 10 generates a bandgap reference voltage The principle is already in the prior art and will not be described in detail in this invention.

[0066] The startup circuit 20 includes a pull-up resistor R3, a control transistor MN1, and a current mirror unit 21. The first end of the pull-up resistor R3 is connected to the power supply voltage VDD, the second end of the pull-up resistor R3 is connected to the second end of the control transistor MN1 and the current mirror unit 21, and the control end of the control transistor MN1 is connected to the first output node to receive the bandgap reference voltage. The first end of the control transistor MN1 is connected to the reference potential GND, the current mirror unit 21 is connected to the control end of the first MOS transistor M1, and the startup circuit 20 is used to start the bandgap reference voltage generating circuit 10.

[0067] Furthermore, the current mirror unit 21 includes a twelfth MOS transistor MN2 and a thirteenth MOS transistor MN3. A first end of the twelfth MOS transistor MN2 is connected to the reference potential GND, a second end of the twelfth MOS transistor MN2 is short-circuited with its own control end, and a second end of the twelfth MOS transistor MN2 is connected to the second end of the pull-up resistor R3. A first end of the thirteenth MOS transistor MN3 is connected to the reference potential GND, a second end of the thirteenth MOS transistor MN3 is connected to the control end of the first MOS transistor M1 in the bandgap reference voltage generating circuit 10, and a control end of the thirteenth MOS transistor MN3 is connected to the control end of the twelfth MOS transistor MN2. In this embodiment, the control transistor MN1, the twelfth MOS transistor MN2, and the thirteenth MOS transistor MN3 are NMOS transistors.

[0068] like Figure 1 As shown, the detection circuit 30 based on the bandgap reference voltage in this embodiment includes:

[0069] The voltage-limited startup control unit 31 is connected between the power supply voltage VDD and the reference potential GND, and is connected to the control terminal of the first MOS transistor M1 in the bandgap reference voltage generating circuit 10. The control unit 31 is configured to mirror the current flowing through the first MOS transistor M1 to generate the first current Ib when the power supply voltage VDD is powered up to a first voltage threshold.

[0070] The voltage margin control unit 32 is connected to the voltage limit start control unit 31 and the first output node A, and is used to generate a voltage margin control unit based on the first current Ib and the bandgap reference voltage when the power supply voltage VDD is powered up to the second voltage threshold. The bandgap reference setup signal BG_S is generated at the second output node A. The second voltage threshold is greater than the first voltage threshold.

[0071] The voltage-limited startup control unit in this embodiment includes a voltage-limiting unit 311 and a first current copying unit 312 .

[0072] The voltage limiting unit 311 includes a second MOS transistor M2 and a voltage limiting device or multiple voltage limiting devices arranged in series. A first terminal of the second MOS transistor M2 is connected to the power supply voltage VDD, a control terminal of the second MOS transistor M2 is connected to the control terminal of the first MOS transistor M1, and a second terminal of the second MOS transistor M2 is connected to the voltage limiting device. In this embodiment, the second MOS transistor M2 is a PMOS transistor.

[0073] Furthermore, if Figure 1 As shown, the voltage limiting device in this embodiment includes a third MOS transistor M3. A first end of the third MOS transistor M3 is connected to the second end of the second MOS transistor M2. A control end of the third MOS transistor M3 is short-circuited with its own second end. A second end of the third MOS transistor M3 is connected to the first current replication unit 312. In this embodiment, the third MOS transistor M3 is a PMOS transistor.

[0074] It is understandable that, in other optional embodiments, the voltage limiting unit 311 may include multiple voltage limiting devices, and the multiple voltage limiting devices may be connected in series. That is, multiple control terminals are sequentially connected to the third MOS transistors M3 whose second terminals are short-circuited, and the first terminal of the first-stage third MOS transistor is connected to the second terminal of the second MOS transistor M2, the first terminal of the next-stage third MOS transistor is connected to the second terminal of the previous-stage third MOS transistor, and the second terminal of the last-stage third MOS transistor is connected to the first current replicating unit 312.

[0075] The first current copy unit 312 is connected to the voltage limiting device and is used to generate the first current Ib. Specifically, the current copy unit 312 includes a fourth MOS transistor M4 and a fifth MOS transistor M5. The fourth MOS transistor M4 and the fifth MOS transistor M5 are NMOS transistors.

[0076] The second end of the fourth MOS transistor M4 is short-circuited with its own control end, the second end of the fourth MOS transistor M4 is connected to the voltage limiting device, and the first end of the fourth MOS transistor M4 is connected to the reference potential GND.

[0077] A second end of the fifth MOS transistor M5 is connected to the control end of the sixth MOS transistor M6 in the voltage margin control unit 32. The control end of the fifth MOS transistor M5 is connected to the control end of the fourth MOS transistor M4. A first end of the fifth MOS transistor M5 is connected to the reference potential GND. It can be understood that the fourth MOS transistor M4 and the fifth MOS transistor M5 form a current mirror.

[0078] Based on the connection structure of the voltage-limited startup control unit 31, it can be seen that the first voltage threshold is ,in, is the drain-source voltage of the second MOS tube, is the conduction threshold voltage of the third MOS tube, is the conduction threshold voltage of the fourth MOS tube. Further, if the number of voltage limiting devices is n, the first voltage threshold is .

[0079] After the power supply voltage VDD is powered up to the first voltage threshold, the current copying unit 312 in the voltage-limited startup control unit 31 is started, and the second MOS transistor M2 and the first MOS transistor M1 also form a current mirror. At this time, the second MOS transistor M2 copies the current in the first MOS transistor M1. The current in the fourth MOS transistor M4 in the current copying unit 312 is equal to the current in the second MOS transistor M2, and the current in the fifth MOS transistor M5 is the first current Ib.

[0080] like Figure 1As shown, the voltage margin control unit 32 in this embodiment includes a second current copy unit 321 , an eighth MOS transistor M8 and a pull-down resistor R4 .

[0081] The second current copy unit 321 is connected to the voltage-limited startup control unit 31 and the power supply voltage VDD. The second current copy unit 321 is used to copy the first current Ib and generate a mirror current Is.

[0082] A first end of the eighth MOS transistor M8 is connected to the second current copy unit 321 , a control end of the eighth MOS transistor M8 is connected to the first output node A, and a second end of the eighth MOS transistor is connected to the second output node A. In this embodiment, the eighth MOS transistor M8 is a PMOS transistor.

[0083] The first end of the pull-down resistor R4 is connected to the second output node A, and the second end of the pull-down resistor R4 is connected to the reference potential GND. The pull-down resistor R4 is used to generate a bandgap reference establishment signal BG_S based on the mirror current Is after the eighth MOS transistor M8 is turned on.

[0084] like Figure 1 As shown, the second current copy unit 321 in this embodiment includes a sixth MOS transistor M6 and a seventh MOS transistor M7.

[0085] The control end of the sixth MOS transistor M6 is short-circuited with its own second end, and the control end of the sixth MOS transistor M6 is connected to the second end of the fifth MOS transistor M5 in the voltage-limited startup control unit 31 . The first end of the sixth MOS transistor M6 is connected to the power supply voltage VDD.

[0086] A first terminal of the seventh MOS transistor M7 is connected to the power supply voltage VDD, a control terminal of the seventh MOS transistor M7 is connected to the control terminal of the sixth MOS transistor M6, and a second terminal of the seventh MOS transistor M7 is connected to the first terminal of the eighth MOS transistor M8. In this embodiment, the sixth MOS transistor M6 and the seventh MOS transistor M7 are PMOS transistors.

[0087] From the circuit structure of the second current copy unit 321, the eighth MOS tube M8 and the pull-down resistor R4, it can be seen that the second voltage threshold is ,in, is the drain-source voltage of the seventh MOS tube M7, is the turn-on threshold voltage of the eighth MOS transistor M8.

[0088] like Figure 1 As shown, in this embodiment, the voltage margin control unit 32 further includes a second capacitor C2, a first end of the second capacitor C2 is connected to the second output node A, and a second end of the second capacitor C2 is connected to the reference potential GND. The setting of the second capacitor C2 further ensures the power-on time of the power supply voltage VDD, that is, ensures the bandgap reference voltage The establishment time.

[0089] like Figure 1 As shown, in this embodiment, the voltage margin control unit 32 further includes a signal shaping unit connected to the second output node A, for shaping the bandgap reference setup signal BG_S and generating an output signal BG_OK.

[0090] The signal shaping unit in this embodiment includes a flip-flop I1, a first inverter I2, and a second inverter I3. The signal shaping unit in this embodiment is connected between a power supply voltage VDD and a reference potential GND. That is, the flip-flop I1, the first inverter I2, and the second inverter I3 operate between the power supply voltage VDD and the reference potential GND.

[0091] An input terminal of flip-flop I1 is connected to the second output node A and receives the bandgap reference setup signal BG_S. An output terminal of flip-flop I1 is connected to the input terminal of the first inverter I2 and generates a first logic level signal. In this embodiment, flip-flop I1 is a non-inverting Schmitt trigger. That is, when the bandgap reference setup signal BG_S is greater than a set flip-flop threshold, the first logic level signal generated by flip-flop I1 is a high level. Conversely, when the bandgap reference setup signal BG_S is less than the set flip-flop threshold, the first logic level signal generated by flip-flop I1 is a low level.

[0092] The output of the first inverter I2 is connected to the input of the second inverter I3 and generates a second logic level signal. The output of the second inverter I3 generates an output signal BG_OK. It can be understood that the second logic level signal is inverted from the first logic level signal, and the output signal BG_OK is inverted from the second logic level signal.

[0093] like Figure 1 As shown, in this embodiment, the voltage margin control unit 32 further includes a current compensation unit 323, which is connected to the second current copy unit 321 and the output end of the first inverter I2 in the signal shaping unit, and is used to generate a compensation current Ic based on the second logic level signal.

[0094] Specifically, the current compensation unit 323 includes a ninth MOS transistor M9 and a tenth MOS transistor M10. A first terminal of the ninth MOS transistor M9 is connected to the power supply voltage VDD, a control terminal of the ninth MOS transistor M9 is connected to the control terminal of the seventh MOS transistor M7 in the second current replication unit 321, and a second terminal of the ninth MOS transistor M9 is connected to the first terminal of the tenth MOS transistor M10. The control terminal of the tenth MOS transistor M10 is connected to the output terminal of the first inverter I2, and a second terminal of the tenth MOS transistor M10 is connected to the first terminal of the eighth MOS transistor M8. The ninth MOS transistor M9 and the tenth MOS transistor M10 are PMOS transistors.

[0095] It can be understood that after the flip-flop I1 is flipped, when the second logic level signal is at a low level, the tenth MOS transistor M10 is turned on, and the ninth MOS transistor M9 and the seventh MOS transistor M7 can be regarded as a set of current mirrors. Then, the ninth MOS transistor M9 copies the current in the seventh MOS transistor M7 to generate the compensation current Ic. Then, after the eighth MOS transistor M8 is turned on, the current in the eighth MOS transistor M8 is the sum of the mirror current Is and the compensation current Ic.

[0096] like Figure 1 As shown, optionally, the signal shaping unit in this embodiment further includes an RC delay unit 322 for performing delay processing on the first logic level signal. The RC delay unit is connected between the output terminal of the trigger and the reference potential GND.

[0097] The RC delay unit 322 includes a third resistor R5 and a first capacitor C1, a first end of the third resistor R5 is connected to the output end of the trigger I1, a second end of the third resistor R5 is connected to the first end of the first capacitor C1, a second end of the first capacitor C1 is connected to the reference potential GND, and a first end of the first capacitor C1 is connected to the input end of the first inverter I2.

[0098] like Figure 1 As shown, the detection circuit in this embodiment further includes a power-on protection unit 33. The power-on protection unit 33 is connected between the second output node A and the reference potential GND, and is connected to the current mirror unit 21 in the startup circuit 20. The power-on protection unit 33 is configured to pull down the potential of the second output node A to a first level after the startup circuit 20 is powered on, that is, to pull down the bandgap reference setup signal BG_S to a first level. In this embodiment, the first level is a low level.

[0099] Specifically, the power-on protection unit 33 includes an eleventh MOS transistor M11. A first end of the eleventh MOS transistor M11 is connected to the reference potential GND, a second end of the eleventh MOS transistor M11 is connected to the second output node A, and a control end of the eleventh MOS transistor M11 is connected to the control end of the thirteenth MOS transistor MN3 in the current mirror unit 21. The eleventh MOS transistor M11 is an NMOS transistor.

[0100] The working principle of the bandgap reference voltage circuit in this embodiment is as follows:

[0101] The present invention is applicable to the slow power-up of the power supply voltage VDD. When the power supply voltage VDD does not start to power up, the bandgap reference voltage generating circuit 10, the starting circuit 20 and the detection circuit 30 are in an inoperative state.

[0102] When the power supply voltage VDD starts to power on and is at a lower voltage value, the startup circuit 20 starts to work: the bandgap reference voltage Very low, the control tube MN1 is in the off state, the thirteenth MOS tube MN3 is turned on, so the control terminal PGATE voltage of the first MOS tube M1 is pulled down, and the bandgap reference voltage is The voltage at the control terminal of the thirteenth MOS transistor MN3 is nearly equal to the power supply voltage VDD. The voltage at the control terminal of the thirteenth MOS transistor MN3 is pulled up to the power supply voltage VDD by the pull-up resistor R3. Therefore, the eleventh MOS transistor M11 is turned on. The eleventh MOS transistor M11 pulls down the potential of the second output node A, that is, the bandgap reference establishment signal BG_S is at a low level, and the output signal BG_OK is at a low level, thereby avoiding generation of an erroneous bandgap reference establishment signal BG_S when the power supply voltage VDD starts to be powered on.

[0103] The power supply voltage VDD continues to increase to about 0.6V and is less than the first voltage threshold ( ), the control transistor MN1 is turned on, the voltage of the control terminal PGATE of the first MOS transistor M1 is pulled down, and the voltage of the second terminal of the pull-up resistor R3 is pulled down, thereby turning off the twelfth MOS transistor MN2, the thirteenth MOS transistor MN3 and the eleventh MOS transistor M11. At this time, the startup circuit 20 is turned off, and the bandgap reference voltage generating circuit 10 relies on its internal loop regulation to generate the bandgap reference voltage. Since the power supply voltage VDD has not risen to the first voltage threshold at this time, the voltage limit startup control unit 31 is not started. Therefore, the first current Ib is 0, the mirror current Is is also 0, the potential of the second output node A is low, the bandgap reference establishment signal BG_S is low, and the output signal BG_OK is low.

[0104] The power supply voltage VDD continues to be powered up to a value greater than the first voltage threshold ( ), the power supply voltage VDD at this time can generally make the bandgap reference voltage When the voltage-limited startup control unit 31 is activated near a stable value, the first current Ib gradually increases. At this point, the eighth MOS transistor M8 is turned off, the potential of the second output node A is low, the bandgap reference establishment signal BG_S is at a low level, and the output signal BG_OK is also at a low level. The voltage-limited startup control unit 31 implements power supply voltage margin control, improving the accuracy of the bandgap reference establishment signal BG_S and the output signal BG_OK.

[0105] The power supply voltage VDD continues to be powered up to a value greater than the second voltage threshold ( ), the eighth MOS transistor M8 is turned on, a mirror current Is is generated in the seventh MOS transistor M7, and the voltage of the second output node A (i.e., the bandgap reference establishment signal BG_S) is pulled high. When the voltage of the second output node A is greater than the flip-flop set threshold, the flip-flop I1 flips and generates a high-level first logic level signal. The first logic level signal generates a high-level output signal BG_OK after passing through the first inverter I2 and the second inverter I3, indicating that the power supply voltage VDD is sufficient to establish the bandgap reference voltage VBG to 1.2V.

[0106] During the VDD establishment process, the voltage of the second output node A is equal to ×R4, where is the current in the seventh MOS tube M7 If the voltage of the second output node A (bandgap reference establishment signal BG_S) is not high enough, the Schmitt trigger may flip, and both the PMOS and NMOS transistors inside the Schmitt trigger are turned on, forming a current path from the power supply voltage VDD to the ground potential GND, and generating leakage current.

[0107] Therefore, this embodiment proposes a current compensation unit 323. When the voltage of the second output node A is greater than the flip-flop threshold set by the trigger, the trigger I1 is flip-triggered, the first logic level signal is high, and the second logic level signal is low. At this time, the current compensation unit 323 generates a compensation current Ic, and the voltage of the second output node A is equal to ( ) × R4. The voltage of the second output node A is close to the power supply voltage VDD, and the Schmitt trigger flips normally while preventing the Schmitt trigger from generating leakage current.

[0108] During the power-down process of the power supply voltage VDD, when the power supply voltage VDD is lower than the second voltage threshold ( ), the eighth MOS transistor M8 is turned off, the pull-down resistor R4 pulls down the voltage of the second output node A, the bandgap reference establishment signal BG_S is low, the trigger I1 is triggered to flip, the first logic level signal changes from high level to low level, the second logic level signal changes from low level to high level, the output signal BG_OK changes to low level, and the subsequent circuit triggers protection.

[0109] The present invention is also applicable to the case where the power supply voltage VDD is quickly powered on. Based on the RC delay unit 322 proposed in this embodiment, when the power supply voltage VDD is about to be powered on to the second voltage threshold, the RC delay unit 322 can filter out high-frequency noise and control the first inverter I2 to delay receiving the first logic level signal, thereby avoiding the generation of an erroneous output signal BG_OK and improving the anti-interference capability and reliability of the system.

[0110] The detection circuit in this embodiment includes four states:

[0111] In the first state (the bandgap reference voltage establishes the startup state), the startup circuit 20 works, and the current in the first MOS tube M1 and the bandgap reference voltage As the voltage gradually increases, the eleventh MOS transistor M11 in the detection circuit 30 is turned on, pulling down the voltage on the second output node A, the bandgap reference establishment signal BG_S is at a low level (0), and the output signal BG_OK output by the signal shaping unit is at a low level (0).

[0112] In the second state (the bandgap reference voltage establishes the primary state), the startup circuit 20 does not work, the eleventh MOS transistor M11 is turned off, and the bandgap reference voltage During the establishment process, as the power supply voltage VDD gradually increases but is less than the first voltage threshold, the bandgap reference voltage The current in the first MOS tube M1 gradually increases, the second MOS tube M2 is turned off, the current in the second MOS tube M2 and the current copy unit is 0, the bandgap reference establishment signal BG_S is low level (0), and the output signal BG_OK is low level (0).

[0113] The third state (bandgap reference voltage establishes a secondary state) is as the power supply voltage VDD and the bandgap reference voltage As the voltage rises, the current in the first MOS transistor M1 gradually increases, the power supply voltage VDD is greater than the first voltage threshold but less than the second voltage threshold, the second MOS transistor M2 is turned on, the second MOS transistor M2, the current copy unit and the seventh MOS transistor M7 copy the current in the first MOS transistor M1 step by step and generate the first current Ib, the eighth MOS transistor M8 is turned off, the current in the eighth MOS transistor M8 is 0, the voltage on the pull-down resistor R4 is 0, that is, the voltage on the second output node A is 0, the bandgap reference establishment signal BG_S is low level (0), and the output signal BG_OK output by the signal shaping unit is low level (0).

[0114] In the fourth state (the state after the bandgap reference voltage is established), the power supply voltage VDD is greater than the second voltage threshold, and the bandgap reference voltage After the establishment is completed, the eighth MOS transistor M8 is turned on, and the voltage on the pull-down resistor R4 (i.e., the voltage on the second output node A) gradually increases. When the voltage on the pull-down resistor R4 exceeds the flip threshold voltage of the Schmitt trigger, the bandgap reference establishment signal BG_S is high (1), and the output signal BG_OK output by the signal shaping unit is high (1).

[0115] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0116] The present invention can judge whether the bandgap reference voltage is established by setting the detection circuit without introducing a reference voltage in the bandgap reference voltage circuit. After establishment, the bandgap reference establishment signal outputting a high level can be applied to the case where the power supply voltage is powered on slowly.

[0117] The power supply voltage margin is limited by the voltage-limited startup control unit to prevent the subsequent circuit from mistakenly generating a bandgap reference establishment signal based on a low bandgap reference signal and the power supply voltage when the power supply voltage is slowly powered on;

[0118] The voltage margin control unit limits the power supply voltage margin again, further ensuring the bandgap reference voltage When the establishment is completed, a low-level bandgap reference establishment signal can be accurately generated when the power supply voltage is powered off to protect the subsequent circuits.

[0119] The present invention is applicable to different power supply voltage and power-on and power-off rates, and the solution is simple in approach, low in cost, high in reliability, and strong in versatility.

[0120] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0121] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A detection circuit based on a bandgap reference voltage, applied to a bandgap reference voltage circuit, wherein the bandgap reference voltage circuit comprises a bandgap reference voltage generating circuit and a start-up circuit, wherein the bandgap reference voltage generating circuit is used to generate a bandgap reference voltage at a first output node. , characterized in that, The detection circuit comprises: a voltage-limited startup control unit, connected between the power supply voltage and the reference potential, and connected to the control terminal of the first MOS transistor in the bandgap reference voltage generating circuit, and configured to mirror the current flowing through the first MOS transistor to generate a first current when the power supply voltage is powered up to a first voltage threshold; A voltage margin control unit is connected to the voltage limit start control unit and the first output node, and is used to generate a voltage margin control unit based on the first current and the bandgap reference voltage when the power supply voltage is powered up to the second voltage threshold. generating a bandgap reference setup signal BG_S at a second output node, wherein the second voltage threshold is greater than the first voltage threshold; The voltage-limited startup control unit includes a voltage-limiting unit and a first current copying unit, wherein the voltage-limiting unit is connected to the power supply voltage and the control end of the first MOS transistor, and the first current copying unit is connected to the voltage-limiting unit for generating a first current; The voltage margin control unit includes a second current copying unit and an eighth MOS transistor. The second current copying unit is connected to the voltage-limited startup control unit and the power supply voltage. The second current copying unit is used to copy the first current and generate a mirror current. The first end of the eighth MOS transistor is connected to the second current copying unit, the control end of the eighth MOS transistor is connected to the first output node, and the second end of the eighth MOS transistor is connected to the second output node.

2. The detection circuit based on the bandgap reference voltage according to claim 1, wherein: The voltage limiting unit includes a second MOS transistor, a voltage limiting device or multiple voltage limiting devices arranged in series, the first end of the second MOS transistor is connected to the power supply voltage, the control end of the second MOS transistor is connected to the control end of the first MOS transistor, and the second end of the second MOS transistor is connected to the voltage limiting device.

3. The detection circuit based on the bandgap reference voltage according to claim 2, wherein: The first current copy unit includes a fourth MOS transistor and a fifth MOS transistor; wherein, The second end of the fourth MOS transistor is short-circuited with the control end, the second end of the fourth MOS transistor is connected to the voltage limiting device, and the first end of the fourth MOS transistor is connected to the reference potential; The control end of the fifth MOS tube is connected to the control end of the fourth MOS tube, the first end of the fifth MOS tube is connected to the reference potential, and the second end of the fifth MOS tube is connected to the voltage margin control unit.

4. The detection circuit based on the bandgap reference voltage according to claim 3, wherein: The first voltage threshold is ,in, is the drain-source voltage of the second MOS tube, is the conduction threshold voltage of the third MOS tube, is the turn-on threshold voltage of the fourth MOS tube.

5. The detection circuit based on bandgap reference voltage according to claim 1, wherein: The voltage margin control unit further includes a pull-down resistor; A first end of the pull-down resistor is connected to the second output node, and a second end of the pull-down resistor is connected to a reference potential.

6. The detection circuit based on bandgap reference voltage according to claim 5, characterized in that: The second current copy unit includes a sixth MOS transistor and a seventh MOS transistor; The control end of the sixth MOS tube is short-circuited with the second end, the control end of the sixth MOS tube is connected to the voltage-limited startup control unit, and the first end of the sixth MOS tube is connected to the power supply voltage; The first end of the seventh MOS tube is connected to the power supply voltage, the control end of the seventh MOS tube is connected to the control end of the sixth MOS tube, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube.

7. The detection circuit based on bandgap reference voltage according to claim 6, characterized in that: The second voltage threshold is ,in, is the drain-source voltage of the seventh MOS tube, is the turn-on threshold voltage of the eighth MOS tube.

8. The detection circuit based on bandgap reference voltage according to claim 5, characterized in that: The voltage margin control unit further includes a signal shaping unit including a trigger, a first inverter and a second inverter; The input terminal of the trigger is connected to the second output node and receives the bandgap reference establishment signal BG_S, and the output terminal of the trigger is connected to the input terminal of the first inverter and generates a first logic level signal; The output terminal of the first inverter is connected to the input terminal of the second inverter and generates a second logic level signal, and the output terminal of the second inverter generates an output signal BG_OK.

9. The detection circuit based on bandgap reference voltage according to claim 8, characterized in that: The voltage margin control unit further includes a current compensation unit; The current compensation unit is connected to the second current copy unit and the output end of the first inverter in the signal shaping unit, and is connected to the power supply voltage. The current compensation unit is used to generate a compensation current based on the second logic level signal.

10. The detection circuit based on bandgap reference voltage according to claim 9, characterized in that: The current compensation unit includes a ninth MOS transistor and a tenth MOS transistor; wherein, The first end of the ninth MOS transistor is connected to the power supply voltage, the control end of the ninth MOS transistor is connected to the second current replication unit, and the second end of the ninth MOS transistor is connected to the first end of the tenth MOS transistor; The control end of the tenth MOS transistor is connected to the output end of the first inverter, and the second end of the tenth MOS transistor is connected to the first end of the eighth MOS transistor.

11. The detection circuit based on bandgap reference voltage according to claim 8, characterized in that: The signal shaping unit also includes an RC delay unit; The RC delay unit is connected between the output terminal of the trigger and the reference potential, and is used to perform delay processing on the first logic level signal.

12. The detection circuit based on bandgap reference voltage according to claim 1, characterized in that: The detection circuit also includes a power-on protection unit; The power-on protection unit is connected between the second output node and the reference potential and is connected to the startup circuit, and is used to pull down the voltage on the second output node to the first level after the startup circuit is powered on.

13. The detection circuit based on bandgap reference voltage according to claim 12, characterized in that: The power-on protection unit includes an eleventh MOS transistor, a first end of the eleventh MOS transistor is connected to the reference potential, a control end of the eleventh MOS transistor is connected to the startup circuit, and a second end of the eleventh MOS transistor is connected to the second output node.

14. A bandgap reference voltage circuit, characterized in that: The bandgap reference voltage circuit comprises: A bandgap reference voltage generating circuit is connected between the power supply voltage and the reference potential and is used to generate a bandgap reference voltage at the first output node. ; A startup circuit is connected between the power supply voltage and the reference potential, and is connected to the first output node and the control terminal of the first MOS transistor in the bandgap reference voltage generating circuit, for starting the bandgap reference voltage generating circuit; A detection circuit, the detection circuit comprising: a voltage-limited startup control unit, connected between the power supply voltage and the reference potential, and connected to the control terminal of the first MOS transistor in the bandgap reference voltage generating circuit, and configured to mirror the current flowing through the first MOS transistor to generate a first current when the power supply voltage is powered up to a first voltage threshold; A voltage margin control unit is connected to the voltage limit start control unit and the first output node, and is used to generate a voltage margin control unit based on the first current and the bandgap reference voltage when the power supply voltage is powered up to the second voltage threshold. A bandgap reference setup signal BG_S is generated at the second output node, and the second voltage threshold is greater than the first voltage threshold.

15. The bandgap reference voltage circuit according to claim 14, wherein: The startup circuit includes a pull-up resistor, a control tube and a current mirror unit. The first end of the pull-up resistor is connected to the power supply voltage, and the second end is connected to the second end of the control tube and the current mirror unit. The control end of the control tube is connected to the first output node, and the first end is connected to the reference potential. The current mirror unit is connected to the control end of the first MOS tube and the detection circuit.

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