On-chip power supply switching circuit of processor and processor

Abstract

The invention relates to an on-chip power supply switching circuit of a processor and the processor. Based on the on-chip power supply switching circuit, the on-chip power supply switching circuit can generate the high-voltage decision voltage equal to the relatively high voltage through high-voltage decision of the LDO output voltage and the standby external voltage. Wherein one of the LDO output voltage and the standby external voltage can be selected by the first PMOS tube to be gated as on-chip power supply voltage of the processor, the high-voltage decision voltage can be used for driving the first PMOS tube to be in a closed state of gating the LDO output voltage, and the high-voltage decision voltage can also keep the substrate voltage of the first PMOS tube as the highest voltage in a device. According to the technical scheme, the first PMOS transistor is completely closed in the closed state, so that the phenomenon of electric leakage from the output voltage of the LDO to the standby external voltage is inhibited, and then the stability of the LDO when providing on-chip power supply for the processor can be considered under the condition that the standby external voltage is used for improving the reliability of on-chip power supply.

Description

Technical Field

[0001] The present application relates to power supply technology, and in particular to an on-chip power supply switching circuit of a processor, and a processor. Background Art

[0002] The on-chip load of the processor has various power supply requirements. For example, the on-chip load of the processor may include an I / O circuit and a core, and the I / O voltage required by the I / O circuit may be higher than the core voltage required by the core. Therefore, the external power supply voltage received by the processor is usually a high voltage that can meet all power supply requirements. Among them, in order to meet the low voltage requirement of the processor that is lower than the external power supply voltage, the processor usually uses an LDO (Low Dropout Regulator) to step down the external power supply voltage. The LDO can generate a stable output voltage by stepping down the external power supply voltage, and the output voltage generated by the LDO can be adapted and adjusted according to the requirements of the target on-chip load (such as the core voltage), so that the target on-chip load can work in a better state when the output voltage generated by the LDO is used as the on-chip power supply voltage.

[0003] If the processor's on-chip power supply relies only on LDO, then when an abnormality occurs in LDO, the processor's target on-chip load will not work properly. Therefore, the reliability of relying solely on LDO to provide on-chip power supply for the processor is not high. In order to improve the reliability of the processor's on-chip power supply, the relevant technology attempts to introduce an additional backup external voltage for the processor. The backup external voltage can be lower than the external power supply voltage. The backup external voltage is a fixed value used to keep the target on-chip load in a basic working state. Moreover, the backup external voltage can replace the output voltage of the LDO as the on-chip power supply voltage of the target on-chip load when the LDO is abnormal.

[0004] However, in the case where the processor additionally introduces a backup external voltage, if the output voltage generated by the LDO during normal operation is adjusted to be greater than the backup external voltage, leakage from the LDO to the backup external voltage may occur, and the leakage phenomenon may cause the output voltage of the LDO to be unstable, thereby causing the stability of the on-chip power supply provided by the processor using the LDO to be low.

[0005] As can be seen above, it is difficult for the processor's on-chip power supply to simultaneously take into account reliability and stability. Summary of the invention

[0006] The embodiments of the present application provide an on-chip power supply switching circuit for a processor and a processor, which help to ensure that the on-chip power supply of the processor can have both reliability and stability.

[0007] In one embodiment of the present application, an on-chip power supply switching circuit of a processor is provided, comprising: A high-voltage decision circuit, the high-voltage decision circuit having a first decision input terminal, a second decision input terminal and a high-voltage decision output terminal, the first decision input terminal receiving an LDO output voltage generated by an LDO in the processor, the second decision input terminal receiving a standby external voltage of the processor, the high-voltage decision output terminal being used to generate a high-voltage decision voltage, the LDO output voltage being adjustable, and the high-voltage decision voltage being set to a relatively higher high voltage between the LDO output voltage and the standby external voltage; a first PMOS transistor, the first PMOS transistor having a gate, and a first electrode and a second electrode respectively located at opposite sides of a substrate channel, the first electrode of the first PMOS transistor being used to connect to a target on-chip load in the processor, the first electrode of the first PMOS transistor receiving the LDO output voltage, the second electrode of the first PMOS transistor receiving the standby external voltage, and the substrate voltage of the first PMOS transistor being normally set to the high-voltage decision voltage; A switching execution circuit, wherein the switching execution circuit is used for: When the LDO is normally enabled, the gate voltage of the first PMOS tube is set to the high-voltage decision voltage, so that the LDO output voltage is gated as the on-chip power supply voltage for the target on-chip load; When an abnormality occurs in the LDO, the gate voltage of the first PMOS tube is set to a pull-down voltage, so that the on-chip power supply voltage is switched from the LDO output voltage to the standby external voltage.

[0008] In some examples, optionally, the high-voltage decision circuit has a competition interlock loop, and the competition interlock loop is used to: when the LDO output voltage is higher than the standby external voltage, connect the first decision input terminal with the high-voltage decision output terminal, and disconnect the second decision input terminal with the high-voltage decision output terminal, so that the high-voltage decision voltage is set to the relatively higher LDO output voltage between the LDO output voltage and the standby external voltage; when the LDO output voltage is lower than the standby external voltage, connect the second decision input terminal with the high-voltage decision output terminal, and disconnect the first decision input terminal with the high-voltage decision output terminal, so that the high-voltage decision voltage is set to the relatively higher standby external voltage between the LDO output voltage and the standby external voltage; when the LDO output voltage is equal to the standby external voltage, maintain the conduction state currently formed between the first decision input terminal or the second decision input terminal and the high-voltage decision output terminal.

[0009] In some examples, optionally, the competition interlock loop includes a second PMOS tube and a third PMOS tube, wherein: the second PMOS tube is located between the first decision input terminal and the high-voltage decision output terminal; the third PMOS tube is located between the second decision input terminal and the high-voltage decision output terminal; the second PMOS tube is turned on when the LDO output voltage is higher than the standby external voltage, and the second PMOS tube is turned off when the standby external voltage is lower than the LDO output voltage; the third PMOS tube is turned on when the standby external voltage is higher than the LDO output voltage, and the second PMOS tube is turned off when the LDO output voltage is lower than the standby external voltage; the second PMOS tube and the third PMOS tube maintain the current on or off state when the LDO output voltage is equal to the standby external voltage.

[0010] In some examples, optionally, the source of the second PMOS tube is connected to the first decision input terminal, the drain of the second PMOS tube is connected to the high-voltage decision output terminal, and the gate of the second PMOS tube is connected to the second decision input terminal; the source of the third PMOS tube is connected to the second decision input terminal, the drain of the third PMOS tube is connected to the high-voltage decision output terminal, and the gate of the third PMOS tube is connected to the first decision input terminal.

[0011] In some examples, optionally, the switching execution circuit uses a control signal to switch and control the gate voltage of the first PMOS tube, wherein the signal level of the control signal is configured as follows: when the LDO is normally enabled, the gate of the first PMOS tube is connected to the high-voltage judgment output terminal, so that the gate voltage of the first PMOS tube is set to the high-voltage judgment voltage; when the LDO is abnormal, the gate of the first PMOS tube is grounded, so that the gate voltage of the first PMOS tube is set to the pull-down voltage with the same potential as the ground level.

[0012] In some examples, optionally, the control signal is generated by a power management module in the processor, and the power management module is independent of the target on-chip load.

[0013] In some examples, optionally, the switching execution circuit includes a first NMOS tube and a second NMOS tube, the first NMOS tube is connected between the gate of the first PMOS tube and the high-voltage judgment output terminal, and the second NMOS tube is connected between the gate of the first PMOS tube and ground; the control signal includes a first control signal and a second control signal with opposite signal levels, wherein: the signal level of the first control signal is configured to: turn on the first NMOS tube when the LDO is normally enabled, and, turn off the first NMOS tube when an abnormality occurs in the LDO; the signal level of the second control signal is configured to: turn off the second NMOS tube when the LDO is normally enabled, and, turn on the second NMOS tube when an abnormality occurs in the LDO.

[0014] In some examples, optionally, the drain of the first NMOS tube is connected to the high-voltage judgment output terminal, the source of the first NMOS tube is connected to the gate of the first PMOS tube, the substrate voltage of the first NMOS tube is set to the ground level, and the gate of the first NMOS tube receives the first control signal; the signal level of the first control signal is set to the ground level when the LDO is normally enabled to turn on the first NMOS tube; and the signal level of the first control signal is set to the reference level when an abnormality occurs in the LDO to turn off the first NMOS tube; the drain of the second NMOS tube is connected to the gate of the first PMOS tube, the source of the second NMOS tube is grounded, the substrate voltage of the second NMOS tube is set to the ground level, and the gate of the second NMOS tube receives the second control signal; the signal level of the second control signal is set to the reference level when the LDO is normally enabled to turn off the second NMOS tube; and the signal level of the second control signal is set to the ground level when an abnormality occurs in the LDO to turn on the second NMOS tube; the reference level is higher than or equal to the high-voltage judgment voltage.

[0015] In some examples, optionally, the LDO generates the LDO output voltage using an external power supply voltage of the processor; the LDO output voltage and the backup external voltage are both lower than the external power supply voltage; and the reference level is at the same potential as the external power supply voltage.

[0016] In another embodiment of the present application, a processor is provided, comprising the on-chip power supply switching circuit as described in the above embodiment.

[0017] Based on the above embodiments of the present application, the on-chip power supply switching circuit can generate a high-voltage judgment voltage equal to a relatively high high voltage by making a high-voltage judgment on the LDO output voltage and the standby external voltage. Wherein, the LDO output voltage and the standby external voltage can be respectively selected as the on-chip power supply voltage of the processor when the first PMOS tube is turned off and turned on, and the high-voltage judgment voltage can be used to drive the first PMOS tube to be in a closed state of gating the LDO output voltage as the on-chip power supply voltage, and the high-voltage judgment voltage can also be applied to the substrate of the first PMOS tube. Thus, by keeping the substrate voltage of the first PMOS tube as the highest voltage in the device when the first PMOS tube is turned off, the forward bias conduction of the first PMOS tube when the LDO output voltage is greater than the standby external voltage can be suppressed, so that the off state of the first PMOS tube is completely closed, thereby suppressing the leakage of the LDO output voltage to the standby external voltage, and further, the stability of the LDO when providing on-chip power supply to the processor can be taken into account while using the standby external voltage to improve the reliability of the on-chip power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following drawings are only used to illustrate and explain the present application, and do not limit the scope of the present application: Figure 1 A schematic diagram of the LDO leaking current to the backup external voltage; Figure 2 is an exemplary structural diagram of an on-chip power supply switching circuit of a processor in an embodiment of the present application; Figure 3 Schematic diagram of an example structure of a high-voltage decision circuit in an on-chip power supply switching circuit in an embodiment of the present application; Figure 4 It is a schematic diagram of an example structure of a switching execution circuit in an on-chip power supply switching circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and examples.

[0020] Figure 1 Schematic diagram of LDO leakage to backup external voltage. Figure 1 , the processor may include an LDO, and in order to improve the reliability of the on-chip power supply provided by the LDO to the processor, the processor may also introduce a backup external voltage VDDC. In this case, the processor may also include a switch tube 10, and the switch tube 10 is used to provide on-chip power supply for the target on-chip load (such as the core) of the processor by switching the LDO output voltage V_LDO generated by the LDO and the backup external voltage VDDC.

[0021] Specifically, the switch tube 10 can be a PMOS (P-Metal Oxide Semiconductor) tube, the standby external voltage VDDC can be connected to the source of the PMOS tube 10, the LDO can have an input end for receiving the external power supply voltage VDDH, and an output end for generating the LDO output voltage V_LDO, the output end of the LDO is connected to the drain of the PMOS tube 10, and the drain of the PMOS tube 10 is connected to the target on-chip load of the processor.

[0022] Based on the above structure, the gate of the PMOS tube 10 is controlled by the switching control signal Sig_sw0. For example, the switching control signal Sig_sw0 can be generated by the power management module of the processor, wherein: When the LDO can supply power normally, the switching control signal Sig_sw0 is set to a high level, so that the gate-source voltage difference Vgs of the PMOS tube 10 is lower than the threshold voltage. At this time, the PMOS tube 10 is turned off, so that the LDO output voltage V_LDO is transmitted from the drain of the PMOS tube 10 to the target on-chip load of the processor as the on-chip power supply voltage; When an abnormality occurs in the LDO, the switching control signal Sig_sw0 is set to a low level, so that the gate-source voltage difference Vgs of the PMOS tube 10 is greater than the threshold voltage. At this time, the PMOS tube 10 is turned on, so that the standby external voltage VDDC connected to the source replaces the LDO output voltage V_LDO as the on-chip power supply voltage and is transmitted from the drain of the PMOS tube 10 to the target on-chip load of the processor.

[0023] If the PMOS tube 10 uses a high-voltage device, that is, the threshold voltage of the PMOS tube 10 is adapted to or close to the external power supply voltage VDDH, then the gate-source voltage difference Vgs formed when the switching control signal Sig_sw0 is set to a low level is equal to the standby external voltage VDDC and is less than the external power supply voltage VDDH. At this time, it is possible that the PMOS tube 10 cannot be fully turned on, and the PMOS tube 10 that cannot be fully turned on cannot fully provide the standby external voltage VDDC to the target on-chip load of the processor. Therefore, in order to ensure the reliability of the on-chip power supply of the standby external voltage VDDC, the PMOS tube 10 preferably uses a low-voltage device, that is, the threshold voltage of the PMOS tube 10 is adapted to or close to the standby external voltage VDDC.

[0024] In the case where the PMOS tube 10 uses a low-voltage device, the anti-leakage capability of the PMOS tube 10 is relatively weak, and if the LDO output voltage V_LDO is adjusted to be greater than the standby external voltage VDDC, the drain voltage of the PMOS tube 10 is higher than the source voltage. At this time, since the substrate and the source of the PMOS tube 10 are at the same potential, the source voltage and the substrate potential of the PMOS tube 10 are lower than the drain voltage, thereby sending a forward bias conduction from the drain through the substrate to the source, and then, the LDO output voltage V_LDO leaks to the standby external voltage VDDC through the forward-biased PMOS tube 10.

[0025] Based on the above analysis, the embodiments of the present application can improve the reliability of the on-chip power supply by using the backup external voltage VDDC, by suppressing the forward bias conduction of the PMOS tube 10 when the LDO output voltage V_LDO is greater than the backup external voltage VDDC, thereby avoiding the leakage of the LDO output voltage V_LDO to the backup external voltage VDDC, thereby taking into account the stability of the LDO when providing on-chip power supply for the processor.

[0026] Figure 2 Schematic diagram of an exemplary structure of an on-chip power supply switching circuit of a processor in an embodiment of the present application. Figure 2 In an embodiment of the present application, the on-chip power supply switching circuit of the processor may include a high-voltage decision circuit 30 , a first PMOS tube 50 , and a switching execution circuit 70 .

[0027] Exemplarily, in an embodiment of the present application, the high-voltage decision circuit 30 may have a first decision input terminal, a second decision input terminal and a high-voltage decision output terminal, the first decision input terminal of the high-voltage decision circuit 30 receives the LDO output voltage V_LDO generated by the LDO in the processor, the second decision input terminal of the high-voltage decision circuit 30 receives the backup external voltage VDDC of the processor, and the high-voltage decision output terminal of the high-voltage decision circuit 30 is used to generate a high-voltage decision voltage.

[0028] Illustratively, in an embodiment of the present application, the LDO may utilize the external power supply voltage VDDH of the processor to generate the LDO output voltage V_LDO, and both the LDO output voltage V_LDO and the standby external voltage VDDC may be lower than the external power supply voltage VDDH.

[0029] Exemplarily, in an embodiment of the present application, the external power supply voltage VDDH can be applicable to the I / O circuit in the on-chip load of the processor, that is, the external power supply voltage VDDH can be used as the I / O voltage of the I / O circuit, for example, the external power supply voltage VDDH can be 1.8V.

[0030] Exemplarily, in an embodiment of the present application, the LDO output voltage V_LDO and the backup external voltage can be applicable to the core in the on-chip load of the processor, that is, the target on-chip load of the processor can include the core, and the LDO output voltage V_LDO and the backup external voltage can be used as the core voltage when serving as the on-chip power supply voltage, for example, the LDO output voltage V_LDO can be adjusted within a range less than 1.8V, and the backup external voltage VDDC can be 0.75V.

[0031] Exemplarily, in an embodiment of the present application, the LDO output voltage V_LDO is adjustable, and the standby external voltage VDDC can be a fixed value, therefore, there may be different situations where the LDO output voltage V_LDO is higher, equal to, or lower than the standby external voltage VDDC, so that the high-voltage decision voltage V_high can be set by the high-voltage decision circuit 30 to a relatively high voltage between the LDO output voltage V_LDO and the standby external voltage VDDC, and when the LDO output voltage V_LDO is equal to the standby external voltage VDDC, the LDO output voltage V_LDO is equal to any one of the standby external voltages VDDC, which can be regarded as a relatively high voltage between the LDO output voltage V_LDO and the standby external voltage VDDC. That is, the high-voltage decision circuit 30 can adaptively set the high-voltage decision voltage V_high to a relatively high voltage between the LDO output voltage V_LDO and the standby external voltage VDDC.

[0032] Illustratively, in an embodiment of the present application, the first PMOS tube 50 has a gate, and a first electrode and a second electrode respectively located on opposite sides of a substrate channel, that is, one of the first electrode and the second electrode of the first PMOS tube 50 can be a source, and the other electrode can be a drain, and the first PMOS tube 50 can preferably use the low-voltage device described above.

[0033] Exemplarily, in an embodiment of the present application, the first pole of the first PMOS tube 50 is used to connect to the target on-chip load in the processor, the first pole of the first PMOS tube 50 receives the LDO output voltage V_LDO, the second pole of the first PMOS tube 50 receives the backup external voltage VDDC, and the substrate voltage of the first PMOS tube 50 is normally set to the high-voltage decision voltage V_high.

[0034] Exemplarily, in an embodiment of the present application, the switching execution circuit 70 may be used to: When the LDO is normally enabled, the gate voltage of the first PMOS tube 50 is set to the high-voltage decision voltage V_high, so that the LDO output voltage V_LDO is gated as the on-chip power supply voltage for the target on-chip load (for example, the core of the processor); that is, the gate voltage of the first PMOS tube 50 is set to the high-voltage decision voltage V_high, so that the first PMOS tube 50 can be turned off when its substrate voltage is at the highest voltage in the device, and the highest voltage in the device refers to the highest voltage among all device internal voltages including the gate voltage, the first electrode voltage, the second electrode voltage and the substrate voltage in the first PMOS tube 50, and the closing of the first PMOS tube 50 can be used to gate the LDO output voltage V_LDO as the on-chip power supply voltage for the target on-chip load (for example, the core of the processor); When an abnormality occurs in the LDO, the gate voltage of the first PMOS tube 50 is set to a pull-down voltage (for example, a low voltage with the same potential as the ground potential), so that the on-chip power supply voltage is switched from the LDO output voltage V_LDO to the standby external voltage VDDC; that is, the gate voltage of the first PMOS tube 50 is set to a pull-down voltage so that the first PMOS tube 50 can be turned on, and the conduction of the first PMOS tube 50 is used to switch the on-chip power supply voltage from the LDO output voltage V_LDO to the standby external voltage VDDC.

[0035] Exemplarily, in an embodiment of the present application, if the LDO output voltage V_LDO is higher than the standby external voltage VDDC, the high-voltage decision voltage V_high is the LDO output voltage V_LDO, that is, the high-voltage decision voltage V_high is equal to the LDO output voltage V_LDO, and when the switching execution circuit 70 sets the gate voltage of the first PMOS tube 50 to the high-voltage decision voltage V_high (that is, when the LDO is normally enabled): The first electrode voltage and substrate voltage of the first PMOS tube 50 are equal, that is, the first electrode voltage and substrate voltage of the first PMOS tube 50 are both the high-voltage decision voltage V_high equal to the LDO output voltage V_LDO. At this time, the first electrode of the first PMOS tube 50 receiving the LDO output voltage V_LDO can be regarded as the source of the first PMOS tube 50, and the second electrode of the first PMOS tube 50 receiving the standby external voltage VDDC can be regarded as the drain of the first PMOS tube 50; The first electrode voltage (e.g., source voltage) and the gate voltage of the first PMOS tube 50 are equal, that is, the first electrode voltage (e.g., source voltage) and the gate voltage of the first PMOS tube 50 are both the high-voltage judgment voltage V_high equal to the LDO output voltage V_LDO. At this time, the gate-source voltage difference Vgs of the first PMOS tube 50 is less than the threshold voltage of the first PMOS tube, so that the first PMOS tube 50 is turned off; The second electrode voltage (for example, drain voltage) of the first PMOS tube 50 is a standby external voltage VDDC which is currently lower than the high voltage judgment voltage V_high. Therefore, the substrate voltage of the first PMOS tube 50 is also higher than the second electrode voltage (for example, drain voltage) of the first PMOS tube 50. Thus, the substrate voltage of the first PMOS tube 50 is at the highest potential of the first PMOS tube 50 when the first PMOS tube 50 is turned off, so as to ensure that the first PMOS tube 50 is completely turned off.

[0036] Exemplarily, in an embodiment of the present application, if the LDO output voltage V_LDO is lower than the standby external voltage VDDC, the high-voltage decision voltage V_high is the standby external voltage VDDC, that is, the high-voltage decision voltage V_high and the standby external voltage VDDC, and when the switching execution circuit 70 sets the gate voltage of the first PMOS tube 50 to the high-voltage decision voltage V_high (that is, when the LDO is normally enabled): The first electrode voltage and substrate voltage of the first PMOS tube 50 are equal, that is, the first electrode voltage and substrate voltage of the first PMOS tube 50 are both the high-voltage decision voltage V_high equal to the standby external voltage VDDC. At this time, the second electrode of the first PMOS tube 50 receiving the standby external voltage VDDC can be regarded as the source of the first PMOS tube 50, and the first electrode of the first PMOS tube 50 receiving the LDO output voltage V_LDO can be regarded as the drain of the first PMOS tube 50; The second electrode voltage (e.g., source voltage) and the gate voltage of the first PMOS tube 50 are equal, that is, the second electrode voltage (e.g., source voltage) and the gate voltage of the first PMOS tube 50 are both the high-voltage decision voltage V_high equal to the standby external voltage VDDC. At this time, the gate-source voltage difference Vgs of the first PMOS tube 50 is less than the threshold voltage of the first PMOS tube, so that the first PMOS tube 50 is turned off; The first electrode voltage (for example, drain voltage) of the first PMOS tube 50 is the LDO output voltage V_LDO which is currently lower than the high-voltage judgment voltage V_high. Therefore, the substrate voltage of the first PMOS tube 50 is also higher than the first electrode voltage (for example, drain voltage) of the first PMOS tube 50. Therefore, the substrate voltage of the first PMOS tube 50 is at the highest potential of the first PMOS tube 50 when the first PMOS tube 50 is turned off, so as to ensure that the first PMOS tube 50 is completely turned off.

[0037] Exemplarily, in an embodiment of the present application, if the LDO output voltage V_LDO is equal to the standby external voltage VDDC, then the LDO output voltage V_LDO is equal to any one of the standby external voltages VDDC, which can be regarded as a relatively higher voltage between the LDO output voltage V_LDO and the standby external voltage VDDC, and when the switching execution circuit 70 sets the gate voltage of the first PMOS tube 50 to the high-voltage decision voltage V_high (that is, when the LDO is normally enabled), it can still be ensured that the first PMOS tube 50 is completely turned off, just like when the LDO output voltage V_LDO is higher or lower than the standby external voltage VDDC.

[0038] Based on the above embodiments of the present application, the on-chip power supply switching circuit can generate a high-voltage decision voltage V_high equal to a relatively high high voltage by making a high-voltage decision on the LDO output voltage V_LDO and the standby external voltage VDDC. The LDO output voltage V_LDO and the standby external voltage VDDC can be respectively selected as the on-chip power supply voltage of the processor when the first PMOS tube 50 is turned off and turned on, and the high-voltage decision voltage V_high can be used to drive the first PMOS tube 50 to be in a closed state in which the LDO output voltage V_LDO is selected as the on-chip power supply voltage, and the high-voltage decision voltage V_high can also be applied to the substrate of the first PMOS tube 50. Thus, by keeping the substrate voltage of the first PMOS tube 50 as the highest voltage in the device when the first PMOS tube 50 is turned off, the forward biased conduction of the first PMOS tube 50 when the LDO output voltage V_LDO is greater than the standby external voltage VDDC can be suppressed, so that the off state of the first PMOS tube 50 is completely turned off. Furthermore, the leakage of the LDO output voltage V_LDO to the backup external voltage VDDC can be suppressed, so as to improve the reliability of the on-chip power supply by utilizing the backup external voltage VDDC while taking into account the stability of the LDO in providing on-chip power supply to the processor.

[0039] Exemplarily, in an embodiment of the present application, the high voltage decision circuit 30 may have a competition interlocking loop, and the competition interlocking loop is used to: When the LDO output voltage V_LDO is higher than the standby external voltage VDDC, the first decision input terminal of the high voltage decision circuit 30 is connected to the high voltage decision output terminal of the high voltage decision circuit 30, and the second decision input terminal of the high voltage decision circuit 30 is disconnected from the high voltage decision output terminal of the high voltage decision circuit 30, so that the high voltage decision voltage V_high is set to the relatively higher LDO output voltage V_LDO between the LDO output voltage V_LDO and the standby external voltage VDDC; When the LDO output voltage V_LDO is lower than the standby external voltage VDDC, the second decision input terminal of the high voltage decision circuit 30 is connected to the high voltage decision output terminal of the high voltage decision circuit 30, and the first decision input terminal of the high voltage decision circuit 30 is disconnected from the high voltage decision output terminal of the high voltage decision circuit 30, so that the high voltage decision voltage V_high is set to the relatively higher standby external voltage VDDC between the LDO output voltage V_LDO and the standby external voltage VDDC; When the LDO output voltage V_LDO is equal to the standby external voltage VDDC, the conduction state currently formed between the first decision input terminal of the high-voltage decision circuit 30 or the second decision input terminal of the high-voltage decision circuit 30 and the high-voltage decision output terminal of the high-voltage decision circuit 30 is maintained.

[0040] Figure 3 This is a schematic diagram of an example structure of a high voltage decision circuit in an on-chip power supply switching circuit in an embodiment of the present application. Figure 3 In the embodiment of the present application, the competition interlock loop of the high voltage decision circuit 30 may include a second PMOS transistor 32 and a third PMOS transistor 33. Preferably, the second PMOS transistor 32 and the third PMOS transistor 33 may be low voltage devices as described above.

[0041] Exemplarily, in an embodiment of the present application, the second PMOS tube 32 can be located between the first decision input terminal of the high-voltage decision circuit 30 for receiving the LDO output voltage V_LDO, and the high-voltage decision output terminal of the high-voltage decision circuit 30 for generating the high-voltage decision voltage V_high, and the third PMOS tube 33 can be located between the second decision input terminal of the high-voltage decision circuit 30 for receiving the standby external voltage VDDC, and the high-voltage decision output terminal of the high-voltage decision circuit 30 for generating the high-voltage decision voltage V_high, and the second PMOS tube 32 and the third PMOS tube 33 can be selectively turned on so that the high-voltage decision voltage V_high can adaptively maintain a relatively higher high voltage between the LDO output voltage V_LDO and the standby external voltage VDDC according to the change in the relative relationship between the LDO output voltage V_LDO and the standby external voltage VDDC.

[0042] Exemplarily, in an embodiment of the present application, the second PMOS tube 32 can be turned on when the LDO output voltage V_LDO is higher than the standby external voltage VDDC, and the second PMOS tube 32 can be turned off when the standby external voltage VDDC is lower than the LDO output voltage V_LDO, so that the first decision input terminal of the high-voltage decision circuit 30 is turned on and the high-voltage decision output terminal of the high-voltage decision circuit 30 is turned on, and the second decision input terminal of the high-voltage decision circuit 30 is disconnected from the high-voltage decision output terminal of the high-voltage decision circuit 30, and thus, the high-voltage decision voltage V_high is set to the relatively higher LDO output voltage V_LDO between the LDO output voltage V_LDO and the standby external voltage VDDC.

[0043] Exemplarily, in an embodiment of the present application, the third PMOS tube 33 can be turned on when the standby external voltage VDDC is higher than the LDO output voltage V_LDO, and the second PMOS tube 32 can be turned off when the LDO output voltage V_LDO is lower than the standby external voltage VDDC, so that the second decision input terminal of the high-voltage decision circuit 30 is turned on and the high-voltage decision output terminal of the high-voltage decision circuit 30 is turned on, and the first decision input terminal of the high-voltage decision circuit 30 is disconnected from the high-voltage decision output terminal of the high-voltage decision circuit 30, and thus, the high-voltage decision voltage V_high is set to the relatively higher standby external voltage VDDC between the LDO output voltage V_LDO and the standby external voltage VDDC.

[0044] Exemplarily, in an embodiment of the present application, the second PMOS tube 32 and the third PMOS tube 33 can maintain the current on or off state when the LDO output voltage V_LDO is equal to the standby external voltage VDDC, so as to maintain the on state currently formed at the first decision input terminal of the high-voltage decision circuit 30 or the second decision input terminal of the high-voltage decision circuit 30 and the high-voltage decision output terminal of the high-voltage decision circuit 30.

[0045] Exemplarily, in an embodiment of the present application, the drain of the second PMOS tube 32 can be connected to the first decision input terminal of the high-voltage decision circuit 30 for receiving the LDO output voltage V_LDO, the source of the second PMOS tube 32 can be connected to the high-voltage decision output terminal of the high-voltage decision circuit 30 for generating the high-voltage decision voltage V_high, and the gate of the second PMOS tube 32 can be connected to the second decision input terminal of the high-voltage decision circuit 30 for receiving the standby external voltage VDDC, so that: the second PMOS tube 32 is turned on when the LDO output voltage V_LDO is higher than the standby external voltage VDDC, is turned off when the LDO output voltage V_LDO is lower than the standby external voltage VDDC, and is turned on or off when the LDO output voltage V_LDO is equal to the standby external voltage VDDC.

[0046] Exemplarily, in an embodiment of the present application, the drain of the third PMOS tube 33 can be connected to the second decision input terminal of the high-voltage decision circuit 30 for receiving the standby external voltage VDDC. For example, a protective element such as an ESD (Electro-Static discharge) resistor can be connected in series between the drain of the third PMOS tube 33 and the second decision input terminal. The source of the third PMOS tube 33 can be connected to the high-voltage decision output terminal of the high-voltage decision circuit 30 for generating the high-voltage decision voltage V_high, and the gate of the third PMOS tube 33 can be connected to the first decision input terminal of the high-voltage decision circuit 30 for receiving the LDO output voltage V_LDO, so that: the third PMOS tube 33 is turned on when the standby external voltage VDDC is higher than the LDO output voltage V_LDO, is turned off when the standby external voltage VDDC is lower than the LDO output voltage V_LDO, and is turned on or off when the standby external voltage VDDC is equal to the LDO output voltage V_LDO.

[0047] Exemplarily, in an embodiment of the present application, the switching execution circuit 70 can utilize a control signal to switch and control the gate voltage of the first PMOS tube 50. For example, the control signal received by the switching execution circuit 70 can be generated by a power management module in the processor, and the power management module in the processor can be independent of the target on-chip load.

[0048] For example, in an embodiment of the present application, the signal level of the control signal used by the switching execution circuit 70 to control the gate voltage of the first PMOS tube 50 can be configured as: When the LDO is normally enabled, the gate of the first PMOS transistor 50 is connected to the high-voltage decision output terminal of the high-voltage decision circuit 30, so that the gate voltage of the first PMOS transistor 50 is set to the high-voltage decision voltage V_high, and then the substrate voltage of the first PMOS transistor 50 is turned off (that is, completely turned off) in the state of the highest voltage in the device, so that the LDO output voltage V_LDO is selected as the on-chip power supply voltage for the target on-chip load (such as the core of the processor); When an abnormality occurs in the LDO, the gate of the first PMOS tube 50 is grounded, so that the gate voltage of the first PMOS tube 50 is set to a pull-down voltage with the same potential as the ground level Vss, and then the first PMOS tube 50 is turned on to switch the on-chip power supply voltage from the LDO output voltage V_LDO to the backup external voltage VDDC.

[0049] Figure 4 Schematic diagram of an example structure of a switching execution circuit in an on-chip power supply switching circuit in an embodiment of the present application. Figure 4In an embodiment of the present application, the switching execution circuit 70 can use an NMOS (N-Metal Oxide Semiconductor) tube or a PMOS tube to perform a response operation to a control signal. Taking the example that the switching execution circuit 70 can use an NMOS tube to perform a response operation to a control signal, the switching execution circuit 70 can include a first NMOS tube 71 and a second NMOS tube 72.

[0050] Exemplarily, in an embodiment of the present application, the first NMOS tube 71 is connected between the gate of the first PMOS tube 50 and the high voltage decision output terminal of the high voltage decision circuit 30, and the second NMOS tube 72 is connected between the gate of the first PMOS tube 50 and ground.

[0051] For example, in an embodiment of the present application, the control signal for the switching execution circuit 70 to control the gate voltage of the first PMOS tube 50 may include a first control signal Sig_sw1 and a second control signal Sig_sw2 having opposite signal levels. The first control signal Sig_sw1 is used to control the first NMOS tube 71, and the second control signal Sig_sw2 may be used to control the second NMOS tube 72.

[0052] Exemplarily, in an embodiment of the present application, the signal level of the first control signal Sig_sw1 may be configured as: When the LDO is normally enabled, the first NMOS transistor 71 is turned on to connect the gate of the first PMOS transistor 50 to the high-voltage decision output terminal of the high-voltage decision circuit 30, so that the gate voltage of the first PMOS transistor 50 is set to the high-voltage decision voltage V_high, and then the substrate voltage of the first PMOS transistor 50 is turned off (that is, completely turned off) in the state of the highest voltage in the device, so that the LDO output voltage V_LDO is selected as the on-chip power supply voltage for the target on-chip load (such as the core of the processor); and, When an abnormality occurs in the LDO, the first NMOS transistor 71 is turned off to disconnect the gate of the first PMOS transistor 50 from the high voltage decision output terminal of the high voltage decision circuit 30 .

[0053] Exemplarily, in an embodiment of the present application, the signal level of the second control signal Sig_sw2 may be configured as: When the LDO is normally enabled, the second NMOS transistor 72 is turned off to disconnect the ground connection of the gate of the first PMOS transistor 50; and, When an abnormality occurs in the LDO, the second NMOS tube 72 is turned on to ground the gate of the first PMOS tube 50, so that the gate voltage of the first PMOS tube 50 is set to a pull-down voltage with the same potential as the ground level Vss, and then the first PMOS tube 50 is turned on to switch the on-chip power supply voltage from the LDO output voltage V_LDO to the backup external voltage VDDC.

[0054] For example, in an embodiment of the present application, the drain of the first NMOS tube 71 can be connected to the high voltage decision output terminal of the high voltage decision circuit 30, the source of the first NMOS tube 71 can be connected to the gate of the first PMOS tube 50, the substrate voltage of the first NMOS tube 71 can be set to the ground level Vss, and the gate of the first NMOS tube 71 receives the first control signal Sig_sw1. In this case: The signal level of the first control signal Sig_sw1 may be set to the ground level Vss when the LDO is normally enabled, so as to turn on the first NMOS tube 71; and, When an abnormality occurs in the LDO, the signal level of the first control signal Sig_sw1 may be set to a reference level to turn off the first NMOS transistor 71 .

[0055] For example, in an embodiment of the present application, the drain of the second NMOS tube 72 may be connected to the gate of the first PMOS tube 50, the source of the second NMOS tube 72 may be grounded, the substrate voltage of the second NMOS tube 72 may be set to the ground level Vss, and the gate of the second NMOS tube 72 receives the second control signal Sig_sw2. In this case: The signal level of the second control signal Sig_sw2 can be set to a reference level when the LDO is normally enabled to turn off the second NMOS tube 72; and, When an abnormality occurs in the LDO, the signal level of the second control signal Sig_sw2 can be set to the ground level Vss to turn on the second NMOS tube 72; For example, in an embodiment of the present application, the reference levels of the first control signal Sig_sw1 and the second control signal Sig_sw2 may be higher than or equal to the high voltage decision voltage V_high, so as to ensure that the gate voltages of the first NMOS tube 71 and the second NMOS tube 72 may be greater than the high voltage decision voltage V_high, thereby ensuring that the first NMOS tube 71 and the second NMOS tube 72 can reach a fully turned-on state when turned on. In this case, the first NMOS tube and the second NMOS tube are preferably high voltage devices as described above.

[0056] For example, in an embodiment of the present application, the reference levels of the first control signal Sig_sw1 and the second control signal Sig_sw2 may be at the same potential as the external power supply voltage VDDH (eg, I / O voltage) of the processor.

[0057] In another embodiment of the present application, a processor is provided, comprising the on-chip power supply switching circuit as described in the above embodiment.

[0058] Exemplarily, in the embodiments of the present application, the processor may be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural Network Processing Unit), a DPU (Deeplearning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit). The above description of the processor type in the embodiments of the present application is intended to express that the implementation of the embodiments of the present application may not be limited by the processor type.

[0059] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A processor on-chip power supply switching circuit, It is characterized in that include: A high-voltage decision circuit, the high-voltage decision circuit having a first decision input terminal, a second decision input terminal and a high-voltage decision output terminal, the first decision input terminal receiving an LDO output voltage generated by an LDO in the processor, the second decision input terminal receiving a standby external voltage of the processor, the high-voltage decision output terminal being used to generate a high-voltage decision voltage, the LDO output voltage being adjustable, and the high-voltage decision voltage being set to a relatively higher high voltage between the LDO output voltage and the standby external voltage; a first PMOS transistor, the first PMOS transistor having a gate, and a first electrode and a second electrode respectively located at opposite sides of a substrate channel, the first electrode of the first PMOS transistor being used to connect to a target on-chip load in the processor, the first electrode of the first PMOS transistor receiving the LDO output voltage, the second electrode of the first PMOS transistor receiving the standby external voltage, and the substrate voltage of the first PMOS transistor being normally set to the high-voltage decision voltage; A switching execution circuit, wherein the switching execution circuit is used for: When the LDO is normally enabled, the gate voltage of the first PMOS tube is set to the high-voltage decision voltage, so that the LDO output voltage is gated as the on-chip power supply voltage of the target on-chip load; When an abnormality occurs in the LDO, the gate voltage of the first PMOS tube is set to a pull-down voltage, so that the on-chip power supply voltage is switched from the LDO output voltage to the standby external voltage.

2. The on-chip power supply switching circuit according to claim 1, It is characterized in that The high-voltage decision circuit has a competition interlocking loop, and the competition interlocking loop is used for: When the LDO output voltage is higher than the standby external voltage, the first decision input terminal is connected to the high-voltage decision output terminal, and the second decision input terminal is disconnected from the high-voltage decision output terminal, so that the high-voltage decision voltage is set to the relatively higher LDO output voltage between the LDO output voltage and the standby external voltage; When the LDO output voltage is lower than the standby external voltage, the second decision input terminal is connected to the high-voltage decision output terminal, and the first decision input terminal is disconnected from the high-voltage decision output terminal, so that the high-voltage decision voltage is set to the relatively higher standby external voltage between the LDO output voltage and the standby external voltage; When the LDO output voltage is equal to the standby external voltage, the conduction state currently formed between the first decision input terminal or the second decision input terminal and the high-voltage decision output terminal is maintained.

3. The on-chip power supply switching circuit according to claim 2, It is characterized in that The competition interlock loop includes a second PMOS tube and a third PMOS tube, wherein: The second PMOS tube is located between the first decision input terminal and the high-voltage decision output terminal; The third PMOS tube is located between the second decision input terminal and the high-voltage decision output terminal; The second PMOS tube is turned on when the LDO output voltage is higher than the standby external voltage, and the second PMOS tube is turned off when the standby external voltage is lower than the LDO output voltage; The third PMOS transistor is turned on when the standby external voltage is higher than the LDO output voltage, and the second PMOS transistor is turned off when the LDO output voltage is lower than the standby external voltage; The second PMOS tube and the third PMOS tube maintain a current on or off state when the LDO output voltage is equal to the standby external voltage.

4. The on-chip power supply switching circuit according to claim 3, It is characterized in that The source of the second PMOS tube is connected to the first decision input terminal, the drain of the second PMOS tube is connected to the high-voltage decision output terminal, and the gate of the second PMOS tube is connected to the second decision input terminal; The source of the third PMOS tube is connected to the second decision input terminal, the drain of the third PMOS tube is connected to the high-voltage decision output terminal, and the gate of the third PMOS tube is connected to the first decision input terminal.

5. The on-chip power supply switching circuit according to claim 1, It is characterized in that The switching execution circuit switches and controls the gate voltage of the first PMOS tube using a control signal, wherein the signal level of the control signal is configured as: When the LDO is normally enabled, the gate of the first PMOS tube is connected to the high-voltage decision output terminal, so that the gate voltage of the first PMOS tube is set to the high-voltage decision voltage; When an abnormality occurs in the LDO, the gate of the first PMOS tube is grounded, so that the gate voltage of the first PMOS tube is set to the pull-down voltage with the same potential as the ground level.

6. The on-chip power supply switching circuit according to claim 5, It is characterized in that The control signal is generated by a power management module in the processor, and the power management module is independent of the target on-chip load.

7. The on-chip power supply switching circuit according to claim 5, It is characterized in that The switching execution circuit includes a first NMOS tube and a second NMOS tube, the first NMOS tube is connected between the gate of the first PMOS tube and the high-voltage judgment output terminal, and the second NMOS tube is connected between the gate of the first PMOS tube and the ground; The control signal includes a first control signal and a second control signal with opposite signal levels, wherein: The signal level of the first control signal is configured to: turn on the first NMOS tube when the LDO is normally enabled, and turn off the first NMOS tube when an abnormality occurs in the LDO; The signal level of the second control signal is configured to: turn off the second NMOS tube when the LDO is normally enabled, and turn on the second NMOS tube when an abnormality occurs in the LDO.

8. The on-chip power supply switching circuit according to claim 7, It is characterized in that The drain of the first NMOS tube is connected to the high-voltage judgment output terminal, the source of the first NMOS tube is connected to the gate of the first PMOS tube, the substrate voltage of the first NMOS tube is set to the ground level, and the gate of the first NMOS tube receives the first control signal; When the LDO is normally enabled, the signal level of the first control signal is set to the ground level to turn on the first NMOS tube; And, when an abnormality occurs in the LDO, the signal level of the first control signal is set to a reference level to turn off the first NMOS tube; The drain of the second NMOS tube is connected to the gate of the first PMOS tube, the source of the second NMOS tube is grounded, the substrate voltage of the second NMOS tube is set to the ground level, and the gate of the second NMOS tube receives the second control signal; When the LDO is normally enabled, the signal level of the second control signal is set to the reference level to turn off the second NMOS tube; And, when an abnormality occurs in the LDO, the signal level of the second control signal is set to the ground level to turn on the second NMOS tube; The reference level is higher than or equal to the high voltage decision voltage.

9. The on-chip power supply switching circuit according to claim 8, It is characterized in that The LDO generates the LDO output voltage using the external power supply voltage of the processor; The LDO output voltage and the standby external voltage are both lower than the external power supply voltage; The reference level is at the same potential as the external power supply voltage.

10. A processor, It is characterized in that The invention comprises the on-chip power supply switching circuit as claimed in any one of claims 1 to 9.

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