Control method of processor, processor and electronic equipment

Abstract

The invention discloses a processor control method, a processor and electronic equipment. The method comprises the following steps: inputting a first mantissa of first data into a first partial product generation unit in the processor, and inputting a second mantissa of second data into a second partial product generation unit; generating a first mantissa and a partial product of the first mantissa through a first partial product generation unit to obtain a first group of partial products, and generating a second mantissa and a partial product of the second mantissa through a second partial product generation unit to obtain a second group of partial products; performing addition processing on the first group of partial products through the first CSA to obtain a first carry value and a first summation value, and performing addition processing on the second group of partial products through the second CSA to obtain a second carry value and a second summation value; and processing the first index, the second index, the first carry value, the first summation value, the second carry value and the second summation value to obtain a target processing result. The technical problem that the processing efficiency of a processor in the related technology is low is solved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a processor control method, a processor, and an electronic device. Background Art

[0002] Floating-point operations are often used in neural network calculations due to their large dynamic range. Floating-point square sum operations are widely used in scenarios such as pattern recognition, filters, and vector normalization. Square sum operations are also often used in scenarios such as solving coordinate amplitudes.

[0003] In the related art, in order to perform a square sum operation on two floating-point numbers, two floating-point multipliers are usually used to perform a multiplication operation on each floating-point data, and then the multiplication results output by the floating-point multipliers are input into a floating-point adder for addition operation.

[0004] However, the above method requires, on the one hand, a first-level standard floating-point multiplication and floating-point addition unit, and the output results of the standard floating-point multiplication and addition unit need to be standardized according to the IEEE-754 protocol, resulting in a large calculation delay; on the other hand, since the floating-point number includes three parts: the sign bit, the exponent bit, and the mantissa bit, the calculation process needs to perform a large number of AND operations and addition operations, and the calculation complexity is relatively high. Affected by the above two factors, it takes a lot of time to process the operation of two floating-point numbers, which means that the processing time of the processor is increased, resulting in a technical problem of low processing efficiency of the processor.

[0005] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0006] The embodiments of the present application provide a method for controlling a processor, a processor, and an electronic device, so as to at least solve the technical problem of low processing efficiency of the processor.

[0007] According to one aspect of an embodiment of the present application, a method for controlling a processor is provided, comprising: inputting a first mantissa of first data into a first partial product generating unit in the processor, and inputting a second mantissa of second data into a second partial product generating unit in the processor, wherein the first data is a floating point number represented by a first mantissa and a first exponent, and the second data is a floating point number represented by a second mantissa and a second exponent; generating a partial product of the first mantissa and the first mantissa by the first partial product generating unit to obtain a first group of partial products, and generating a partial product of the second mantissa and the second mantissa by the second partial product generating unit to obtain a second group of partial products, wherein, The number of AND operations performed in the process of generating a first group of partial products is less than the square of the number of bits of the first mantissa, and the number of AND operations performed in the process of generating a second group of partial products is less than the square of the number of bits of the second mantissa; the first group of partial products are added by a first carry-preserving adder CSA in the processor to obtain a first carry value and a first summation value, and the second group of partial products are added by a second CSA in the processor to obtain a second carry value and a second summation value; the first exponent, the second exponent, the first carry value and the first summation value, the second carry value and the second summation value are processed by the processor to obtain a target processing result.

[0008] Optionally, the above-mentioned generating the partial product of the first mantissa and the first mantissa by the first partial product generating unit to obtain the first group of partial products includes: when the first mantissa includes N bits and N is a positive integer greater than or equal to 2, determining the AND operations to be performed on each bit in the N bits and each bit in the N bits respectively, to obtain a total of N×N AND operations to be performed; merging the N×N AND operations to obtain M AND operations, wherein M is less than N×N and M is a positive integer greater than or equal to 2; performing M AND operations to obtain the first group of partial products.

[0009] Optionally, the above-mentioned N×N AND operations are merged to obtain M AND operations, including: replacing the AND operation between the i-th bit and the i-th bit in N bits to be executed with the i-th bit, where i is a positive integer greater than or equal to 1 and less than or equal to N; when i is greater than j, merging the AND operation between the i-th bit and the j-th bit in the N bits to be executed at the p-th position and the AND operation between the j-th bit and the i-th bit to be executed at the p-th position into the AND operation between the i-th bit and the j-th bit to be executed at the p+1-th position.

[0010] Optionally, the second partial product generating unit generates the partial product of the second mantissa and the second mantissa to obtain a second group of partial products, including: when the second mantissa includes N bits and N is a positive integer greater than or equal to 2, determining the AND operations to be performed on each bit in the N bits and each bit in the N bits, respectively, to obtain a total of N×N AND operations to be performed; merging the N×N AND operations to obtain M AND operations, where M is less than N×N and M is a positive integer greater than or equal to 2; and performing M AND operations to obtain a second group of partial products.

[0011] Optionally, the above-mentioned processing of the first exponent, the second exponent, the first carry value and the first summation value, the second carry value and the second summation value by the processor to obtain the target processing result includes: comparing the first exponent and the second exponent by a comparator in the processor to obtain a comparison result and a first exponent difference, wherein the comparison result is used to indicate whether the first exponent is greater than the second exponent, and the first exponent difference is the difference between the first exponent and the second exponent; when the comparison result indicates that the first exponent is greater than the second exponent, shifting the second carry value and the second summation value according to the first exponent difference to obtain a third carry value and a third summation value, wherein the third carry value and the third summation value are the same as the exponents corresponding to the first carry value and the first summation value; processing the first exponent, the third carry value and the third summation value, the first carry value and the first summation value by the processor to obtain the target processing result.

[0012] Optionally, the above-mentioned shifting the second carry value and the second sum value according to the first exponent difference value to obtain a third carry value and a third sum value includes: shifting the first exponent difference value left by one position through a processor to obtain a second exponent difference value; shifting the second carry value and the second sum value by the second exponent difference value to obtain a third carry value and a third sum value.

[0013] Optionally, the above-mentioned processing of the first exponent, the third carry value and the third summation value, the first carry value and the first summation value by the processor to obtain the target processing result includes: shifting the first exponent left by one position by the processor to obtain the third exponent; adding the third carry value and the third summation value, the first carry value and the first summation value by the third CSA in the processor to obtain the fourth carry value and the fourth summation value; performing fixed-point addition processing on the fourth carry value and the fourth summation value by the fixed-point adder in the processor to obtain the third mantissa and the first exponent adjustment value; adjusting the third exponent by the processor using the first exponent adjustment value to obtain the fourth exponent; normalizing and rounding the third mantissa by the processor to obtain the fourth mantissa; and determining the first target data represented by the fourth exponent and the fourth mantissa as the target processing result.

[0014] Optionally, the above-mentioned processing of the first exponent, the second exponent, the first carry value and the first summation value, the second carry value and the second summation value by the processor to obtain the target processing result also includes: when the comparison result indicates that the first exponent is less than the second exponent, shifting the first carry value and the first summation value according to the first exponent difference to obtain a fifth carry value and a fifth summation value, wherein the fifth carry value and the fifth summation value are the same as the exponents corresponding to the second carry value and the second summation value; processing the second exponent, the fifth carry value and the fifth summation value, the second carry value and the second summation value by the processor to obtain the target processing result.

[0015] Optionally, the above-mentioned shifting the first carry value and the first sum value according to the first exponent difference value to obtain a fifth carry value and a fifth sum value includes: shifting the first exponent difference value left by one position through a processor to obtain a second exponent difference value; shifting the first carry value and the first sum value by the second exponent difference value to obtain a fifth carry value and a fifth sum value.

[0016] Optionally, the above-mentioned processing of the second exponent, the fifth carry value and the fifth summation value, the second carry value and the second summation value by the processor to obtain the target processing result includes: shifting the second exponent left by one position by the processor to obtain the fifth exponent; adding the fifth carry value and the fifth summation value, the second carry value and the second summation value by the third CSA in the processor to obtain the sixth carry value and the sixth summation value; performing fixed-point addition processing on the sixth carry value and the sixth summation value by the fixed-point adder in the processor to obtain the fifth mantissa and the second exponent adjustment value; adjusting the fifth exponent by the processor using the second exponent adjustment value to obtain the sixth exponent; normalizing and rounding the fifth mantissa by the processor to obtain the sixth mantissa; and determining the second target data represented by the sixth exponent and the sixth mantissa as the target processing result.

[0017] Optionally, the first data and the second data are data used to perform a target operation in a target neural network model, wherein the target processing result is a result obtained by performing the target operation on the first data and the second data; when the target neural network model is a model for image recognition, the first data and the second data are data related to the image; when the target neural network model is a model for audio recognition, the first data and the second data are data related to audio; when the target neural network model is a model for information synthesis, the first data and the second data are data related to the information.

[0018] According to another aspect of an embodiment of the present application, a processor is further provided, including: a first partial product generating unit, used to generate a partial product of a first mantissa of first data and a first mantissa, to obtain a first group of partial products, wherein the first data is a floating point number represented by the first mantissa and the first exponent; a second partial product generating unit, used to generate a partial product of a second mantissa of second data and a second mantissa, to obtain a second group of partial products, wherein the second data is a floating point number represented by the second mantissa and the second exponent; a first carry-preserving adder CSA, an input end of the first CSA and an output end of the first partial product generating unit The first CSA is connected to the output end of the second partial product generating unit, and is used to perform addition processing on the first group of partial products to obtain a first carry value and a first sum value; the second CSA, the input end of the second CSA is connected to the output end of the second partial product generating unit, and the second CSA is used to perform addition processing on the second group of partial products to obtain a second carry value and a second sum value; the processing unit, the input end of the processing unit is respectively connected to the output end of the first CSA and the output end of the second CSA, and the processing unit is used to process the first exponent, the second exponent, the first carry value and the first sum value, the second carry value and the second sum value to obtain the target processing result.

[0019] Optionally, the above-mentioned first partial product generating unit includes: a merging component, used to determine the AND operations to be performed on each bit in the N bits and each bit in the N bits respectively when the first mantissa includes N bits and N is a positive integer greater than or equal to 2, so as to obtain a total of N×N AND operations to be performed; merging the N×N AND operations to obtain M AND operations, where M is less than N×N and M is a positive integer greater than or equal to 2; and an AND operation execution component, used to execute M AND operations to obtain a first group of partial products.

[0020] Optionally, the above-mentioned merging component includes: a replacement device, used to replace the AND operation between the i-th bit and the i-th bit in N bits to be performed with the i-th bit, where i is a positive integer greater than or equal to 1 and less than or equal to N; a first shift device, used to merge the AND operation between the i-th bit and the j-th bit in N bits to be performed at the p-th position and the AND operation between the j-th bit and the i-th bit to be performed at the p-th position into the AND operation between the i-th bit and the j-th bit to be performed at the p+1-th position when i is greater than j.

[0021] Optionally, the above-mentioned processing unit includes: a comparator, used to compare the first exponent and the second exponent to obtain a comparison result and a first exponent difference, wherein the comparison result is used to indicate whether the first exponent is greater than the second exponent, and the first exponent difference is the difference between the first exponent and the second exponent; a processing module, used to shift the second carry value and the second summation value according to the first exponent difference when the comparison result indicates that the first exponent is greater than the second exponent to obtain a third carry value and a third summation value, wherein the third carry value and the third summation value are the same as the exponents corresponding to the first carry value and the first summation value; and the first index, the third carry value and the third summation value, the first carry value and the first summation value are processed by the processor to obtain the target processing result.

[0022] Optionally, the processing module includes: a second shift device, used to shift the first exponent difference value left by one position through a processor to obtain a second exponent difference value; a third shift device, used to shift the second carry value and the second sum value by the second exponent difference value to obtain a third carry value and a third sum value.

[0023] Optionally, the above-mentioned processing module includes: a fourth shift device, used to shift the first exponent left by one position through a processor to obtain a third exponent; a third CSA, used to add the third carry value and the third summation value, the first carry value and the first summation value, to obtain a fourth carry value and a fourth summation value; a fixed-point adder, used to perform fixed-point addition processing on the fourth carry value and the fourth summation value to obtain a third mantissa and a first exponent adjustment value; a first processing sub-module, used to adjust the third exponent using the first exponent adjustment value to obtain a fourth exponent; a second processing sub-module, used to normalize and round the third mantissa to obtain a fourth mantissa; and a third processing sub-module, used to determine the first target data represented by the fourth exponent and the fourth mantissa as the target processing result.

[0024] Optionally, the above-mentioned processing module also includes: a fifth shift device, used to shift the first carry value and the first summation value according to the first exponent difference when the comparison result indicates that the first exponent is less than the second exponent, so as to obtain a fifth carry value and a fifth summation value, wherein the fifth carry value and the fifth summation value are the same as the exponents corresponding to the second carry value and the second summation value; a fourth processing sub-module, used to process the second exponent, the fifth carry value and the fifth summation value, the second carry value and the second summation value to obtain the target processing result.

[0025] Optionally, the above-mentioned processing module also includes: a sixth shift device, used to shift the first exponent difference value left by one position through a processor to obtain a second exponent difference value; a seventh shift device, used to shift the first carry value and the first sum value by the second exponent difference value to obtain a fifth carry value and a fifth sum value.

[0026] Optionally, the above-mentioned processing module also includes: an eighth shift device, used to shift the second exponent left by one position through the processor to obtain a fifth exponent; a third CSA, used to add the fifth carry value and the fifth summation value, the second carry value and the second summation value to obtain a sixth carry value and a sixth summation value; a fixed-point adder, used to perform fixed-point addition processing on the sixth carry value and the sixth summation value to obtain a fifth mantissa and a second exponent adjustment value; a fifth processing sub-module, used to adjust the fifth exponent using the second exponent adjustment value through the processor to obtain a sixth exponent; a sixth processing sub-module, used to normalize and round the fifth mantissa to obtain a sixth mantissa; and a seventh processing sub-module, used to determine the second target data represented by the sixth exponent and the sixth mantissa as the target processing result.

[0027] According to another aspect of the embodiments of the present application, an electronic device is provided, comprising the processor in the above embodiments.

[0028] Through the above-mentioned embodiment provided by the present application, the first partial product generating unit in the processor is used to generate the first group of partial products of the first data; the second partial product generating unit in the processor is used to generate the second group of partial products of the second data; then the first carry-preserving adder CSA is used to perform addition processing on the first group of partial products, and the second CSA is used to perform addition processing on the second group of partial products, and the first exponent, the second exponent, the first carry value, the first sum value, the second carry value and the second sum value obtained by the addition processing are processed to obtain the target processing result. Among them, the number of AND operations performed in the process of generating the first group of partial products is less than the square of the number of bits of the first mantissa of the first data, and the number of AND operations performed in the process of generating the second group of partial products is less than the square of the number of bits of the second mantissa of the second data, which reduces the number of AND operations of the partial product dot matrix in the square operation process, simplifies the processing flow of the first data and the second data, solves the technical problem of low processing efficiency of the processor in the related technology, and achieves the technical effect of improving the processing efficiency of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0030] Figure 1 is a schematic diagram of an application scenario of an optional processor control method according to an embodiment of the present application;

[0031] Figure 2 is a flowchart of an optional processor control method according to an embodiment of the present application;

[0032] Figure 3 is an overall architecture diagram of an optional processor control method according to an embodiment of the present application;

[0033] Figure 4 is a schematic diagram of an optional partial product folding process according to an embodiment of the present application;

[0034] Figure 5 is a result of an optional partial product folding process according to an embodiment of the present application;

[0035] Figure 6 is a merging operation performed during an optional partial product folding process according to an embodiment of the present application;

[0036] Figure 7 is a replacement operation performed during an optional partial product folding process according to an embodiment of the present application;

[0037] Figure 8 is a schematic diagram of an optional floating point number exponent processing according to an embodiment of the present application;

[0038] Fig. 9 is a flow chart comparing the square sum operation of floating point numbers in the related art and the embodiment of the present application;

[0039] Fig.10 It is a schematic diagram of the structure of an optional electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0041] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] The technical solutions in the embodiments of the present application will comply with legal provisions during implementation. When performing operations according to the technical solutions in the embodiments, the data used will not involve user privacy. While ensuring that the operation process is compliant and legal, the security of the data is guaranteed.

[0043] Glossary:

[0044] CSA: carry save adder, carry save adder.

[0045] According to one aspect of the embodiments of the present application, a method for controlling a processor is provided. As an optional implementation, the method for controlling a processor may be, but is not limited to, applied to Figure 1 The application scenario shown in Figure 1 In the application scenario shown, the target neural network model can be but is not limited to a model for image recognition, audio recognition or information synthesis, and the first data and the second data can be but are not limited to the data of one layer of the target neural network. The first data is input into a first partial product generation unit in the processor, and the second data is input into a second partial product generation unit in the processor, and a first set of partial products corresponding to the first data and a second set of partial products corresponding to the second data are generated. Finally, other processing units or processing modules in the processor are used to complete the square sum operation of the first data and the second data to obtain the target processing result.

[0046] In a specific embodiment, it is assumed that the first data and the second data are data used to perform a target operation in a target neural network model, wherein the target processing result is a result obtained by performing the target operation on the first data and the second data;

[0047] In the case where the target neural network model is a model for image recognition, the first data and the second data are data related to the image;

[0048] In the case where the target neural network model is a model for audio recognition, the first data and the second data are data related to audio;

[0049] In the case where the target neural network model is a model for information synthesis, the first data and the second data are data related to the information.

[0050] Obviously, the target neural network model in the above embodiment is only an example and is not limited thereto.

[0051] In addition, both the first data and the second data are floating-point numbers. Floating-point operations are often used in neural network calculations due to their larger dynamic range. The square sum operation of floating-point numbers is widely used in scenarios such as pattern recognition, filters, and vector normalization. In addition, the square sum operation is also often used in scenarios such as solving coordinate amplitudes.

[0052] In order to solve the problem of low processing efficiency of the above-mentioned processor, a control method of the processor is proposed in an embodiment of the present application. Figure 2 is a flowchart of a control method of a processor according to an embodiment of the present application, the process comprising the following steps:

[0053] Step S202, inputting a first mantissa of the first data into a first partial product generating unit in the processor, and inputting a second mantissa of the second data into a second partial product generating unit in the processor, wherein the first data is a floating point number represented by a first mantissa and a first exponent, and the second data is a floating point number represented by a second mantissa and a second exponent;

[0054] Step S204, generating a partial product of the first mantissa and the first mantissa by a first partial product generating unit to obtain a first set of partial products, and generating a partial product of the second mantissa and the second mantissa by a second partial product generating unit to obtain a second set of partial products, wherein the number of AND operations performed in the process of generating the first set of partial products is less than the square of the number of bits of the first mantissa, and the number of AND operations performed in the process of generating the second set of partial products is less than the square of the number of bits of the second mantissa;

[0055] Step S206, performing an addition process on the first group of partial products through a first carry-save adder CSA in the processor to obtain a first carry value and a first sum value, and performing an addition process on the second group of partial products through a second CSA in the processor to obtain a second carry value and a second sum value;

[0056] Step S208: Processing the first index, the second index, the first carry value and the first sum value, the second carry value and the second sum value by a processor to obtain a target processing result.

[0057] In order to facilitate understanding of the technical solution in this embodiment, the basic concept of floating-point numbers is first briefly introduced.

[0058] A floating point number is a digital representation of a number that belongs to a specific subset of rational numbers. It is used in computers to approximate any real number. Specifically, this real number is obtained by multiplying an integer or fixed-point number (i.e., the mantissa) by an integer power of a specified base (e.g., 2). For example, a = 1.0 x 10 5 , where 5 is the exponent of the floating point number a and 1.0 is the mantissa of the floating point number a.

[0059] For the square sum operation of two floating-point numbers, it is usually necessary to first perform a square operation on the two floating-point numbers (which can also be understood as a multiplication operation), and then perform a sum operation to obtain the final square sum operation result. In the multiplication operation process, it is necessary to first generate the partial product dot matrix corresponding to the two floating-point numbers, and then process the partial products in the partial product dot matrix to obtain the multiplication result of the two floating-point numbers.

[0060] The most critical link in the processing of partial products is the processing of AND operations in the partial product matrix. Each AND operation requires a corresponding transistor, which means that the more AND operations are performed in the partial product matrix, the larger the area of ​​the processor or chip consumed; conversely, the fewer AND operations are performed in the partial product matrix, the smaller the area of ​​the processor or chip consumed.

[0061] In such Figure 3 In the embodiment shown, assuming that the first exponent of the first data is exp_a and the first mantissa is man_a, and the second exponent of the second data is exp_b and the second mantissa is man_b, and assuming that the first mantissa and the second mantissa are only 8-bit, the first mantissa is input into the second partial product generation unit in the processor, and the result is as follows: Figure 5 The partial product dot matrix shown in Table 5 in FIG. 5 ; similarly, inputting the second mantissa into the second partial product generating unit in the processor will also generate a partial product dot matrix similar to that in Table 5.

[0062] In the related art, for the 8-bit first mantissa, by using the partial product generation unit, the generated partial product matrix is ​​as follows: Figure 4 Table 1 shown, wherein Table 1 includes the partial product of a[7:0]×a[7:0] and forms a parallelogram (including 8 2 =64 nodes), where each node is an AND operation, for example, a[1]a[0] is a[1]&a[0], a[1]a[2] is a[1]&a[2], and so on.

[0063] In the first partial product generating unit of the embodiment of the present application, the number of AND operations performed in the process of generating the partial product of the first mantissa is 36. This is because the 64 nodes (64 partial products) originally generated are folded to obtain the following: Figure 5 The partial product matrix (first group of partial products) shown in Table 5. The folding process of partial products will be described below in conjunction with specific embodiments.

[0064] Referring to the above process, you can also use Figure 3 The second partial product generating unit shown generates a partial product lattice of a second mantissa, and obtains a second group of partial products including 36 nodes.

[0065] After that, the first group of partial products is input into the first carry-preserving adder CSA in the processor, and the first group of partial products are added to obtain the first carry bit carry1 and the first sum value sum1; the second group of partial products is input into the second CSA in the processor, and the first group of partial products are added to obtain the second carry bit carry2 and the second sum value sum2.

[0066] The first exponent, the second exponent, the first carry value and the first sum value, the second carry value and the second sum value are processed by the processing unit in the processor (including the switch, the third CSA, the comparator, the fixed-point adder, etc.) to obtain the target processing result.

[0067] It can be seen that by folding the partial products in the partial product dot matrix of the first mantissa and the second mantissa, the number of nodes that the processor needs to process is reduced by almost half, which improves the processing efficiency of the partial products, and also reduces the number of transistors in the processor, and reduces the area and delay of the multiplier. In addition, the processing flow of the subsequent addition process is simplified, and the area overhead of the processor is reduced.

[0068] In order to more clearly understand the processing of each of the above processing units, Figure 3 The overall process of the control method of the above processor is described.

[0069] S302, inputting the first data and the second data into a first partial product generating unit and a second partial product generating unit respectively;

[0070] After the mantissa of the first data a is input into the first CSA, several partial products are obtained; after the mantissa of the second data b is input into the second CSA, several partial products are also obtained, wherein, in the first partial product generation unit, a first group of partial products of the mantissa of the first data a is generated by performing several AND operations; similarly, in the second partial product generation unit, a second group of partial products of the second mantissa of the second data b is obtained by performing several AND operations.

[0071] It should be noted that, in the process of generating the first set of partial products using the first partial product generating unit, and generating the second set of partial products using the second partial product generating unit, the number of AND operations performed is less than the square of the number of bits of the first mantissa. The number of the above-mentioned AND operations will be described in detail below in conjunction with specific embodiments.

[0072] S304, inputting the first group of partial products and the second group of partial products into the first CSA and the second CSA respectively to obtain a first carry value, a first sum value, a second carry value and a second sum value;

[0073] The first group of partial products are added using the first CSA to obtain a first carry value carry1 and a first sum value sum1; the second group of partial products are added using the second CSA to obtain a second carry value carry2 and a second sum value sum2.

[0074] S306, determining whether a swap operation needs to be performed according to the first index of the first data and the second index of the second data;

[0075] Assume that the first data is a and the second data is b, both a and b are floating point numbers, and a=1.0x10 5 b = 1.0 x 10 4 , then the first exponent exp_a is 5 and the second exponent exp_b is 4. The comparator exp_cmp is used to compare the sizes of exp_a and exp_b. Since exp_a is greater than exp_b, it is necessary to exchange the first carry value carry1 and the first sum value sum1, and the second carry value carry2 and the second sum value sum2. For details, refer to step S308.

[0076] S308, when the first index is greater than the second index, using swap1 (switch 1) and swap2 (switch 2), swapping the first carry value carry1 and the first sum value sum1 from switch 1 to switch 2, and swapping the second carry value carry2 and the second sum value sum2 from switch 2 to switch 1;

[0077] Among them, the switch is a device that performs "2 to 1" on two data in two channels at the input end, that is, according to the comparison result of the first exponent and the second exponent, the product with the smaller exponent enters the left channel (that is, enters switch 1), and the product with the larger exponent enters the right channel (that is, enters switch 2). The purpose is to shift the second data with the smaller exponent to achieve alignment between the decimal points of the mantissa of the first data and the mantissa of the second data, thereby solving the problem of decimal point offset of the first data and the second data involved in the addition operation.

[0078] S310, shifting the second carry value carry2 and the second sum value sum2 according to the difference between the first exponent and the second exponent to obtain a third carry value carry3 and a third sum value sum3;

[0079] Through the above-mentioned shift processing, the exponent of the second carry value is adjusted to the exponent of the third carry value, and the exponent of the second summation value is adjusted to the exponent of the third summation value, so as to ensure that the third carry value and the third summation value used in the addition operation performed using the third CSA are the same as the exponents corresponding to the first carry value and the first summation value.

[0080] S312, using the third CSA, adding the third carry value and the third sum value, the first carry value and the first sum value in step S310 to obtain a fourth carry value and a fourth sum value;

[0081] S314, using a fixed-point adder, performing a standard fixed-point addition operation on the fourth carry value and the fourth sum value;

[0082] Since the result of the square operation of a floating-point number must be a positive number, the result of the fixed-point adder will not produce leading zeros. Therefore, it is only necessary to perform normalization processing according to the number of overflow bits to obtain the target square number.

[0083] The target square number represents the multiplication result of the first data and the second data.

[0084] S316, after the normalization process, the mantissa is rounded and the exponent is sent to exp_adj to adjust the exponent;

[0085] The adjustment is based on how many bits the addition result of the fixed-point adder overflows.

[0086] S318, concatenate the larger exponent of the first exponent and the second exponent and the rounded mantissa (the sum of the squares of the mantissas) to obtain a target processing result.

[0087] Since the square sum of the two data must be a positive number, the sign of the square sum result is sign=0. It is only necessary to concatenate the exponent and the number of bits to obtain the final target processing result.

[0088] The specific implementation process of each step in the above steps S302 to S318 will be further described below in conjunction with specific embodiments.

[0089] In the above manner, the first partial product generating unit in the processor is used to generate the first group of partial products of the first data; the second partial product generating unit in the processor is used to generate the second group of partial products of the second data; then the first carry-preserving adder CSA is used to perform addition processing on the first group of partial products, and the second CSA is used to perform addition processing on the second group of partial products, and the first exponent, the second exponent, the first carry value, the first sum value, the second carry value and the second sum value obtained by the addition processing are processed to obtain the target processing result. Among them, the number of AND operations performed in the process of generating the first group of partial products is less than the square of the number of bits of the first mantissa of the first data, and the number of AND operations performed in the process of generating the second group of partial products is less than the square of the number of bits of the second mantissa of the second data, which reduces the number of AND operations of the partial product dot matrix in the square operation process, simplifies the processing flow of the first data and the second data, solves the technical problem of low processing efficiency of the processor in the related technology, and achieves the technical effect of improving the processing efficiency of the processor.

[0090] As an optional example, the first partial product generating unit generates a partial product of the first mantissa and the first mantissa to obtain a first set of partial products, including:

[0091] When the first mantissa includes N bits and N is a positive integer greater than or equal to 2, determine an AND operation to be performed on each bit in the N bits and each bit in the N bits, respectively, to obtain a total of N×N AND operations to be performed;

[0092] Perform a merge operation on the N×N AND operations to obtain M AND operations, where M is less than N×N and is a positive integer greater than or equal to 2;

[0093] Perform M AND operations to obtain the first set of partial products.

[0094] For example, assuming that the first mantissa includes 8 bits, which are 0 to 7 respectively, determine the AND operations to be performed on each bit in the 8 bits and each bit in the 8 bits respectively, for example, determine the AND operations a[0]a[0], a[0]a[1], a[1]a[0], and a[1]a[1] to be performed, where each AND operation can be regarded as a node.

[0095] According to the above process, 64 AND operations (64 nodes) to be performed consisting of 8 bits of the first mantissa can be determined, as follows: Figure 4 Table 1. The same nodes in the same column are merged. For example, a[7]a[6] is the same as a[6]a[7], so they can be merged into 2a[7]a[6]; a[7]a[5] is the same as a[5]a[7], so they can be merged into 2a[7]a[5], etc. For details, please refer to Figure 6The merge operation process is shown.

[0096] Among them, the first set of partial products includes Figure 5 All AND operations (or nodes) in the partial product matrix in Table 5 shown in FIG. 5 , and the number of the first group of partial products output by the first partial product generation unit is related to the bit width m of the first mantissa, and the number of partial products is

[0097] As an optional implementation, the above-mentioned N×N AND operations are combined to obtain M AND operations, including:

[0098] Replace the AND operation to be performed between the ith bit and the ith bit of N bits with the ith bit, where i is a positive integer greater than or equal to 1 and less than or equal to N;

[0099] When i is greater than j, the AND operation between the i-th bit and the j-th bit among the N bits to be executed at the p-th position and the AND operation between the j-th bit and the i-th bit to be executed at the p-th position are combined into the AND operation between the i-th bit and the j-th bit to be executed at the p+1-th position.

[0100] like Figure 7 As shown in Table 2-3, the result of performing the AND operation between the 8th bit a[7] and a[7] of the 8 bits a[0] to a[7] of the first mantissa is still a[7] itself, and the result of performing the AND operation between the 7th bit a[6] and a[6] is still a[6] itself. Based on this, Figure 7 The first line shown in Table 2-3 is replaced by the first line shown in Table 2-4.

[0101] Further, after performing the above merging and replacing operations, the following is obtained: Figure 4 The partial product matrix shown in Table 4 in FIG. 4 converts the 2a[7]a[6] operation shown in Table 4 into a shift operation. Specifically, for Figure 4 For the AND operation 2a[7]a[6] in the second row of the table, assuming that its position is the column numbered 13 in the table, after shifting 2a[7]a[6] one position to the left, its position is updated to Figure 5 The column numbered 14 is shown, and the AND operation between 2 a[7] and 2 a[6] is merged into the AND operation between a[7]a[6].

[0102] Likewise, Figure 4 2a[7]a[5], 2a[7]a[4], 2a[7]a[3], etc. in Table 4 are all shifted left by one position, and the result is Figure 5 As shown in Table 5.

[0103] In order to more clearly understand the folding process of the above partial products, the following takes the input of the first mantissa of the first data a as an 8-bit as an example, and combines Figure 4 and Figure 5 Explain its overall implementation process.

[0104] S41, by inputting the 8-bit first mantissa into the first partial product generation unit, obtaining a[7:0]*a[7:0];

[0105] like Figure 4 As shown in Table 1, the partial product matrix of a[7:0]*a[7:0] forms a parallelogram, and each node is an AND operation. For example, a[1]a[0] means a[1]&a[0].

[0106] S42, extract the nodes on the diagonal line to the first row;

[0107] Since the two operands of the AND operation on the diagonal are the same, extract each AND operation to the first row of the corresponding column according to the column where the operation is located. For example, Figure 4 In Table 2, a[7]a[7], a[6]a[6], a[5]a[5], a[4]a[4], etc. are extracted to the first row.

[0108] It should be noted that after any operand is ANDed with itself, it is still the operand itself. For example, after a[7]a[7] is ANDed with itself, it is still a[7], and after a[6]a[6] is ANDed with itself, it is still a[6].

[0109] S43, merge the same nodes in the same column to obtain Figure 4 middle table 3;

[0110] For example, since a[1]a[0] and a[0]a[1] perform the same operation, they can be merged into 2a[1]a[0]. The same method can be used to merge the same nodes in other columns.

[0111] S44, folding part of the product lattice to form Figure 4 The inverted pyramid shape shown in Table 4;

[0112] S45, convert the 2a[1]a[0] operation into a shift operation, and move the corresponding grid point one unit to the left, and obtain Figure 5 The final partial plot dot plot is shown.

[0113] From the above process, it can be seen that originally 64 nodes needed to be processed for AND operations. After the above-mentioned merging, replacement, and folding processes, only 36 nodes need to be processed. The number of processed nodes is reduced by nearly half, which reduces the calculation delay of floating-point operations and improves the processing efficiency of the processor.

[0114] The second mantissa of the second data is processed in the same manner as the first data, specifically including:

[0115] When the second mantissa includes N bits and N is a positive integer greater than or equal to 2, determine an AND operation to be performed on each bit in the N bits and each bit in the N bits, respectively, to obtain a total of N×N AND operations to be performed;

[0116] Perform a merge operation on the N×N AND operations to obtain M AND operations, where M is less than N×N and is a positive integer greater than or equal to 2;

[0117] Perform M AND operations to obtain a second set of partial products.

[0118] Assume that the second mantissa b includes 8 bits, which are 0 to 7 respectively, and determine the AND operations to be performed on each bit in the 8 bits and each bit in the 8 bits respectively. For example, determine the AND operations b[0]b[0], b[0]b[1], b[1]b[0], and b[1]b[1] to be performed, where each AND operation can be regarded as a node.

[0119] According to the above process, 64 AND operations (64 nodes) to be performed consisting of 8 bits of the second mantissa can be determined. For details, please refer to Figure 4 The partial product dot matrix corresponding to the first mantissa shown in Table 1. The same nodes in the same column are merged. For example, b[7]b[6] is the same as b[6]b[7], so they can be merged into 2b[7]b[6]; b[7]b[5] is the same as b[5]b[7], so they can be merged into 2b[7]b[5], etc. For details, please refer to Figure 6 The merging operation process shown will not be repeated here.

[0120] The second set of partial products includes all partial products in the folded partial product matrix (which can also be understood as AND operations). For details, please refer to Figure 5 Table 5 shows a partial plot matrix.

[0121] As an optional example, the processor processes the first index, the second index, the first carry value and the first sum value, the second carry value and the second sum value to obtain a target processing result, including:

[0122] Comparing the first index and the second index by a comparator in the processor to obtain a comparison result and a first index difference, wherein the comparison result is used to indicate whether the first index is greater than the second index, and the first index difference is the difference between the first index and the second index;

[0123] When the comparison result indicates that the first exponent is greater than the second exponent, the second carry value and the second sum value are shifted according to the first exponent difference to obtain a third carry value and a third sum value, wherein the third carry value and the third sum value have the same exponent as the first carry value and the first sum value.

[0124] The processor processes the first exponent, the third carry value and the third sum value, the first carry value and the first sum value to obtain a target processing result.

[0125] It should be noted that when performing addition and subtraction operations on two floating-point numbers, it is first necessary to determine whether the exponents of the two data are the same, that is, whether the decimal points are aligned. Only when the decimal points of the two data are aligned can the mantissas be added or subtracted. On the contrary, if the exponents of the two data are different, it means that the decimal points are not aligned. At this time, the exponents of the two data are made the same by performing exponent processing.

[0126] Before processing the order, it is necessary to first determine the difference between the order codes (which can also be understood as exponents) of the first data and the second data, as follows: Figure 3 As shown:

[0127] The first index and the second index are compared by the comparator exp_cmp. For example, the first data is 1.0 x 10 5 The second data is 1.0 x 10 4 , then the first index is 5 and the second index is 4, the first index is greater than the second index, and according to the comparison result, the product of the first data with the larger exponent value and the product of the second data with the smaller exponent value are exchanged.

[0128] The specific process of the swap operation is: the first carry value carry1 and the first sum value sum1 originally input to switch 1 (swap1) are swapped to switch 2 (swap2), and the second carry value carry2 and the second sum value sum2 originally input to switch 2 (swap2) are swapped to switch 1 (swap1).

[0129] After the exchange operation, switch 1 outputs the second carry value carry2 and the second sum value sum2, and switch 2 outputs the first carry value carry1 and the first sum value sum1, and then the second carry value and the second sum value are shifted using two right shifters (two align units) connected to the output end of switch 1 to obtain the third carry value carry1 and the third sum value sum3.

[0130] The first index, the third carry value and the third sum value, the first carry value and the first sum value are processed to obtain a target processing result.

[0131] It should be noted that the switch swap is a device that performs "2 to 1" on the two data in the two channels at the input end, that is, according to the comparison result of the first exponent and the second exponent, the product with the smaller exponent enters the left channel (that is, enters the switch 1), and the product with the larger exponent enters the right channel (that is, enters the switch 2). The purpose is to shift the second data with the smaller exponent to achieve alignment between the decimal points of the mantissa of the first data and the mantissa of the second data, thereby solving the problem of decimal point offset of the first data and the second data involved in the addition operation.

[0132] As an optional example, the above-mentioned shifting process of the second carry value and the second sum value according to the first exponent difference value to obtain the third carry value and the third sum value includes:

[0133] The processor shifts the first exponent difference value left by one bit to obtain a second exponent difference value;

[0134] The second carry value and the second sum value are shifted by the second exponent difference to obtain a third carry value and a third sum value.

[0135] In the above embodiment, it is assumed that the first data is 1.0×10 5 The second data is 1.0 x 10 4 , the first exponent difference is 5-4=1, the first exponent difference is shifted left by one bit to obtain the second exponent difference sft_amt. This is because the sft_amt output by the comparator is the exponent difference of the first data and the second data after squaring, so the first exponent difference needs to be shifted left.

[0136] As an optional implementation, the processor processes the first exponent, the third carry value and the third sum value, the first carry value and the first sum value to obtain a target processing result, including:

[0137] The processor shifts the first index left by one bit to obtain a third index;

[0138] performing, by a third CSA in the processor, an addition process on the third carry value and the third sum value, the first carry value and the first sum value, to obtain a fourth carry value and a fourth sum value;

[0139] Performing fixed-point addition processing on the fourth carry value and the fourth sum value by a fixed-point adder in the processor to obtain a third mantissa and a first exponent adjustment value;

[0140] The processor adjusts the third index using the first index adjustment value to obtain a fourth index;

[0141] The processor performs normalization and rounding processing on the third mantissa to obtain a fourth mantissa;

[0142] The first target data represented by the fourth exponent and the fourth mantissa is determined as a target processing result.

[0143] like Figure 3 As shown, the third CSA is used to add carry3 and sum3 after shifting of the left channel (swap1) and carry1 and sum1 output by the right channel (swap2) to obtain a fourth carry value and a fourth sum value, wherein the third CSA is a 4-input 2-output carry-retaining adder.

[0144] The fourth carry value and the fourth sum value output by the third CSA are subjected to fixed-point addition to obtain a third mantissa and a first exponent adjustment value adj_num. Figure 3 As shown, the larger one (exp_large) of the first index and the second index is shifted left to obtain a third index, and then the third index is adjusted according to the first index adjustment value to obtain a fourth index.

[0145] Since the result of the floating-point square operation must be a positive number, the result of the fixed-point adder will not produce leading zeros, so it only needs to be normalized and rounded according to the number of bits that overflow. The processed exponent is sent to the exp_adj (exponent adjust) unit for exponent adjustment. The adjustment is based on how many bits the addition result overflows after the fixed-point adder performs the addition processing, that is, the number of bits of overflow.

[0146] The reason for normalizing the third mantissa is that the processed data is not necessarily a regular value, and the floating-point operations supported by the processor need to be compatible with the standard format specified by the IEEE-75 protocol. For example, the standard format is 1.01×2 ex , and the processed data may be 10.1×2 ex , therefore, it needs to be normalized.

[0147] Since the square sum result must be a positive number, the sign of the result is sign=0, and finally the exponent and the mantissa are concatenated to obtain the final result (target processing result).

[0148] In order to more clearly understand the processing flow of the first index of the first data and the second index of the second data, the following is combined with Figure 8 The index processing flow chart shown is described.

[0149] S81, such as Figure 8 As shown, firstly, a comparator is used to compare the first exponents exp_a and exp_b, and the larger value exp_large is output;

[0150] S82, determining whether a swap operation needs to be performed based on the comparison result;

[0151] Specifically determine whether the swap_en signal needs to be exchanged, and the difference between the two exp_delta.

[0152] S83, since the actual exponent after square is twice the original exponent, exp_large is shifted left by 1 bit (i.e., multiplied by 2), and then bias (the offset of the exponent) is subtracted from it;

[0153] That is, the original exp_a contains a bias, and after multiplying by 2, it contains two biases, so one needs to be subtracted.

[0154] S84, adjusting the exponent according to the overflow of the fixed-point adder;

[0155] This is because a 1-bit overflow may occur during the multiplication process and a 1-bit overflow may occur during the addition process, so a maximum of 2 bits of overflow may occur overall. Therefore, the exp_adj unit has three situations: unchanged, plus 1, or plus 2.

[0156] In addition, since exp_delta is the difference between the original two operands (i.e., the difference between the first exponent and the second exponent, for example, 5-4=1 above), the squared difference is exp_delta*2, so after shifting exp_delta left by 1 bit, the one-dimensional quantity sft_amt can be obtained.

[0157] As another optional implementation, when the first index is less than the second index, the processor processes the first index, the second index, the first carry value and the first sum value, the second carry value and the second sum value to obtain the target processing result, further comprising:

[0158] When the comparison result indicates that the first exponent is less than the second exponent, the first carry value and the first sum value are shifted according to the first exponent difference to obtain a fifth carry value and a fifth sum value, wherein the fifth carry value and the fifth sum value are the same as the exponents corresponding to the second carry value and the second sum value;

[0159] The processor processes the second exponent, the fifth carry value and the fifth sum value, the second carry value and the second sum value to obtain a target processing result.

[0160] According to the description in the above embodiment, when performing addition and subtraction operations on two floating-point numbers, it is first necessary to determine whether the exponents of the two data are the same, that is, whether the decimal points are aligned. Only when the decimal points of the two data are aligned can the mantissas be added or subtracted. On the contrary, if the exponents of the two data are different, it means that the decimal points are not aligned. At this time, the exponents of the two data are made the same by performing exponent processing.

[0161] Before processing the order, it is necessary to first determine the difference between the order codes (which can also be understood as exponents) of the first data and the second data, as follows: Figure 3 As shown:

[0162] The first index and the second index are compared by the comparator exp_cmp. For example, the first data is 1.0 x 10 4 The second data is 1.0 x 10 5 , then the first exponent is 4 and the second exponent is 5. The first exponent is smaller than the second exponent. According to the comparison result, it is determined that the input of the left channel is the product with a smaller exponent. Therefore, there is no need to perform an exchange operation.

[0163] In order to ensure that the exponents of the last two data are the same, the first carry value and the first summation value corresponding to the first data with a smaller exponent are shifted according to the first exponent difference to obtain the fifth carry value and the fifth summation value, and the second exponent, the fifth carry value and the fifth summation value, the second carry value and the second summation value are processed to obtain the target processing result.

[0164] As an optional example, the shifting process of the first carry value and the first sum value according to the first exponent difference value to obtain the fifth carry value and the fifth sum value includes:

[0165] The processor shifts the first exponent difference value left by one bit to obtain a second exponent difference value;

[0166] The first carry value and the first sum value are shifted by the second exponent difference value to obtain a fifth carry value and a fifth sum value.

[0167] Combined with the description of the above embodiment, assuming that the first data is 1.0×10 4The second data is 1.0 x 10 5 , the first exponent difference is 5-4=1, the first exponent difference is shifted left by one bit to obtain the second exponent difference sft_amt. This is because the sft_amt output by the comparator is the exponent difference of the first data and the second data after squaring, so the first exponent difference needs to be shifted left.

[0168] The first carry value and the first sum value are shifted according to the second exponent difference to obtain a fifth carry value and a fifth sum value.

[0169] As an optional example, the processor processes the second exponent, the fifth carry value and the fifth sum value, the second carry value and the second sum value to obtain a target processing result, including:

[0170] The processor shifts the second index left by one position to obtain the fifth index;

[0171] performing, by a third CSA in the processor, an addition process on the fifth carry value and the fifth sum value, the second carry value and the second sum value to obtain a sixth carry value and a sixth sum value;

[0172] Performing fixed-point addition processing on the sixth carry value and the sixth sum value by a fixed-point adder in the processor to obtain a fifth mantissa and a second exponent adjustment value;

[0173] The processor adjusts the fifth index using the second index adjustment value to obtain a sixth index;

[0174] The processor performs normalization and rounding processing on the fifth mantissa to obtain a sixth mantissa;

[0175] The second target data represented by the sixth exponent and the sixth mantissa is determined as the target processing result.

[0176] When the first index is less than the second index, we can still use Figure 3 The third CSA shown adds the fifth carry value and the fifth sum value, the second carry value and the second sum value to obtain the sixth carry value and the sixth sum value, wherein the third CSA is a 4-input 2-output carry-preserved adder.

[0177] The sixth carry value and the sixth sum value output by the third CSA are input into a fixed-point adder, and fixed-point addition is performed to obtain a fifth mantissa and a second exponent adjustment value adj_num. Figure 3 As shown, the larger one (exp_large) of the first index and the second index is shifted left to obtain the fifth index, and then the fifth index is adjusted according to the second index adjustment value to obtain the sixth index.

[0178] Since the result of the floating-point square operation must be a positive number, the result of the fixed-point adder will not produce leading zeros, so it only needs to be normalized and rounded according to the number of bits that overflow. The processed exponent is sent to the exp_adj (exponent adjust) unit for exponent adjustment. The adjustment is based on how many bits the addition result overflows after the fixed-point adder performs the addition processing, that is, the number of bits of overflow.

[0179] The reason for normalizing the fifth mantissa is that the processed data is not necessarily a regular value, and the floating-point operations supported by the processor need to be compatible with the standard format specified by the IEEE-75 protocol. For example, the standard format is 1.01×2 ex , and the processed data may be 10.1×2 ex , therefore, it needs to be normalized.

[0180] Since the square sum result must be a positive number, the sign of the result is sign=0, and finally the sixth exponent and the sixth mantissa are concatenated to obtain the final result (target processing result).

[0181] According to the description of the addition processing in the two cases where the first index is greater than the second index, and the first index is less than the second index in the above embodiment, since the number of AND operations is reduced in the above process of executing the partial product of the first data and the second data, the addition processing flow is simplified accordingly, and the overall calculation delay of the processing is further reduced.

[0182] Combine the following Fig. 9 The flowchart shown compares the process of square sum operation of floating-point numbers in the related art with that in the technical solution of the present application.

[0183] The overall calculation process is compared as above Fig. 9 As shown, Fig. 9 The left figure in (a) shows the delay of the floating-point multiplication-addition unit in the related art. Fig. 9 (b) is the floating point square sum unit calculation delay in the embodiment of the present application.

[0184] By comparison, it can be intuitively seen that: (1) the multiplication part of the floating-point multiplication-addition unit in the related art needs to be booth-encoded first, while the embodiment of the present application directly generates partial products; (2) the shift amount of the alignment shifter in the embodiment of the present application is always an even number, and the implementation of the shifter can be simplified here; the multiplication result of the traditional floating-point multiplication-addition unit may be a negative number, and the multiplication result needs to be converted into the form of 2's complement (binary complement); (3) In addition, in the related art, after the addition operation is performed, the addition result needs to be converted into an unsigned number, but this step is not required in the calculation process of the embodiment of the present application; (4) in the final normalization shift, the floating-point multiplication-addition unit in the related art may generate a large number of leading zeros in the final addition process, so its normalization shift requires a 2*m-bit shifter (where m is the mantissa bit width), while the embodiment of the present application only involves overflow scenarios, with a maximum overflow of 2 bits, and only a 2-bit shifter is required.

[0185] By comparison, it can be seen that compared with the related art, the technology in the embodiment of the present application has at least the following beneficial effects:

[0186] 1) Through the folding process of the partial product matrix, the scale of the partial product matrix is ​​reduced, the number of AND operations is reduced, and the area of ​​the multiplier and the calculation delay are reduced;

[0187] 2) Floating-point multiplication and addition are integrated, and the floating-point multiplication output retains the result of the carry, which reduces the calculation delay while retaining the intermediate calculation accuracy;

[0188] 3) Based on the characteristics of floating-point square sum, the processing flow of addition operation is simplified, further reducing the overall calculation delay of the processor;

[0189] 4) The area of ​​the processor (chip) is reduced: through synthesis by the synthesis tool design compiler, the area of ​​the processor in the related art is 978um^2, and the area of ​​the processor in the embodiment of the present application is 536um^2, that is, the area of ​​the processor in the embodiment of the present application is 54.8% of the area of ​​the processor in the related art;

[0190] 5) Improved processor performance: The floating-point square sum operation proposed in the embodiment of the present application reduces operations such as boothencoder (interleaved encoder), 2's complement (binary complement), large bit width normalized shift, etc., effectively reducing latency.

[0191] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0192] According to another aspect of the embodiment of the present application, there is also provided Figure 1 or Figure 3 A processor as shown, the processor comprising:

[0193] A first partial product generating unit, configured to generate a partial product of a first mantissa and a first exponent of first data to obtain a first set of partial products, wherein the first data is a floating point number represented by the first mantissa and the first exponent;

[0194] A second partial product generating unit, configured to generate a partial product of a second mantissa of second data and a second exponent to obtain a second set of partial products, wherein the second data is a floating point number represented by the second mantissa and the second exponent;

[0195] A first carry-save adder CSA, wherein an input end of the first CSA is connected to an output end of the first partial product generating unit, and the first CSA is used to perform an addition process on the first group of partial products to obtain a first carry value and a first sum value;

[0196] a second CSA, wherein an input end of the second CSA is connected to an output end of the second partial product generating unit, and the second CSA is used to perform an addition process on the second group of partial products to obtain a second carry value and a second sum value;

[0197] A processing unit, wherein the input end of the processing unit is respectively connected to the output end of the first CSA and the output end of the second CSA, and the processing unit is used to process the first index, the second index, the first carry value and the first sum value, the second carry value and the second sum value to obtain a target processing result.

[0198] Optionally, the first partial product generating unit includes:

[0199] a merging component, configured to, when the first mantissa includes N bits and N is a positive integer greater than or equal to 2, determine an AND operation to be performed on each bit in the N bits and each bit in the N bits, respectively, to obtain a total of N×N AND operations to be performed; and perform a merging operation on the N×N AND operations to obtain M AND operations, wherein M is less than N×N and is a positive integer greater than or equal to 2;

[0200] The AND operation execution unit is used to execute M AND operations to obtain a first set of partial products.

[0201] Optionally, the above-mentioned merging component includes:

[0202] A replacement device, used to replace the AND operation to be performed between the ith bit and the ith bit of N bits with the ith bit, where i is a positive integer greater than or equal to 1 and less than or equal to N;

[0203] The first shift device is used to combine the AND operation of the i-th bit and the j-th bit among the N bits to be executed at the p-th position and the AND operation of the j-th bit and the i-th bit to be executed at the p-th position into the AND operation of the i-th bit and the j-th bit to be executed at the p+1-th position when i is greater than j.

[0204] Optionally, the processing unit includes:

[0205] A comparator, used to compare the first index with the second index to obtain a comparison result and a first index difference, wherein the comparison result is used to indicate whether the first index is greater than the second index, and the first index difference is the difference between the first index and the second index;

[0206] A processing module is used for, when a comparison result indicates that the first exponent is greater than the second exponent, shifting the second carry value and the second summation value according to the first exponent difference to obtain a third carry value and a third summation value, wherein the third carry value and the third summation value are the same as the exponents corresponding to the first carry value and the first summation value; and processing the first exponent, the third carry value and the third summation value, the first carry value and the first summation value through a processor to obtain a target processing result.

[0207] Optionally, the processing module includes:

[0208] A second shift device, used for shifting the first exponent difference value left by one bit through a processor to obtain a second exponent difference value;

[0209] The third shift device is used for shifting the second carry value and the second sum value by the second exponent difference to obtain a third carry value and a third sum value.

[0210] Optionally, the processing module includes:

[0211] a fourth shift device, configured to shift the first index left by one bit through the processor to obtain a third index;

[0212] a third CSA, configured to add the third carry value and the third sum value, the first carry value and the first sum value, to obtain a fourth carry value and a fourth sum value;

[0213] A fixed-point adder, used for performing fixed-point addition processing on the fourth carry value and the fourth sum value to obtain a third mantissa and a first exponent adjustment value;

[0214] A first processing submodule, configured to adjust the third index using the first index adjustment value to obtain a fourth index;

[0215] A second processing submodule is used for performing normalization processing and rounding processing on the third mantissa to obtain a fourth mantissa;

[0216] The third processing submodule is used to determine the first target data represented by the fourth exponent and the fourth mantissa as the target processing result.

[0217] Optionally, the processing module further includes:

[0218] a fifth shift device, for shifting the first carry value and the first sum value according to the first exponent difference to obtain a fifth carry value and a fifth sum value when the comparison result indicates that the first exponent is less than the second exponent, wherein the fifth carry value and the fifth sum value have the same exponent as the second carry value and the second sum value;

[0219] The fourth processing submodule is used to process the second exponent, the fifth carry value and the fifth sum value, the second carry value and the second sum value to obtain a target processing result.

[0220] Optionally, the processing module further includes:

[0221] a sixth shift device, configured to shift the first exponent difference value left by one bit through a processor to obtain a second exponent difference value;

[0222] The seventh shift device is used to shift the first carry value and the first sum value by the second exponent difference to obtain a fifth carry value and a fifth sum value.

[0223] Optionally, the processing module further includes:

[0224] an eighth shift device, configured to shift the second index left by one bit through the processor to obtain a fifth index;

[0225] a third CSA, configured to add the fifth carry value and the fifth sum value, the second carry value and the second sum value to obtain a sixth carry value and a sixth sum value;

[0226] a fixed-point adder, used for performing fixed-point addition processing on the sixth carry value and the sixth sum value to obtain a fifth mantissa and a second exponent adjustment value;

[0227] a fifth processing submodule, configured to adjust the fifth index by using the second index adjustment value through a processor to obtain a sixth index;

[0228] A sixth processing submodule, used for performing normalization processing and rounding processing on the fifth mantissa to obtain a sixth mantissa;

[0229] The seventh processing submodule is used to determine the second target data represented by the sixth exponent and the sixth mantissa as the target processing result.

[0230] The above-mentioned processor is applied to generate a first group of partial products of the first data by using the first partial product generating unit in the processor; and a second group of partial products of the second data by using the second partial product generating unit in the processor; and then the first group of partial products are added by using the first carry-preserving adder CSA, and the second group of partial products are added by using the second CSA, and the first exponent, the second exponent, the first carry value, the first sum value, the second carry value and the second sum value obtained by the addition process are processed to obtain the target processing result. Among them, the number of AND operations performed in the process of generating the first group of partial products is less than the square of the number of bits of the first mantissa of the first data, and the number of AND operations performed in the process of generating the second group of partial products is less than the square of the number of bits of the second mantissa of the second data, which reduces the number of AND operations of the partial product dot matrix in the square operation process, simplifies the processing flow of the first data and the second data, solves the technical problem of low processing efficiency of the processor in the related technology, and achieves the technical effect of improving the processing efficiency of the processor.

[0231] It should be noted that the embodiment of the processor here can refer to the embodiment of the control method of the above-mentioned processor, which will not be repeated here.

[0232] According to another aspect of the embodiment of the present application, an electronic device for implementing the control method of the processor is also provided. The electronic device may be Fig.10 The terminal device shown in FIG. This embodiment is described by taking the electronic device as a background device as an example. Fig.10 As shown, the electronic device includes a memory 1002 and a processor 1004. The memory 1002 stores a computer program, and the processor 1004 is configured to execute the steps in any of the above method embodiments through the computer program.

[0233] Alternatively, a person skilled in the art may understand that: Fig.10 The structure shown is for illustration only, and the electronic device may also be a target terminal such as a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, and a mobile Internet device (MID), a PAD, etc. Fig.10 The electronic device and the electronic equipment described above are not limited in structure. Fig.10More or fewer components (such as network interfaces, etc.) as shown in, or with Fig.10 Different configurations are shown.

[0234] Among them, the memory 1002 can be used to store software programs and modules, such as program instructions / modules corresponding to the control method of the processor in the embodiment of the present application. The processor 1004 executes various functional applications and data processing by running the software programs and modules stored in the memory 1002, that is, the control method of the processor described above is realized. The memory 1002 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 1002 may further include a memory remotely arranged relative to the processor 1004, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. Among them, the memory 1002 may be specifically used, but not limited to, for storing first data, second data, and target processing results, etc. In addition, it may also include, but is not limited to, other module units in the above-mentioned processor, which will not be repeated in this example.

[0235] Optionally, the transmission device 1006 is used to receive or send data via a network. Specific examples of the above-mentioned network may include a wired network and a wireless network. In one example, the transmission device 1006 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices and routers via a network cable so as to communicate with the Internet or a local area network. In one example, the transmission device 1006 is a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0236] In addition, the electronic device further includes: a display 1008 for displaying the direction prompt information of the target sound; and a connection bus 1010 for connecting various module components in the electronic device.

[0237] In other embodiments, the target terminal or server may be a node in a distributed system, wherein the distributed system may be a blockchain system, and the blockchain system may be a distributed system formed by connecting the multiple nodes in the form of network communication. Among them, the nodes may form a peer-to-peer (P2P) network, and any form of computing device, such as a server, terminal or other electronic device, may become a node in the blockchain system by joining the peer-to-peer network.

[0238] Optionally, in this embodiment, a person of ordinary skill in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the hardware related to the target terminal through a program, and the program may be stored in a computer-readable storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0239] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0240] If the integrated units in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in the above computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling one or more computer devices (which can be personal computers, servers or network devices, etc.) to execute all or part of the steps of the methods of each embodiment of the present application.

[0241] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0242] In the several embodiments provided in the present application, it should be understood that the disclosed client can be implemented in other ways. Among them, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0243] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0244] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0245] The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A method for controlling a processor, characterized in that: include: Inputting a first mantissa of first data into a first partial product generating unit in a processor, and inputting a second mantissa of second data into a second partial product generating unit in the processor, wherein the first data is a floating point number represented by the first mantissa and a first exponent, and the second data is a floating point number represented by the second mantissa and a second exponent; Generate a partial product of the first mantissa and the first mantissa by the first partial product generating unit to obtain a first set of partial products, and generate a partial product of the second mantissa and the second mantissa by the second partial product generating unit to obtain a second set of partial products, wherein the number of AND operations performed in the process of generating the first set of partial products is less than the square of the number of bits of the first mantissa, and the number of AND operations performed in the process of generating the second set of partial products is less than the square of the number of bits of the second mantissa; Performing an addition process on the first group of partial products through a first carry-save adder CSA in the processor to obtain a first carry value and a first sum value, and performing an addition process on the second group of partial products through a second CSA in the processor to obtain a second carry value and a second sum value; The processor processes the first index, the second index, the first carry value and the first sum value, the second carry value and the second sum value to obtain a target processing result.

2. The method according to claim 1, characterized in that Generating the partial product of the first mantissa and the first mantissa by the first partial product generating unit to obtain a first set of partial products includes: When the first mantissa includes N bits, and N is a positive integer greater than or equal to 2, determine an AND operation to be performed on each bit in the N bits and each bit in the N bits, respectively, to obtain a total of N×N AND operations to be performed; The N×N AND operations are combined to obtain M AND operations, where: M is less than N×N, and M is a positive integer greater than or equal to 2; The M AND operations are performed to obtain the first set of partial products.

3. The method according to claim 2, characterized in that The combining operation on the N×N AND operations to obtain M AND operations includes: Replace the AND operation to be performed between the i-th bit of the N bits and the i-th bit with the i-th bit, where i is a positive integer greater than or equal to 1 and less than or equal to N; When i is greater than j, the AND operation between the i-th bit and the j-th bit among the N bits to be performed at the p-th position and the AND operation between the j-th bit and the i-th bit to be performed at the p-th position are combined into the AND operation between the i-th bit and the j-th bit to be performed at the p+1-th position.

4. The method according to claim 1, characterized in that Generating the partial product of the second mantissa and the second mantissa by the second partial product generating unit to obtain a second set of partial products includes: When the second mantissa includes N bits, and N is a positive integer greater than or equal to 2, determine an AND operation to be performed on each bit in the N bits and each bit in the N bits, respectively, to obtain a total of N×N AND operations to be performed; The N×N AND operations are combined to obtain M AND operations, where: M is less than N×N, and M is a positive integer greater than or equal to 2; The M AND operations are performed to obtain the second set of partial products.

5. The method according to claim 1, characterized in that The processing of the first index, the second index, the first carry value and the first sum value, the second carry value and the second sum value by the processor to obtain a target processing result includes: Comparing the first index and the second index by a comparator in the processor to obtain a comparison result and a first index difference, wherein the comparison result is used to indicate whether the first index is greater than the second index, and the first index difference is the difference between the first index and the second index; When the comparison result indicates that the first exponent is greater than the second exponent, shifting the second carry value and the second sum value according to the first exponent difference to obtain a third carry value and a third sum value, wherein the third carry value and the third sum value are the same as the exponents corresponding to the first carry value and the first sum value; The processor processes the first exponent, the third carry value and the third sum value, the first carry value and the first sum value to obtain the target processing result.

6. The method according to claim 5, characterized in that The step of performing shift processing on the second carry value and the second sum value according to the first exponent difference value to obtain a third carry value and a third sum value includes: Left-shifting the first exponent difference by one bit by the processor to obtain a second exponent difference; The second carry value and the second sum value are shifted by the second exponent difference value to obtain the third carry value and the third sum value.

7. The method according to claim 5, characterized in that The processing of the first exponent, the third carry value and the third sum value, the first carry value and the first sum value by the processor to obtain the target processing result includes: Left-shifting the first index by one bit by the processor to obtain a third index; performing, by a third CSA in the processor, an addition process on the third carry value and the third sum value, the first carry value and the first sum value, to obtain a fourth carry value and a fourth sum value; Performing fixed-point addition processing on the fourth carry value and the fourth sum value by a fixed-point adder in the processor to obtain a third mantissa and a first exponent adjustment value; The processor adjusts the third index using the first index adjustment value to obtain a fourth index; The processor performs normalization and rounding processing on the third mantissa to obtain a fourth mantissa; The first target data represented by the fourth exponent and the fourth mantissa is determined as the target processing result.

8. The method according to claim 5, characterized in that The processing of the first index, the second index, the first carry value and the first sum value, the second carry value and the second sum value by the processor to obtain a target processing result further includes: When the comparison result indicates that the first exponent is less than the second exponent, shifting the first carry value and the first sum value according to the first exponent difference to obtain a fifth carry value and a fifth sum value, wherein the fifth carry value and the fifth sum value are the same as the exponents corresponding to the second carry value and the second sum value; The processor processes the second exponent, the fifth carry value and the fifth sum value, the second carry value and the second sum value to obtain the target processing result.

9. The method according to claim 8, characterized in that The step of performing shift processing on the first carry value and the first sum value according to the first exponent difference value to obtain a fifth carry value and a fifth sum value includes: Left-shifting the first exponent difference by one bit by the processor to obtain a second exponent difference; The first carry value and the first sum value are shifted by the second exponent difference value to obtain the fifth carry value and the fifth sum value.

10. The method according to claim 8, characterized in that The processing of the second exponent, the fifth carry value and the fifth sum value, the second carry value and the second sum value by the processor to obtain the target processing result includes: Left-shifting the second index by one bit by the processor to obtain a fifth index; performing, by a third CSA in the processor, an addition process on the fifth carry value and the fifth sum value, the second carry value and the second sum value to obtain a sixth carry value and a sixth sum value; Performing fixed-point addition processing on the sixth carry value and the sixth sum value by a fixed-point adder in the processor to obtain a fifth mantissa and a second exponent adjustment value; The processor adjusts the fifth index using the second index adjustment value to obtain a sixth index; The processor performs normalization and rounding processing on the fifth mantissa to obtain a sixth mantissa; The second target data represented by the sixth exponent and the sixth mantissa is determined as the target processing result.

11. The method according to any one of claims 1 to 10, characterized in that The first data and the second data are data used to perform a target operation in a target neural network model, wherein the target processing result is a result obtained by performing the target operation on the first data and the second data; In a case where the target neural network model is a model for image recognition, the first data and the second data are data related to an image; In a case where the target neural network model is a model for audio recognition, the first data and the second data are data related to audio; In a case where the target neural network model is a model for information synthesis, the first data and the second data are information-related data.

12. A processor, characterized in that: include: A first partial product generating unit, configured to generate a partial product of a first mantissa of first data and the first mantissa to obtain a first set of partial products, wherein the first data is a floating point number represented by the first mantissa and a first exponent; A second partial product generating unit, configured to generate a partial product of a second mantissa of second data and the second mantissa to obtain a second set of partial products, wherein the second data is a floating point number represented by the second mantissa and a second exponent; a first carry-save adder CSA, wherein an input end of the first CSA is connected to an output end of the first partial product generating unit, and the first CSA is used to perform an addition process on the first group of partial products to obtain a first carry value and a first sum value; a second CSA, wherein an input end of the second CSA is connected to an output end of the second partial product generating unit, and the second CSA is used to perform an addition process on the second group of partial products to obtain a second carry value and a second sum value; A processing unit, wherein the input end of the processing unit is respectively connected to the output end of the first CSA and the output end of the second CSA, and the processing unit is used to process the first index, the second index, the first carry value and the first sum value, the second carry value and the second sum value to obtain a target processing result.

13. The processor according to claim 12, characterized in that The first partial product generating unit comprises: A merging component is used to determine, when the first mantissa includes N bits and N is a positive integer greater than or equal to 2, an AND operation to be performed on each bit in the N bits and each bit in the N bits, respectively, to obtain a total of N×N AND operations to be performed; and perform a merging operation on the N×N AND operations to obtain M AND operations, wherein, M is less than N×N, and M is a positive integer greater than or equal to 2; An AND operation execution component is used to execute the M AND operations to obtain the first group of partial products.

14. The processor according to claim 13, characterized in that The merging component comprises: A replacement device, used for replacing the AND operation to be performed between the i-th bit of the N bits and the i-th bit with the i-th bit, wherein i is a positive integer greater than or equal to 1 and less than or equal to N; The first shift device is used to combine the AND operation of the i-th bit and the j-th bit among the N bits to be executed at the p-th position and the AND operation of the j-th bit and the i-th bit to be executed at the p-th position into the AND operation of the i-th bit and the j-th bit to be executed at the p+1-th position when i is greater than j.

15. The processor according to claim 12, wherein: The processing unit comprises: a comparator, configured to compare the first index with the second index to obtain a comparison result and a first index difference, wherein the comparison result is used to indicate whether the first index is greater than the second index, and the first index difference is a difference between the first index and the second index; A processing module is used for, when the comparison result indicates that the first exponent is greater than the second exponent, shifting the second carry value and the second summation value according to the first exponent difference to obtain a third carry value and a third summation value, wherein the third carry value and the third summation value are the same as the exponents corresponding to the first carry value and the first summation value; and processing the first exponent, the third carry value and the third summation value, the first carry value and the first summation value by the processor to obtain the target processing result.

16. The processor according to claim 15, characterized in that The processing module comprises: a second shift device, configured to shift the first exponent difference value left by one bit through the processor to obtain a second exponent difference value; The third shift device is used to shift the second carry value and the second sum value by the second exponent difference to obtain the third carry value and the third sum value.

17. The processor according to claim 15, characterized in that The processing module comprises: a fourth shift device, configured to shift the first index left by one bit through the processor to obtain a third index; a third CSA, configured to add the third carry value and the third sum value, the first carry value and the first sum value to obtain a fourth carry value and a fourth sum value; a fixed-point adder, configured to perform fixed-point addition processing on the fourth carry value and the fourth sum value to obtain a third mantissa and a first exponent adjustment value; A first processing submodule, configured to adjust the third index using the first index adjustment value to obtain a fourth index; A second processing submodule is used to perform normalization and rounding processing on the third mantissa to obtain a fourth mantissa; The third processing submodule is used to determine the first target data represented by the fourth exponent and the fourth mantissa as the target processing result.

18. The processor according to claim 15, characterized in that The processing module further includes: a fifth shifting device, configured to shift the first carry value and the first sum value according to the first exponent difference to obtain a fifth carry value and a fifth sum value when the comparison result indicates that the first exponent is less than the second exponent, wherein the fifth carry value and the fifth sum value have the same exponent as the second carry value and the second sum value; The fourth processing submodule is used to process the second exponent, the fifth carry value and the fifth sum value, the second carry value and the second sum value to obtain the target processing result.

19. The processor according to claim 18, characterized in that The processing module further includes: a sixth shift device, configured to shift the second index left by one bit through the processor to obtain a fifth index; a third CSA, configured to add the fifth carry value and the fifth sum value, the second carry value and the second sum value to obtain a sixth carry value and a sixth sum value; a fixed-point adder, configured to perform fixed-point addition processing on the sixth carry value and the sixth sum value to obtain a fifth mantissa and a second exponent adjustment value; a fifth processing submodule, configured to adjust the fifth index by using the second index adjustment value through the processor to obtain a sixth index; a sixth processing submodule, configured to perform normalization and rounding processing on the fifth mantissa to obtain a sixth mantissa; The seventh processing submodule is used to determine the second target data represented by the sixth exponent and the sixth mantissa as the target processing result.

20. An electronic device comprising the processor as claimed in any one of claims 12 to 19.

Images