True random number sequence generator, chip and electronic equipment

Abstract

The invention provides a true random number sequence generator, a chip and electronic equipment, and belongs to the technical field of electronics. The true random number sequence generator comprises a processing circuit and M entropy source acquisition circuits, each entropy source acquisition circuit is configured to output a random sequence, the random sequences output by different entropy source acquisition circuits are different, and M is an integer not less than 2; and the processing circuit is connected with each entropy source acquisition circuit, and the processing circuit is configured to perform XOR processing on the random sequence output by each entropy source acquisition circuit to obtain a random number. According to the application, the random sequences output by the M entropy source acquisition circuits are subjected to XOR processing, so that random numbers with better quality can be obtained.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and specifically relates to a true random number sequence generator, a chip and an electronic device. Background Art

[0002] True Random Number Generator (TRNG) has a wide range of applications in statistics, information security and other fields. In chip or system design, it is often used for statistics, encryption, information entropy related algorithm implementation, etc. In these fields, the data sequences generated by TRNG are not only required to be evenly distributed and independent of each other, but also required to be unpredictable and able to resist attacks against randomness. When evaluating the quality of random numbers generated by TRNG, my country's national secret standard GM / T0005-2021 "Randomness Detection Specification" points out: The inspection should be carried out for 100,000 random numbers of 1048576 bits (or 1000000 bits) continuously generated by TRNG, divided into 100 tests (that is, 1000 random numbers generated by 1048576 bits each time), and the minimum pass rate of each test and the number of tests with a pass rate of not less than 98.1% should be counted.

[0003] The structure of the most commonly used TRNG in digital chips is as follows Figure 1 As shown. This TRNG adopts the principle of clock acquisition circuit. Two clock sources exist as entropy sources, a DFF (Data Flip Flop) is used as the acquisition circuit, and the outputs of the high-frequency clock source and the low-frequency clock source are used as the inputs of the D end and the CLK end of the DFF respectively. Both the high-frequency clock source and the low-frequency clock source are ring oscillators composed of digital standard units (buffers and inverters). The frequencies of the two clock sources generally meet a fixed ratio, usually (2M+1) / 2, where M is a positive integer.

[0004] Figure 1 The TRNG in the manner shown easily causes the DFF output sequence to have a periodic "101010" sequence and lack of randomness, so that the randomness quality of the generated random numbers is limited. For example, for the aforementioned "Randomness Detection Specification", the pass rate of each detection of 1000 1048576-bit random outputs is often less than 95%, and the number of detections with a pass rate of not less than 98.1% for every 100 detections is often less than 50 times. Summary of the invention

[0005] In view of this, the purpose of the present application is to provide a true random number sequence generator, a chip and an electronic device to improve the output efficiency and quality of the random number sequence output by the true random number sequence generator.

[0006] The embodiment of the present application is implemented as follows:

[0007] In a first aspect, an embodiment of the present application provides a true random number sequence generator, comprising: a processing circuit and M entropy source acquisition circuits, each entropy source acquisition circuit is configured to output a random sequence, and the random sequences output by different entropy source acquisition circuits are different, and M is an integer not less than 2; the processing circuit is connected to each entropy source acquisition circuit, and the processing circuit is configured to perform XOR processing on the random sequence output by each entropy source acquisition circuit to obtain a random number.

[0008] In the above embodiment, M entropy source acquisition circuits are designed and different entropy source acquisition circuits output different random sequences. Then, a processing circuit is used to perform XOR processing on the random sequence output by each entropy source acquisition circuit. This can further improve the output efficiency and quality of the random number sequence output by the true random number sequence generator.

[0009] In combination with a possible implementation manner of the embodiment of the first aspect, the M entropy source acquisition circuits include N entropy source acquisition circuits of different types, where N is an integer not less than 2.

[0010] In the above embodiments, a plurality of different types of entropy source acquisition circuits are designed so that the randomness quality of the random sequence finally formed is better.

[0011] In combination with a possible implementation manner of the embodiment of the first aspect, the M entropy source acquisition circuits include: a first entropy source acquisition circuit, a second entropy source acquisition circuit and a third entropy source acquisition circuit; the first entropy source acquisition circuit is configured to generate a random sequence based on a ring oscillator; the second entropy source acquisition circuit is configured to generate a random sequence based on a relaxation oscillator; the third entropy source acquisition circuit is configured to generate a random sequence based on a chaotic circuit.

[0012] In the above embodiment, three entropy source acquisition circuits based on different principles are designed to make the randomness quality of the random sequence finally formed better.

[0013] In combination with a possible implementation manner of the embodiment of the first aspect, the first entropy source acquisition circuit includes: a first entropy source, a second entropy source and a first acquisition circuit; the first entropy source is configured to generate a first clock source based on two ring oscillators with different frequencies; the second entropy source is configured to generate a second clock source based on two ring oscillators with different frequencies, wherein the frequency of the first clock source is less than the frequency of the second clock source; the first acquisition circuit is connected to the first entropy source and the second entropy source respectively, and the first acquisition circuit is configured to sample the second clock source based on the first clock source and output a random sequence.

[0014] In the above embodiment, the first entropy source acquisition circuit of the above structure is adopted, so that the clock source output by the first entropy source and the second entropy source is a clock source in which the clock jitter of the clock signal generated by another ring oscillator is superimposed on the clock signal generated by one of the ring oscillators, and then a random sequence is obtained based on such a clock source, so that the obtained random sequence has better randomness and is less likely to show periodic characteristics.

[0015] In combination with a possible implementation manner of the embodiment of the first aspect, the first entropy source includes: a first ring oscillator, a second ring oscillator, and a trigger; the first ring oscillator is configured to generate a first initial clock source; the second ring oscillator is configured to generate a second initial clock source, the frequency of the second initial clock source is greater than the frequency of the first initial clock source, and is not an integer ratio with the frequency of the first initial clock source; the trigger is connected to the first ring oscillator and the second ring oscillator, respectively, and the trigger is configured to sample the first initial clock source based on the second initial clock source to obtain the first clock source.

[0016] In the above embodiment, since the frequency of the second initial clock source is greater than the frequency of the first initial clock source and is not an integer ratio with the frequency of the first initial clock source, when the first initial clock source is sampled based on the second initial clock source, the clock jitter of the second initial clock source will be superimposed on the first initial clock source, thereby generating an irregular first clock source.

[0017] In combination with a possible implementation manner of the embodiment of the first aspect, the first entropy source also includes: a selector, a first input end of the selector is connected to the first ring oscillator, a second input end of the selector is connected to the output end of the trigger, and an output end of the selector is connected to the first acquisition circuit.

[0018] In the above embodiment, a selector is provided so that different signal outputs can be selected through the selector, thereby improving the flexibility and applicability of the solution.

[0019] In combination with a possible implementation manner of the embodiment of the first aspect, the first entropy source acquisition circuit also includes: a third entropy source, a second acquisition circuit, and a first selection circuit; the third entropy source is configured to generate a third clock source based on two ring oscillators with different frequencies, wherein the frequency of the first clock source is less than the frequency of the third clock source; the second acquisition circuit is respectively connected to the first entropy source and the third entropy source, and the second acquisition circuit is configured to sample the third clock source based on the first clock source and output a random sequence; the first selection circuit is respectively connected to the first acquisition circuit and the second acquisition circuit, and the first selection circuit is configured to select and output the random sequence output by the first acquisition circuit or the second acquisition circuit.

[0020] In the above embodiment, by further setting the third entropy source, the second acquisition circuit and the first selection circuit, the first selection circuit can be used to select and output the random sequence output by the first acquisition circuit or the second acquisition circuit, so as to improve the flexibility and applicability of the solution.

[0021] In combination with a possible implementation manner of the embodiment of the first aspect, the first entropy source acquisition circuit also includes: a third acquisition circuit, which is respectively connected to the first entropy source, the second entropy source, the third entropy source and the first selection circuit, and the third acquisition circuit is configured to sample the XOR result of the second clock source and the third clock source based on the first clock source, and output a random sequence.

[0022] In the above embodiment, a third acquisition circuit is further provided to sample the XOR result of the second clock source and the third clock source, so that a random sequence output by the first acquisition circuit, the second acquisition circuit or the third acquisition circuit can be selected and output.

[0023] In combination with a possible implementation manner of the embodiment of the first aspect, the first selection circuit includes: a first selector, a second selector, and a third selector; the first input end of the first selector is connected to the first acquisition circuit, and the second input end of the first selector is connected to the second acquisition circuit; the first input end of the second selector is used to receive an XOR result of a random sequence output by the first acquisition circuit and a random sequence output by the second acquisition circuit, and the second input end of the second selector is connected to the third acquisition circuit; the first input end of the third selector is connected to the output end of the first selector, and the second input end of the third selector is connected to the output end of the second selector.

[0024] In the above embodiment, a selection circuit including a first selector, a second selector, and a third selector is used to flexibly select the required output signal, thereby improving the configurability of the first entropy source acquisition circuit to meet the needs of various usage scenarios.

[0025] In combination with a possible implementation manner of the embodiment of the first aspect, the second entropy source acquisition circuit includes: a relaxation oscillator for generating a third clock source, wherein the third clock source is related to the random sequence generated by the second entropy source acquisition circuit, and the relaxation oscillator includes: a current mirror, a load capacitor, an inverting amplifier circuit, and a feedback circuit; the current mirror is respectively connected to a power supply and a digital ground; the load capacitor is respectively connected to the current mirror and the digital ground; the inverting amplifier circuit is respectively connected to a power supply, a digital ground, and the load capacitor; the feedback circuit is respectively connected to an output end of the inverting amplifier circuit, the current mirror, and the digital ground, and the target position of the feedback circuit is used to output the third clock source; wherein, when the load capacitor is discharged through the current mirror, the terminal voltage of the load capacitor gradually decreases, and after passing through the inverting amplifier circuit, a gradually increasing first drive signal is outputted, and when the first drive signal is greater than the flip threshold of the feedback circuit, the feedback circuit controls the current mirror to charge the load capacitor; when the current mirror charges the load capacitor, the terminal voltage of the load capacitor gradually increases, and after passing through the inverting amplifier circuit, a gradually decreasing second drive signal is outputted, and when the second drive signal is less than the flip threshold of the feedback circuit, the feedback circuit controls the current mirror to discharge the load capacitor.

[0026] In the above embodiment, the relaxation oscillator using the above structure can simplify the circuit structure while achieving the purpose of the invention, thereby reducing the circuit area and implementation difficulty, compared with other relaxation oscillators.

[0027] In combination with a possible implementation manner of the embodiment of the first aspect, the third entropy source acquisition circuit includes: a first oscillator, a second oscillator, a chaotic circuit, and a full-swing circuit; the first oscillator is configured to generate a first signal; the second oscillator is configured to generate a second signal; the chaotic circuit is connected to the first oscillator and the second oscillator, respectively, and the chaotic circuit is configured to generate a third signal with an uncertain state based on the first signal and the second signal; the full-swing circuit is connected to the chaotic circuit, and the full-swing circuit is configured to generate a fourth clock source determined based on the state of the third signal, wherein the fourth clock source is related to the random sequence generated by the three entropy source acquisition circuit.

[0028] In the above embodiment, a chaotic circuit is used to generate a third signal with an uncertain state (such as a signal that is not all 1, 0, such a state-determined signal, but also includes an intermediate state between 0 and 1) based on the first signal and the second signal to improve randomness, and then a full-swing circuit is used to determine the fourth clock source based on the state generated by the third signal (only including 1, 0, such a state-determined signal), so that the randomness of the random sequence finally generated is better and the quality is higher. In combination with a possible implementation of the embodiment of the first aspect, the true random number sequence generator also includes: a second selection circuit, which is respectively connected to the M entropy source acquisition circuits and the processing circuit, and the second selection circuit is configured to select the number of entropy source acquisition circuits connected to the processing circuit.

[0029] In the above embodiment, the second selection circuit is used to select the number of entropy source acquisition circuits connected to the processing circuit, so that the M entropy source acquisition circuits can work independently or collaboratively. By combining different types of entropy source acquisition circuits, a better random number output effect can be obtained.

[0030] In a second aspect, an embodiment of the present application further provides a chip, comprising a true random number sequence generator as provided in the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment.

[0031] In a third aspect, an embodiment of the present application further provides an electronic device, including: a chip as provided in the embodiment of the second aspect above.

[0032] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The above and other purposes, features and advantages of the present application will be more clear as shown in the drawings.

[0034] Figure 1 The figure is a schematic diagram of the structure of a true random number sequence generator in the related art.

[0035] Figure 2 A schematic structural diagram of a true random number sequence generator provided in an embodiment of the present application is shown.

[0036] Figure 3A schematic structural diagram of a first entropy source acquisition circuit provided in an embodiment of the present application is shown.

[0037] Figure 3a A schematic diagram of the principle of a first entropy source acquisition circuit provided in an embodiment of the present application is shown.

[0038] Figure 3b A schematic diagram of the principle of a second first entropy source acquisition circuit provided in an embodiment of the present application is shown.

[0039] Figure 4 A schematic structural diagram of a second first entropy source acquisition circuit provided in an embodiment of the present application is shown.

[0040] Figure 4a A schematic diagram of the principle of a third first entropy source acquisition circuit provided in an embodiment of the present application is shown.

[0041] Figure 5 A schematic structural diagram of a third first entropy source acquisition circuit provided in an embodiment of the present application is shown.

[0042] Figure 5a A schematic diagram of the principle of a fourth first entropy source acquisition circuit provided in an embodiment of the present application is shown.

[0043] Figure 5b A principle schematic diagram of a fifth first entropy source acquisition circuit provided in an embodiment of the present application is shown.

[0044] Figure 6 A schematic structural diagram of a first relaxation oscillator provided in an embodiment of the present application is shown.

[0045] Figure 6a A schematic diagram of the principle of a first relaxation oscillator provided in an embodiment of the present application is shown.

[0046] Figure 6b A schematic diagram of the principle of a first relaxation oscillator provided in an embodiment of the present application is shown.

[0047] Figure 7 A schematic diagram of the structure of an entropy source circuit in a third entropy source acquisition circuit provided in an embodiment of the present application is shown.

[0048] Figure 7a A schematic diagram of the principle of an entropy source circuit in a third entropy source acquisition circuit provided in an embodiment of the present application is shown.

[0049] Figure 8 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0051] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0052] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0053] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0054] Given that Figure 1 The output sequence (random number) generated by the true random number generator (TRNG) shown has limited random number quality, which makes the output sequence have a low pass rate for randomness detection according to national secret standards. Based on this, an embodiment of the present application provides a configurable true random number generator composed of multiple entropy sources to further improve the output efficiency and quality of the random number sequence and improve the flexibility of use.

[0055] Combine the following Figure 2 The principle of the true random number sequence generator provided in the embodiment of the present application is described. The true random number sequence generator includes: a processing circuit and M entropy source acquisition circuits, and the M entropy source acquisition circuits are all connected to the processing circuit. In a possible implementation, the M entropy source acquisition circuits may include N different types of entropy source acquisition circuits. It can be understood that Figure 2Only the case of N=3 is shown, and N is not limited to 3. For example, N may also be 1. In this case, the M entropy source acquisition circuits are all of the same type.

[0056] In one possible implementation, the M entropy source acquisition circuits include N entropy source acquisition circuits of different types, and each entropy source acquisition circuit is configured to output a random sequence, wherein the random sequence output by each entropy source acquisition circuit is different, and M and N are integers not less than 2. The processing circuit is connected to each entropy source acquisition circuit, and the processing circuit is configured to perform XOR processing on the random sequence output by each entropy source acquisition circuit to obtain a random number. By combining M and N entropy source acquisition circuits, a better random number output effect can be formed.

[0057] The processing circuit may include an XOR hardware circuit for performing XOR processing on the random sequence output by each entropy source acquisition circuit. In one possible implementation, the processing circuit may include a programmable device, and the XOR logic may be implemented by firmware burned into the programmable device.

[0058] Each of the above entropy source acquisition circuits may be an analog circuit, a digital circuit, or a combination of an analog circuit and a digital circuit.

[0059] When M=N=2, the true random number sequence generator includes 2 types of entropy source acquisition circuits, and the number of each entropy source acquisition circuit is one. When M is greater than 2 and N=2, the true random number sequence generator includes 2 types of entropy source acquisition circuits, and the number of each entropy source acquisition circuit is one or more. Usually M is greater than or equal to N, that is, the number of entropy source acquisition circuits is greater than or equal to the types of entropy source acquisition circuits. In other words, the number of at least one entropy source acquisition circuit is greater than 1. When the number of a certain entropy source acquisition circuit is multiple, although these multiple entropy source acquisition circuits generate random sequences based on the same principle, the random sequences generated by each entropy source acquisition circuit are different.

[0060] In one possible implementation, the M entropy source acquisition circuits include: a first entropy source acquisition circuit, a second entropy source acquisition circuit, and a third entropy source acquisition circuit. In some possible implementations, the true random number sequence generator includes 8 entropy source acquisition circuits, and the 8 entropy source acquisition circuits are composed of 3 types of entropy source acquisition circuits, for example, including 2 first entropy source acquisition circuits, 4 second entropy source acquisition circuits, and 2 third entropy source acquisition circuits, wherein the random sequences generated by the 2 first entropy source acquisition circuits are different, the random sequences generated by the 4 second entropy source acquisition circuits are different, and the random sequences generated by the 2 third entropy source acquisition circuits are different. These 8 entropy source acquisition circuits can work independently or in collaboration. By combining different types of entropy source acquisition circuits, a better random number output effect can be obtained.

[0061] The first entropy source acquisition circuit is configured to generate a random sequence based on a ring oscillator. The second entropy source acquisition circuit is configured to generate a random sequence based on a relaxation oscillator. The third entropy source acquisition circuit is configured to generate a random sequence based on a chaotic circuit. The embodiment of the present application combines the random sequences generated by three different principles to output random numbers with better random number quality.

[0062] In one possible way, the schematic diagram of the first entropy source acquisition circuit can be as follows: Figure 3 As shown, it includes: a first entropy source, a second entropy source and a first acquisition circuit. The first acquisition circuit is connected to the first entropy source and the second entropy source respectively, and the first acquisition circuit is configured to sample the second clock source generated by the second entropy source based on the first clock source generated by the first entropy source, and output a random sequence.

[0063] The first acquisition circuit may include a D flip-flop (Data Flip-Flop). In some possible implementations, the first entropy source and the second entropy source correspond to Figure 1 The low-frequency clock source and high-frequency clock source shown in FIG. 1 are shown in FIG. 1 . At this time, the circuit diagram of the first entropy source acquisition circuit is equivalent to Figure 1 The circuit diagram shown. Among them, Figure 1 The low-frequency clock source and high-frequency clock source are relative. For example, for a high-frequency clock source, as long as the frequency of the high-frequency clock source is greater than or equal to the frequency of the low-frequency clock source with a specified multiple (such as 3.5 times), it is not that its frequency must be greater than a certain frequency to be called a high-frequency clock source. For a low-frequency clock source, the frequency is usually not less than MHz.

[0064] In some possible implementations, the first entropy source is configured to generate a first clock source based on two ring oscillators with different frequencies. The second entropy source is configured to generate a second clock source based on two ring oscillators with different frequencies, wherein the frequency of the first clock source is less than the frequency of the second clock source. The present application generates a clock source based on two ring oscillators with different frequencies, so that the generated clock source can achieve the superposition of clock jitter, which is conducive to improving the uncertainty of random numbers.

[0065] In some possible implementations, the first entropy source includes: a first ring oscillator (such as represented by ring oscillator 1A), a second ring oscillator (such as represented by ring oscillator 2B) and a trigger (DFF1), such as Figure 3a . Figure 3a In the figure, ring oscillator 1A represents the first ring oscillator in the first entropy source, ring oscillator 1B represents the second ring oscillator in the first entropy source, ring oscillator 2A represents the first ring oscillator in the second entropy source, and ring oscillator 2B represents the second ring oscillator in the second entropy source. Figure 3a DDF4 in FIG. 1 is a trigger included in the first acquisition circuit.

[0066] The first ring oscillator is configured to generate a first initial clock source (which may be referred to as an A clock signal). The second ring oscillator is configured to generate a second initial clock source (which may be referred to as a B clock signal). The frequency of the second initial clock source is f B Greater than the frequency f of the first initial clock source A , and the frequency of the first initial clock source is not an integer ratio, for example, f B >2f A , and f B and f A is not an integer ratio. In one possible implementation, f B The frequency corresponds to f A 4 to 5 times of , if it is not an integer ratio, the more irregular the better.

[0067] The trigger is connected to the first ring oscillator and the second ring oscillator respectively, and the trigger is configured to sample the first initial clock source based on the second initial clock source to obtain the first clock source. Since the sampling clock frequency of the trigger is higher than the frequency of the first initial clock source as data, the clock jitter of the second initial clock source can be superimposed on the first initial clock source. A The clock signal A is used as the D input of the trigger, with a frequency of f B Another non-isochronous clock B is used as the CLK input of the trigger. The maximum delay of the new clock after sampling compared to the edge of the clock signal A is 1 / f B , the minimum delay is 0. If the frequency is f B The clock frequency is f A The trigger is sampled by the clock, and the jitter of the trigger output signal is about 1 / f B .

[0068] In some possible implementations, the first entropy source further includes: a selector (such as represented by X1), a first input end of the selector is connected to the first ring oscillator, a second input end of the selector is connected to the output end of the trigger, and an output end of the selector is connected to the first acquisition circuit, and its schematic diagram is as follows: Figure 3b As shown. That is, the signal at the first input end of the selector is the first initial clock source, and the signal at the second input end of the selector is the first clock source. Using the method shown in the present application, the selector can be used to select whether the signal input to the D end of the first acquisition circuit is the first initial clock source or the first clock source. The selector can be controlled by CONF[0]. For example, when CONF[0]=1, the selector selects to output the first clock source, and when CONF[0]=0, the selector selects to output the first initial clock source.

[0069] The structure of the second entropy source is similar to that of the first entropy source. For example, in some possible implementations, the second entropy source includes: a first ring oscillator (such as represented by ring oscillator 2A), a second ring oscillator (such as represented by ring oscillator 2B) and a trigger (DFF2), and its schematic diagram is as follows Figure 3a In some other possible implementations, the second entropy source further includes: a selector (such as represented by X2), whose schematic diagram is shown in Figure 3b As shown, the specific principle can refer to the description of the first entropy source.

[0070] In a possible implementation mode, the first entropy source acquisition circuit further includes: a third entropy source, a second acquisition circuit, and a first selection circuit. Figure 4 Show.

[0071] The third entropy source is configured to generate a third clock source based on two ring oscillators with different frequencies, wherein the frequency of the first clock source is less than the frequency of the third clock source, wherein the frequency of the first clock source, the frequency of the second clock source, and the frequency of the third clock source are different from each other.

[0072] The structure of the third entropy source is similar to that of the first entropy source and the second entropy source. For example, in some possible implementations, the third entropy source includes: a first ring oscillator (such as represented by ring oscillator 3A), a second ring oscillator (such as represented by ring oscillator 3B) and a trigger (DFF3). In some other possible implementations, the third entropy source also includes: a selector (such as represented by X3), and its specific principle can refer to the description of the first entropy source.

[0073] The second acquisition circuit is connected to the first entropy source and the third entropy source respectively, and the second acquisition circuit is configured to sample the third clock source based on the first clock source and output a random sequence. The structure of the second acquisition circuit can be similar to that of the first acquisition circuit, for example, it can include a trigger (such as DFF5).

[0074] The first selection circuit is connected to the first acquisition circuit and the second acquisition circuit respectively, and the first selection circuit is configured to select and output the random sequence output by the first acquisition circuit or the second acquisition circuit.

[0075] In one implementation, the first selection circuit may include a selector (such as represented by X4), which may be a two-or-one selector, and the selector is used to select and output the random sequence output by the first acquisition circuit or the second acquisition circuit.

[0076] In another embodiment, the first selection circuit may include a first selector (such as represented by X4) and a second selector (such as represented by X5), and its schematic diagram is as follows: Figure 4aAs shown. The first input end of the first selector is connected to the first acquisition circuit (DFF4), and the second input end of the first selector is connected to the second acquisition circuit (DFF5). The first input end of the second selector is used to receive the XOR result of the random sequence output by the first acquisition circuit and the random sequence output by the second acquisition circuit, and the second input end of the second selector is connected to the output end of the first selector.

[0077] In some possible implementations, the first entropy source acquisition circuit further includes a third acquisition circuit, which is respectively connected to the first entropy source, the second entropy source, the third entropy source and the first selection circuit, and its schematic diagram is as follows: Figure 5 The third acquisition circuit is configured to sample the XOR result of the second clock source and the third clock source based on the first clock source, and output a random sequence. The structure of the third acquisition circuit can be similar to that of the first acquisition circuit, for example, it can include a trigger (such as DFF6).

[0078] exist Figure 5 In the embodiment shown, the first selection circuit may include a selector (select one from three), and the selector is used to select and output the random sequence output by the first acquisition circuit, the second acquisition circuit or the third acquisition circuit. The principle diagram is as follows Figure 5a , Figure 5a X4 in FIG. 1 represents a first selection circuit.

[0079] In another embodiment, the first selection circuit may include a first selector (such as represented by X4), a second selector (such as represented by X5), and a third selector (such as represented by X6), and its schematic diagram is as follows: Figure 5b As shown. The first input end of the first selector is connected to the first acquisition circuit, and the second input end of the first selector is connected to the second acquisition circuit. The first input end of the second selector is used to receive the XOR result of the random sequence output by the first acquisition circuit and the random sequence output by the second acquisition circuit, and the second input end of the second selector is connected to the third acquisition circuit. The first input end of the third selector is connected to the output end of the first selector, and the second input end of the third selector is connected to the output end of the second selector.

[0080] by Figure 5b Taking the first entropy source acquisition circuit shown as an example, the first entropy source acquisition circuit can be configured through CONF[0]~CONF[4] so that the random sequence output by it is configurable, thereby obtaining a better random number output effect. In practical applications, the values ​​of CONF[0]~CONF[4] can be continuously switched in a certain way through software or algorithms to achieve the best random number output effect.

[0081] CONF[0]=0, the output of ring oscillator 1A is used as the output of the first entropy source; CONF[0]=1, the output of ring oscillator 1B is used for output sampling of ring oscillator 1A, so that the output jitter of ring oscillator 1B is superimposed on the output of ring oscillator 1A as the output of the first entropy source.

[0082] CONF[1]=0, the output of ring oscillator 2A is used as the output of the second entropy source; CONF[1]=1, the output of ring oscillator 2B is used for sampling the output of ring oscillator 1A, so that the output jitter of ring oscillator 2B is superimposed on the output of ring oscillator 2A as the output of the second entropy source.

[0083] CONF[2]=0, the output of ring oscillator 3A is used as the output of the third entropy source; CONF[2]=1, the output of ring oscillator 3B is used for output sampling of ring oscillator 3A, so that the output jitter of ring oscillator 3B is superimposed on the output of ring oscillator 3A as the output of the third entropy source.

[0084] CONF[4:3]=00, the first entropy source acquisition circuit outputs the sampling result of DFF5; CONF[4:3]=01, the first entropy source acquisition circuit outputs the sampling result of DFF4; CONF[4:3]=10, the first entropy source acquisition circuit outputs the XOR result of the sampling result of DDF4 and the sampling result of DFF5; CONF[4:3]=11, the first entropy source acquisition circuit outputs the sampling result of DFF6.

[0085] Combining the above situations, we can see that the six ring oscillators can be connected to the circuit in different ways through different configurations, which can increase clock jitter and improve the unpredictability of DFF sampling through XOR operations. CONF[4:0] can be controlled to switch continuously in a certain way to achieve the best random number output effect.

[0086] The overall structure of the second entropy source acquisition circuit is Figure 1 The structures shown are similar, for example, both include two clock sources with different frequencies and an acquisition circuit, but the difference is that the implementation principle of the clock source is different. For example, the second entropy source acquisition circuit includes: a relaxation oscillator for generating a third clock source, and the third clock source is related to the random sequence generated by the second entropy source acquisition circuit. The relaxation oscillator can be used to replace Figure 1 The original low-frequency clock source can be sampled by the third clock source generated by the relaxation oscillator to obtain a random sequence. Since the relaxation oscillator is an analog circuit, the clock jitter and PVT (short for Process, Voltage, and Temperature) in the circuit vary more, which can also make the DFF present a more irregular sampling characteristic. In some possible implementations, the relaxation oscillator can also be used to replace Figure 1 The original high-frequency clock source.

[0087] In some possible implementations, the relaxation oscillator includes: a current mirror, a load capacitor, an inverting amplifier circuit, and a feedback circuit, and its schematic diagram is as follows: Figure 6 As shown. The current mirror is connected to the power supply and the digital ground respectively. The load capacitor is connected to the current mirror and the digital ground respectively. The inverting amplifier circuit is connected to the power supply, the digital ground, and the load capacitor respectively. The feedback circuit is connected to the output end of the inverting amplifier circuit, the current mirror, and the digital ground respectively, and the target position of the feedback circuit is used to output the third clock source.

[0088] Among them, when the load capacitor is discharged through the current mirror, the terminal voltage of the load capacitor gradually decreases, and after passing through the inverting amplifier circuit, a gradually increasing first drive signal is output. When the first drive signal increases to be greater than the flip threshold of the feedback circuit, the feedback circuit controls the current mirror to charge the load capacitor; when the current mirror charges the load capacitor, the terminal voltage of the load capacitor gradually increases, and after passing through the inverting amplifier circuit, a gradually decreasing second drive signal is output. When the second drive signal decreases to be less than the flip threshold of the feedback circuit, the feedback circuit controls the current mirror to discharge the load capacitor; this cycle repeats, the load capacitor is repeatedly charged and discharged, and oscillation is formed.

[0089] In one embodiment, the current mirror includes 4 transistors, including 2 P-type transistors and 2 N-type transistors, wherein a P-type transistor is connected in series with an N-type transistor, two P-type transistors are connected in parallel, the two P-type transistors share a gate and are driven by a bias voltage VBB, the two N-type transistors share a gate and are connected to the drain of the N-type transistor, the source of the N-type transistor is grounded, and the source of the P-type transistor is connected to a power supply. The drain of one of the N-type transistors is connected to a feedback circuit, and the drain of the other N-type transistor is connected to a load capacitor.

[0090] In one embodiment, the inverting amplifier circuit can be a single-tube single-stage inverting amplifier, which includes two transistors, including a P-type transistor and an N-type transistor, the P-type transistor and the N-type transistor are connected in series, the source of the P-type transistor is connected to the power supply, the source of the N-type transistor is grounded, the gate of the P-type transistor is driven by a bias voltage VBB, the gate of the N-type transistor is connected to the load capacitor, and the drain of the N-type transistor (the drain of the P-type transistor) is connected to the feedback circuit. In addition, the inverting amplifier circuit can also be a dual-tube dual-stage inverting amplifier.

[0091] In one implementation, the feedback circuit includes multiple stages of inverters and feedback transistors connected in series, for example, including: an even-numbered series of inverters and N-type transistors (or including an odd-numbered series of inverters and P-type transistors). The first stage of the inverter is connected to the inverting amplifier circuit, the last stage output of the inverter is connected to the gate of the N-type transistor, the source of the N-type transistor is grounded, and the drain of the N-type transistor is connected to the current mirror, specifically, it can be connected to the drain of the current mirror N-type transistor. In some possible implementations, the feedback circuit may also include a buffer, for example, the buffer may be located between the inverter and the inverting amplifier circuit to enhance the driving capability of the circuit.

[0092] In a possible implementation manner, the main structure of the relaxation oscillator can be as follows: Figure 6a As shown, Figure 6a The ellipsis in the feedback circuit may be a buffer. Figure 6a The tubes M3 and M4 in the circuit serve as active loads for the current mirror tubes M1 and M2, respectively. The tubes M5 and M6 form a single-tube single-stage inverting amplifier. The advantage of using a single-tube single-stage amplifier is that there is no need to design an additional reference voltage circuit, thereby simplifying the circuit structure. Usually, the output of I4 or I2 is used as the output signal of the relaxation oscillator. C is a variable capacitor, which can be used to adjust the frequency of the relaxation oscillator so that the frequency ratio of the high-frequency clock source and the low-frequency clock source is not easy to meet the integer ratio, thereby making the output sequence less likely to have periodicity.

[0093] The above-mentioned bias voltage can be provided by a bias circuit. In addition, in order to facilitate the control of the opening and closing of the relaxation oscillator, the relaxation oscillator can also include an enabling circuit, a starting circuit and a bias circuit. The starting circuit, the enabling circuit and the bias circuit can all be common starting circuits, enabling circuits and bias circuits in the relevant technology.

[0094] In a possible implementation manner, the circuit structure of the relaxation oscillator can be as follows: Figure 6b The startup circuit includes Figure 6b The middle resistor R2, resistor R3, MB tube, and MC tube are responsible for starting the entire circuit and establishing the static operating point of the current mirror. The bias circuit includes Figure 6b The resistor R1, M tube and MA tube are responsible for providing bias voltage VBB for M3 tube, M4 tube and M5 tube. The enabling circuit includes M0 tube, M01 tube and M02 tube. The position of M0 tube is not limited to Figure 6bIn the position shown in , the M0 and M02 tubes are controlled by the enable signal EN, and the M01 tube is controlled by the inverted signal ENB of the enable signal. When EN=0, transistor M0 is turned on, the gates of the M3~M5 tubes are short-circuited to VDD, all are in high-impedance state, and the relaxation oscillator is turned off; when EN=1, the M0 tube is disconnected, and the gates of the M3~M5 tubes are biased by VBB. EN can be configured by registers or software. When EN is 0, the M02 tube pulls C up to VDD, and the function of the M01 tube is to provide an enable switch. It can be understood that the structure of the relaxation oscillator is not limited to the above structure. In one implementation, it can also be replaced by a relaxation oscillator in the related art.

[0095] When the oscillator starts working, that is, when EN=1, the MS tube is disconnected (that is, the gate end of the MS tube is at a low level), the M2 tube provides a discharge path for C, and C discharges at a certain rate through the internal resistance of M2. The voltage at the top of the capacitor C decreases, and through the amplification of the M6 ​​tube, a gradually increasing signal is formed at the drain end of the M6 ​​tube. When the signal increases to a value greater than the threshold of the inverter I1, the output of the inverter I1 flips from a high level to a low level, and then the output of I4 flips to a high level, and the MS tube is turned on.

[0096] After the MS tube is turned on, the gate terminals of the M1 and M2 tubes are short-circuited to the ground, and the M2 tube is disconnected, presenting a high-impedance state. The M4 tube acts as a current source to charge C, and the potential at the top of C gradually increases. Through the amplification of the M6 ​​tube, a gradually decreasing signal is formed at the drain end of the M6 ​​tube. When the signal decreases to less than the threshold of the inverter I1, the output of the inverter I1 flips from a low level to a high level, and then the output of I4 flips to a low level, and the MS tube is disconnected, and this cycle repeats, resulting in relaxation oscillation.

[0097] The overall structure of the third entropy source acquisition circuit is Figure 1 The structures shown are similar, for example, both include two clock sources with different frequencies and acquisition circuits, the difference being that the implementation principles of the clock sources are different. For example, the third entropy source acquisition circuit includes: an entropy source circuit that generates a fourth clock source based on a chaotic circuit. The fourth clock source is related to the random sequence generated by the third entropy source acquisition circuit. For example, the fourth clock source generated by the entropy source circuit can be used to sample the high-frequency clock source to obtain a random sequence. In some possible implementations, the entropy source circuit can also be used to replace Figure 1 The original high-frequency clock source.

[0098] In a possible implementation manner, the third entropy source acquisition circuit includes: a first oscillator, a second oscillator, a chaotic circuit and a full swing circuit, and its structure is as follows: Figure 7 As shown. The first oscillator and the second oscillator are both connected to the chaotic circuit, and the chaotic circuit is also connected to the full swing circuit. Figure 7 The circuit shown is replaced by Figure 1 The original low-frequency clock source.

[0099] The first oscillator is configured to generate a first signal. The second oscillator is configured to generate a second signal. The chaotic circuit is connected to the first oscillator and the second oscillator respectively, and the chaotic circuit is configured to generate a third signal with an uncertain state (such as a signal that is not all 1, 0, such a state-determined signal, but also includes an intermediate state between 0 and 1) based on the first signal and the second signal. The full-swing circuit is connected to the chaotic circuit, and the full-swing circuit is configured to generate a fourth clock source determined by the state based on the third signal, that is, the fourth clock source only includes the determined state of 1, 0.

[0100] In one implementation, the frequency ratio of the first signal to the second signal is within 2, that is, the frequency ratio of the two does not exceed 2. The frequency of the first signal can be greater than the frequency of the second signal, or the frequency of the first signal can be less than the frequency of the second signal.

[0101] The first oscillator and the second oscillator mentioned above can both be relaxation oscillators, etc. For example, in one embodiment, the first oscillator and the second oscillator can both be Figure 6b The relaxation oscillator shown in FIG. The outputs of the two relaxation oscillators are connected together through a chaotic circuit to form competition and adventure, thereby generating a third signal with an uncertain state, which is then connected to a full-swing circuit to generate a clock source signal of a state-determined signal such as 1 or 0.

[0102] In one implementation, the chaotic circuit can be implemented using an adjustable nonlinear resistor-capacitor network, as shown in the schematic diagram. Figure 7a As shown. The full-swing circuit can be implemented using the full-swing circuit in the related art, which will not be introduced here. Both the variable resistor and the variable capacitor can adopt the variable resistor and the variable capacitor in the related art, which will not be introduced here. The first signal and the second signal will form competition and adventure at the nonlinear resistor-capacitor network. If the resistance of R11 and the capacitive reactance of C11 are respectively greater than the resistance of R12 and the capacitive reactance of C12, the third signal is closer to the second signal; if the resistance of R11 and the capacitive reactance of C11 are respectively less than the resistance of R12 and the capacitive reactance of C12, the third signal is closer to the first signal.

[0103] Among them, each of the above entropy source acquisition circuits can be directly connected to the processing circuit. In a possible implementation, the M entropy source acquisition circuits can also be connected to the processing circuit through a second selection circuit, and the number of entropy source acquisition circuits connected to the processing circuit is selected by the second selection circuit, that is, Figure 2A second selection circuit is added between the M entropy source acquisition circuits and the processing circuit in the circuit shown. The second selection circuit may include a selector, and the number of selectors may be multiple, and one entropy source acquisition circuit may be connected to the processing circuit through one selector, or multiple entropy source acquisition circuits may be connected to the processing circuit through the same selector. In one possible implementation, the number of selectors is N, and the same entropy source acquisition circuit may be connected to the processing circuit through one selector. The outputs of all entropy source acquisition circuits are connected to subsequent circuits through XOR operations, and these entropy source acquisition circuits can be flexibly turned on or off according to requirements through configuration, with at least 1 turned on and at most M turned on.

[0104] Using the true random number sequence generator shown in this application, after the standard inspection process, the randomness test pass rate of the generated 1000 1048576-bit random numbers is more than 97%, and the test is performed 100 times in a row, with an average pass rate of 60% above 98.1%, while the traditional true random number sequence generator (such as Figure 1 ), the number of tests with a pass rate of not less than 98.1% for every 100 tests is usually less than 50.

[0105] An embodiment of the present application also provides a chip, which includes the above-mentioned true random number sequence generator. The chip can be any chip that requires random numbers, for example, it can be an encryption chip, a communication chip, a processing chip, etc. In one implementation mode, the chip can be a processor.

[0106] The chip provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned true random number sequence generator embodiment. For the sake of brief description, for matters not mentioned in the chip embodiment, reference may be made to the corresponding contents in the aforementioned true random number sequence generator embodiment.

[0107] The present application also provides an electronic device, which includes the above-mentioned chip. In one implementation, the structural block diagram of the electronic device is as follows: Figure 8 The electronic device comprises: a transceiver, a memory, a communication bus and a processor. The processor can be the above-mentioned chip including a true random number sequence generator.

[0108] The transceiver, the memory, and the processor are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver is used to send and receive data. The memory is used to store computer programs, wherein the computer program 100 includes at least one software function module that can be stored in the memory in the form of software or firmware or solidified in the operating system (OS) of the electronic device. The processor is used to execute the software function module or computer program stored in the memory.

[0109] Among them, the memory can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0110] The processor may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Or the processor may also be any conventional processor, etc.

[0111] The above-mentioned electronic devices include but are not limited to mobile devices, computing devices, security devices, network and communication devices, vehicles, etc. Among them, mobile devices include but are not limited to smart phones, tablets, wearable devices. Computing devices include but are not limited to personal computers, servers, computing cards, etc. Security devices include but are not limited to cameras, smart locks, access control systems, etc. Network and communication devices include but are not limited to routers, switches, firewalls, etc. Vehicles include but are not limited to various vehicles containing electronic control units.

[0112] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0113] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0114] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A true random number sequence generator, characterized in that: include: M entropy source acquisition circuits, each of which is configured to output a random sequence, and different entropy source acquisition circuits output different random sequences, and M is an integer not less than 2; A processing circuit is connected to each entropy source acquisition circuit, and the processing circuit is configured to perform XOR processing on the random sequence output by each entropy source acquisition circuit to obtain a random number.

2. The true random number sequence generator according to claim 1, characterized in that: The M entropy source acquisition circuits include N entropy source acquisition circuits of different types, where N is an integer not less than 2.

3. The true random number sequence generator according to claim 2, characterized in that: The M entropy source acquisition circuits include: A first entropy source acquisition circuit is configured to generate a random sequence based on a ring oscillator; A second entropy source acquisition circuit is configured to generate a random sequence based on a relaxation oscillator; The third entropy source acquisition circuit is configured to generate a random sequence based on a chaotic circuit.

4. The true random number sequence generator according to claim 3, characterized in that: The first entropy source acquisition circuit comprises: A first entropy source is configured to generate a first clock source based on two ring oscillators with different frequencies; a second entropy source, configured to generate a second clock source based on two ring oscillators with different frequencies, wherein the frequency of the first clock source is less than the frequency of the second clock source; The first acquisition circuit is connected to the first entropy source and the second entropy source respectively, and the first acquisition circuit is configured to sample the second clock source based on the first clock source and output a random sequence.

5. The true random number sequence generator according to claim 4, characterized in that: The first entropy source comprises: A first ring oscillator configured to generate a first initial clock source; a second ring oscillator, configured to generate a second initial clock source, wherein a frequency of the second initial clock source is greater than a frequency of the first initial clock source and is not an integer ratio to a frequency of the first initial clock source; A trigger is connected to the first ring oscillator and the second ring oscillator respectively, and the trigger is configured to sample the first initial clock source based on the second initial clock source to obtain the first clock source.

6. The true random number sequence generator according to claim 5, characterized in that: The first entropy source also includes: A selector, wherein a first input end of the selector is connected to the first ring oscillator, a second input end of the selector is connected to an output end of the trigger, and an output end of the selector is connected to the first acquisition circuit.

7. The true random number sequence generator according to claim 4, characterized in that: The first entropy source acquisition circuit also includes: a third entropy source, configured to generate a third clock source based on two ring oscillators with different frequencies, wherein the frequency of the first clock source is less than the frequency of the third clock source; a second acquisition circuit, connected to the first entropy source and the third entropy source respectively, and the second acquisition circuit is configured to sample the third clock source based on the first clock source and output a random sequence; The first selection circuit is connected to the first acquisition circuit and the second acquisition circuit respectively, and the first selection circuit is configured to select and output the random sequence output by the first acquisition circuit or the second acquisition circuit.

8. The true random number sequence generator according to claim 7, characterized in that: The first entropy source acquisition circuit also includes: The third acquisition circuit is connected to the first entropy source, the second entropy source, the third entropy source and the first selection circuit respectively, and the third acquisition circuit is configured to sample the XOR result of the second clock source and the third clock source based on the first clock source, and output a random sequence.

9. The true random number sequence generator according to claim 8, characterized in that: The first selection circuit comprises: A first selector, wherein a first input end of the first selector is connected to the first acquisition circuit, and a second input end of the first selector is connected to the second acquisition circuit; a second selector, wherein a first input end of the second selector is used to receive an XOR result of a random sequence output by the first acquisition circuit and a random sequence output by the second acquisition circuit, and a second input end of the second selector is connected to the third acquisition circuit; A third selector, wherein a first input terminal of the third selector is connected to an output terminal of the first selector, and a second input terminal of the third selector is connected to an output terminal of the second selector.

10. The true random number sequence generator according to claim 3, characterized in that: The second entropy source acquisition circuit includes: a relaxation oscillator for generating a third clock source, wherein the third clock source is related to the random sequence generated by the second entropy source acquisition circuit, and the relaxation oscillator includes: A current mirror, connected to the power supply and the digital ground respectively; load capacitors, connected to the current mirror and the digital ground respectively; An inverting amplifier circuit is connected to a power supply, a digital ground, and the load capacitor respectively; A feedback circuit is connected to the output end of the inverting amplifier circuit, the current mirror and the digital ground respectively, and the target position of the feedback circuit is used to output the third clock source; Wherein, when the load capacitor is discharged through the current mirror, the terminal voltage of the load capacitor gradually decreases, and a gradually increasing first drive signal is output after passing through the inverting amplifier circuit, and when the first drive signal is greater than the flip threshold of the feedback circuit, the feedback circuit controls the current mirror to charge the load capacitor; When the current mirror charges the load capacitor, the terminal voltage of the load capacitor gradually increases, and after passing through the inverting amplifier circuit, a gradually decreasing second drive signal is output. When the second drive signal is less than the flip threshold of the feedback circuit, the feedback circuit controls the current mirror to discharge the load capacitor.

11. The true random number sequence generator according to claim 3, characterized in that: The third entropy source acquisition circuit comprises: a first oscillator configured to generate a first signal; a second oscillator configured to generate a second signal; a chaotic circuit connected to the first oscillator and the second oscillator respectively, wherein the chaotic circuit is configured to generate a third signal with an uncertain state based on the first signal and the second signal; A full-swing circuit is connected to the chaotic circuit, and the full-swing circuit is configured as a fourth clock source determined based on the third signal generation state, wherein the fourth clock source is related to the random sequence generated by the three-entropy source acquisition circuit.

12. The true random number sequence generator according to any one of claims 1 to 11, characterized in that: The true random number sequence generator also includes: a second selection circuit, which is connected to the M entropy source acquisition circuits and the processing circuit respectively, and the second selection circuit is configured to select the number of entropy source acquisition circuits connected to the processing circuit.

13. A chip, characterized in that: Comprising: a true random number sequence generator as claimed in any one of claims 1-12.

14. An electronic device, characterized in that: include: The chip as claimed in claim 13.

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