Method of garbage collection management of memory device, memory controller, memory device, and electronic device

Abstract

The invention provides a method for garbage collection management of a memory device with aid of dedicated information control and related equipment. The method may include: receiving at least one first command, and performing at least one access operation on the non-volatile memory according to the at least one first command; and performing a garbage collection process to begin garbage collection of the non-volatile memory, for example: dividing a memory region of a volatile memory into a plurality of sub-regions as a plurality of dedicated memory regions; selecting a plurality of source blocks; comparing the address mapping table to respectively generate and store valid data position information in the plurality of special memory areas; and performing a plurality of garbage collection operations according to the valid data location information respectively stored in the plurality of dedicated memory areas.

Description

Technical Field

[0001] The present invention relates to memory control, and more particularly to a method for performing garbage collection (GC) management of a memory device by means of dedicated information control and related apparatus such as a memory controller of the memory device, the memory device and an electronic device including the memory device. Background Art

[0002] According to the related art, a memory device may perform GC in an attempt to free up a portion of storage space for further use, which may reduce overall performance. In particular, during access in response to a host request, a controller integrated circuit (IC) of the memory device may, under certain circumstances, spend too much time performing internal operations of the memory device. The related art attempts to solve this problem, however, may introduce more problems (e.g., certain side effects). Therefore, a novel method and related architecture are needed to solve these problems without introducing any side effects or in a manner that is less likely to introduce side effects. Summary of the invention

[0003] Therefore, one of the objects of the present invention is to provide a method for performing GC management of a memory device by means of dedicated information control and related equipment such as a memory controller of the memory device, the memory device and an electronic device including the memory device to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a method for performing GC management of a memory device by means of dedicated information control, wherein the method can be applied to a memory controller of the memory device. The memory device can include the memory controller and a non-volatile (NV) memory, the NV memory can include at least one NV memory element (e.g., one or more NV memory elements), and the at least one NV memory element can include multiple blocks. The method can include: using the memory controller to receive at least one first command from a host device through a transmission interface circuit in the memory controller, and performing at least one access operation on the NV memory according to the at least one first command, wherein the at least one first command indicates at least one write request from the host device; and executing a garbage collection process to start garbage collection on the NV memory. For example, the garbage collection process may include: dividing a memory area of ​​a volatile memory in the memory controller into a plurality of sub-areas as a plurality of dedicated memory regions according to the number of the at least one NV memory element, wherein the number of the at least one NV memory element is greater than one; selecting a plurality of source blocks from the plurality of blocks; reading respective physical-to-logical (P2L) address mapping tables of the plurality of source blocks; reading at least one latest logical-to-physical (L2P) address mapping table in the NV memory according to the respective physical-to-logical address mapping tables of the plurality of source blocks; comparing the respective physical-to-logical address mapping tables of the plurality of source blocks and the at least one latest logical-to-physical address mapping table to generate and store valid data location information (valid-data-location information) in the plurality of dedicated memory regions, respectively. The invention relates to a method for storing a plurality of garbage collection operations, wherein at least a portion of the plurality of garbage collection operations is performed in a parallel processing manner. The method comprises: providing a plurality of garbage collection operations, wherein the plurality of garbage collection operations are performed in a parallel processing manner. The plurality of garbage collection operations are performed in a parallel processing manner.

[0005] In addition to the above method, the present invention further provides a memory controller of a memory device, wherein the memory device may include the memory controller and an NV memory. The NV memory may include at least one NV memory element (e.g., one or more NV memory elements), and the at least one NV memory element may include multiple blocks. In addition, the memory controller includes a processing circuit, which is used to control the memory controller according to multiple host commands from a host device to allow the host device to access the NV memory through the memory controller, wherein the processing circuit is used to perform GC management of the memory device by means of dedicated information control. The memory controller further includes a transmission interface circuit, and the transmission interface circuit is used to communicate with the host device. For example, the memory controller receives at least one first command from the host device through the transmission interface circuit in the memory controller, and performs at least one access operation on the NV memory according to the at least one first command, wherein the at least one first command indicates at least one write request from the host device; and the memory controller executes a garbage collection process to start garbage collection of the NV memory. In particular, the garbage collection process may include: dividing a memory area of ​​a volatile memory in the memory controller into a plurality of sub-areas as a plurality of dedicated memory areas according to the number of the at least one NV memory element, wherein the number of the at least one NV memory element is greater than one; selecting a plurality of source blocks from the plurality of blocks; reading respective physical-to-logical address mapping tables of the plurality of source blocks; reading at least one latest logical-to-physical address mapping table in the NV memory according to the respective physical-to-logical address mapping tables of the plurality of source blocks; comparing the respective physical-to-logical address mapping tables of the plurality of source blocks and the at least one latest logical-to-physical address mapping table to generate and store valid data location information in the plurality of dedicated memory areas respectively for indicating the location of valid data of each NV memory element; and performing a plurality of garbage collection operations according to the valid data location information respectively stored in the plurality of dedicated memory areas, wherein at least a portion of the plurality of garbage collection operations are performed in a parallel processing manner.

[0006] In addition to the above method, the present invention further provides the memory device comprising the above memory controller, wherein the memory device comprises the NV memory and the memory controller. The NV memory is used to store information. The memory controller is coupled to the NV memory and is used to control the operation of the memory device.

[0007] In addition to the above method, the present invention further provides a related electronic device. The electronic device may include the above memory device, and may further include: the host device, which is coupled to the memory device. The host device may include: at least one processor, which is used to control the operation of the host device; and a power supply circuit, which is coupled to the at least one processor and is used to provide power to the at least one processor and the memory device. In addition, the memory device can provide storage space for the host device.

[0008] According to certain embodiments, the device may include at least a portion (e.g., a portion or all) of the electronic device. For example, the device may include the memory controller in the memory device. For another example, the device may include the memory device. As another example, the device may include the host device. In some examples, the device may include the electronic device.

[0009] According to some embodiments, the memory controller in the memory device may control the operation of the memory device according to the method, and the memory device may be disposed in the electronic device. In addition, the memory device may store data for the host device. The memory device may read the stored data in response to a host command from the host device, and provide the data read from the NV memory to the host device.

[0010] The method and related apparatus of the present invention can ensure that the memory device can operate properly in different situations, in particular, at least a part of the multiple blocks of the NV memory can be divided into blocks corresponding to multiple channels respectively, and when performing a GC operation, a first block corresponding to a first channel is used together as a first source block of a first GC operation and a first target block corresponding to the first channel is determined as a first destination block of the first GC operation, and a second block corresponding to a second channel is used together as a second source block of a second GC operation and a second target block corresponding to the second channel is determined as a second destination block of the second GC operation, so that the GC operation is performed according to the multiple channels respectively, so as to improve the overall GC performance. In addition, the method and apparatus of the present invention can solve the problems of the related art without introducing any side effects or in a manner that is unlikely to introduce side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2An NV-memory-element-unaware block selection control scheme is shown.

[0013] Figure 3A Draw Figure 2 A first portion of a timing diagram of the NV memory device unaware block select control scheme is shown.

[0014] Figure 3B Draw Figure 2 A second portion of the timing diagram of the NV memory device unaware block select control scheme is shown.

[0015] Figure 3C Draw Figure 2 A third portion of the timing diagram of the NV memory device unaware block select control scheme is shown.

[0016] Figure 3D Draw Figure 2 A fourth portion of the timing diagram of the NV memory device unaware block select control scheme is shown.

[0017] Figure 3E Draw Figure 2 A fifth portion of the timing diagram of the NV memory device unaware block select control scheme is shown.

[0018] Figure 3F Draw Figure 2 A sixth portion of the timing diagram of the NV memory device unaware block select control scheme is shown.

[0019] Figure 4 According to one embodiment of the present invention, a method for performing GC management of a memory device by means of dedicated information control is described, which is an NV memory element-aware block selection control scheme.

[0020] Figure 5A Draw Figure 4 A first portion of a timing diagram of the NV memory device aware block select control scheme is shown.

[0021] Figure 5B Draw Figure 4 A second portion of the timing diagram of the NV memory device aware block select control scheme is shown.

[0022] Figure 5C Draw Figure 4 A third portion of the timing diagram of the NV memory device aware block select control scheme is shown.

[0023] Figure 6A comparison control scheme of the method is illustrated according to an embodiment of the present invention.

[0024] Fig. 7A An NV-memory-element-dedicated memory region control scheme of the method is described according to an embodiment of the present invention.

[0025] Figure 7B Draw Fig. 7A Some implementation details of the NV memory element dedicated memory region control scheme are shown.

[0026] Figure 7C Draw Fig. 7A Some other implementation details of the NV memory element dedicated memory region control scheme are shown.

[0027] Figure 8 A workflow of the method is described according to an embodiment of the present invention.

[0028] Fig.9A An example of multiple dedicated memory areas involved in the method is shown.

[0029] Fig. 9B Examples of multiple die-dedicated memory regions involved in the method are shown. Fig. 9C Examples of multiple chip-dedicated memory regions involved in the method are shown.

[0030]

Explanation of symbols

[0031] 10: Electronic devices

[0032] 50: Host device

[0033] 52: Processor

[0034] 54: Power supply circuit

[0035] 58: Transmission interface circuit

[0036] 100: memory device

[0037] 110: memory controller

[0038] 112: Microprocessor

[0039] 112C: Program code

[0040] 112M: Read-only memory

[0041] 114: Control logic circuit

[0042] 116: Random Access Memory

[0043] 116AM: Temporary logical to physical (L2P) address mapping table

[0044] 116DM: Temporary dedicated garbage collection (DGC) management table

[0045] 116R: Memory area

[0046] 118: Transmission interface circuit

[0047] 120: Non-volatile (NV) memory

[0048] 120AM: Global logical to physical (L2P) address mapping table

[0049] 120DM: Dedicated Garbage Collection (DGC) Management Table

[0050] 122-1~122-N E :Non-volatile (NV) memory devices

[0051] 610: Physical to logical (P2L) address mapping table

[0052] 620: Logical to Physical (L2P) Address Mapping Table

[0053] DIE(X),DIE(Y): Bare crystal

[0054] BLK(A),BLK(B),BLK(C),BLK(D),BLK(M),BLK(N),BLK(W): Block BLK SYSTEM :System Block

[0055] PAGE(0)~PAGE(N P ):page

[0056] R_Dedicated(1)~R_Dedicated(N E ): Dedicated memory area

[0057] R_DIE(1)~R_DIE(N E ), R_DIE(X), R_DIE(Y): bare die dedicated memory area R_CHIP(1)~R_CHIP(N E ),R_CHIP(X),R_CHIP(Y): chip-specific memory area

[0058] DM(1)~DM(N E ),DM(X),DM(Y): Dedicated Garbage Collection (DGC) Management Table

[0059] DDM(1)~DDM(N E ): Die-specific garbage collection (DDGC) management table

[0060] CDM(1)~CDM(N E ):Chip Dedicated Garbage Collection (CDGC) Management Table

[0061] LBA(A), LBA(B), LBA(C), LBA(D), LBA(Z): Logical Block Address

[0062] A0,A2,A3,A5,A8,B2,B4~B6,B8,C1~C3,C8,D2,D4,D6,D8:Data

[0063] t: time

[0064] t0~t16,t20~t29: time points

[0065] T READ :Read busy time

[0066] T PROGRAM : Busy programming time

[0067] S11~S21: Steps DETAILED DESCRIPTION

[0068] Figure 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors), which may be collectively referred to as a processor 52, and includes a power supply circuit 54 and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other via a bus, and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more driving voltages to the memory device 100, wherein the memory device 100 may provide storage space for the host device 50, and may obtain the one or more driving voltages from the host device 50 as a power supply for the memory device 100. Examples of the host device 50 may include (but are not limited to): a multi-function mobile phone, a tablet computer, a wearable device, and a personal computer, such as a desktop computer and a notebook computer. Examples of the memory device 100 may include (but are not limited to): portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS or XD specifications, solid state drives (SSDs), and various types of embedded memory devices (e.g., embedded memory devices conforming to universal flash storage (UFS) specifications or embedded multi-media card (eMMC) specifications). According to the present embodiment, the memory device 100 may include a controller, such as a memory controller 110, and may further include a non-volatile (NV) memory 120, wherein the controller is used to access the NV memory 120, and the NV memory 120 is used to store information. The NV memory 120 may include at least one NV memory element (e.g., one or more NV memory elements), such as a plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E , where "N E " may represent a positive integer greater than 1. For example, the NV memory 120 may be a flash memory, and the plurality of NV memory elements 122-1, 122-2, ..., and 122-N may be E The flash memory chips {CHIP} may be multiple flash memory chips {CHIP} (for example, chips CHIP (1), CHIP (2), ..., and CHIP (N E )) or multiple flash memory die {DIE} (for example, die DIE (1), DIE (2), ..., and DIE (N E )), but the present invention is not limited to this.

[0069] like Figure 1 As shown, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage unit such as a read only memory (ROM) 112M, a control logic circuit 114, a random access memory (RAM) 116 (for example, it can be implemented by a static random access memory) and a transmission interface circuit 118, wherein at least a portion (for example, a portion or all) of the above components can be coupled to each other via a bus. The random access memory 116 can be used to provide internal storage space to the memory controller 110 (for example, it can temporarily store information), but the present invention is not limited to this. In addition, the read only memory 112M of this embodiment is used to store program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access of the NV memory 120. Please note that the program code 112C can also be stored in the random access memory 116 or any type of memory. In addition, the control logic circuit 114 can be used to control the NV memory 120. The control logic circuit 114 may include an error correction code (ECC) circuit (not shown). Figure 1 ), which can perform error correction code encoding and error correction code decoding to protect data, and / or perform error correction. The transmission interface circuit 118 can comply with one or more communication specifications among various communication specifications (such as Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIe) specification, Non-Volatile Memory Express (NVMe; also known as "NVM Express") specification, Embedded Multimedia Card specification and Universal Flash Storage specification), and can communicate with the memory device 100 and the host device 50 (such as the transmission interface circuit 58) according to the one or more communication specifications. Similarly, the transmission interface circuit 58 can comply with the one or more communication specifications, and can communicate with the host device 50 and the memory device 100 (such as the transmission interface circuit 118) according to the one or more communication specifications.

[0070] In the present embodiment, the host device 50 may transmit a plurality of host commands corresponding to the logical addresses to the memory controller 110 to indirectly access the NV memory 120 in the memory device 100. The memory controller 110 receives the plurality of host commands and the logical addresses, converts the plurality of host commands into memory operation commands (which may be referred to as operation commands for simplicity), and further controls the NV memory 120 with the operation commands to read or write / program the memory cells or data pages of the specific physical addresses in the NV memory 120, wherein the physical addresses may be associated with the logical addresses. For example, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between the physical addresses and the logical addresses. The NV memory 120 may store a global L2P address mapping table 120AM to provide the memory controller 110 to control the memory device 100 to access the data in the NV memory 120, but the present invention is not limited thereto. In addition, the memory controller 110 may generate or update at least one dedicated GC (DGC) management table, such as a DGC management table 120DM, and the NV memory 120 may store the DGC management table 120DM. The memory controller 110 may generate or update GC-management-related information in the DGC management table 120DM for managing GC operations.

[0071] For better understanding, the global L2P address mapping table 120AM and the DGC management table 120DM may be located in a predetermined area within the NV memory element 122-1, such as a system area, but the present invention is not limited thereto. For example, the global L2P address mapping table 120AM may be divided into a plurality of local L2P address mapping tables, and the plurality of local L2P address mapping tables may be stored in the plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E In one or more NV memory elements, in particular, the NV memory elements 122-1, 122-2, ..., and 122-N may be stored in the plurality of NV memory elements 122-1, 122-2, ..., and 122-N, respectively. EWhen necessary, the memory controller 110 may load at least a portion (e.g., a portion or all) of the global L2P address mapping table 120AM into the random access memory 116 or other memory. For example, the memory controller 110 may load a local L2P address mapping table from the plurality of local L2P address mapping tables into the random access memory 116 as a temporary L2P address mapping table 116AM to access data in the NV memory 120 according to the local L2P address mapping table stored as the temporary L2P address mapping table 116AM, but the present invention is not limited thereto. The memory controller 110 may generate or update address mapping information in the temporary L2P address mapping table 116AM, and update the global L2P address mapping table 120AM according to the latest address mapping information in the temporary L2P address mapping table 116AM. In addition, the memory controller 110 may load the DGC management table 120DM into the random access memory 116 or other memory. For example, the memory controller 110 may load the DGC management table 120DM into the random access memory 116 as a temporary DGC management table 116DM to manage GC operations according to the temporary DGC management table 116DM. The memory controller 110 may generate or update GC management related information in the DGC management table 116DM, and update the DGC management table 120DM according to the latest GC management related information in the DGC management table 116DM.

[0072] In addition, the at least one NV memory element (eg, one or more NV memory elements, such as the plurality of NV memory elements 122-1, 122-2, ..., and 122-N) E ) may include a plurality of blocks {BLK}, wherein the minimum unit for the memory controller 110 to perform a data erase operation on the NV memory 120 may be a block, and the minimum unit for the memory controller 110 to perform a data write operation on the NV memory 120 may be a page, but the present invention is not limited thereto. For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E Any NV memory element 122-n within (where “n” may represent an interval [1, N E ] may include multiple blocks, and a block among the multiple blocks may include and record a specific number of pages, wherein the memory controller 110 may access a page within a block among the multiple blocks according to the block address and the page address.

[0073] According to some embodiments, the memory controller 110 may calculate the number of pages with valid data in any block BLK among the plurality of blocks {BLK} as the valid page count (valid page count) VPC of the aforementioned any block BLK, and select a block {BLK} with a smaller valid page count {VPC} as a GC source block for performing at least one GC operation to maximize the number of blocks {BLK} released by the aforementioned at least one GC operation, but the present invention is not limited thereto. According to some embodiments, the memory controller 110 may perform a per-NV-memory-element GC operation such as a per-die / per-chip GC operation to improve overall performance, in particular, at least a portion of the plurality of blocks {BLK} among the plurality of blocks {BLK} are divided into corresponding to a plurality of channels {CH} (for example: channels {CH(c)|c=1,2,…,c MAX}), and when performing a GC operation, a first block {BLK} corresponding to a channel CH (c=c1) is used together as a first source block {BLK} of a first GC operation. SOURCE} and determine a first target block BLK corresponding to the channel CH (c=c1) as a first destination block BLK of the first GC operation DESTINATION , and using a second block {BLK} corresponding to a channel CH (c=c2) as a second source block {BLK} for a second GC operation SOURCE} and determine a second target block BLK corresponding to the channel CH (c=c2) as a second destination block BLK of the second GC operation DESTINATION GC operations are performed according to the multiple channels {CH} to improve the overall GC performance.

[0074] Figure 2 An NV-memory-element-unaware block selection control scheme is shown. For ease of understanding, when necessary, the memory controller 110 may operate according to the NV-memory-element-unaware block selection control scheme, but the present invention is not limited thereto. For example, the memory controller 110 may operate according to at least one other control scheme. In addition, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E The plurality of flash memory dies {DIE} (eg, dies DIE(X) and DIE(Y)) may be used to implement the present invention, but the present invention is not limited thereto. According to some embodiments, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N EIt can be implemented by the plurality of flash memory chips {CHIP}, wherein Figure 2 The bare die DIE(X) and DIE(Y) shown may be replaced by chips CHIP(X) and CHIP(Y), respectively.

[0075] For example, blocks BLK(A), BLK(B), BLK(C), and BLK(D) may store data such as valid data (e.g., data A0, A2, A3, A5, A8, B2, B4, B5, B6, B8, C1, C2, C3, C8, D2, D4, D6, and D8) and invalid data (marked as For simplicity), blocks BLK(M) and BLK(N) may be blocks that have been erased and have not stored any data. Figure 2 As shown in the left half of , blocks BLK(A), BLK(C) and BLK(M) may belong to a certain NV memory element, such as bare die DIE(X), while blocks BLK(B), BLK(D) and BLK(N) may belong to another NV memory element, such as bare die DIE(Y). The multiple pages of block BLK(A) may include 5 valid pages that respectively store valid data (e.g., data A0, A2, A3, A5 and A8), the multiple pages of block BLK(B) may include 5 valid pages that respectively store valid data (e.g., data B2, B4, B5, B6 and B8), the multiple pages of block BLK(C) may include 4 valid pages that respectively store valid data (e.g., data C1, C2, C3 and C8), and the multiple pages of block BLK(D) may include 4 valid pages that respectively store valid data (e.g., data D2, D4, D6 and D8). As shown in FIG. Figure 2 As shown in the right half of , during GC, the memory controller 110 may first write the data A0, A2, A3, A5 and A8 in the valid page of block BLK(A) into block BLK(M) in sequence, then write the data B2, B4, B5, B6 and B8 in the valid page of block BLK(B) into blocks BLK(M) and BLK(N) in sequence, and then write the data C1, C2, C3 and C8 in the valid page of block BLK(C) and the data D2, D4, D6 and D8 in the valid page of block BLK(D) into block BLK(N).

[0076] FIG. 3A to FIG. 3F Draw separately Figure 2 Portions of a timing diagram of the NV memory device unaware block select control scheme are shown, wherein any two adjacent intervals in intervals [t0, t1], [t1, t2], ..., and [t15, t16] between a series of time points {t0, t1, ..., t16} may be equal to each other. Figure 3AThe first part shown contains the respective timings of the intervals [t0, t1], [t1, t2] and [t2, t3], Figure 3B The second portion shown contains the respective timings of the intervals [t3, t4], [t4, t5] and [t5, t6], Figure 3C The third portion shown contains the respective timings of the intervals [t6, t7], [t7, t8] and [t8, t9], Figure 3D The fourth portion shown contains the respective timings of the intervals [t9, t10], [t10, t11] and [t11, t12], Figure 3E The fifth portion shown contains the respective timings of the intervals [t12, t13], [t13, t14], and [t14, t15], and Figure 3F The sixth portion shown contains the timing of the interval [t15, t16].

[0077] In addition, any of the valid data (e.g., data A0, A2, A3, A5, A8, B2, B4, B5, B6, B8, C1, C2, C3, C8, D2, D4, D6, and D8) can be marked at a busy time (e.g., programming busy time T PROGRAM Or read the busy time T READ ) to indicate the busy time corresponding to any of the above data. The busy time may represent the busy time of any of the above NV memory elements 122-n operating in response to a received operation command. For example, the busy time T READ The programming busy time T may represent the busy time of any of the NV memory elements 122-n (eg, die DIE(X) or die DIE(Y)) operating in response to a received first operation command, such as a read operation command. PROGRAM It may represent the busy time of any of the above NV memory elements 122-n (eg, bare die DIE(X) or bare die DIE(Y)) operating in response to a received second operation command such as a programming operation command, but the present invention is not limited thereto. According to some embodiments, FIG. 3A to FIG. 3F The bare die DIE(X) and DIE(Y) shown may be replaced by chips CHIP(X) and CHIP(Y), respectively.

[0078] The programming busy time T of a programming operation of the NV memory 120 (or any of the NV memory elements 122 - n therein) is PROGRAM The read busy time T of a read operation of the NV memory 120 (or any of the NV memory elements 122 - n therein) may be significantly greater than the read busy time T of a read operation of the NV memory 120 (or any of the NV memory elements 122 - n therein). READ For ease of understanding, assume that the programming busy time T PROGRAM The busy time T can be read READ6 times, but the present invention is not limited thereto. FIG. 3A to FIG. 3F As shown, the total time, for example, the length of the interval [t0, t16], may be equal to the read busy time T READ During GC, any two NV memory elements {122-n} (e.g., die DIE(X) and die DIE(Y)) may be idle for some time periods, which may result in a decrease in overall performance. E The total number of GCs is increased to configure a larger storage capacity, and the overall performance may become lower. The memory controller 110 may operate according to at least one other control scheme, in particular, performing a per-NV-memory-element block selection operation such as a per-die / per-chip block selection operation for GC to improve the overall performance.

[0079] Figure 4 According to one embodiment of the present invention, a method for performing GC management of a memory device by means of dedicated information control is described in which an NV memory element is aware of a block selection control scheme. The memory controller 110 can operate according to at least one control scheme of the method (e.g., the NV memory element aware block selection control scheme). For ease of understanding, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E The plurality of flash memory dies {DIE} (eg, dies DIE(X) and DIE(Y)) may be used to implement the present invention, but the present invention is not limited thereto. According to some embodiments, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E It can be implemented by the plurality of flash memory chips {CHIP}, wherein Figure 4 The bare die DIE(X) and DIE(Y) shown may be replaced by chips CHIP(X) and CHIP(Y), respectively.

[0080] During the GC, the memory controller 110 may control any two NV memory elements {122-n} (e.g., bare die DIE(X) and bare die DIE(Y)) to perform parallel operations, and in particular, simultaneously perform GC operations on one of the two NV memory elements {122-n} (e.g., bare die DIE(X)) and the other of the two NV memory elements {122-n} (e.g., bare die DIE(Y)). Figure 4As shown in the left half of FIG. , blocks BLK(A), BLK(B), BLK(C), and BLK(D) may store data such as the valid data (e.g., data A0, A2, A3, A5, A8, B2, B4, B5, B6, B8, C1, C2, C3, C8, D2, D4, D6, and D8) and the invalid data (marked as For simplicity), blocks BLK(M) and BLK(N) may be blocks that have been erased and have not stored any data. Figure 4 As shown in the right half of , the above parallel operations may include:

[0081] (1) For the bare die DIE(X), the memory controller 110 may first write the data A0, A2, A3, A5 and A8 in the valid page of the block BLK(A) into the block BLK(M) in sequence, and then write the data C1, C2, C3 and C8 in the valid page of the block BLK(C) into the block BLK(M) in sequence; and

[0082] (2) For the bare die DIE(Y), the memory controller 110 may first write the data B2, B4, B5, B6 and B8 in the valid page of the block BLK(B) into the block BLK(N) in sequence, and then write the data D2, D4, D6 and D8 in the valid page of the block BLK(D) into the block BLK(N) in sequence;

[0083] However, the present invention is not limited thereto. According to some embodiments, the memory controller 110 may first perform a first set of parallel operations among the above-mentioned parallel operations, and then perform a second set of parallel operations among the above-mentioned parallel operations. For example, the first set of parallel operations may include:

[0084] (1) For the bare die DIE (X), the memory controller 110 may write the data A0, A2, A3, A5 and A8 in the valid pages of the block BLK (A) into the block BLK (M) in sequence; and

[0085] (2) For the bare die DIE (Y), the memory controller 110 may first write the data B2, B4, B5, B6 and B8 in the valid pages of the block BLK (B) into the block BLK (N) in sequence.

[0086] Additionally, the second set of parallel operations may include:

[0087] (1) For the bare die DIE (X), the memory controller 110 may write the data C1, C2, C3 and C8 in the valid pages of the block BLK (C) into the block BLK (M) in sequence; and

[0088] (2) For the die DIE(Y), the memory controller 110 may write the data D2, D4, D6 and D8 in the valid pages of the block BLK(D) into the block BLK(N) in sequence.

[0089] Figure 5A , Figure 5B and Figure 5C Draw separately Figure 4 A first part, a second part and a third part of a timing diagram of the NV memory element aware block selection control scheme are shown, wherein any two adjacent intervals in the intervals [t20, t21], [t21, t22], ... and [t28, t29] between a series of time points {t20, t21, ..., t29} may be equal to each other. Figure 5A The first part shown contains the respective timings of the intervals [t20, t21], [t21, t22] and [t22, t23], Figure 5B The second portion shown contains the respective timings of the intervals [t23, t24], [t24, t25] and [t25, t26], and Figure 3C The third part shown contains the respective timings of the intervals [t26, t27], [t27, t28] and [t28, t29]. In addition, the busy time T READ The programming busy time T may represent the busy time of any of the NV memory elements 122-n (eg, die DIE(X) or die DIE(Y)) operating in response to the received first operation command, such as the read operation command. PROGRAM It may represent the busy time of any of the NV memory elements 122-n (eg, bare die DIE(X) or bare die DIE(Y)) operating in response to the received second operation command, such as the programming operation command, but the present invention is not limited thereto. According to some embodiments, FIG. 5A to FIG. 5C The bare die DIE(X) and DIE(Y) shown may be replaced by chips CHIP(X) and CHIP(Y), respectively.

[0090] For ease of understanding, any of the valid data (e.g., data A0, A2, A3, A5, A8, B2, B4, B5, B6, B8, C1, C2, C3, C8, D2, D4, D6, and D8) may be marked at a busy time (e.g., programming busy time T PROGRAM Or read the busy time T READ ) next to the busy time corresponding to any of the above data, where it can be assumed that the programming busy time T PROGRAM Read busy time T READ 6 times, but the present invention is not limited thereto. FIG. 5A to FIG. 5CAs shown, the total time, for example, the length of the interval [t20, t29], may be equal to the read busy time T READ 63 times. Assume that "T1" represents the length of the interval [t0, t16], and "T2" represents the length of the interval [t20, t29]. Since T1 = (112*T READ ) and T2=(63*T READ ), so the ratio of T1 to T2 R(T1,T2) can be calculated as follows:

[0091] R(T1,T2)=(T1 / T2)=((112*T READ ) / (63*T READ ))=(112 / 63)~=1.778.

[0092] Compared to Figure 2 The NV memory device shown is unaware of the block select control scheme, Figure 4 The NV memory device-aware block selection control scheme shown can significantly improve the GC performance of the memory device 100 , and thus improve the overall performance of the electronic device 10 .

[0093] According to some embodiments, the bare die DIE (X) and DIE (Y) may be respectively configured in different channels among the plurality of channels {CH}, but the present invention is not limited thereto. According to some embodiments, it is not necessary to configure the bare die DIE (X) and DIE (Y) in different channels among the plurality of channels {CH}.

[0094] Figure 6A comparison control scheme of the method is described according to an embodiment of the present invention. After erasing any of the above blocks BLK among the plurality of blocks {BLK}, the memory controller 110 may start writing (or programming) host data from the host device 50 into any of the above blocks BLK. For example, any of the above blocks BLK may be a block BLK(W), and the memory controller 110 may write (or program) a set of local data of the host data into a set of pages of the block BLK(W) to become valid data stored in the set of pages, and write a set of physical-to-logical (P2L) address mapping information of the set of local data into at least one P2L address mapping table in the block BLK(W) to indicate a set of P2L mapping relationships from a set of physical addresses of the set of pages of the block BLK(W) to a set of logical addresses of the set of local data, wherein the above at least one P2L address mapping table may be collectively referred to as a P2L address mapping table 610. In addition, the set of P2L address mapping information may include a set of P2L address mapping table entries such as the set of logical addresses, and the arrangement order of the set of P2L address mapping table entries in the P2L address mapping table 610 may represent the set of physical addresses, but the present invention is not limited thereto. For example, the set of P2L address mapping information may include a combination of the set of physical addresses and the set of logical addresses.

[0095] like Figure 6 As shown in the left half of , after writing (or programming) at least a portion of the host data to the block BLK(W), the memory controller 110 may have recorded the group of logical addresses such as logical block addresses (logical block addresses, LBA) {LBA(A), LBA(B), LBA(Z), LBA(C), ..., LBA(Z)} as the group of P2L address mapping table entries in the P2L address mapping table 610, and the ranking of the group of P2L address mapping table entries in the P2L address mapping table 610 may represent the group of physical addresses, such as pages {PAGE(0), PAGE(1), PAGE(2), PAGE(3), ..., PAGE(N)} of the block BLK(W). P )} (denoted as "BLK(W)" and "{PAGE(0),PAGE(1),PAGE(2),PAGE(3),…,PAGE(N P )}" combination for simplicity). The P2L address mapping table 610 can be used to indicate which LBA / s the valid data in the host data written to the NV memory 120 is located. For example, the memory controller 110 can store internal information (or non-host data) such as the multiple local L2P address mapping tables in the predetermined area such as a system block BLK in the system area.SYSTEM , and at least one corresponding local L2P address mapping table may be selected from the plurality of local L2P address mapping tables according to the set of P2L address mapping table entries in the P2L address mapping table 610 (e.g., the set of logical addresses such as LBA {LBA(A), LBA(B), LBA(Z), LBA(C), ..., LBA(Z)}) for address comparison, wherein the at least one corresponding local L2P address mapping table may be collectively referred to as an L2P address mapping table 620. The L2P address mapping table 620 may include L2P address mapping information such as a set of L2P address mapping table entries for indicating a set of L2P mapping relationships from a series of logical addresses (e.g., a series of LBAs such as LBA {LBA(A), LBA(B), LBA(C), LBA(D), ..., LBA(Z)}) to associated physical addresses (e.g., the location of valid data in the host data in the NV memory 120). Assuming that there are no duplicate P2L address mapping table entries in the group of P2L address mapping table entries (for example, the group of logical addresses), the group of P2L mapping relationships indicated by the P2L address mapping table 610 and the group of L2P mapping relationships indicated by the L2P address mapping table 620 can be reverse mapping relationships to each other, but the present invention is not limited to this.

[0096] like Figure 6 As shown in the right half of the L2P address mapping table 620, the set of L2P address mapping information, such as the set of L2P address mapping table entries, may be the above-mentioned associated physical addresses (e.g., the location of the valid data in the host data in the NV memory 120), such as the pages {PAGE(0), PAGE(1), PAGE(2), PAGE(3), ..., PAGE(N)} of the block BLK(W) of the die DIE(X). P )} (denoted as "DIE(X)", "BLK(W)" and "{PAGE(0),PAGE(1),PAGE(2),PAGE(3),…,PAGE(N P )}" combination for simplicity), but the present invention is not limited to this. For example, the set of L2P address mapping information may include a combination of the series of logical addresses and the above-mentioned associated physical addresses. In addition, the memory controller 110 may refer to the P2L address mapping table 610 and the L2P address mapping table 620 to determine which LBAs the valid data in the host data written to the NV memory 120 is in. For example, during GC, the memory controller 110 may read the P2L address mapping table 610 of block BLK(W) from block BLK(W), and read the system block BLK SYSTEMThe latest L2P address mapping information in the P2L address mapping table 610, such as the group of L2P address mapping information in the L2P address mapping table 620, is sequentially compared with the group of P2L address mapping table entries in the P2L address mapping table 610 (for example: the group of logical addresses such as LBA {LBA(A), LBA(B), LBA(Z), LBA(C),…, LBA(Z)}) and the corresponding L2P address mapping table entries in the P2L address mapping table 610 to obtain the location of the valid data of the block BLK(W).

[0097] The memory controller 110 may update any local L2P address mapping table in the global L2P address mapping table 120AM, such as the L2P address mapping table 620, to maintain the set of L2P address mapping information therein as the latest L2P address mapping information. When the set of L2P address mapping information in the L2P address mapping table 620 is the latest L2P address mapping information, the memory controller 110 may determine whether the stored data is valid or invalid data based on the L2P address mapping table 620. In addition, the set of L2P address mapping information can be implemented as per-NV-memory-element mapping information such as per-die / per-chip mapping information to integrate the die / chip information indicating the die / chip to which the block BLK(W) belongs (e.g., die DIE(X) or chip CHIP(X)) into the set of L2P address mapping table entries (e.g., the above-mentioned associated physical addresses) to allow the memory controller 110 to refer to the L2P address mapping table 620 to determine in which block BLK (e.g., block BLK(W)) the valid data is located and to determine to which die / chip (e.g., die DIE(X) or chip CHIP(X)) this block BLK (e.g., block BLK(W)) belongs. For example, during the GC, the memory controller 110 may determine that the latest data of LBA LBA(Z) is located in page PAGE(N) of block BLK(W) of die DIE(X). P ), but the present invention is not limited thereto. According to some embodiments, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E It can be implemented by the plurality of flash memory chips {CHIP}, and Figure 6In the set of L2P address mapping table entries in the L2P address mapping table 620 shown, the local L2P address mapping table information for indicating the bare die DIE(X) (labeled as "DIE(X)" for simplicity) can be replaced by the local L2P address mapping table information for indicating the chip CHIP(X) (which can be labeled as "CHIP(X)" for simplicity). During the GC, the memory controller 110 can determine that the latest data of LBALBA(Z) is located at the page PAGE(N) of the block BLK(W) of the chip CHIP(X). P ).

[0098] Fig. 7A According to one embodiment of the present invention, a NV memory device dedicated memory region control scheme of the method is described. Assuming that the plurality of NV memory devices 122-1, 122-2, ..., and 122-N E The memory controller 110 may be implemented by the plurality of flash memory dies {DIE} for ease of understanding. The memory controller 110 may be implemented by the plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E (For example: bare die DIE(1), DIE(2), ..., and DIE(N E ))Number of E A memory area 116R in the random access memory 116 for storing the temporary DGC management table 116DM is divided into N E sub-regions corresponding to the bare die DIE(1), DIE(2), ..., and DIE(N E ) E A die-specific memory area {R_DIE} (for example: a die-specific memory area {R_DIE(1), R_DIE(2), …, R_DIE(N E )}), and respectively in the N E The die-specific memory area {R_DIE} stores the corresponding die DIE(1), DIE(2), ..., and DIE(N E ) E DGC management table {DM} (for example: DGC management table {DM(1), DM(2),…, DM(N E )}), where N E The sub-regions can be regarded as N E For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N may be configured to have a per-die dedicated sub-region, but the present invention is not limited thereto. E can be implemented by the plurality of flash memory chips {CHIP}, and the N EThe die-specific memory area {R_DIE} can be replaced by N E chip-specific memory area {R_CHIP} (for example: chip-specific memory area {R_CHIP(1), R_CHIP(2),…, R_CHIP(N E )}) to store the N E DGC management table {DM}. In this case, the N E The sub-regions can be regarded as N E A per-chip dedicated sub-region.

[0099] like Fig. 7A As shown, the N E The die-specific memory region {R_DIE} may include die-specific memory regions R_DIE(X) and R_DIE(Y) corresponding to the die DIE(X) and DIE(Y), respectively, for storing the DGC management tables DM(X) and DM(Y) corresponding to the die DIE(X) and DIE(Y), respectively, wherein the temporary DGC management table 116DM may include the DGC management tables DM(X) and DM(Y), but the present invention is not limited thereto. According to some embodiments, more sub-regions such as more die-specific memory regions {R_DIE} and more DGC management tables {DM} therein may be depicted in the memory region 116R.

[0100] Figure 7B Draw Fig. 7A The memory controller 110 may operate according to the above-mentioned at least one control scheme (e.g., the NV memory element aware block selection control scheme, the comparison control scheme, and the NV memory element dedicated memory region control scheme) of the method, and in particular, update the above-mentioned at least one DGC management table (e.g., DGC management table 116DM, and / or DGC management table 120DM) for related operations. The memory controller 110 may compare the P2L address mapping table 610 and the L2P address mapping table 620 to determine the location information of the valid data in the host data written to the NV memory 120, and record the location information to indicate the location of the valid data, for example, indicating which pages {PAGE} of which block BLK (e.g., block BLK (W)) the valid data is located and which bare die (e.g., bare die DIE (X)) this block BLK (e.g., block BLK (W)) belongs to.

[0101] For example, during GC, the memory controller 110 may update the N EAt least a portion of the DGC management tables {DM} in the DGC management tables {DM}, such as DGC management tables DM(X) and DM(Y). Figure 7B As shown in the left half of , the location information recorded by the memory controller 110 in the DGC management table DM(X) may include the addresses of the pages {PAGE(0), PAGE(2), PAGE(3), PAGE(5), PAGE(8)} of the block BLK(A) of the bare die DIE(X) (labeled as a combination of "DIE(X)", "BLK(A)" and "{PAGE(0), PAGE(2), PAGE(3), PAGE(5), PAGE(8)}" for simplicity), and may include the addresses of the pages {PAGE(1), PAGE(2), PAGE(3), PAGE(8)} of the block BLK(C) of the bare die DIE(X) (labeled as a combination of "DIE(X)", "BLK(C)" and "{PAGE(1), PAGE(2), PAGE(3), PAGE(8)}" for simplicity). Figure 7B As shown in the right half of , the location information recorded by the memory controller 110 in the DGC management table DM(Y) may include the addresses of pages {PAGE(2), PAGE(4), PAGE(5), PAGE(6), PAGE(8)} of block BLK(B) of the bare die DIE(Y) (labeled as a combination of "DIE(Y)", "BLK(B)" and "{PAGE(2), PAGE(4), PAGE(5), PAGE(6), PAGE(8)}" for simplicity), and may include the addresses of pages {PAGE(2), PAGE(4), PAGE(6), PAGE(8)} of block BLK(D) of the bare die DIE(Y) (labeled as a combination of "DIE(Y)", "BLK(D)" and "{PAGE(2), PAGE(4), PAGE(6), PAGE(8)}" for simplicity).

[0102] Figure 7C Draw Fig. 7A Some other implementation details of the NV memory element dedicated memory area control scheme shown, such as Figure 7B The die-specific memory regions R_DIE(X) and R_DIE(Y) shown corresponding to die DIE(X) and DIE(Y) respectively may be replaced by Figure 7C The chip-specific memory regions R_CHIP(X) and R_CHIP(Y) are shown corresponding to the chips CHIP(X) and CHIP(Y), but the present invention is not limited thereto. According to some embodiments, more sub-regions such as more chip-specific memory regions {R_CHIP} and more DGC management tables {DM} therein may be depicted in the memory region 116R.

[0103] Figure 8 A workflow of the method is described according to an embodiment of the present invention. The memory controller 110 may receive at least one first command (e.g., a write command) among the multiple host commands from the host device 50 via the transmission interface circuit 118 within the memory controller 110, and perform at least one access operation on the NV memory 120 according to the at least one first command, wherein the at least one first command may indicate at least one write request from the host device 50, and the at least one access operation may represent at least one write operation. For example, the memory controller 110 may write (or program) the host data from the host device 50 to at least one block BLK among the multiple blocks {BLK}, and correspondingly update the global L2P address mapping table 120AM in the NV memory 120 to indicate the mapping relationship between the logical address and the physical address. In addition, the memory controller 110 may execute a GC process such as Figure 8 The workflow shown starts to perform GC on the NV memory 120. Since the memory controller 110 has updated the global L2P address mapping table 120AM before performing the GC process, the multiple local L2P address mapping tables in the global L2P address mapping table 120AM can be regarded as the latest local L2P address mapping tables.

[0104] In step S11, the memory controller 110 may generate a plurality of NV memory elements (eg, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N) according to the at least one NV memory element. E , such as bare die DIE(1), DIE(2), ..., and DIE(N E ) or chips CHIP(1), CHIP(2), ..., and CHIP(N E ))Number of E The memory area 116R for storing the temporary DGC management table 116DM in the random access memory 116 in the memory controller 110 is divided into the N E sub-regions as N E a dedicated memory region {R_Dedicated}, wherein the number of the at least one NV memory element is N E In particular, the at least one NV memory element may include the plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E , and the N E The dedicated memory regions {R_Dedicated} may represent the memory regions corresponding to the plurality of NV memory elements 122 - 1 , 122 - 2 , . . . , and 122 -N, respectively. E NE NV-memory-element-dedicated memory regions, such as corresponding to NV memory elements {122-1, 122-2, ..., 122-N E} of the dedicated memory area {R_Dedicated(1), R_Dedicated(2), …, R_Dedicated(N E )} for storing the NV memory elements {122-1, 122-2, ..., 122-N respectively. E} E DGC management table {DM} (for example: DGC management table {DM(1), DM(2),…, DM(N E )}).

[0105] For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E The plurality of flash memory dies {DIE} may be represented by dies DIE(1), DIE(2), ..., and DIE(N E ), and the N E A dedicated memory area {R_Dedicated} such as a dedicated memory area {R_Dedicated(1), R_Dedicated(2), ..., R_Dedicated(N E )} may represent the N corresponding to the plurality of flash memory bare dies {DIE} respectively. E There are die-specific memory regions {R_DIE}, such as corresponding to the die {DIE(1), DIE(2), ..., DIE(N E )} of the die-specific memory area {R_DIE(1), R_DIE(2), …, R_DIE(N E )}(For example: Fig. 7A As another example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N may be configured to have a plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E can represent the plurality of flash memory chips {CHIP} such as chips CHIP(1), CHIP(2), . . . , and CHIP(N E ), and the N E A dedicated memory area {R_Dedicated} such as a dedicated memory area {R_Dedicated(1), R_Dedicated(2), ..., R_Dedicated(N E )} may represent the N corresponding to the plurality of flash memory chips {CHIP} respectively. Echip-specific memory regions {R_CHIP}, such as corresponding to chips CHIP(1), CHIP(2), . . . , and CHIP(N E ) of the chip-specific memory area {R_CHIP(1), R_CHIP(2),…, R_CHIP(N E )}(For example: Figure 7C The chip-specific memory areas R_CHIP(X) and R_CHIP(Y) are shown.

[0106] In step S12, the memory controller 110 may select a plurality of source blocks {BLK} from the plurality of blocks {BLK}. SOURCE}.

[0107] In step S13, the memory controller 110 may read the plurality of source blocks {BLK SOURCE Any source block BLK in SOURCE A P2L address mapping table (for example: Figure 6 P2L address mapping table 610 shown).

[0108] In step S14, the memory controller 110 may generate a memory block BLK according to any of the above source blocks BLK. SOURCE The P2L address mapping table (for example: Figure 6 The P2L address mapping table 610 shown in FIG. 6 shows a read of a latest L2P address mapping table (eg, Figure 6 In particular, according to any P2L address mapping table entry in the P2L address mapping table, a corresponding L2P address mapping table entry in the latest L2P address mapping table is read to determine whether any of the above source blocks BLK SOURCE Whether the data corresponding to the P2L address mapping table entry is valid data.

[0109] For example, the latest L2P address mapping table may represent the address corresponding to any of the above source blocks BLK in the plurality of local L2P address mapping tables. SOURCEA local L2P address mapping table. According to a logical address indicated by any of the above P2L address mapping table entries in the P2L address mapping table, the memory controller 110 may select a local L2P address mapping table having the corresponding L2P address mapping table entry (e.g., an L2P address mapping table entry for mapping from the logical address to an associated physical address) from the multiple local L2P address mapping tables as the latest L2P address mapping table, wherein the local L2P address mapping table may have a predetermined mapping range for mapping from a series of logical addresses including the logical address to the associated physical addresses respectively. Since the memory controller 110 has updated the multiple local L2P address mapping tables in the global L2P address mapping table 120AM before executing the GC process, all L2P address mapping table entries in the latest L2P address mapping table should be correct. Therefore, if any of the above P2L address mapping table entries and the corresponding L2P address mapping table entry match each other (for example, the P2L address mapping relationship indicated by the P2L address mapping table entry and the L2P address mapping relationship indicated by the L2P address mapping table entry are the reverse mapping relationship of each other), then in any of the above source blocks BLK SOURCE The data corresponding to any of the above P2L address mapping table entries is valid data; otherwise, in any of the above source blocks BLK SOURCE The data corresponding to any of the above P2L address mapping table entries is invalid data.

[0110] like Figure 8 As shown, the memory controller 110 may execute at least one loop including at least a portion of steps S13 to S19, and in particular, execute step S14 multiple times to generate a plurality of source blocks BLK according to any of the above source blocks BLK. SOURCE A set of P2L address mapping table entries in the P2L address mapping table is used to read a set of L2P address mapping table entries in the latest L2P address mapping table to determine whether any of the above source blocks BLK SOURCE Whether the data corresponding to the group of P2L address mapping table entries is valid data, Figure 6 The P2L address mapping table entries in the P2L address mapping table 610 shown may be used as an example of the set of P2L address mapping table entries. Figure 6 The L2P address mapping table entries in the L2P address mapping table 620 shown can be used as examples of the group of L2P address mapping table entries, but the present invention is not limited thereto. Assume that any of the above P2L address mapping table entries is one of the group of P2L address mapping table entries, and the corresponding L2P address mapping table entry is one of the group of L2P address mapping table entries. If any of the above P2L address mapping table entries and the corresponding L2P address mapping table entry match each other, then in any of the above source blocks BLKSOURCE The data corresponding to any of the above P2L address mapping table entries is valid data; otherwise, in any of the above source blocks BLK SOURCE Similarly, if the set of P2L address mapping table entries and the set of L2P address mapping table entries match each other (for example, the P2L address mapping relationship indicated by the set of P2L address mapping table entries and the L2P address mapping relationship indicated by the set of L2P address mapping table entries are the reverse mapping relationship of each other), then in any of the above source blocks BLK SOURCE All data corresponding to the group of P2L address mapping table entries are valid data.

[0111] In step S15, the memory controller 110 may compare any of the above source blocks BLK SOURCE The P2L address mapping table and the latest L2P address mapping table, in particular, compare any of the above P2L address mapping table entries with the corresponding L2P address mapping table entry to generate a comparison result for indicating that any of the above source blocks BLK SOURCE Whether the data corresponding to any of the above P2L address mapping table entries is valid data. For example, the comparison result may be equal to one of a plurality of predetermined comparison results, and the plurality of predetermined comparison results may include:

[0112] (1) a first predetermined comparison result: any of the P2L address mapping table entries and the corresponding L2P address mapping table entry match each other, wherein the P2L address mapping relationship indicated by the P2L address mapping table entry and the L2P address mapping relationship indicated by the L2P address mapping table entry are reverse mapping relationships to each other; and

[0113] (2) a second predetermined comparison result: any of the P2L address mapping table entries and the corresponding L2P address mapping table entry do not match each other, wherein the P2L address mapping relationship indicated by the P2L address mapping table entry and the L2P address mapping relationship indicated by the L2P address mapping table entry are not reverse mapping relationships to each other;

[0114] However, the present invention is not limited thereto.

[0115] In step S16, the memory controller 110 may determine, based on the comparison result, whether any of the source blocks BLK SOURCE Whether the data corresponding to any of the P2L address mapping table entries is valid data. If yes (for example, the comparison result is equal to the first predetermined comparison result), proceed to step S17; if no (for example, the comparison result is equal to the second predetermined comparison result), proceed to step S19.

[0116] In step S17, the memory controller 110 can obtain the valid data position information of the data corresponding to any one of the above P2L address mapping table entries, such as the position information of the data corresponding to any one of the above source blocks BLK SOURCE in the data corresponding to any one of the above P2L address mapping table entries. In particular, store the valid data position information in one of the N E corresponding dedicated memory areas {R_Dedicated} of the dedicated memory areas, such as the dedicated memory area R_Dedicated of the NV memory element to which any one of the above source blocks BLK SOURCE belongs.

[0117] In step S18, the memory controller 110 can determine whether the data volume DataSize of the valid data corresponding to the checked P2L address mapping table entry reaches a first predetermined data volume threshold DataSizeTh. If so (for example: DataSize = DataSizeTh), go to step S21; if not (for example: DataSize < DataSizeTh), go to step S19. For example, the first predetermined data volume can represent the storage capacity of a data area of a destination block BLK DESTINATION but the present invention is not limited thereto. According to some embodiments, the first predetermined data volume can be varied to initiate at least one GC operation earlier.

[0118] In step S19, the memory controller 110 can determine whether to continue reading the P2L address mapping table of any one of the above source blocks BLK SOURCE If so, go to step S13; if not, go to step S20. For example, when the P2L address mapping table of this source block BLK SOURCE has not been completely read (for example: at least one P2L address mapping table entry in this P2L address mapping table has not been read), the memory controller 110 can execute step S13 to continue reading the P2L address mapping table. In particular, execute at least a part of steps S13 to S18 to perform a similar operation on the next P2L address mapping table entry in this P2L address mapping table. For another example, when the P2L address mapping table of this source block BLK SOURCE has been completely read (for example: all P2L address mapping table entries in this P2L address mapping table have been read), the memory controller 110 can execute step S20 to perform subsequent operations.

[0119] In step S20, the memory controller 110 can determine whether there is a next source block BLK to be checked in the plurality of source blocks {BLK SOURCE} SOURCE(marked as "next BLK SOURCE If yes, go to step S13; if no, go to step S21. For example, when the plurality of source blocks {BLK SOURCE} has not been fully checked (for example: the multiple source blocks {BLK SOURCE At least one source block BLK in SOURCE Has not been checked, and / or at least one of the above source blocks BLK SOURCE At least one P2L address mapping table has not been read yet), the memory controller 110 may execute step S13 to continue checking the plurality of source blocks {BLK SOURCE In particular, at least a portion of steps S13 to S19 is executed to select the next source block BLK to be checked. SOURCE And for the next source block BLK to be checked SOURCE Perform similar operations. For another example, when the multiple source blocks {BLK SOURCE} has been fully checked (for example: the multiple source blocks {BLK SOURCE Each source block BLK in SOURCE has been checked), the memory controller 110 may execute step S21 to perform subsequent operations.

[0120] like Figure 8 As shown, the memory controller 110 may execute at least one loop including at least a portion of steps S13 to S20, and in particular, execute step S13 multiple times to read the multiple source blocks {BLK SOURCE}, execute step S14 multiple times to map the P2L addresses of the multiple source blocks {BLK SOURCE}, and execute step S15 multiple times to compare the multiple source blocks {BLK SOURCE}, and the at least one latest L2P address mapping table to generate multiple sets of comparison results. For example, the at least one latest L2P address mapping table may represent the local L2P address mapping tables corresponding to the multiple source blocks {BLK SOURCE}at least one local L2P address mapping table.

[0121] The memory controller 110 may compare the plurality of source blocks {BLK SOURCE} respective P2L address mapping tables and the at least one latest L2P address mapping table are respectively EIn the dedicated memory area {R_Dedicated}, valid data location information {INFO_VDL_Dedicated} is generated and stored to indicate the location of valid data per non-volatile memory element (per-NV-memory-element). In particular, the at least one NV memory element includes the plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E In the case of SOURCE} respective P2L address mapping tables and the at least one latest L2P address mapping table are respectively E The valid data location information {INFO_VDL_Dedicated} is generated and stored in the dedicated memory area {R_Dedicated} to indicate the plurality of NV memory elements 122-1, 122-2, ..., and 122-N respectively. E The location of the respective valid data, such as in the plurality of source blocks {BLK SOURCE} the respective positions of all valid data in it.

[0122] For example, the N E The valid data location information {INFO_VDL_Dedicated} of the dedicated memory region {R_Dedicated} may include the valid data location information {INFO_VDL_Dedicated} corresponding to the plurality of NV memory elements 122-1, 122-2, . . . , and 122-N. E Multiple sets of valid data location information, such as N E Group valid data location information {INFO_VDL_Dedicated(1),INFO_VDL_Dedicated(2),…,INFO_VDL_Dedicated(N E )}. The memory controller 110 can obtain E A dedicated memory region {R_Dedicated} selects a dedicated memory region R_Dedicated(n) corresponding to any of the above NV memory elements 122-n (eg, bare die DIE(n) or chip CHIP(n)), and generates and stores the N in the dedicated memory region R_Dedicated(n). E Group valid data location information {INFO_VDL_Dedicated(1),INFO_VDL_Dedicated(2),…,INFO_VDL_Dedicated(N E)} corresponding to any of the NV memory elements 122-n, for indicating the plurality of source blocks {BLK SOURCE} in all source blocks {BLK SOURCE}The location of valid data.

[0123] In step S21, the memory controller 110 may store the N E The valid data location information {INFO_VDL_Dedicated} of the dedicated memory areas {R_Dedicated}, such as respectively stored in the dedicated memory areas {R_Dedicated(1), R_Dedicated(2), ..., R_Dedicated(N E )} E Group valid data location information {INFO_VDL_Dedicated(1),INFO_VDL_Dedicated(2),…,INFO_VDL_Dedicated(N E )}, perform a plurality of GC operations, wherein at least a portion of the plurality of GC operations (e.g., a portion of the GC operations or all of the GC operations) are performed in a parallel processing manner. For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E The NV memory element 122-n1 and the NV memory element 122-n2 may be included (eg, "n1" and "n2" may represent an interval [1, N E ]), and the at least part of the GC operations may include a first GC operation and a second GC operation corresponding to the NV memory element 122-n1 and the NV memory element 122-n2, respectively. In particular, the memory controller 110 may perform the first GC operation on the NV memory element 122-n1 and the second GC operation on the NV memory element 122-n2. Assuming n1=X and n2=Y for ease of understanding, the NV memory element 122-n1 may represent a bare die DIE(X) / chip CHIP(X), and the NV memory element 122-n2 may represent a bare die DIE(Y) / chip CHIP(Y), but the present invention is not limited thereto.

[0124] In the first GC operation, the memory controller 110 may sequentially read the first valid data of the NV memory element 122-n1 (e.g., bare die DIE(X) or chip CHIP(X)) according to an n1th set of valid data location information INFO_VDL_Dedicated(n1) stored in the dedicated memory area R_Dedicated(n1), and write the first valid data to a destination area block BLK belonging to the NV memory element 122-n1. DESTINATION In addition, in the second GC operation, the memory controller 110 may sequentially read the second valid data of the NV memory element 122-n2 (e.g., bare die DIE(Y) or chip CHIP(Y)) according to an n2th set of valid data location information INFO_VDL_Dedicated(n2) stored in the dedicated memory area R_Dedicated(n2), and write the second valid data to a destination area block BLK belonging to the NV memory element 122-n2. DESTINATION (n2) For the sake of brevity, similar contents in this embodiment are not repeated here.

[0125] For a better understanding, the method can be used Figure 8 According to some embodiments, one or more steps may be performed in Figure 8 Add, delete or modify the workflow shown.

[0126] Fig.9A The N involved in this method is shown E An example of a dedicated memory region {R_Dedicated}, Fig. 9B The N involved in this method is shown E For example, a die-specific memory area {R_DIE} Fig. 9C The N involved in this method is shown E An example of a chip-specific memory area {R_CHIP}. Fig.9A As shown, memory region 116R may include the N E A dedicated memory area {R_Dedicated} such as a dedicated memory area {R_Dedicated(1), ..., R_Dedicated(N E )}, and the memory controller 110 may use the dedicated memory regions {R_Dedicated(1), ..., R_Dedicated(N E )} to store the DGC management table {DM(1),…,DM(N E )}. When the N EA dedicated memory region {R_Dedicated} is implemented as the N E There are die-specific memory areas {R_DIE} such as die-specific memory areas {R_DIE(1), ..., R_DIE(N E )}, the above DGC management table {DM(1),…,DM(N E )} can also be called a die-dedicated GC (DDGC) management table, and can therefore be used in Fig. 9B is rewritten as the DDGC management table {DDM(1),…,DDM(N E )}, and the memory controller 110 may use the die-specific memory areas {R_DIE(1), ..., R_DIE(N E )} to store the DDGC management table {DDM(1),…,DDM(N E )}. When the N E A dedicated memory region {R_Dedicated} is implemented as the N E chip-specific memory areas {R_CHIP} such as chip-specific memory areas {R_CHIP(1), ..., R_CHIP(N E )}, the above DGC management table {DM(1),…,DM(N E )} can also be called a chip-dedicated GC (CDGC) management table, and can therefore be used in Fig. 9C is rewritten as the CDGC management table {CDM(1),…,CDM(N E )}, and the memory controller 110 may use chip-specific memory areas {R_CHIP(1), . . . , R_CHIP(N E )} to store the CDGC management table {CDM(1),…,CDM(N E For the sake of brevity, similar contents in these embodiments are not repeated here.

[0127] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for performing garbage collection (GC) management of a memory device by means of dedicated information control, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the non-volatile memory comprising at least one non-volatile memory element, the at least one non-volatile memory element comprising a plurality of blocks, the method comprising: Utilizing the memory controller to receive at least one first command from a host device via a transmission interface circuit in the memory controller, and performing at least one access operation on the non-volatile memory according to the at least one first command, wherein the at least one first command indicates at least one write request from the host device; as well as Executing a garbage collection process to start garbage collection of the non-volatile memory, wherein the garbage collection process includes: Dividing a memory region of a volatile memory in the memory controller into a plurality of sub-regions according to the number of the at least one non-volatile memory element to serve as a plurality of dedicated memory regions, wherein the number of the at least one non-volatile memory element is greater than one; selecting a plurality of source blocks from the plurality of blocks; Reading respective physical-to-logical (P2L) address mapping tables of the plurality of source blocks; Reading at least one latest logical-to-physical (L2P) address mapping table in the non-volatile memory according to the respective physical-to-logical address mapping tables of the plurality of source blocks; Comparing the respective physical-to-logical address mapping tables of the plurality of source blocks with the at least one latest logical-to-physical address mapping table to generate and store valid-data-location information in the plurality of dedicated memory regions respectively for indicating the location of valid data per-NV-memory-element; as well as A plurality of garbage collection operations are performed according to the valid data location information respectively stored in the plurality of dedicated memory areas, wherein at least a portion of the plurality of garbage collection operations are performed in a parallel processing manner.

2. The method according to claim 1, characterized in that The at least one non-volatile memory element includes a plurality of non-volatile memory elements, and the plurality of dedicated memory regions represent a plurality of non-volatile memory element dedicated (NV-memory-element-dedicated) memory regions respectively corresponding to the plurality of non-volatile memory elements.

3. The method according to claim 2, characterized in that The plurality of non-volatile memory elements represent a plurality of flash memory dies, and the plurality of dedicated memory regions represent a plurality of die-dedicated memory regions respectively corresponding to the plurality of flash memory dies.

4. The method according to claim 2, characterized in that The plurality of non-volatile memory elements represent a plurality of flash memory chips, and the plurality of dedicated memory regions represent a plurality of chip-specific memory regions respectively corresponding to the plurality of flash memory chips.

5. The method according to claim 1, characterized in that The memory controller is used to write host data from the host device into at least one of the multiple blocks, and correspondingly update a global logical-to-physical address mapping table in the non-volatile memory to indicate a mapping relationship between a logical address and a physical address, wherein the global logical-to-physical address mapping table is divided into a plurality of local logical-to-physical address mapping tables; and the at least one latest logical-to-physical address mapping table represents at least one local logical-to-physical address mapping table corresponding to the multiple source blocks in the multiple local logical-to-physical address mapping tables.

6. The method according to claim 1, characterized in that The at least one non-volatile memory element comprises a plurality of non-volatile memory elements; and comparing the respective physical to logical address mapping tables of the plurality of source blocks and the at least one latest logical to physical address mapping table to respectively generate and store the valid data location information in the plurality of dedicated memory areas further comprises: The respective physical-to-logical address mapping tables of the plurality of source blocks and the at least one latest logical-to-physical address mapping table are compared to generate and store the valid data location information in the plurality of dedicated memory areas respectively, so as to indicate the locations of the respective valid data of the plurality of non-volatile memory elements respectively.

7. The method according to claim 6, characterized in that The valid data location information respectively stored in the plurality of dedicated memory areas includes a plurality of sets of valid data location information corresponding to the plurality of non-volatile memory elements; The memory controller is used to select a dedicated memory area corresponding to any non-volatile memory element among the multiple dedicated memory areas, and generate and store a set of valid data location information corresponding to the any non-volatile memory element among the multiple sets of valid data location information in the dedicated memory area, so as to indicate the location of the valid data of all source blocks belonging to the any non-volatile memory element among the multiple source blocks.

8. The method according to claim 1, characterized in that The at least one non-volatile memory element includes a plurality of non-volatile memory elements, the plurality of non-volatile memory elements include a first non-volatile memory element and a second non-volatile memory element, and the at least a portion of the garbage collection operation includes a first garbage collection operation and a second garbage collection operation corresponding to the first non-volatile memory element and the second non-volatile memory element, respectively; And the memory controller is used to perform the first garbage collection operation on the first non-volatile memory element and the second garbage collection operation on the second non-volatile memory element.

9. The method according to claim 8, characterized in that In the first garbage collection operation, the memory controller reads first valid data of the first non-volatile memory element according to a first set of valid data location information stored in a first dedicated memory area, and writes the first valid data to a first destination area block belonging to the first non-volatile memory element; And in the second garbage collection operation, the memory controller reads second valid data of the second non-volatile memory element according to a second set of valid data location information stored in a second dedicated memory area, and writes the second valid data to a second destination area block belonging to the second non-volatile memory element.

10. The method according to claim 1, characterized in thatThe valid data location information respectively stored in the multiple dedicated memory areas includes multiple sets of valid data location information corresponding to the multiple non-volatile memory elements, wherein the multiple sets of valid data location information include a first set of valid data location information corresponding to the first non-volatile memory element and a second set of valid data location information corresponding to the second non-volatile memory element, and the first set of valid data location information and the second set of valid data location information are respectively stored in a first dedicated memory area and a second dedicated memory area among the multiple dedicated memory areas.

11. A memory controller of a memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the non-volatile memory comprising at least one non-volatile memory element, the at least one non-volatile memory element comprising a plurality of blocks, the memory controller comprising: a processing circuit for controlling the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, wherein the processing circuit is used to perform garbage collection (GC) management of the memory device by means of dedicated information control; as well as a transmission interface circuit for communicating with the host device; in: The memory controller receives at least one first command from the host device through the transmission interface circuit in the memory controller, and performs at least one access operation on the non-volatile memory according to the at least one first command, wherein the at least one first command indicates at least one write request from the host device; and The memory controller executes a garbage collection process to start garbage collection of the non-volatile memory, wherein the garbage collection process includes: Dividing a memory region of a volatile memory in the memory controller into a plurality of sub-regions according to the number of the at least one non-volatile memory element to serve as a plurality of dedicated memory regions, wherein the number of the at least one non-volatile memory element is greater than one; selecting a plurality of source blocks from the plurality of blocks; Reading respective physical-to-logical (P2L) address mapping tables of the plurality of source blocks; Reading at least one latest logical-to-physical (L2P) address mapping table in the non-volatile memory according to the respective physical-to-logical address mapping tables of the plurality of source blocks; Comparing the respective physical-to-logical address mapping tables of the plurality of source blocks with the at least one latest logical-to-physical address mapping table to generate and store valid-data-location information in the plurality of dedicated memory regions respectively for indicating the location of valid data per-NV-memory-element; and A plurality of garbage collection operations are performed according to the valid data location information respectively stored in the plurality of dedicated memory areas, wherein at least a portion of the plurality of garbage collection operations are performed in a parallel processing manner.

12. The memory device comprising the memory controller as claimed in claim 11, wherein the memory device comprises: The non-volatile memory is used to store information; and The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

13. An electronic device comprising the memory device as claimed in claim 12, and further comprising: The host device is coupled to the memory device, wherein the host device comprises: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor for providing power to the at least one processor and the memory device; The memory device provides storage space for the host device.

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