Information packet transmitting and reading method
By using cyclic redundancy checksum converter type judgment on the serial universal input and output protocol bus between the substrate management controller and complex programmable logic devices, the elasticity and reliability problems of information packet transmission are solved, and the problem of realization of the implementation of the Efficient transmission and accurate reading of diversified data are enhanced, and the reliability of the signal is enhanced.
Patent Information
- Application Number
- CN202310686862.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-09
- Publication Date
- 2024-12-10
AI Technical Summary
The existing information packet delivery method lacks flexibility and variation between the substrate management controller and complex programmable logic devices, making it difficult to effectively transmit diversified information data, especially on buses that support serial universal input and output protocols. There are problems with reliability and incorrect judgments.
Cyclic redundancy is performed by defining each packet containing 16 bits of bytes, including check bits and channel number bits, on the serial universal input and output protocol bus between the substrate management controller and complex programmable logic devices. Checksum converter type judgment ensures the accuracy and reliability of data transmission, and processes and converts information in sequence according to pre-set rules.
It realizes efficient transmission and reading of diversified information data, enhances signal reliability, avoids misjudgment of error messages, and supports numerical judgment of voltage of 8-bit or 10-bit analog-to-digital converters, improving data transmission Flexibility and accuracy.
Smart Images
Figure CN119105984A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an information packet transmission and reading method, and in particular to an information packet transmission and reading method used between a baseboard management controller and a complex programmable logic device (CPLD). Background Art
[0002] An existing computer system receives a packet from a complex programmable logic device (CPLD) via a baseboard management controller (BMC) to obtain multiple numerical data from multiple sensors of the computer system. In more detail, the complex programmable logic device receives the numerical data from the sensors in digital form (Digital), or receives the digital data in part digital form and part analog form (Analog), and converts the analog and digital formats by a built-in analog-to-digital converter. The packet is transmitted via a bus that is electrically connected between the baseboard management controller and the complex programmable logic device and supports a serial general purpose input and output (SGPIO) protocol. However, although the packet supports the specification of the serial general purpose input and output protocol, whether it has other flexibility and changes to transmit information becomes a problem to be solved. Summary of the invention
[0003] Therefore, the object of the present invention is to provide a more diverse information packet transmission and reading method.
[0004] Therefore, the present invention provides a method for transmitting and reading information packets, which is suitable for a bus electrically connected between a baseboard management controller and a complex programmable logic device and supports a serial general purpose input and output (SGPIO) protocol, and includes steps (A) to (G). In step (A), the baseboard management controller and the complex programmable logic device act as an initiator (Initiator) and a target (Target) of the serial general purpose input and output protocol on the bus respectively. In step (B), the complex programmable logic device transmits multiple packets to the baseboard management controller via an SDataIn signal line of the bus, and each of the packets includes a plurality of bits whose total number is a multiple of 16. The complex programmable logic device defines the bits of each packet in sequence according to a pre-set rule, wherein all or part of them are bytes, each byte includes the 16 bits that are not repeated, and two of the 16 bits are two check bits, and one of the 16 bits is a converter type bit, and three of the 16 bits are three channel number bits. In step (C), the baseboard management controller obtains the bytes in sequence according to a pre-set rule for the bits of the packet received each time. In step (D), the baseboard management controller performs and determines whether the cyclic redundancy check (CRC) of the remaining 14 bits of the byte is correct according to the logic values of the two check bits corresponding thereto for each byte. In step (E), when the baseboard management controller determines that the cyclic redundancy check of the 14 bits of the byte is correct, a converter value corresponding to the 10 bits of the byte is determined according to the logic value of the converter type bit corresponding thereto. In step (F), the baseboard management controller determines a corresponding channel number for the byte according to the logic values of the three channel number bits corresponding thereto. In step (G), the baseboard management controller determines a converter number corresponding to the converter value according to the channel number.
[0005] In some implementations, in step (B), the number of bits included in each packet is 128, and the 128 bits are represented by Addr[0:127]. In step (C), the number of bytes is four, and they are Addr[64:79], Addr[80:95], Addr[96:111], and Addr[112:127].
[0006] In some implementations, in step (C), the baseboard management controller determines the logic value of the bits Addr[0:63] of each of the packets according to a preset rule to obtain a plurality of logic states corresponding to a plurality of different signals.
[0007] In some other implementations, in step (D), the 16 bits of each byte are defined as a 0th bit to a 15th bit, and the two check bits of each byte are the 7th bit and the 15th bit.
[0008] In some implementations, in step (E), the converter type bit of each byte is bit 14. When the baseboard management controller determines that the converter type bit of the byte is equal to a first logic value, the converter value of the byte is determined to be equal to bits 0 to 3 and bits 8 to 11 arranged from the most significant bit (MSB) to the least significant bit (LSB).
[0009] In some embodiments, wherein, in step (E), when the baseboard management controller determines that the converter type bit of the byte is equal to a second logic value, it determines that the converter value of the byte is equal to the 0th to the 3rd bits and the 8th to the 13th bits arranged from the most significant bit to the least significant bit.
[0010] In some implementations, in step (F), the three channel number bits of each byte are bit 4 to bit 6. The baseboard management controller determines the decimal value of the bit 4 to bit 6 of the byte arranged from the most significant bit to the least significant bit as the channel number.
[0011] In some implementations, in step (G), when the baseboard management controller determines that the channel numbers corresponding to the bytes of Addr[64:79] are 0 to 7, the corresponding converter numbers are 1, 5, 9, 13, 17, 21, 25, and 29. When the baseboard management controller determines that the channel numbers corresponding to the bytes of Addr[80:95] are 0 to 7, the corresponding converter numbers are 2, 6, 10, 14, 18, 22, 26, and 30. When the baseboard management controller determines that the channel numbers corresponding to the bytes of Addr[96:111] are 0 to 7, the corresponding converter numbers are 3, 7, 11, 15, 19, 23, 27, and 31. When the baseboard management controller determines that the channel numbers corresponding to the bytes of Addr[112:127] are 0 to 7, the corresponding converter numbers are 4, 8, 12, 16, 20, 24, 28, and 32.
[0012] In some embodiments, in step (B), the complex programmable logic device is capable of transmitting at least one digital measurement signal that corresponds to the at least one portion of the bytes of each packet and has a higher update frequency by using the at least one converter value of the at least one portion of the bytes of each packet, and transmitting multiple other digital measurement signals that correspond to the at least one portion of the bytes of each packet and have a lower update frequency by using the at least one converter value of the at least one portion of the bytes of each packet.
[0013] Compared with the prior art, the information packet transmission and reading method of the present invention, when the complex programmable logic device utilizes the bus supporting the serial universal input and output protocol to transmit a large amount of voltage detection data (i.e., the converter values corresponding to the converter numbers respectively) to the baseboard management controller, the baseboard management controller can not only determine whether it is the voltage value (i.e., the converter values) corresponding to the 8-bit or 10-bit analog-to-digital converter (i.e., corresponding to the converter type bit), but also perform cyclic redundancy check to enhance the reliability of the signal, thereby avoiding misjudgment due to receiving erroneous messages. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, in which: Figure 1 is a block diagram illustrating a baseboard management controller and a complex programmable logic device to which the information packet transmission and reading method of the present invention is applicable; Figure 2 is a flow chart illustrating an embodiment of the information packet transmission and reading method of the present invention; and Figure 3 is a schematic diagram, exemplarily illustrating a packet of this embodiment. DETAILED DESCRIPTION
[0015] Before the present invention is described in detail, it should be noted that similar elements are denoted by the same reference numerals in the following description.
[0016] See also Figure 1 and Figure 2 and Figure 3, one embodiment of the information packet transmission and reading method of the present invention is applicable to a baseboard management controller 1 and a complex programmable logic device 2. The baseboard management controller 1 and the complex programmable logic device 2 are electrically connected by a bus 3 that supports a serial general purpose input and output (SGPIO) protocol. The bus 3 includes a SClock signal line, an SLoad signal line, an SDataOut signal line, and an SDataIn signal line. The complex programmable logic device 2 is used to receive measurement signals from multiple sensors (not shown) and has multiple built-in analog-to-digital converters (ADCs) to convert the measurement signals into multiple digital measurement signals. For example, in this embodiment, the number of the analog-to-digital converters is 32, and they are respectively defined as numbered 1 to 32, and the digital measurement signals are respectively equal to a first voltage to a thirty-second voltage.
[0017] The information packet transmission and reading method includes steps S1 to S8.
[0018] In step S1, the baseboard management controller 1 and the CPLD 2 are used as an initiator and a target of the serial general purpose input / output protocol on the bus 3. Therefore, the baseboard management controller 1 transmits a SClock signal, an SLoad signal, and an SDataOut signal to the CPLD 2 via the SClock signal line, the SLoad signal line, and the SDataOut signal line, and receives an SDataIn signal from the CPLD 2 via the SDataIn signal line. Then, step S2 is executed.
[0019] In step S2, the complex programmable logic device 2 transmits a plurality of packets (i.e., the SDataIn signal) to the baseboard management controller 1 via the SDataIn signal line of the bus 3, each of the packets including a plurality of bits whose total number is a multiple of 16. The complex programmable logic device defines the bits of each packet as a plurality of bytes in whole or in part in sequence according to a pre-set rule, each byte including the 16 bits that are not repeated, and two of the 16 bits are two check bits, and one of the 16 bits is a converter type bit, and three of the 16 bits are three channel number bits. In this embodiment, refer to Figure 3 The number of bits contained in each packet is 128, and the 128 bits are represented by Addr[0:127]. The number of bytes is four, and they are Addr[64:79], Addr[80:95], Addr[96:111], and Addr[112:127]. Then, step S3 is executed.
[0020] In step S3, the baseboard management controller 1 obtains the bytes in sequence according to the pre-set rules for the bits (i.e., Addr[0:127]) of the packet received each time. In addition, the baseboard management controller 1 determines the logic value of the bits Addr[0:63] of each packet according to the pre-set rules, and obtains multiple logic states corresponding to multiple different signals. For example, Addr[3]=1 indicates that the state of a power supply voltage is normal. Then, step S4 is executed.
[0021] In step S4, the baseboard management controller 1 performs and determines whether the cyclic redundancy check (CRC) of the remaining 14 bits of each byte is correct according to the logic values of the two check bits corresponding thereto. More specifically, the 16 bits of each byte are defined as a 0th bit to a 15th bit (such as Figure 3 In the embodiment of the present invention, the two check bits of each byte are the 7th bit and the 15th bit. That is to say, the check bits of Addr[64:79], Addr[80:95], Addr[96:111], and Addr[112:127] are Addr
[71] and Addr
[79] , Addr
[87] and Addr
[95] , Addr
[103] and Addr
[111] , and Addr
[119] and Addr
[127] . When the baseboard management controller 1 determines that the byte is correct and performs a cyclic redundancy check, step S5 is executed. When the baseboard management controller 1 determines that the byte is incorrect and performs a cyclic redundancy check, step S8 is executed.
[0022] In step S5, the baseboard management controller 1 determines a converter value corresponding to the 10 bits of the byte according to the logic value of the converter type bit corresponding to the byte. In this embodiment, the converter type bit of each byte is the 14th bit, that is, the converter type bits of Addr[64:79], Addr[80:95], Addr[96:111], and Addr[112:127] are Addr
[78] , Addr
[94] , Addr
[110] , and Addr
[126] respectively.
[0023] When the baseboard management controller 1 determines that the converter type bit of the byte is equal to a first logic value (such as logic 0), the baseboard management controller 1 determines the converter value of the byte (such as logic 0). Figure 3The bit [7:0] of the 8-bit ADC) is equal to the 0th to the 3rd bit and the 8th to the 11th bit arranged from the most significant bit (MSB) to the least significant bit (LSB), that is, when the converter type bit is equal to the first logic value, the converter value is a binary 8-bit value (can also be represented by a decimal value), so the complex programmable logic device 2 can transmit the value of the digital measurement signal of one of the 8-bit analog-to-digital converters to the baseboard management controller 1. For example, Addr
[78] = 0, then Addr [64: 67] = 1010, Addr [72: 75] = 0101 of Addr [64: 79], then the converter value is equal to 10100101 in binary, that is, equal to 128 + 32 + 4 + 1 = 165 in decimal.
[0024] When the baseboard management controller 1 determines that the converter type bit of the byte is equal to a second logic value (such as logic 1), the converter value of the byte is determined (such as logic 1). Figure 3 The bit [9:0] of the 10-bit ADC of the ADC is equal to the 0th to the 3rd bit and the 8th to the 13th bit arranged from the most significant bit to the least significant bit. That is, when the converter type bit is equal to the second logic value, the converter value is a binary 10-bit value (which can also be represented by a decimal value), so the complex programmable logic device 2 can transmit the value of the digital measurement signal of one of the 10-bit analog-to-digital converters to the baseboard management controller 1. For example, Addr
[78] = 1, then Addr [64: 67] = 1010, Addr [72: 77] = 010101 of Addr [64: 79], then the converter value is equal to 1010010101 in binary, that is, equal to 512 + 128 + 16 + 4 + 1 = 661 in decimal. It can be seen that in this embodiment, the converter type bit refers to the currently common 8-bit or 10-bit types supported by the resolution of the corresponding analog-to-digital converter (ADC), that is, an analog-to-digital converter resolution setting. The baseboard management controller 1 determines whether the voltage data of the analog-to-digital converter is an 8-bit or 10-bit analog-to-digital converter by the analog-to-digital converter resolution setting. Next, step S6 is executed.
[0025] In step S6, the baseboard management controller 1 determines a corresponding channel number for the byte according to the logic values of the three channel number bits corresponding thereto. In the present embodiment, the three channel number bits of each byte are the 4th to the 6th bit, that is, the channel number bits of Addr[64:79], Addr[80:95], Addr[96:111], and Addr[112:127] are Addr[68:70], Addr[84:86], Addr[100:102], and Addr[116:118], respectively. The baseboard management controller 1 determines the decimal value of the 4th to the 6th bit of the byte arranged from the most significant bit to the least significant bit as the channel number. Then, step S7 is executed.
[0026] In step S7, the baseboard management controller 1 determines a converter number corresponding to the converter value according to the channel number. That is, the converter number refers to the number of the analog-to-digital converter (i.e., one of 1 to 32). For example, when the baseboard management controller 1 determines that the channel numbers corresponding to the bytes of Addr[64:79] are 0 to 7, respectively, the corresponding converter numbers (i.e., the numbers of the analog-to-digital converters) are 1, 5, 9, 13, 17, 21, 25, and 29, respectively. When the baseboard management controller 1 determines that the channel numbers corresponding to the bytes of Addr[80:95] are 0 to 7, respectively, the corresponding converter numbers are 2, 6, 10, 14, 18, 22, 26, and 30, respectively. When the baseboard management controller 1 determines that the channel numbers corresponding to the bytes of Addr[96:111] are 0 to 7, respectively, the corresponding converter numbers are 3, 7, 11, 15, 19, 23, 27, and 31, respectively. When the baseboard management controller 1 determines that the channel numbers corresponding to the bytes of Addr[112:127] are 0 to 7, the corresponding converter numbers are 4, 8, 12, 16, 20, 24, 28, and 32, respectively.
[0027] In other words, by selecting each of the four converter numbers in each packet to be equal to one of 0 to 7, each packet can transmit the four digital measurement signals of the four analog-to-digital converters (respectively in the four bytes), and a total of up to 32 digital measurement signals of the 32 analog-to-digital converters can be transmitted. For example, when the four converter numbers of the packet are all equal to 0, the four digital measurement signals are the first voltage to the fourth voltage (i.e., the numbers of the four analog-to-digital converters are 1 to 4, respectively). When the four converter numbers are equal to 7, 1, 3, and 4, respectively, the four digital measurement signals are the twenty-ninth voltage, the sixth voltage, the fifteenth voltage, and the twentieth voltage (i.e., the numbers of the four analog-to-digital converters are 29, 6, 15, and 20, respectively). In addition, by selecting the logic value of each of the converter type bits, it is also possible to flexibly select whether the analog-to-digital converters are 8-bit or 10-bit digital measurement signals. On the other hand, the CPLD 2 can transmit the at least one digital measurement signal corresponding to a part of the bytes of each packet and having a higher update frequency by using the at least one converter value of the part of the bytes of each packet, and can transmit the other digital measurement signals (i.e., at least two) corresponding to a part of the bytes of each packet in turn by using the at least one converter value of the other part of the bytes of each packet in turn. In other words, the CPLD 2 can transmit the at least one digital measurement signal having a higher update frequency (e.g., twice per second) by using the part of the bytes of the packet, and can transmit the digital measurement signals having a lower update frequency (e.g., once per second) in turn by using the other part of the bytes of the packet in turn. For example, Addr[64:79], Addr[80:95], and Addr[96:111] transmit a first digital measurement signal to a third digital measurement signal twice per second, respectively, and although Addr[112:127] transmits twice per second, it first transmits a fourth digital measurement signal once per second and then transmits a fifth digital measurement signal once per second. This method provides flexibility in mixed transmission of digital measurement signals. Digital measurement signals with higher frequency of change, such as voltage change, or digital measurement signals with lower frequency of change, such as temperature change, can be mixed and transmitted, thereby improving transmission efficiency.
[0028] In step S8 , the baseboard management controller 1 regards the byte with incorrect cyclic redundancy check as invalid data and discards the byte.
[0029] In summary, when the complex programmable logic device 2 utilizes the bus 3 that supports the serial universal input and output protocol to transmit a large amount of voltage detection data (i.e., corresponding to those digital measurement signals) to the baseboard management controller 1, the baseboard management controller 1 can not only determine whether it is a voltage value (i.e., those converter values) corresponding to an 8-bit or 10-bit analog-to-digital converter (i.e., corresponding to the converter type bit), but can also perform a cyclic redundancy check to enhance the reliability of the signal and avoid misjudgment due to receiving an erroneous message, thereby truly achieving the purpose of the present invention.
[0030] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A method for transmitting and reading information packets, applicable to a bus electrically connected between a baseboard management controller and a complex programmable logic device and supporting a serial general purpose input and output (SGPIO) protocol, characterized in that: And contains: (A) using the baseboard management controller and the complex programmable logic device as an initiator and a target of the serial general purpose input and output protocol on the bus respectively; (B) transmitting, by the CPLD, a plurality of packets to the BMC via an SDataIn signal line of the bus, each of the packets comprising a plurality of bits whose total number is a multiple of 16, the CPLD defining all or part of the bits of each packet as a plurality of bytes in sequence according to a pre-defined rule, each of the bytes comprising the 16 bits which are not repeated, two of the 16 bits being two check bits, one of the 16 bits being a converter type bit, and three of the 16 bits being three channel number bits; (C) obtaining the bytes in sequence according to a preset rule for the bits of the packet received each time by the baseboard management controller; (D) executing and determining, by the baseboard management controller, for each of the bytes, according to the logic values of the two check bits corresponding thereto, whether a cyclic redundancy check (CRC) of the remaining 14 bits of the byte is correct; (E) when the baseboard management controller determines that the cyclic redundancy check of the 14 bits of the byte is correct, determining a converter value corresponding to the 10 bits of the byte according to the logic value of the converter type bit corresponding to the byte; (F) determining, by the baseboard management controller, a corresponding channel number for the byte according to the logic values of the three corresponding channel number bits therein; and (G) Determining, by the baseboard management controller, a converter number corresponding to the converter value according to the channel number.
2. The information packet transmission and reading method according to claim 1, characterized in that: In step (B), the number of bits contained in each packet is 128, and the 128 bits are represented by Addr[0:127]. In step (C), the number of bytes is four, namely Addr[64:79], Addr[80:95], Addr[96:111], and Addr[112:127].
3. The information packet transmission and reading method according to claim 2, characterized in that: In step (C), the baseboard management controller determines the logic value of the bits Addr[0:63] of each packet according to a preset rule to obtain a plurality of logic states corresponding to a plurality of different signals.
4. The information packet transmission and reading method according to claim 2, characterized in that: In step (D), the 16 bits of each byte are defined as a 0th bit to a 15th bit, and the two check bits of each byte are the 7th bit and the 15th bit.
5. The information packet transmission and reading method according to claim 4, characterized in that: In step (E), the converter type bit of each byte is the 14th bit. When the baseboard management controller determines that the converter type bit of the byte is equal to a first logic value, the converter value of the byte is determined to be equal to the 0th bit to the 3rd bit and the 8th bit to the 11th bit arranged from the most significant bit (MSB) to the least significant bit (LSB).
6. The information packet transmission and reading method according to claim 5, characterized in that: In step (E), when the baseboard management controller determines that the converter type bit of the byte is equal to a second logic value, the converter value of the byte is determined to be equal to the 0th to the 3rd bits and the 8th to the 13th bits arranged from the most significant bit to the least significant bit.
7. The information packet transmission and reading method according to claim 6, characterized in that: In step (F), the three channel number bits of each byte are the 4th to the 6th bits, and the baseboard management controller determines the decimal values of the 4th to the 6th bits of the byte arranged from the most significant bit to the least significant bit as the channel number.
8. The information packet transmission and reading method according to claim 7, characterized in that: In step (G), when the baseboard management controller determines that the channel numbers corresponding to the bytes of Addr[64:79] are 0 to 7, the corresponding converter numbers are 1, 5, 9, 13, 17, 21, 25, and 29, respectively; when the baseboard management controller determines that the channel numbers corresponding to the bytes of Addr[80:95] are 0 to 7, respectively; the corresponding converter numbers are 2, 6, 10, 14, 18, 22, 26, and 30, respectively; when the baseboard management controller determines that the channel numbers corresponding to the bytes of Addr[96:111] are 0 to 7, respectively; the corresponding converter numbers are 3, 7, 11, 15, 19, 23, 27, and 31, respectively; and when the baseboard management controller determines that the channel numbers corresponding to the bytes of Addr[112:127] are 0 to 7, respectively; the corresponding converter numbers are 4, 8, 12, 16, 20, 24, 28, and 32, respectively.
9. The information packet transmission and reading method according to claim 8, characterized in that: In step (B), the complex programmable logic device is capable of transmitting at least one digital measurement signal that corresponds to a portion of the bytes of each packet and has a higher update frequency by using the at least one converter value of a portion of the bytes of each packet, and of transmitting multiple other digital measurement signals that correspond to a portion of the bytes of each packet and have a lower update frequency in turn by using the at least one converter value of another portion of the bytes of each packet.