CPLD-based SelectMAP configuration mode implementation method and system

Abstract

The invention belongs to the technical field of FPGA (Field Programmable Gate Array) peripheral configuration, and discloses a CPLD (Complex Programmable Logic Device)-based SelectMAP configuration mode implementation method and system. The method comprises the following steps: electrifying equipment; clearing the configuration register; a sampling configuration mode pin; a mode is configured for the SelectMAP synchronously; checking the ID of the equipment; loading the configuration data; performing CRC (cyclic redundancy check); starting a sequence; and the SalveSelectMAP configuration control module at the CPLD end is used for pre-storing bit stream configuration data into FIFO (First In First Out) when the configuration data is valid, and then configuring the bit stream configuration data into an FPGA-K7 through a SelectMAP interface by matching with a configuration clock generated by the SalveSelectMAP configuration control module. According to the invention, a high-performance configuration data transmission channel is realized. The configuration scheme has the characteristics of simplicity in development, low configuration cost, high speed and flexibility in use, and has very high practicability.

Description

Technical Field

[0001] The invention belongs to the technical field of FPGA peripheral configuration, and in particular relates to a method and system for realizing a SelectMAP configuration mode based on CPLD. Background Art

[0002] FPGA has multiple configuration modes: the parallel master mode is a method of adding one FPGA to one EPROM; the master-slave mode can support one PROM to program multiple FPGAs; the serial mode can use a serial PROM to program the FPGA; the peripheral mode can use the FPGA as a peripheral of the microprocessor and program it by the microprocessor.

[0003] FPGA devices combine the high performance of ASICs with the flexibility of microprocessors. They not only have abundant logic resources, but also can be configured conveniently and flexibly. Although the active configuration method has fast configuration speed and simple implementation, it does not give full play to the flexible configuration characteristics of FPGAs. It is suitable for occasions where FPGAs are used for single applications. In addition, the large-capacity configuration chips and the circuit board area they occupy also bring high costs. The passive configuration method requires the use of an external control unit to generate the configuration timing, which is generally more complicated to implement. In addition, in the current common solutions, the configuration speed is often not high due to reasons such as interface rate limitations or the use of microprocessors to intervene in data transmission. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the disclosed embodiment of the present invention provides a method and system for implementing the SelectMAP configuration mode based on CPLD.

[0005] The technical solution is as follows: A method for implementing the SelectMAP configuration mode based on CPLD, comprising:

[0006] S1, device power on;

[0007] S2, clear configuration register;

[0008] S3, sampling configuration mode pin;

[0009] S4, synchronization for SelectMAP configuration mode;

[0010] S5, device ID check;

[0011] S6, loading configuration data;

[0012] S7, CRC check;

[0013] S8, start sequence;

[0014] S9, the SalveSelectMAP configuration control module at the CPLD end, is used to pre-store the bitstream configuration data into the FIFO when the configuration data is valid, and then configure the FPGA-K7 through the SelectMAP interface with the bitstream configuration data in conjunction with the configuration clock generated by the module.

[0015] In step S2, clearing the configuration register includes: after the device is powered on, setting the PROGRAM_B pin pulse to a low level, clearing the configuration memory in sequence, and PROGRAM_B being set to a low level and then changing to a high level after being set to a low level for 1 ms;

[0016] In step S3, sampling the configuration mode pin includes: when the INIT_B pin is converted to a high level, the device acquisition configuration mode is completed.

[0017] In step S4, synchronization for the SelectMAP configuration mode includes: first detecting the configuration bus width; then sending a 32-bit synchronization word to the FPGA internal configuration logic; the synchronization word informs the FPGA that configuration data appears in the received bit stream.

[0018] In step S5, the device ID check includes:

[0019] After the device is synchronized, it first passes the device ID check and loads the configuration data frame;

[0020] In step S6, configuration data is loaded, including: after the device is synchronized and the device ID check is passed, the configuration data frame is loaded into the target device, and the configuration data is loaded into the FPGA device in bytes at the rising edge of the configuration clock.

[0021] In step S7, CRC check includes:

[0022] During configuration data frame loading, the device calculates the cyclic redundancy check CRC value based on the configuration data in the configuration data packet; after loading the configuration data frame, the FPGA calculates the CRC value in the configuration data; if the CRC value calculated by the device does not match the expected CRC value in the bit stream, the device will pull down INIT_B and abort the configuration.

[0023] In step S9, the SalveSelectMAP configuration control module on the CPLD side includes:

[0024] WR_CLK, used as a metaphor for the write clock of the FIFO;

[0025] RD_CLK, read clock for FIFO;

[0026] Configuration data input port DATA_IN[15:0] is used for configuration data input;

[0027] Configure the data length input port Length[31:0], which is used to configure the data length input;

[0028] RST, used to display the reset signal, high level is valid;

[0029] FIFO write enable port WR_EN is used to enable internal FIFO write. When the bus decodes that the configuration data is valid, WR_EN becomes high level.

[0030] Configuration status output interface STATE[1:0] is used to configure status output.

[0031] CPU, used to read STATE[1:0] status to know the configuration status;

[0032] Configuration data output port DATA_OUT[15:0] is used for configuration data output. The configuration data is sent to the bidirectional data port of the SelectMAP configuration interface of FPGA-K7 at the rising edge of the configuration clock;

[0033] FULL, used to display the internal FIFO full signal;

[0034] Prog_full, used to display the internal FIFO programming full signal. The user determines whether the internal FIFO is full based on this signal. When it is full, the user stops writing configuration data to the FIFO.

[0035] DONE, connected to the DONE pin of FPGA-K7. When the DONE signal is high, the configuration sequence is completed;

[0036] CSIB, used to enable the SelectMAP configuration interface of K7 when the signal is low;

[0037] RDWR_B, used to determine the direction of the SelectMAP data bus through the signal;

[0038] INIT_B interface is used to initialize the FPGA pin. When the FPGA is in the reset state, the FPGA is in the initialization configuration register state, or the FPGA detects a configuration error, INIT_B is pulled low.

[0039] CCLK is used to provide the configuration clock.

[0040] In step S9, the bitstream configuration data is configured through the SelectMAP interface in coordination with the configuration clock generated by the module, including:

[0041] The global bitstream file configures the state machine of FPGA-K7 through the SlaveSelectMAP interface. The ID of the global bitstream file is 2'b01.

[0042] First, when the ID is detected as 2'b01, PROGRAM_B is pulled low for 1ms to start entering the configuration register clearing state; when the 1.1ms low timing is detected, the end;

[0043] Start entering the sampling configuration mode pin state. When INIT_B is high, it means that the configuration mode has been sampled successfully.

[0044] Enter the configuration data loading state and count the loaded data. When the count value reaches the configuration file data length, it means that the configuration data download is completed.

[0045] Enter the CRC check state. When INIT_B=1'b1 is detected, it means that there is no CRC error. Then enter the waiting state for the DONE pin to be pulled high. When the DONE pin is pulled high, the configuration process ends.

[0046] It starts to enter the compensation clock stage, and after sending the compensation clock, it enters the static configuration success state;

[0047] The entire static configuration process ends and returns to the initialization state.

[0048] Furthermore, in the CRC check state, if INIT_B=1'b0 is detected, it indicates that the CRC check is wrong, and the static configuration error waiting stage is entered, and then the initialization state is jumped; the configuration state is represented by the Configstate value during the entire state machine operation process of configuring FPGA-K7.

[0049] In step S9, the bit stream configuration data is configured through the SelectMAP interface to configure the FPGA-K7 in coordination with the configuration clock generated by the module, including loading the local bit stream configuration data to configure the FPGA-K7 through the SelectMAP interface; specifically, the following steps are included:

[0050] First, when the ID of the bitstream file is detected to be 2'b10 in the initialization state, the configuration data download state is entered; the downloaded data is counted, and when it is detected that the count reaches the configuration file data length, it indicates that the configuration data download is completed;

[0051] Start to enter the CRC check state. When INIT_B=1'b1 is detected, it means that the CRC check is successful.

[0052] In the compensation clock phase, after sending 8 to 20 cycles of compensation clock, the dynamic configuration success state is entered;

[0053] The entire dynamic configuration process ends and returns to the initialization state. In the CRC check state, if INI_B=1'b0 is detected, it means that the CRC check is wrong and enters the dynamic configuration error waiting stage; further jumps to the initialization state; during the entire state machine operation process, the Configstate value indicates whether the SelectMAP interface configures FPGA-K7 successfully.

[0054] Another object of the present invention is to provide a CPLD-based SelectMAP configuration mode implementation system, the system is configured by a CPLD-based SelectMAP configuration mode implementation method, the system comprising:

[0055] Configuration establishment process module, used to run device power-on, clear configuration registers, sample configuration mode pins, synchronize for SelectMAP configuration mode, and device ID check;

[0056] Configuration bitstream loading process module, used to run loading of global and local bitstream configuration data and CRC check;

[0057] The startup sequence module is used to configure some internal circuits of the FPGA and then start the sequence after the CRC check passes;

[0058] The control module is used for the SalveSelectMAP configuration block at the CPLD end. When the configuration data is valid, the bitstream configuration data is pre-stored in the FIFO, and then the bitstream configuration data is configured through the SelectMAP interface in conjunction with the configuration clock generated by the module to configure the FPGA-K7.

[0059] In combination with all the above technical solutions, the beneficial effects of the present invention are as follows: the present invention proposes an implementation scheme of the FPGASelectMap configuration method based on CPLD, which not only has the characteristics of flexible passive configuration and low design cost, but also is simple to implement and fast to configure. The scheme uses the K7 series FPGA as the configuration target and selects CPLD as the device FPGABIT file configuration chip to realize a high-performance configuration data transmission channel. This configuration scheme has the characteristics of simple development, low configuration cost, fast speed, and flexible use, and is very practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure;

[0061] Figure 1 It is a flow chart of a method for implementing the SelectMAP configuration mode based on CPLD provided by an embodiment of the present invention;

[0062] Figure 2 It is a top-level schematic diagram of a SalveSelectMAP configuration control module on a CPLD side provided by an embodiment of the present invention;

[0063] Figure 3 It is a state machine flow chart of configuring FPGA-K7 through the SlaveSelectMAP interface of the global bitstream file provided by the embodiment of the present invention;

[0064] Figure 4 It is a state machine principle diagram for configuring FPGA-K7 through the SlaveSelectMAP interface using a local bitstream file provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.

[0066] Embodiment 1, as Figure 1 As shown, the CPLD-based SelectMAP configuration mode implementation method provided in the embodiment of the present invention is based on the CPLD. The FPGA basic configuration process can be divided into three stages: configuration establishment process, configuration bit stream loading process and startup sequence; specifically, it includes:

[0067] S1, device power on;

[0068] There are multiple operating voltages inside Xilinx FPGA, including core voltage VcCINT, BRAM power supply voltage VCCBRAM, FPGA auxiliary power supply voltage VcCAUx, internal Bank power supply voltage Vcco, internal gigabit transceiver power supply voltage VMGTAVCc, etc.

[0069] S2, clear configuration register;

[0070] After the device is powered on, the PROGRAM_B pin pulse is set to a low level, and the configuration memory is cleared in sequence. PROGRAM_B is set to a low level and then becomes a high level 1ms later.

[0071] S3, sampling configuration mode pin;

[0072] When the INIT_B pin transitions to a high level, it indicates that the device has completed acquisition configuration mode.

[0073] S4, synchronization for SelectMAP configuration mode;

[0074] First, the configuration bus width is detected; then a 32-bit synchronization word (0xAA995566) is sent to the FPGA's internal configuration logic; the synchronization word informs the FPGA that configuration data will appear in the received bit stream. The FPGA will not process any data packets before detecting the synchronization word.

[0075] S5, device ID check;

[0076] After the device is synchronized, it must pass the device ID check before loading the configuration data frame. In order to prevent different FPGA models from loading configuration data into the target FPGA, Xilinx has designed a unique device ID number for each FPGA.

[0077] S6, loading configuration data;

[0078] After the device is synchronized and the device ID check is passed, the configuration data frame can be loaded into the target device. The configuration data is loaded into the FPGA device in bytes at the rising edge of the configuration clock.

[0079] S7, CRC check;

[0080] As the configuration data frame is loaded, the device calculates a cyclic redundancy check (CRC) value based on the configuration data in the configuration data packet. After loading the configuration data frame, the FPGA calculates the CRC value in the configuration data. If the CRC value calculated by the device does not match the expected CRC value in the bitstream, the device pulls INIT_B low and aborts configuration.

[0081] S8, start sequence;

[0082] After the CRC check passes, the FPGA will not execute the user logic immediately, but will also configure some internal circuits, such as releasing the DONE pin and locking the digital clock manager.

[0083] Among them, loading the global bitstream file must strictly follow the 8 basic steps of FPGA configuration. Control each pin of the SelectMAP configuration mode according to the requirements of each step.

[0084] S9, based on all the above steps, configure the control module at the SalveSelectMAP of the CPLD end; the top-level design is as follows Figure 2 The function of the control module is to store the bit stream configuration data in the FIFO in advance when the configuration data is valid, and then configure the FPGA-K7 through the SelectMAP interface with the configuration clock generated by the module. In the present invention, the SelectMAP interface adopts a 16-bit bidirectional data bus.

[0085] In this control module, WR_CLK is the write clock of the FIFO in the module, and RD_CLK is the read clock of the FIFO in the module, both with a frequency of 100MHz; DATA_IN[15:0] is the configuration data input port; Length[31:0] is the configuration data length input port; RST is the reset signal of the module, which is valid at a high level; WR_EN is the write enable port of the internal FIFO of the module, and WR_EN becomes a high level when the bus decodes that the configuration data is valid; STATE[1:0] is the configuration status output interface, and the configuration status is shown in Table 1. The CPU reads the STATE[1:0] status to obtain the configuration status; DATA_OUT[15:0] is the configuration data output port, and the configuration data is to be sent to the bidirectional data port of the SelectMAP configuration interface of FPGA-K7 at the rising edge of the configuration clock; FULL is the internal FIFO full signal, and Prog_full is the internal FIFO programming full signal. The user determines whether the internal FIFO is full based on this signal, and stops writing configuration data to the FIFO when it is full.

[0086] Table 1 Configuration status table

[0087] STATE Configuration Status 2'b00 idle 2'b01 Configuring 2'b10 Configuration successful 2'b11 Configuration error

[0088] The DONE signal is connected to the DONE pin of FPGA-K7. When the DONE signal is high, it indicates the completion of the configuration sequence. When the CSIB signal is low, the SelectMAP configuration interface of K7 is enabled. The RDWR_B signal determines the direction of the SelectMAP data bus. In the present invention, the CPLD only configures FPGA-K7, so RDWR_B is always set to low during the configuration process.

[0089] The INIT_B interface is the FPGA initialization pin. When the FPGA is in the reset state, the FPGA is in the initialization configuration register state, or the FPGA detects a configuration error, INIT_B will be pulled low.

[0090] When PROGRAM_B pulse is low, the FPGA configuration is cleared and a new configuration sequence is started. The CPLD generates the configuration clock CCLK and transmits it to FPGA-K7. The configuration data is loaded into FPGA-K7 at the rising edge of the configuration clock.

[0091] The state machine process design of configuring FPGA-K7 through the SlaveSelectMAP interface with the global bitstream file is as follows Figure 3 As shown, both the global file and the local file have an ID. In the present invention, the ID of the global file is 2'b01.

[0092] First, when the ID is detected as 2'b01, PROGRAM_B is pulled low for 1ms to start clearing the configuration register. The timing ends when the 1.1ms pull-down is detected.

[0093] Further, the configuration mode pin state is entered and sampled. When INIT_B is high, it indicates that the configuration mode has been sampled successfully.

[0094] The configuration data loading state is then entered, and the loaded data is counted. When it is detected that the count value reaches the configuration file data length, it indicates that the configuration data download is completed.

[0095] Then, the CRC check state is entered. When INIT_B=1'b1 is detected, it indicates that there is no CRC error, and then the state of waiting for the DONE pin to be pulled high is entered. When the DONE pin is pulled high, it indicates that a configuration process is completed.

[0096] The next step is to enter the compensation clock phase. After sending the compensation clock, the static configuration is successful.

[0097] The entire static configuration process is then completed and returns to the initialization state.

[0098] Further, in the CRC check state, if INIT_B=1'b0 is detected, it means that the CRC check is wrong, and the static configuration error waiting stage is entered, and then jumps to the initialization state. The Configstate value is extremely important in the entire configuration of the FPGA-K7 state machine operation process. It indicates the configuration state. The value of Configstate in each state is shown in Table 2.

[0099] Table 2 Configstate values ​​in each state

[0100] State Machine Status Configstate Values Initialization state 2'b00 Clear configuration register status 2'b01 Sample configuration mode pin status 2'b01 Loading configuration data status 2'b01 CRC check status 2'b01 Wait for DONE to be pulled high 2'b01 Compensation Clock Stage 2'b01 Configuration success status 2'b10 Configuration failure status 2'b11

[0101] The FPGA configuration process when loading a local bitstream is slightly different from that when loading a global bitstream. There is no need to clear the configuration memory and sample the configuration mode state, and the DONE pin does not change and remains at a high level. The state machine principle design of configuring the local bitstream file through the SlaveSelectMAP interface of FPGA-K7 is as follows Figure 4 shown.

[0102] First, when the ID of the bitstream file is detected to be 2'b10 in the initialization state, the configuration data download state is entered. The downloaded data is counted, and when it is detected that the count reaches the configuration file data length, it indicates that the configuration data download is completed.

[0103] Then, the CRC check state is entered. When INIT_B=1'b1 is detected, it indicates that the CRC check is successful.

[0104] The system then enters the compensation clock phase. After sending 8 to 20 cycles of compensation clock, the system enters the dynamic configuration success state.

[0105] The entire dynamic configuration process ends and returns to the initialization state. In addition, in the CRC check state, if INI_B=1'b0 is detected, it means that the CRC check is wrong and enters the dynamic configuration error waiting stage. Further jump to the initialization state. The Configstate value is extremely important in the entire state machine operation process. It indicates whether the SelectMAP interface configures FPGA-K7 successfully. The value of Configstate in each state is shown in Table 3.

[0106] Table 3 Configstate values ​​in each state

[0107] State Machine Status Configstate Values Local loading data status 2'b01 CRC check status 2'b01 Compensation Clock Stage 2'b01 Configuration success status 2'b10 Configuration failure status 2'b11

[0108] Embodiment 2, the embodiment of the present invention provides a SelectMAP configuration mode implementation system based on CPLD, the system comprising:

[0109] Configuration establishment process module, used to run device power-on, clear configuration registers, sample configuration mode pins, synchronize for SelectMAP configuration mode, and device ID check;

[0110] Configuration bitstream loading process module, used to run loading of global and local bitstream configuration data and CRC check;

[0111] The startup sequence module is used to configure some internal circuits of the FPGA and then start the sequence after the CRC check passes;

[0112] The control module is used for the SalveSelectMAP configuration block at the CPLD end. When the configuration data is valid, the bitstream configuration data is pre-stored in the FIFO, and then the bitstream configuration data is configured through the SelectMAP interface in conjunction with the configuration clock generated by the module to configure the FPGA-K7.

[0113] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0114] Since the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present invention, their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0115] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment.

[0116] An embodiment of the present invention further provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps in any of the above-mentioned method embodiments when executing the computer program.

[0117] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0118] An embodiment of the present invention further provides an information data processing terminal, which, when executed on an electronic device, provides a user input interface to implement the steps in the above method embodiments. The information data processing terminal is not limited to mobile phones, computers, and switches.

[0119] An embodiment of the present invention further provides a server, which is used to provide a user input interface to implement the steps in the above method embodiments when executed on an electronic device.

[0120] An embodiment of the present invention provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0121] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a disk or an optical disk.

[0122] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for implementing the SelectMAP configuration mode based on CPLD, characterized in that: The method includes: S1, device power on; S2, clear configuration register; S3, sampling configuration mode pin; S4, synchronization for SelectMAP configuration mode; S5, device ID check; S6, loading configuration data; S7, CRC check; S8, start sequence; S9, the SalveSelectMAP configuration control module at the CPLD end, is used to pre-store the bitstream configuration data into the FIFO when the configuration data is valid, and then configure the FPGA-K7 through the SelectMAP interface with the bitstream configuration data in conjunction with the configuration clock generated by the module.

2. The method for implementing the SelectMAP configuration mode based on CPLD according to claim 1, characterized in that: In step S2, clearing the configuration register includes: after the device is powered on, setting the PROGRAM_B pin pulse to a low level, clearing the configuration memory in sequence, and PROGRAM_B being set to a low level and then changing to a high level after being set to a low level for 1 ms; In step S3, sampling the configuration mode pin includes: when the INIT_B pin is converted to a high level, the device acquisition configuration mode is completed.

3. The method for implementing the SelectMAP configuration mode based on CPLD according to claim 1, characterized in that: In step S4, synchronization for the SelectMAP configuration mode includes: first detecting the configuration bus width; then sending a 32-bit synchronization word to the FPGA internal configuration logic; the synchronization word informs the FPGA that configuration data appears in the received bit stream.

4. The method for implementing the SelectMAP configuration mode based on CPLD according to claim 1, characterized in that: In step S5, the device ID is checked, including: After the device is synchronized, it first passes the device ID check and loads the configuration data frame; In step S6, configuration data is loaded, including: after the device is synchronized and the device ID check is passed, the configuration data frame is loaded into the target device, and the configuration data is loaded into the FPGA device in bytes at the rising edge of the configuration clock.

5. The method for implementing the SelectMAP configuration mode based on CPLD according to claim 1, characterized in that: In step S7, CRC check includes: During configuration data frame loading, the device calculates the cyclic redundancy check CRC value based on the configuration data in the configuration data packet; after loading the configuration data frame, the FPGA calculates the CRC value in the configuration data; if the CRC value calculated by the device does not match the expected CRC value in the bit stream, the device will pull down INIT_B and abort the configuration.

6. The method for implementing the SelectMAP configuration mode based on CPLD according to claim 1, characterized in that: In step S9, the SalveSelectMAP configuration control module on the CPLD side includes: WR_CLK, used as a metaphor for the FIFO's write clock; RD_CLK, read clock for FIFO; Configuration data input port DATA_IN[15:0] is used for configuration data input; Configure the data length input port Length[31:0], which is used to configure the data length input; RST, used to display the reset signal, high level is valid; FIFO write enable port WR_EN is used to enable internal FIFO write. When the bus decodes that the configuration data is valid, WR_EN becomes high level. Configuration status output interface STATE[1:0] is used to configure status output. CPU, used to read STATE[1:0] status to know the configuration status; Configuration data output port DATA_OUT[15:0] is used for configuration data output. The configuration data is sent to the bidirectional data port of the SelectMAP configuration interface of FPGA-K7 at the rising edge of the configuration clock; FULL, used to display the internal FIFO full signal; Prog_full, used to display the internal FIFO programming full signal. The user determines whether the internal FIFO is full based on this signal. When it is full, the user stops writing configuration data to the FIFO. DONE, connected to the DONE pin of FPGA-K7. When the DONE signal is high, the configuration sequence is completed; CSIB, used to enable the SelectMAP configuration interface of K7 when the signal is low; RDWR_B, used to determine the direction of the SelectMAP data bus through the signal; INIT_B interface is used to initialize the FPGA pin. When the FPGA is in the reset state, the FPGA is in the initialization configuration register state, or the FPGA detects a configuration error, INIT_B is pulled low. CCLK is used to provide the configuration clock.

7. The method for implementing the SelectMAP configuration mode based on CPLD according to claim 1, characterized in that: In step S9, the bitstream configuration data is configured through the SelectMAP interface in coordination with the configuration clock generated by the module, including: The global bitstream file configures the state machine of FPGA-K7 through the SlaveSelectMAP interface. The ID of the global bitstream file is 2'b01. First, when the ID is detected as 2'b01, PROGRAM_B is pulled low for 1ms to start entering the configuration register clearing state; when the 1.1ms low timing is detected, the end; Start entering the sampling configuration mode pin state. When INIT_B is high, it means that the configuration mode has been sampled successfully. Enter the configuration data loading state and count the loaded data. When the count value reaches the configuration file data length, it means that the configuration data download is completed. Enter the CRC check state. When INIT_B=1'b1 is detected, it means that there is no CRC error. Then enter the waiting state for the DONE pin to be pulled high. When the DONE pin is pulled high, the configuration process ends. It starts to enter the compensation clock stage, and after sending the compensation clock, it enters the static configuration success state; The entire static configuration process ends and returns to the initialization state.

8. The method for implementing the SelectMAP configuration mode based on CPLD according to claim 7, characterized in that: In the CRC check state, if INIT_B=1'b0 is detected, it means that the CRC check is wrong, and the static configuration error waiting stage is entered, and then the initialization state is jumped; the configuration state is represented by the Configstate value during the entire process of configuring the state machine of FPGA-K7.

9. The method for implementing the SelectMAP configuration mode based on CPLD according to claim 1, characterized in that: In step S9, the bit stream configuration data is configured through the SelectMAP interface to configure the FPGA-K7 in coordination with the configuration clock generated by the module, including loading the local bit stream configuration data to configure the FPGA-K7 through the SelectMAP interface; specifically, the following steps are included: First, when the ID of the bitstream file is detected to be 2'b10 in the initialization state, the configuration data download state is entered; the downloaded data is counted, and when it is detected that the count reaches the configuration file data length, it indicates that the configuration data download is completed; Start to enter the CRC check state. When INIT_B=1'b1 is detected, it means that the CRC check is successful. In the compensation clock phase, after sending 8 to 20 cycles of compensation clock, the dynamic configuration success state is entered; The entire dynamic configuration process ends and returns to the initialization state. In the CRC check state, if INI_B=1'b0 is detected, it means that the CRC check is wrong and enters the dynamic configuration error waiting stage; further jumps to the initialization state; during the entire state machine operation process, the Configstate value indicates whether the SelectMAP interface configures FPGA-K7 successfully.

10. A SelectMAP configuration mode implementation system based on CPLD, characterized in that: The system is configured by the CPLD-based SelectMAP configuration mode implementation method according to any one of claims 1 to 9, and the system includes: Configuration establishment process module, used to run device power-on, clear configuration registers, sample configuration mode pins, synchronize for SelectMAP configuration mode, and device ID check; Configuration bitstream loading process module, used to run loading of global and local bitstream configuration data and CRC check; The startup sequence module is used to configure some internal circuits of the FPGA and then start the sequence after the CRC check passes; The control module is used for the SalveSelectMAP configuration block at the CPLD end. When the configuration data is valid, the bitstream configuration data is pre-stored in the FIFO, and then the bitstream configuration data is configured through the SelectMAP interface in conjunction with the configuration clock generated by the module to configure the FPGA-K7.

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