Data processing method and system based on FPGA

Abstract

The FPGA-based data processing method and system provided in the present application relate to the field of data storage technology. In the present application, firstly, an analog signal to be processed is converted and processed by an analog-to-digital converter to output a target digital signal; secondly, the target digital signal is stored and processed by a field programmable gate array so that it is stored in a first storage device, and when the stored digital signal is read from the first storage device, the target digital signal sent by the analog-to-digital converter is written to the second storage device for caching, and when the stored digital signal is not read from the first storage device, the acquired digital signal is written to the first storage device for storage, and the acquired digital signal includes the target digital signal sent by the analog-to-digital converter and / or the cached digital signal read from the second storage device. Based on the above content, the problem of relatively low reliability of data storage existing in the prior art can be improved.

Description

Technical Field

[0001] The present application relates to the field of data storage technology, and in particular to a data processing method and system based on FPGA. Background Art

[0002] With the development of communication technology and electronic technology, the requirements for the frequency band and bandwidth of signal acquisition are getting higher and higher. According to the Nyquist theorem, the corresponding signal acquisition chip speed is also getting higher and higher, and the data rate that needs to be transmitted is also getting higher and higher. The amount of data transmitted and collected is getting larger and larger. Correspondingly, a large amount of data needs to be stored. However, the inventors have found that since storage devices generally cannot support synchronous data storage and reading, the continuity of data storage will be interrupted by the demand for data reading, thereby reducing the reliability of data storage, such as data loss. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a data processing method and system based on FPGA to improve the problem of relatively low reliability of data storage existing in the prior art.

[0004] To achieve the above objectives, this application adopts the following technical solutions:

[0005] A data processing method based on FPGA is applied to a data processing system based on FPGA. The data processing system based on FPGA includes an analog-to-digital converter, a field programmable gate array, a first storage device and a second storage device. The analog-to-digital converter is connected to the field programmable gate array, and the field programmable gate array is connected to the first storage device and the second storage device respectively. The data processing method based on FPGA includes:

[0006] The analog-to-digital converter converts the received analog signal to be processed and outputs a target digital signal corresponding to the analog signal to be processed;

[0007] The target digital signal is stored and processed by the field programmable gate array so that the target digital signal is stored in the first storage device, wherein when the stored digital signal is read from the first storage device, the target digital signal sent by the analog-to-digital converter is written to the second storage device for caching, and when the stored digital signal is not read from the first storage device, the acquired digital signal is written to the first storage device for storage, wherein the acquired digital signal includes the target digital signal sent by the analog-to-digital converter and / or the cached digital signal read from the second storage device.

[0008] In a preferred embodiment of the present application, in the above-mentioned FPGA-based data processing method, the step of performing storage processing on the target digital signal through the field programmable gate array so that the target digital signal is stored in the first storage device includes:

[0009] Receiving a target digital signal sent by the analog-to-digital converter through a first field programmable gate array included in the field programmable gate array, wherein the first field programmable gate array is further used to perform signal analysis processing on the target digital signal;

[0010] Receiving the target digital signal forwarded by the first field programmable gate array through a second field programmable gate array included in the field programmable gate array;

[0011] The received target digital signal is subjected to storage processing through the second field programmable gate array, so that the target digital signal is stored in the first storage device.

[0012] In a preferred embodiment of the present application, in the above-mentioned FPGA-based data processing method, the step of performing storage processing on the received target digital signal through the second field programmable gate array so that the target digital signal is stored in the first storage device includes:

[0013] Writing the received target digital signal into the second storage device through the second field programmable gate array to achieve caching of the target digital signal;

[0014] When the second field programmable gate array does not read the stored digital signal from the first storage device, the cached target digital signal is read from the second storage device, and the target digital signal is written to the first storage device for storage, wherein the data storage capacity of the second storage device is smaller than the data storage capacity of the first storage device, and the data transmission efficiency of the second storage device is higher than the data transmission efficiency of the first storage device.

[0015] In a preferred embodiment of the present application, in the above-mentioned FPGA-based data processing method, when the second field programmable gate array does not read the stored digital signal from the first storage device, the step of reading the cached target digital signal from the second storage device and writing the target digital signal into the first storage device for storage includes:

[0016] When the second field programmable gate array does not read the stored digital signal from the first storage device, reading the cached target digital signal from the second storage device through the second field programmable gate array;

[0017] Writing the read cached target digital signal into the first storage device through the second field programmable gate array;

[0018] determining, by the second field programmable gate array, a data length of a target digital signal written to the first storage device;

[0019] Sending a query write data instruction to the second field programmable gate array through the first field programmable gate array;

[0020] In response to the query write data instruction, sending the data length of the target digital signal written to the first storage device to the first field programmable gate array;

[0021] Through the first field programmable gate array, the data length of the target digital signal written to the first storage device is compared with the data length obtained by the first field programmable gate array through signal analysis processing when receiving the target digital signal, and when the compared two data lengths are consistent, the first storage device completes storage of the target digital signal.

[0022] In a preferred embodiment of the present application, in the above-mentioned FPGA-based data processing method, the step of performing storage processing on the target digital signal through the field programmable gate array so that the target digital signal is stored in the first storage device further includes:

[0023] Verifying the read and write functions of the second field programmable gate array;

[0024] After the read and write functions of the second field programmable gate array are verified to be passed, it is determined to execute the step of receiving the target digital signal sent by the analog-to-digital converter through the first field programmable gate array included in the field programmable gate array.

[0025] In a preferred embodiment of the present application, in the above-mentioned FPGA-based data processing method, the step of verifying the read and write functions of the second field programmable gate array includes:

[0026] Reading a parameter of a first register of the second field programmable gate array to obtain a first parameter, and comparing the first parameter with a first preset parameter;

[0027] Reading a parameter of a second register of the second field programmable gate array to obtain a second parameter, and comparing the second parameter with a second preset parameter;

[0028] configuring the parameter of the second register as a third parameter;

[0029] After executing the step of configuring the parameter of the second register as the third parameter, reading the parameter of the second register to obtain a fourth parameter, and comparing the third parameter with the fourth parameter, and when the first parameter matches the first preset parameter, the second parameter matches the second preset parameter, and the third parameter matches the fourth parameter, determining that the read and write function verification of the second field programmable gate array has passed.

[0030] In a preferred embodiment of the present application, in the above-mentioned FPGA-based data processing method, the step of performing storage processing on the target digital signal through the field programmable gate array so that the target digital signal is stored in the first storage device further includes:

[0031] configuring a signal storage speed of the second field programmable gate array, and configuring a signal storage address of the second field programmable gate array;

[0032] After the signal storage speed and the signal storage address are configured, it is determined to execute the step of receiving the target digital signal sent by the analog-to-digital converter through the first field programmable gate array included in the field programmable gate array.

[0033] On the basis of the above, the present application further provides a data processing system based on FPGA, the data processing system based on FPGA includes an analog-to-digital converter, a field programmable gate array, a first storage device and a second storage device, the analog-to-digital converter is connected to the field programmable gate array, and the field programmable gate array is connected to the first storage device and the second storage device respectively;

[0034] Wherein, the FPGA-based data processing system is used to execute the above-mentioned FPGA-based data processing method.

[0035] In a preferred selection of the present application, in the above-mentioned FPGA-based data processing system, the field programmable gate array includes a first field programmable gate array and a second field programmable gate array, the first field programmable gate array is connected to the analog-to-digital converter, and the second field programmable gate array is respectively connected to the first field programmable gate array, the first storage device and the second storage device;

[0036] Among them, the first field programmable gate array is used to receive the target digital signal sent by the analog-to-digital converter, and the first field programmable gate array is also used to perform type analysis processing on the target digital signal. The second field programmable gate array is used to receive the target digital signal forwarded by the first field programmable gate array and store the target digital signal so that the target digital signal is stored in the first storage device.

[0037] In a preferred option of the present application, in the above-mentioned FPGA-based data processing system, the data storage capacity of the second storage device is smaller than the data storage capacity of the first storage device, and the data transmission efficiency of the second storage device is higher than the output transmission efficiency of the first storage device.

[0038] The FPGA-based data processing method and system provided in the present application can convert the analog signal to be processed through an analog-to-digital converter and output a target digital signal; secondly, the target digital signal can be stored and processed through a field programmable gate array so that the target digital signal is stored in a first storage device. Based on this, when the stored digital signal is read from the first storage device, the target digital signal sent by the analog-to-digital converter will be written to the second storage device for caching, and when the stored digital signal is not read from the first storage device, the acquired digital signal will be written to the first storage device for storage, and the acquired digital signal includes the target digital signal sent by the analog-to-digital converter and / or the cached digital signal read from the second storage device. Therefore, the continuous storage of the digital signal can be guaranteed, and even when the stored digital signal is read from the first storage device, it can be cached by the second storage device first, so that compared with the conventional technical solution in which data storage cannot be performed when the stored digital signal is read from the first storage device, it can have higher data storage reliability, avoid the problem of easy data loss caused by the inability to perform data storage continuously, thereby improving the problem of relatively low data storage reliability in the prior art, and since continuous data storage can be achieved, the front-end data acquisition can also be performed continuously and at high speed, thereby improving the efficiency of data processing and meeting the needs of high-speed data acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings.

[0040] Figure 1 A system block diagram of an FPGA-based data processing system provided in an embodiment of the present application.

[0041] Figure 2 Another system block diagram of an FPGA-based data processing system provided in an embodiment of the present application.

[0042] Figure 3 A flowchart of a data processing method based on FPGA provided in an embodiment of the present application.

[0043] Figure 4A schematic diagram of communication instructions between the first field programmable gate array and the second field programmable gate array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0045] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0046] like Figure 1 As shown, an embodiment of the present application provides a data processing system based on FPGA, wherein the data processing system based on FPGA may include an analog-to-digital converter, a field programmable gate array, a first storage device, and a second storage device.

[0047] In detail, the analog-to-digital converter is connected to the field programmable gate array, and the field programmable gate array is connected to the first storage device and the second storage device respectively. It should be noted that the specific functions of each device included in the FPGA-based data processing system can refer to the relevant explanations of the FPGA-based data processing method provided later, and will not be repeated here.

[0048] It is understandable that, in an alternative implementation, the model and quantity of the analog-to-digital converter may not be limited and may be selected according to actual needs. For example, the FPGA-based data processing system may include three analog-to-digital converters of the same model, such as AD9652.

[0049] It is understood that in an alternative embodiment, in combination with Figure 2As shown, the field programmable gate array may include a first field programmable gate array and a second field programmable gate array. The first field programmable gate array is connected to the analog-to-digital converter, and the second field programmable gate array is respectively connected to the first field programmable gate array, the first storage device, and the second storage device. The specific functions of the first field programmable gate array and the second field programmable gate array can refer to the relevant explanations of the FPGA-based data processing method provided later, and will not be repeated here. For example, the first field programmable gate array is used to receive the target digital signal sent by the analog-to-digital converter, and the first field programmable gate array is also used to perform type parsing processing on the target digital signal. The second field programmable gate array is used to receive the target digital signal forwarded by the first field programmable gate array, and store the target digital signal so that the target digital signal is stored in the first storage device.

[0050] Understandably, Figure 1 and Figure 2 The structure shown is for illustration only. The FPGA-based data processing system may also include Figure 1 and Figure 2 More or fewer components as shown, or with Figure 1 and Figure 2 Different configurations shown, for example, may also include a central processor (for example, when the first field programmable gate array forwards the received target digital signal to the second field programmable gate array, it may also forward the target digital signal to the central processor for processing. The specific processing method may be selected according to actual needs. For example, the target digital signal may be analyzed for abnormalities. For example, the first field programmable gate array may transmit the target digital signal to the central processor through PCIe2.0, and may send the target digital signal to the second field programmable gate array through a high-speed interface in accordance with the SPI protocol). For another example, the FPGA-based data processing system may also include a clock chip (such as AD9516), and may also include a controller for controlling the first field programmable gate array, the clock chip and the external radio frequency device, such as ZYNQ XC7Z100, which is a chip of Xilinx that integrates an ARM processor and FPGA (called SoC, System on Chip), which can effectively manage multiple functions and processes and improve the efficiency and performance of the system.

[0051] It is understandable that, in an alternative implementation, the models of the first field programmable gate array and the second field programmable gate array may be different or the same, such as both may be XC7VX485T. In addition, the types of the first storage device and the second storage device may be different, for example, the data storage capacity of the second storage device is smaller than the data storage capacity of the first storage device, and the data transmission efficiency of the second storage device is higher than the output transmission efficiency of the first storage device. For example, the first storage device may be SATA (SATA can store a large amount of data, but due to the simplex communication mode, data cannot be written when reading), and the second storage device may be DDR3 (DDR3 has a sufficient speed but a small space).

[0052] Based on the above configuration, the communication between the first field programmable gate array and the second field programmable gate array is SPI protocol communication, the communication clock is 125MHz, the communication data received by the second field programmable gate array is cached in DDR3, and the AURORA communication protocol can be used, the clock is 200MHz, and finally, the cached data is stored in the SATA storage matrix, and the SATA3.0 protocol can be used, and the clock is 150MHz. In the actual specific application process, the SATA storage matrix is ​​used for direct storage. Because it cannot be written during reading, the collected data will be discontinuous, which may cause the loss of useful data. However, the resources in the field programmable gate array do not support setting too large a cache in the field programmable gate array. For large bandwidth application scenarios, too small a cache is not conducive to signal-related processing and application. Taking these problems into consideration, by selecting DDR3 with a transmission efficiency twice that of SATA for caching, the SATA is continuously written by switching the DDR3 interface in the field programmable gate array, and then when reading the internal data of SATA, it can also be cached through DDR3 to avoid data loss during data reading.

[0053] For the above configuration, after a large number of data recording and playback (storage and reading) tests, no data transmission loss occurred, and the transmission rate can reach more than 2.18GB / s.

[0054] Combination Figure 3, the embodiment of the present application also provides an FPGA-based data processing method that can be applied to the above-mentioned FPGA-based data processing system. Among them, the method steps defined in the process related to the FPGA-based data processing method can be implemented by the FPGA-based data processing system, and the FPGA-based data processing system includes an analog-to-digital converter, a field programmable gate array, a first storage device and a second storage device, the analog-to-digital converter is connected to the field programmable gate array, and the field programmable gate array is respectively connected to the first storage device and the second storage device. The following will be Figure 3 The specific process shown is explained in detail.

[0055] Step S110: converting the received analog signal to be processed by the analog-to-digital converter, and outputting a target digital signal corresponding to the analog signal to be processed.

[0056] In the embodiment of the present application, the analog-to-digital converter can be used to convert the received analog signal to be processed and output a target digital signal corresponding to the analog signal to be processed.

[0057] Step S120: performing storage processing on the target digital signal through the field programmable gate array, so that the target digital signal is stored in the first storage device.

[0058] In an embodiment of the present application, the target digital signal can be stored and processed by the field programmable gate array so that the target digital signal is stored in the first storage device. When the stored digital signal is read from the first storage device, the target digital signal sent by the analog-to-digital converter is written to the second storage device for caching, and when the stored digital signal is not read from the first storage device, the acquired digital signal is written to the first storage device for storage, wherein the acquired digital signal includes the target digital signal sent by the analog-to-digital converter and / or the cached digital signal read from the second storage device. In other words, the first storage device can be used as the final storage device for the digital signal, and the second storage device can be used as a cache device for the digital signal to ensure reliable storage of data.

[0059] Based on the above content, when the stored digital signal is read from the first storage device, the target digital signal sent by the analog-to-digital converter will be written to the second storage device for caching, and when the stored digital signal is not read from the first storage device, the acquired digital signal will be written to the first storage device for storage, and the acquired digital signal includes the target digital signal sent by the analog-to-digital converter and / or the cached digital signal read from the second storage device. Therefore, the continuous storage of the digital signal can be guaranteed, and even when the stored digital signal is read from the first storage device, it can be cached by the second storage device first, so that compared with the conventional technical solution in which data storage cannot be performed when the stored digital signal is read from the first storage device, it can have higher data storage reliability, avoid the problem of easy data loss caused by the inability to perform data storage continuously, thereby improving the problem of relatively low data storage reliability in the prior art, and since continuous data storage can be achieved, the front-end data acquisition can also be performed continuously and at high speed, thereby improving the efficiency of data processing and meeting the needs of high-speed data acquisition.

[0060] It should be noted that for step S120, the specific method of storing and processing the target digital signal is not limited and can be selected according to actual needs.

[0061] For example, in an alternative embodiment, in order to improve the reliability of data storage to a certain extent, the field programmable gate array may include a first field programmable gate array and a second field programmable gate array. Based on this, the above-mentioned step S120 may further include step S121, step S122 and step S123, and the specific content of each step is described as follows.

[0062] Step S121: receiving a target digital signal sent by the analog-to-digital converter through a first field programmable gate array included in the field programmable gate array.

[0063] In an embodiment of the present application, the target digital signal sent by the analog-to-digital converter can be received by the first field programmable gate array included in the field programmable gate array. That is, the analog-to-digital converter can be connected to the first field programmable gate array so that the analog-to-digital converter can send the target digital signal to the first field programmable gate array. Among them, the first field programmable gate array is also used to perform signal analysis processing on the target digital signal, for example, to determine the type and data length of the target digital signal. In addition, the first field programmable gate array can also send the target digital signal to the connected central processing unit, so that the central processing unit can analyze the target digital signal, etc. Since the processing of the target digital signal by the first field programmable gate array and the central processing unit does not belong to the improvement point of the present application, no specific limitation is made here.

[0064] Step S122: receiving the target digital signal forwarded by the first field programmable gate array through a second field programmable gate array included in the field programmable gate array.

[0065] In the embodiment of the present application, the target digital signal forwarded by the first field programmable gate array can be received by the second field programmable gate array included in the field programmable gate array. That is to say, the first field programmable gate array can be connected to the second field programmable gate array, so that the first field programmable gate array can forward the target digital signal to the second field programmable gate array. In addition, the timing of the first field programmable gate array analyzing and processing the signal of the target digital signal, forwarding it to the central processor, and forwarding it to the first field programmable gate array is not limited, for example, it can be synchronous or asynchronous.

[0066] Step S123: performing storage processing on the received target digital signal through the second field programmable gate array, so that the target digital signal is stored in the first storage device.

[0067] In the embodiment of the present application, the received target digital signal can be stored and processed by the second field programmable gate array, so that the target digital signal is stored in the first storage device, that is, the second field programmable gate array can be used to store and manage the target digital signal, so that the target digital signal can be finally reliably stored in the first storage device. Based on this, the storage and signal analysis processing of the target digital signal can be performed by the first field programmable gate array and the second field programmable gate array respectively, avoiding the occurrence of problems such as data loss due to resource conflicts of the field programmable gate arrays.

[0068] It can be understood that, in the above step S123, the specific manner of storing and processing the received target digital signal by the second field programmable gate array is not limited and can be selected according to actual needs.

[0069] For example, in an alternative implementation, in order to reduce the consumption of cache resources of the second storage device to a certain extent, the above step S123 may include:

[0070] After receiving the target digital signal, the second field programmable gate array can first determine whether a read operation is currently being performed on the data in the first storage device. If no read operation is being performed, the target digital signal is directly written into the first storage device for storage. If a read operation is being performed, the target digital signal is first written into the second storage device for caching until the read operation is completed, and then the target digital signal is read out from the second storage device and written into the first storage device for storage.

[0071] For another example, in another alternative implementation, in order to ensure the overall reliability of data storage, the above-mentioned step S123 may further include step S123a and step S123b, and the specific content of each step is described as follows.

[0072] Step S123a: writing the received target digital signal into the second storage device through the second field programmable gate array to achieve caching of the target digital signal.

[0073] In the embodiment of the present application, the received target digital signal can be written into the second storage device through the second field programmable gate array to achieve caching of the target digital signal. In other words, regardless of whether a read operation is currently being performed on the first storage device, the received target digital signal can be first written into the second storage device for caching.

[0074] Step S123b: when the second field programmable gate array does not read the stored digital signal from the first storage device, read the cached target digital signal from the second storage device, and write the target digital signal into the first storage device for storage.

[0075] In an embodiment of the present application, when the second field programmable gate array does not read the stored digital signal from the first storage device, the cached target digital signal can be read from the second storage device, and the target digital signal can be written to the first storage device for storage. The data storage capacity of the second storage device is smaller than the data storage capacity of the first storage device, and the data transmission efficiency of the second storage device is higher than the data transmission efficiency of the first storage device. In this way, the high data transmission efficiency of the second storage device can be fully utilized to meet the high-speed data acquisition of the front end, and avoid the problem of data loss caused by directly writing data to the first storage device due to the excessively high data acquisition rate of the front end.

[0076] For another example, in another alternative implementation, in order to achieve a balance between cache resource consumption and data loss, the following configuration may be performed in the second field programmable gate array to achieve dynamic management of the data storage solution:

[0077] The second field programmable gate array may first obtain the data acquisition rate configured by the front end before performing data storage. If the data acquisition rate is greater than or equal to the data transmission efficiency (i.e., the data writing efficiency) of the first storage device, the second field programmable gate array may write the received digital signal to the second storage device for caching, and then read it from the second storage device and write it to the first storage device for storage (this storage step is performed when there is no reading operation on the first storage device); if the data acquisition rate is less than the data transmission efficiency of the first storage device, after receiving the digital signal, if the first storage device is not currently performing a reading operation, the second field programmable gate array directly writes the digital signal to the first storage device for storage; if the first storage device is currently performing a reading operation, the digital signal is first written to the second storage device for caching, and then read it from the second storage device (after the reading operation of the first storage device is completed) and written to the first storage device for storage.

[0078] It can be understood that, in the above-mentioned step S123b, the specific method of reading the cached target digital signal from the second storage device and writing the target digital signal to the first storage device for storage is not limited and can be selected according to actual needs. For example, in an alternative implementation, in order to ensure the reliability of digital signal storage, the above-mentioned step S123b can further include step b1, step b2, step b3, step b4, step b5 and step b6, and the specific content of each step is described as follows.

[0079] Step b1: when the second field programmable gate array does not read the stored digital signal from the first storage device, read the cached target digital signal from the second storage device through the second field programmable gate array.

[0080] In an embodiment of the present application, when the second field programmable gate array does not read the stored digital signal from the first storage device, the cached target digital signal can be read from the second storage device through the second field programmable gate array. In this way, the conflict between the read operation and the write operation can be avoided, thereby avoiding data loss and ensuring the reliability of data storage.

[0081] Step b2: writing the read cached target digital signal into the first storage device through the second field programmable gate array.

[0082] In an embodiment of the present application, after the cached target digital signal is read, the cached target digital signal can be written into the first storage device through the second field programmable gate array, so that the target digital signal can be stored in the first storage device.

[0083] Step b3: determining the data length of the target digital signal written into the first storage device through the second field programmable gate array.

[0084] In an embodiment of the present application, after the target digital signal is written to the first storage device, the data length of the target digital signal written to the first storage device can be determined by the second field programmable gate array, and the data length can be recorded, for example, it can be recorded in the cache of the second field programmable gate array.

[0085] Step b4: sending a query write data instruction to the second field programmable gate array through the first field programmable gate array.

[0086] In the embodiment of the present application, after the data length is determined, a query write data instruction can be sent to the second field programmable gate array through the first field programmable gate array, and the query write data instruction can be used to query the data length.

[0087] Step b5: In response to the query write data instruction, the data length of the target digital signal written to the first storage device is sent to the first field programmable gate array.

[0088] In an embodiment of the present application, after receiving the query write data instruction, the second field programmable gate array may send the data length of the target digital signal written to the first storage device to the first field programmable gate array in response to the query write data instruction.

[0089] Step b6: Through the first field programmable gate array, the data length of the target digital signal written to the first storage device is compared with the data length obtained by the first field programmable gate array when performing signal analysis processing when receiving the target digital signal, and when the compared two data lengths are consistent, the first storage device completes the storage of the target digital signal.

[0090] In the embodiment of the present application, the second field programmable gate array can receive the data length of the target digital signal written to the first storage device. Based on this, the first field programmable gate array can compare the data length of the target digital signal written to the first storage device with the data length obtained by the first field programmable gate array when performing signal analysis processing when receiving the target digital signal, and when the two compared data lengths are consistent, the first storage device completes the storage of the target digital signal, which indicates that the storage of the target digital signal is complete and no loss occurs. On the contrary, if the two compared data lengths are inconsistent, it indicates that the stored data is abnormal, such as partial data loss, etc. At this time, the abnormality record can be made, and the target digital signal can also be resent through the first field programmable gate array.

[0091] It is understandable that, in an alternative implementation, in order to ensure the reliability of data storage, before executing the above-mentioned step S121, the above-mentioned step S120 may also include step S124 and step S125, and the specific content of each step is described as follows.

[0092] Step S124, verifying the read and write functions of the second field programmable gate array.

[0093] In an embodiment of the present application, the read and write functions of the second field programmable gate array can be verified. Specifically, the second field programmable gate array can perform corresponding verification on its own read and write functions, that is, determine whether data reading and writing operations can be performed.

[0094] Step S125, after the read and write functions of the second field programmable gate array are verified, determining to execute the step of receiving the target digital signal sent by the analog-to-digital converter through the first field programmable gate array included in the field programmable gate array.

[0095] In an embodiment of the present application, after the read and write function verification of the second field programmable gate array is passed, it can be determined to execute the step of receiving the target digital signal sent by the analog-to-digital converter through the first field programmable gate array included in the field programmable gate array, that is, after the read and write function verification is passed, it can be determined that the above-mentioned step S121 can be executed.

[0096] It can be understood that, in the above step S124, the specific method of verifying the read and write functions of the second field programmable gate array is not limited and can be selected according to actual needs.

[0097] For example, in an alternative implementation, in order to ensure the reliability of the verification of the read and write functions, the above step S124 may further include the following specific contents:

[0098] First, a parameter of a first register of the second field programmable gate array may be read to obtain a first parameter, and the first parameter may be compared with a first preset parameter;

[0099] Secondly, the parameter of the second register of the second field programmable gate array may be read to obtain a second parameter, and the second parameter may be compared with a second preset parameter;

[0100] Then, the parameter of the second register may be configured as a third parameter;

[0101] Finally, after executing the step of configuring the parameter of the second register as the third parameter, read the parameter of the second register to obtain the fourth parameter, and compare the third parameter with the fourth parameter, and when the first parameter matches the first preset parameter, the second parameter matches the second preset parameter, and the third parameter matches the fourth parameter, determine that the read and write function verification of the second field programmable gate array has passed. For example, when the first parameter is consistent with the first preset parameter, the second parameter is consistent with the second preset parameter, and the third parameter is consistent with the fourth parameter, determine that the read and write function verification of the second field programmable gate array has passed.

[0102] It is understandable that, in an alternative implementation, in order to improve the reliability of data storage management and control, before executing the above-mentioned step S121, the above-mentioned step S120 may also include step S126 and step S127, and the specific content of each step is described as follows.

[0103] Step S126, configuring the signal storage speed of the second field programmable gate array, and configuring the signal storage address of the second field programmable gate array.

[0104] In the embodiment of the present application, the signal storage speed of the second field programmable gate array can be configured, and the signal storage address of the second field programmable gate array can be configured to achieve accurate signal storage. In some other implementations, the signal reading speed can also be configured, and the address of the read signal can be configured to achieve accurate signal reading.

[0105] Step S127, after the signal storage speed and the signal storage address are configured, determine to execute the step of receiving the target digital signal sent by the analog-to-digital converter through the first field programmable gate array included in the field programmable gate array.

[0106] In the embodiment of the present application, after the signal storage speed and the signal storage address are configured, it is determined to execute the step of receiving the target digital signal sent by the analog-to-digital converter through the first field programmable gate array included in the field programmable gate array. That is, after the signal storage speed and the signal storage address are configured, it is determined that the above step S121 can be executed.

[0107] Regarding the above-mentioned read and write function verification, in a specific application example, it may include:

[0108] Verify read function: Read register 0x0000 (RO_VERSION_ID), the value should be 0x0000_0000_2023_0531;

[0109] Verify the read function: Read register 0x0004 (RW_DEBUG_REG0), the value should be 0xffff_ffff_ffff_ffff;

[0110] Verify the read and write functions: Configure register 0x0004 (RW_DEBUG_REG0) to any value, then read register 0x0004 (RW_DEBUG_REG0). The read value is the configured value.

[0111] In addition, in some examples, register 0x1000 (RW_RAID_SOFT_RESET) can also be configured to 1 to start the second storage device. Register 0x000C (RO_FPGA_INIT_STATUS) can also be read, and the value should be 0x3 to verify the status of the second storage device. Only when the status is normal can subsequent storage processing be performed.

[0112] With respect to the above signal storage / reading speed and signal storage / reading address configuration, in a specific application example, it may include:

[0113] The first step is to configure the signal storage / reading speed: this can be done by operating registers 0x1004-0x1014 (RW_RAID_WR_SECTOR, RW_RAID_WR_LOOP_NUM, RW_RAID_RD_SECTOR, RW_RAID_RD_LOOP_NUM, RW_RAID_PARAM_VLD);

[0114] The second step is to configure the starting address of storage / reading: this can be done by operating registers 0x2004-0x200C (RW_RECORD_START_ADDR3, RW_RECORD_LENGTH, RW_RECORD_PARAM_VLD), 0x2018-0x2020 (RW_REPLAY_START_ADDR3, RW_REPLAY_LENGTH, RW_REPLAY_PARAM_VLD).

[0115] In addition, in some examples, the following configurations can also be performed:

[0116] Start the storage / reading function: This can be done by operating registers 0x2000 (RW_RECORD_START) and 0x2014 (RW_REPLAY_START), sending a trigger signal to start the storage / reading process;

[0117] Turn off the storage / read function: After confirming that the storage / reading is completed (judging whether the storage operation is completed by operating register 0x2010 (RW_RECORD_FINISH), and judging whether the reading operation is completed by counting the read data), complete it by operating registers 0x2000 (RW_RECORD_START) and 0x2014 (RW_REPLAY_START), send a trigger signal, and end the storage / reading process.

[0118] In addition, in some examples, the following initialization controls can also be performed:

[0119] Determine whether the second field programmable gate array is normal and whether the communication between the second field programmable gate array and the first field programmable gate array is normal: This can be accomplished by operating registers 0x000-0x008 (RO_VERSION_ID, RW_DEBUG_REG0, RW_DEBUG_REG1).

[0120] In addition, in some examples, combined with Figure 4, the communication modules of the first field programmable gate array and the second field programmable gate array can be separately encapsulated (such as the first field programmable gate array includes F1 logic and F1SPI communication module; the second field programmable gate array includes F2 logic and F2SPI communication module) to facilitate the corresponding integrated call. For example, the Clk of the F1SPI communication module is always high. When it is necessary to send an instruction, first assign values ​​to Addr and Outdata, and then, Rst_n is pulled low to trigger, and after this communication is completed, Cs_flog is pulled high once; specifically, when it is necessary to send a query instruction, the steps are the same as above, and after Cs_flog is triggered, the F1 logic reads the data in Indata as the data after the query; when the data is written to SATA, the flog flag is pulled high once, indicating that the write operation is completed.

[0121] To summarize, the FPGA-based data processing method and system provided in the present application can convert the analog signal to be processed through an analog-to-digital converter and output a target digital signal; secondly, the target digital signal can be stored and processed through a field programmable gate array so that the target digital signal is stored in a first storage device. Based on this, when the stored digital signal is read from the first storage device, the target digital signal sent by the analog-to-digital converter will be written to the second storage device for caching, and when the stored digital signal is not read from the first storage device, the acquired digital signal will be written to the first storage device for storage, and the acquired digital signal includes the target digital signal sent by the analog-to-digital converter and / or the cached digital signal read from the second storage device. Therefore, the continuous storage of the digital signal can be guaranteed, and even when the stored digital signal is read from the first storage device, it can be cached by the second storage device first, so that compared with the conventional technical solution in which data storage cannot be performed when the stored digital signal is read from the first storage device, it can have higher data storage reliability, avoid the problem of easy data loss caused by the inability to perform data storage continuously, thereby improving the problem of relatively low data storage reliability in the prior art, and since continuous data storage can be achieved, the front-end data acquisition can also be performed continuously and at high speed, thereby improving the efficiency of data processing and meeting the needs of high-speed data acquisition.

[0122] In several embodiments provided in the embodiments of the present application, it should be understood that the disclosed device and method can also be implemented in other ways. The device and method embodiments described above are merely schematic, for example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the device, method and computer program product according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0123] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0124] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, an electronic device, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk. It should be noted that, in this article, the term "include", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such a process, method, article or device. Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0125] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A data processing method based on FPGA, characterized in that: Applied to a data processing system based on FPGA, the data processing system based on FPGA includes an analog-to-digital converter, a field programmable gate array, a first storage device and a second storage device, the analog-to-digital converter is connected to the field programmable gate array, the field programmable gate array is connected to the first storage device and the second storage device respectively, and the data processing method based on FPGA includes: The analog-to-digital converter converts the received analog signal to be processed and outputs a target digital signal corresponding to the analog signal to be processed; The target digital signal is stored and processed by the field programmable gate array so that the target digital signal is stored in the first storage device, wherein when the stored digital signal is read from the first storage device, the target digital signal sent by the analog-to-digital converter is written to the second storage device for caching, and when the stored digital signal is not read from the first storage device, the acquired digital signal is written to the first storage device for storage, wherein the acquired digital signal includes the target digital signal sent by the analog-to-digital converter and / or the cached digital signal read from the second storage device; The step of performing storage processing on the target digital signal through the field programmable gate array so that the target digital signal is stored in the first storage device includes: Receiving a target digital signal sent by the analog-to-digital converter through a first field programmable gate array included in the field programmable gate array, wherein the first field programmable gate array is further used to perform signal analysis processing on the target digital signal; Receiving the target digital signal forwarded by the first field programmable gate array through a second field programmable gate array included in the field programmable gate array; performing storage processing on the received target digital signal through the second field programmable gate array, so that the target digital signal is stored in the first storage device; The step of performing storage processing on the received target digital signal through the second field programmable gate array so that the target digital signal is stored in the first storage device includes: After receiving the target digital signal, the second field programmable gate array determines whether a read operation is currently being performed on data in the first storage device. If no read operation is being performed, the target digital signal is written into the first storage device for storage. If a read operation is being performed, the target digital signal is written into the second storage device for caching until the read operation is completed, and then the target digital signal is read out of the second storage device and written into the first storage device for storage; or Before storing data, the second field programmable gate array obtains the data acquisition rate configured by the front end. If the data acquisition rate is greater than or equal to the data transmission efficiency of the first storage device, the second field programmable gate array writes the received digital signal to the second storage device for caching, and then reads it from the second storage device and writes it to the first storage device for storage; if the data acquisition rate is less than the data transmission efficiency of the first storage device, after receiving the digital signal, if the first storage device is not currently performing a read operation, the second field programmable gate array writes the digital signal to the first storage device for storage; if the first storage device is currently performing a read operation, the digital signal is written to the second storage device for caching, and then reads it from the second storage device and writes it to the first storage device for storage.

2. The FPGA-based data processing method according to claim 1, characterized in that: The step of performing storage processing on the target digital signal through the field programmable gate array so that the target digital signal is stored in the first storage device further includes: Verifying the read and write functions of the second field programmable gate array; After the read and write functions of the second field programmable gate array are verified to be passed, it is determined to execute the step of receiving the target digital signal sent by the analog-to-digital converter through the first field programmable gate array included in the field programmable gate array.

3. The FPGA-based data processing method according to claim 2, characterized in that: The step of verifying the read and write functions of the second field programmable gate array comprises: Reading a parameter of a first register of the second field programmable gate array to obtain a first parameter, and comparing the first parameter with a first preset parameter; Reading a parameter of a second register of the second field programmable gate array to obtain a second parameter, and comparing the second parameter with a second preset parameter; configuring the parameter of the second register as a third parameter; After executing the step of configuring the parameter of the second register as the third parameter, reading the parameter of the second register to obtain a fourth parameter, and comparing the third parameter with the fourth parameter, and when the first parameter matches the first preset parameter, the second parameter matches the second preset parameter, and the third parameter matches the fourth parameter, determining that the read and write function verification of the second field programmable gate array has passed.

4. The FPGA-based data processing method according to claim 1, characterized in that: The step of performing storage processing on the target digital signal through the field programmable gate array so that the target digital signal is stored in the first storage device further includes: configuring a signal storage speed of the second field programmable gate array, and configuring a signal storage address of the second field programmable gate array; After the configuration of the signal storage speed and the signal storage address is completed, it is determined to execute the step of receiving the target digital signal sent by the analog-to-digital converter through the first field programmable gate array included in the field programmable gate array.

5. A data processing system based on FPGA, characterized in that: The FPGA-based data processing system includes an analog-to-digital converter, a field programmable gate array, a first storage device and a second storage device, wherein the analog-to-digital converter is connected to the field programmable gate array, and the field programmable gate array is connected to the first storage device and the second storage device respectively; Wherein, the FPGA-based data processing system is used to execute the FPGA-based data processing method described in any one of claims 1-4.

6. The FPGA-based data processing system according to claim 5, characterized in that: The field programmable gate array comprises a first field programmable gate array and a second field programmable gate array, the first field programmable gate array is connected to the analog-to-digital converter, and the second field programmable gate array is connected to the first field programmable gate array, the first storage device and the second storage device respectively; Among them, the first field programmable gate array is used to receive the target digital signal sent by the analog-to-digital converter, and the first field programmable gate array is also used to perform type analysis processing on the target digital signal. The second field programmable gate array is used to receive the target digital signal forwarded by the first field programmable gate array and store the target digital signal so that the target digital signal is stored in the first storage device.

7. The FPGA-based data processing system according to claim 5, characterized in that: The data storage capacity of the second storage device is smaller than that of the first storage device, and the data transmission efficiency of the second storage device is higher than the output transmission efficiency of the first storage device.

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