Pixel circuit of display screen

Abstract

The invention discloses a pixel circuit of a display screen. The pixel circuit comprises a light-emitting component, a driving transistor, a capacitor, a first reset transistor and a second reset transistor, the driving transistor has a gate terminal. A first terminal of the capacitor is coupled to the gate terminal of the driving transistor, and a second terminal of the capacitor is coupled to a reset input terminal of the pixel circuit. A first terminal of the first reset transistor is coupled to the gate terminal of the driving transistor, and a second terminal of the capacitor is coupled to the reset input terminal. A first end of the second reset transistor is coupled to the light-emitting component, and a second end of the second reset transistor is coupled to the reset input end.

Description

Technical Field

[0001] The invention relates to a pixel circuit of a display screen, and in particular to a pixel circuit structure of a display screen capable of eliminating critical voltage offset. Background Art

[0002] Among various next-generation display technologies, the importance of micro-OLED (micro Organic Light Emitting Diode) panels has gradually increased in recent years. Unlike traditional LED or OLED panels, whose screens are built on glass substrates, the screens of micro-OLED panels are directly mounted on silicon wafers. This silicon-based implementation method can achieve a lot of benefits, such as small size, light weight, low power consumption, high luminous efficiency, high contrast, high pixel density, etc. With the above advantages, micro-OLED panels are particularly suitable for augmented reality (AR) and virtual reality (VR) applications. Summary of the invention

[0003] Therefore, the main purpose of the present invention is to provide a new pixel circuit for an organic light emitting diode (OLED) panel (especially a micro-OLED panel).

[0004] An embodiment of the present invention discloses a pixel circuit of a display screen, which includes a light-emitting component, a driving transistor, a capacitor, a first reset transistor and a second reset transistor. The driving transistor has a gate terminal. A first end of the capacitor is coupled to the gate terminal of the driving transistor, and a second end of the capacitor is coupled to a reset input terminal of the pixel circuit. A first end of the first reset transistor is coupled to the gate terminal of the driving transistor, and a second end of the first reset transistor is coupled to the reset input terminal. A first end of the second reset transistor is coupled to the light-emitting component, and a second end of the second reset transistor is coupled to the reset input terminal.

[0005] Another embodiment of the present invention discloses a pixel circuit of a display screen, which includes a light-emitting component, a driving transistor, a capacitor, a first reset transistor and a second reset transistor. The driving transistor has a gate terminal for driving the light-emitting component. The capacitor is coupled between a reset input terminal of the pixel circuit and the gate terminal of the driving transistor. The first reset transistor is coupled between the reset input terminal and the gate terminal of the driving transistor to initialize the driving transistor. The second reset transistor is coupled between the reset input terminal and the light-emitting component to initialize the light-emitting component. The driving transistor and the light-emitting component are initialized simultaneously.

[0006] Another embodiment of the present invention discloses a pixel circuit of a display screen, which includes a light-emitting component, a driving transistor, a capacitor, a first reset transistor and a second reset transistor. The driving transistor has a gate terminal for driving the light-emitting component. The capacitor is coupled between a reset input terminal of the pixel circuit and the gate terminal of the driving transistor. The first reset transistor is coupled between the reset input terminal and the gate terminal of the driving transistor. The second reset transistor is coupled between the reset input terminal and the light-emitting component. The first reset transistor is connected in parallel with the capacitor.

[0007] Another embodiment of the present invention discloses a pixel circuit of a display screen, which includes a light-emitting component, a driving transistor, a capacitor, a first reset transistor, a second reset transistor and a cut-off transistor. The driving transistor has a gate terminal for driving the light-emitting component. The capacitor is coupled between a reset input terminal of the pixel circuit and the gate terminal of the driving transistor. The first reset transistor is coupled between the reset input terminal and the gate terminal of the driving transistor. The second reset transistor is coupled between the reset input terminal and the light-emitting component. The cut-off transistor is coupled to the driving transistor and is used to cut off a current path through the driving transistor when an initial voltage for initializing the driving transistor or the light-emitting component is received. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of a pixel circuit of a display screen.

[0009] Figure 2 The figure is a schematic diagram of a pixel circuit of a display screen according to an embodiment of the present invention.

[0010] Figure 3 for Figure 2 Waveform diagram of relevant signals and voltages of the pixel circuit in FIG.

[0011] Figure 4A , Figure 4B , Figure 4C and Figure 4D The operation of the pixel circuit is shown in several stages.

[0012] Figure 5 The figure is a schematic diagram of a pixel circuit of a display screen according to an embodiment of the present invention.

[0013] Figure 6 The operation of the pixel circuit in the reset phase is shown.

[0014] Figure 7 The figure is a schematic diagram of a pixel circuit of a display screen according to an embodiment of the present invention.

[0015] Figure 8 for Figure 7 Waveform diagram of relevant signals and voltages of the pixel circuit in FIG.

[0016] Fig. 9 The operation of the pixel circuit in the reset phase is shown.

[0017] Fig.10 The figure is a schematic diagram of a pixel circuit of a display screen according to an embodiment of the present invention.

[0018] Fig.11 for Fig.10 Waveform diagram of relevant signals and voltages of the pixel circuit in FIG.

[0019] Fig.12 The operation of the pixel circuit in the reset phase is shown.

[0020] Fig.13 The figure is a schematic diagram of a pixel circuit of a display screen according to an embodiment of the present invention.

[0021] Fig.14 The figure is a schematic diagram of a pixel circuit of a display screen according to an embodiment of the present invention.

[0022] Fig.15 The figure is a schematic diagram of a pixel circuit of a display screen according to an embodiment of the present invention.

[0023] Fig.16 FIG. 4 is a schematic diagram of another pixel circuit of a display screen according to an embodiment of the present invention.

[0024] Fig.17 FIG. 4 is a schematic diagram of another pixel circuit of a display screen according to an embodiment of the present invention.

[0025] The reference numerals are described as follows:

[0026] 10, 20, 50, 70, 100, 130, 140, pixel circuit 150, 160, 170

[0028] M1, M2 transistors

[0029] C1, C2 capacitors

[0030] L1 Organic Light Emitting Diode

[0031] S0, S1, S2, S3, S4, EM control signals

[0032] VDATA Display data

[0033] ILED drive current

[0034] ELVDD Power supply voltage

[0035] VSG Source to Gate Voltage

[0036] MDRV driver transistor

[0037] MIN, MIN2 input transistor

[0038] MAZ offset control transistor

[0039] MEMs light emission control transistor

[0040] MR1, MR2 reset transistor

[0041] MC Cut-off transistor

[0042] L2 Light Emitting Component

[0043] VG Gate voltage

[0044] VC Reference Node

[0045] VPAD data input terminal

[0046] VPAD2 Reset input

[0047] VTH Threshold Voltage

[0048] VINT Initial voltage

[0049] VREF reference voltage

[0050] P1~P4 stage DETAILED DESCRIPTION

[0051] Figure 1Schematic diagram of a pixel circuit 10 of a display screen. The display screen may be an organic light emitting diode (OLED) panel or a micro-OLED panel. The pixel circuit 10 includes transistors M1 and M2, a capacitor C1 and an organic light emitting diode L1. The transistor M1 may be a driving transistor for outputting a driving current ILED to control the organic light emitting diode L1 to emit light. The transistor M2 is controlled by a control signal S0 and may be used as a switch for receiving a display data VDATA. The display data VDATA reaching the gate terminal of the transistor M1 may determine the size of the driving current ILED flowing through the organic light emitting diode L1, thereby determining the brightness of the organic light emitting diode L1. The capacitor C1 may be used to store the display data VDATA received by the gate terminal of the transistor M1. The pixel circuit 10 may be operated by receiving a power supply voltage ELVDD from a power supply terminal.

[0052] Based on the behavior of transistor M1, the magnitude of the driving current ILED can be determined according to the corresponding relationship between the driving current ILED and the source-to-gate voltage VSG of transistor M1. Based on the device mobility of transistor M1, the relationship between the driving current ILED and the source-to-gate voltage VSG may follow a square law or an exponential law. For example, if the pixel circuit 10 is implemented by a thin-film transistor (TFT) process, its device mobility is low, and thus the driving current ILED output by transistor M1 is relatively low. Therefore, transistor M1 is more likely to operate in a saturation region and follow the square law. If the pixel circuit 10 is implemented by a complementary metal-oxide semiconductor (CMOS) process, that is, a silicon-based implementation of a micro-OLED panel, its device mobility is higher than that of a thin-film transistor process. Therefore, in order to achieve a comparable current, transistor M1 may operate in a sub-threshold region to follow the exponential law.

[0053] Regardless of whether transistor M1 is operated according to the square law or the exponential law, the driving current ILED and the source-to-gate voltage VSG are in a one-to-one correspondence, so that the driving current ILED can be determined according to the source-to-gate voltage VSG, and the source-to-gate voltage VSG is also determined according to the display data VDATA. For simplicity, this article uses the square law formula as follows:

[0054] ILED=β(VSG-VTH) 2 ; (1)

[0055] Wherein, β represents the gain factor of transistor M1, which is determined by mobility, normalized oxide capacitance, and the aspect ratio of the transistor; VTH is the threshold voltage of transistor M1. When the display data VDATA is received, since the source voltage of transistor M1 is equal to the power supply voltage ELVDD and the gate voltage of transistor M1 is equal to the display data VDATA, equation (1) can be rewritten as:

[0056] ILED=β(ELVDD-VDATA-VTH) 2 (2)

[0057] It should be noted that the formula used to calculate the driving current ILED includes the threshold voltage VTH. On a display screen, due to variations in the process and / or components, different pixels may have inconsistent threshold voltages VTH. The mismatch and offset of the threshold voltage VTH may cause uneven brightness between pixels and produce a Mura effect. Therefore, the present invention proposes a new pixel circuit that can minimize the Mura effect caused by the offset of the threshold voltage VTH through appropriate control. Various embodiments of a pixel circuit with a DeMura compensation function will be described below.

[0058] Figure 2 Schematic diagram of a pixel circuit 20 of a display screen according to an embodiment of the present invention. The pixel circuit 20 includes a driving transistor MDRV, an input transistor MIN, an offset control transistor MAZ, a light-emitting control transistor MEM, two reset transistors MR1 ​​and MR2, two capacitors C1 and C2, and a light-emitting element L2. The driving transistor MDRV can be used to output a driving current ILED to control the light-emitting element L2 according to a display data VDATA. More specifically, the driving transistor MDRV can generate a drain current according to the received display data VDATA, and the drain current can be output as the driving current ILED to drive the light-emitting element L2 to emit light.

[0059] Other transistors in the pixel circuit 20 can be used as control switches to control the operation of the driving transistor MDRV and the light-emitting element L2. These transistors can eliminate the offset of the driving current ILED caused by the variation of the threshold voltage VTH of the driving transistor MDRV through proper setting and control. In this example, these transistors can receive control signals S1, S2, S3 and EM respectively to achieve offset elimination in several stages of operation.

[0060] The capacitor C1 is coupled between the gate terminal of the driving transistor MDRV and a reference node VC, and the capacitor C2 is coupled between the gate terminal of the driving transistor MDRV and a power supply terminal for providing a power supply voltage ELVDD. When the display data VDATA is received, information about the display data VDATA can be stored in the capacitor C1 and / or C2, and the capacitor C1 and / or C2 can also be used to store information about the threshold voltage VTH of the driving transistor MDRV. In addition, the capacitor C1 is coupled between a reset input terminal of the pixel circuit 20 and the gate terminal of the driving transistor MDRV. In this example, the reset input terminal is the same as the data input terminal (i.e., VPAD); that is, the initial voltage VINT (for resetting or initialization) and the display data VDATA are received by the same terminal.

[0061] The input transistor MIN is coupled between the data input terminal VPAD and the reference node VC of the pixel circuit 20 to serve as a switch for controlling the reception of the display data VDATA. Specifically, a first terminal of the input transistor MIN is coupled to the data input terminal VPAD to receive the display data VDATA, a second terminal of the input transistor MIN is coupled to the reference node VC, and a gate terminal of the input transistor MIN receives the control signal S1. The input transistor MIN is responsible for controlling the pixel circuit 20 to receive the display data VDATA.

[0062] The offset control transistor MAZ is coupled between the gate terminal of the driving transistor MDRV and the drain terminal of the driving transistor MDRV to serve as a switch for synchronizing the offset information (i.e., the threshold voltage VTH information) between the gate and drain terminals of the driving transistor MDRV. Specifically, a first terminal of the offset control transistor MAZ is coupled to the drain terminal of the driving transistor MDRV, a second terminal of the offset control transistor MAZ is coupled to the gate terminal of the driving transistor MDRV, and the gate terminal of the offset control transistor MAZ receives the control signal S3.

[0063] The light emitting control transistor MEM is coupled between the drain terminal of the driving transistor MDRV and the light emitting element L2 to serve as a switch for controlling the light emitting of the pixel circuit 20. Specifically, a first terminal of the light emitting control transistor MEM is coupled to the drain terminal of the driving transistor MDRV, a second terminal of the light emitting control transistor MEM is coupled to the anode of the light emitting element L2, and a gate terminal of the light emitting control transistor MEM receives a light emitting control signal EM. The light emitting control transistor MEM is responsible for controlling the driving current ILED generated by the driving transistor MDRV to flow to the light emitting element L2.

[0064] The reset transistor MR1 is coupled between the gate terminal of the driving transistor MDRV and the reference node VC to serve as a switch for initializing the gate terminal of the driving transistor MDRV. Specifically, a first terminal of the reset transistor MR1 is directly connected to the gate terminal of the driving transistor MDRV, a second terminal of the reset transistor MR1 is coupled to the reference node VC to be further coupled to the reset input terminal (the data input terminal VPAD in this example), and the gate terminal of the reset transistor MR1 receives the control signal S2. The reset transistor MR1 is responsible for controlling the initialization or resetting of the driving transistor MDRV, wherein the reset transistor MR1 can form a signal path for transmitting the initial voltage VINT to the driving transistor MDRV to initialize the driving transistor MDRV.

[0065] The reset transistor MR2 is coupled between the light emitting element L2 and the gate terminal of the driving transistor MDRV to serve as a switch for initializing the light emitting element L2. Specifically, a first terminal of the reset transistor MR2 is directly connected to the anode of the light emitting element L2, and a second terminal of the reset transistor MR2 is coupled to the gate terminal of the driving transistor MDRV to be further coupled to the reference node VC and the reset input terminal (the data input terminal VPAD in this example). The reset transistor MR2 is responsible for controlling the initialization or resetting of the light emitting element L2, wherein the reset transistor MR2 can form a signal path for transmitting the initial voltage VINT to the light emitting element L2 to initialize the light emitting element L2.

[0066] The light emitting element L2 is coupled between the light emitting control transistor MEM and the ground terminal. The light emitting element L2 can be driven by the driving current ILED from the driving transistor MDRV to emit light, and can be any element capable of receiving current to emit light, such as an organic light emitting diode.

[0067] The operation of the pixel circuit 20 includes several stages. Figure 32 is a waveform diagram of related signals and voltages of the pixel circuit 20, which shows the waveforms of the control signals S1-S3, the light emitting control signal EM, the voltage of the data input terminal VPAD, the voltage of the reference node VC, and the gate voltage VG of the driving transistor MDRV. It should be noted that in this embodiment, the transistors in the pixel circuit 20 are all P-type metal oxide semiconductor transistors (PMOS transistors), so the signal at a low level can turn on the corresponding transistor and at a high level can turn off the corresponding transistor. Figure 3 The operation of the pixel circuit 20 has four phases P1 to P4, which are respectively Figures 4A to 4D Provide explanation.

[0068] Please refer to Figure 4A Matching Figure 3 As shown, the phase P1 can be regarded as a reset phase (or an initial phase or a pre-charging phase), in which the input transistor MIN and the reset transistors MR1 ​​and MR2 are turned on, and the offset control transistor MAZ and the light-emitting control transistor MEM are turned off. In the phase P1, the pixel circuit 20 can receive an initial voltage VINT through the data input terminal VPAD. Since the input transistor MIN and the reset transistor MR1 are both turned on, the gate terminal of the driving transistor MDRV can be initialized or reset to the initial voltage VINT. In addition, since the reset transistor MR2 is turned on, the anode of the light-emitting component L2 can also be initialized or reset to the initial voltage VINT. For the light-emitting component L2, the level of the initial voltage VINT should be low enough to prevent the light-emitting component L2 from emitting light in this phase.

[0069] In an embodiment of the present invention, the driving transistor MDRV and the light-emitting component L2 can be initialized at the same time in stage P1, and the driving transistor MDRV and the light-emitting component L2 can be initialized by receiving the same initial voltage VINT. In the pixel circuit 20, the initial voltage VINT is received from the data input terminal VPAD, that is, the reset input terminal is the data input terminal VPAD, indicating that the initial voltage VINT and the display data VDATA are received through the same endpoint. The reset input and the data input share the same endpoint, which helps to reduce the number of ports and wirings between pixels on the display screen. For example, the wires used to control the pixel circuit 20 include a power line, a ground line, and a data / signal line (through VPAD), which is simpler than other traditional pixel circuits.

[0070] In addition, in phase P1, since the light-emitting control transistor MEM is turned off, there is no leakage current through the current path of the driving transistor MDRV and the light-emitting element L2. In this case, the light-emitting control transistor MEM can be used as a cutoff transistor to cut off the current path through the driving transistor MDRV and the light-emitting element L2 in the reset phase of receiving the initial voltage VINT, thereby reducing the overall current consumption of the display screen.

[0071] If there is leakage current in the reset phase P1, the initial voltage actually received by the anode of the light-emitting component L2 may be pulled by the leakage current, thereby deviating from the initial voltage VINT received by the reset input terminal. Therefore, in the reset phase, it is preferred to avoid leakage current flowing through the light-emitting component L2 to better control the initial voltage actually received by the light-emitting component L2.

[0072] As described above, the light emission control transistor MEM is turned off in phase P1 , therefore, the reset transistor MR2 should be directly connected to the light emission element L2 instead of being connected through the light emission control transistor MEM, so that the light emission element L2 can be initialized smoothly through the reset transistor MR2 .

[0073] Please refer to Figure 4B Matching Figure 3 As shown, in phase P2, the reset transistors MR1 ​​and MR2 are turned off, the offset control transistor MAZ is turned on, the input transistor MIN remains turned on, and the light-emitting control transistor MEM remains turned off. Phase P2 is used to store information of the threshold voltage VTH. More specifically, the source terminal of the driving transistor MDRV can receive the power supply voltage ELVDD, so that the gate voltage of the driving transistor MDRV rises to ELVDD-VTH, and through the turned-on offset control transistor MAZ, the drain voltage of the driving transistor MDRV also reaches ELVDD-VTH. The charge corresponding to the gate voltage ELVDD-VTH can be stored in the capacitors C1 and C2. At this time, the voltage of the data input terminal VPAD can rise from the initial voltage VINT to a reference voltage VREF, ready to receive the display data VDATA in the next stage, and the voltage of the reference node VC is also pulled to VREF.

[0074] Please refer to Figure 4C Matching Figure 3 As shown, phase P3 can be regarded as a scanning phase, in which the offset control transistor MAZ is turned off, the input transistor MIN remains turned on, and the light-emitting control transistor MEM and the reset transistors MR1 ​​and MR2 remain turned off. In this phase, the display data VDATA is input from the data input terminal VPAD. Through the turned-on input transistor MIN, the voltage of the reference node VC drops to the voltage of the display data VDATA, which can be written to the gate terminal of the driving transistor MDRV through the capacitor C1. More specifically, the voltage of the reference node VC can change from the reference voltage VREF to the display data VDATA, and this voltage change can be coupled to the gate terminal of the driving transistor MDRV through the capacitor C1. Through the voltage division of the capacitors C1 and C2, the gate voltage VG will be equal to:

[0075]

[0076] In this stage, the gate voltage VG may include information of the display data VDATA and the threshold voltage VTH.

[0077] Please refer to Figure 4D Matching Figure 3 As shown, phase P4 can be regarded as a light-emitting phase, wherein the light-emitting control transistor MEM is turned on and the other transistors are turned off. The conduction of the light-emitting control transistor MEM causes the driving current ILED to be transmitted to the light-emitting element L2, so that the light-emitting element L2 emits light. Since the information of the gate voltage VG is stored in the capacitors C1 and C2, the driving current ILED can be maintained at its target level during the light-emitting period.

[0078] As described above, the brightness of the light emitting element L2 can be determined according to the size of the driving current ILED, and the driving current ILED is also determined according to the source-to-gate voltage VSG of the driving transistor MDRV. In one embodiment, if the pixel circuit 20 is implemented by a thin film transistor process and is disposed on a panel, the operation of the driving transistor MDRV follows the square law, and the driving current ILED can be calculated as follows:

[0079]

[0080]

[0081] Where β represents the gain factor of the drive transistor MDRV, which is equal to:

[0082]

[0083] Among them, μ n is the mobility of the driving transistor MDRV, C OX is the standard oxide capacitance of the driving transistor MDRV, and W / L is the width-to-length ratio of the driving transistor MDRV.

[0084] From equation (4), it can be seen that the value of the driving current ILED only includes a signal-dependent item composed of the display data VDATA, and is not dependent on the threshold voltage VTH, which means that the offset of the threshold voltage VTH between pixels will not affect the current size and the brightness of the light-emitting component L2, and the parameter β will not produce a significant mismatch or offset and need to be eliminated. In this way, the problem of inconsistent brightness can be solved.

[0085] In another embodiment, the pixel circuit 20 can be implemented in an integrated circuit (IC) in a silicon-based manner through a complementary metal oxide semiconductor process, such as a micro organic light emitting diode panel. Therefore, the device mobility of its transistor is higher than that of a thin film transistor process, so that the driving transistor MDRV in the pixel circuit 20 operates in a subcritical region, which follows the following formula:

[0086]

[0087] as well as

[0088]

[0089] Among them, μ n is the mobility of the driving transistor MDRV, C OX is the standard oxide capacitance of the driving transistor MDRV, W / L is the width-to-length ratio of the driving transistor MDRV, V t is the thermal voltage, n is equal to (C OX +C depl ) / C OX ≈1.5, where C depl is the depletion capacitance of the driving transistor MDRV. It should be noted that under the exponential law, the effect of the threshold voltage VTH can also be minimized or eliminated.

[0090] like Figure 2 As shown, in the pixel circuit 20, the reset transistor MR1 and the capacitor C1 are coupled between the reset / data input terminal VPAD and the driving transistor MDRV. More specifically, a first end of the reset transistor MR1 and a first end of the capacitor C1 are commonly coupled to the reset / data input terminal VPAD through the input transistor MIN, and a second end of the reset transistor MR1 and a second end of the capacitor C1 are commonly directly connected to the gate terminal of the driving transistor MDRV. In this case, the reset transistor MR1 is connected in parallel with the capacitor C1.

[0091] Although the reset transistor MR1 and the capacitor C1 are connected in parallel, they provide different functions. In the reset phase (i.e., P1), the reset transistor MR1 is turned on, and the initial voltage VINT received from the data input terminal VPAD can be transmitted to the gate terminal of the drive transistor MDRV through the reset transistor MR1. In the scan phase (i.e., P3), the reset transistor MR1 is turned off, and the display data VDATA received from the data input terminal VPAD can be coupled to the gate terminal of the drive transistor MDRV through the capacitor C1 to generate a voltage change on the gate terminal of the drive transistor MDRV.

[0092] It should be noted that the structure of the pixel circuit 20 is only an exemplary embodiment of the present invention. In order to reduce or eliminate the Mura effect caused by the deviation of the threshold voltage VTH, other similar pixel structures may also be used.

[0093] Figure 5FIG. 5 is a schematic diagram of a pixel circuit 50 of a display screen according to an embodiment of the present invention. The structure of the pixel circuit 50 is similar to that of the pixel circuit 20, so signals or components with similar functions are represented by the same symbols. The difference between the pixel circuit 50 and the pixel circuit 20 is that in the pixel circuit 50, the reset transistor MR2 is directly connected to the reference node VC, rather than being coupled to the reference node VC through the reset transistor MR1.

[0094] Figure 6 The operation of the pixel circuit 50 in phase P1 (i.e., the reset phase) is shown, wherein the input transistor MIN and the reset transistors MR1 ​​and MR2 are turned on, and the offset control transistor MAZ and the light emitting control transistor MEM are turned off. In the reset phase, the pixel circuit 20 receives an initial voltage VINT through the data input terminal VPAD. The initial voltage VINT can be transmitted to the gate terminal of the driving transistor MDRV through the input transistor MIN and the reset transistor MR1 to initialize the driving transistor MDRV. The initial voltage VINT can also be transmitted to the anode of the light emitting component L2 through the input transistor MIN and the reset transistor MR2 to initialize the light emitting component L2. The detailed operation of the pixel circuit 50 is similar to that of the pixel circuit 20, and will not be repeated here.

[0095] Figure 7 Schematic diagram of a pixel circuit 70 of a display screen according to an embodiment of the present invention. The structure of the pixel circuit 70 is similar to that of the pixel circuit 20, so signals or components with similar functions are represented by the same symbols. The difference between the pixel circuit 70 and the pixel circuit 20 is that, in addition to the data input terminal VPAD, the pixel circuit 70 also includes a reset input terminal VPAD2, and the reset input terminal VPAD2 is coupled to the reference node VC through another input transistor MIN2. In addition, the pixel circuit 70 also includes a truncation transistor MC coupled to the source terminal of the driving transistor MDRV, and the reset transistor MR2 is omitted, wherein the initialization of the light emitting element L2 can be performed using the offset control transistor MAZ and the light emitting control transistor MEM. The truncation transistor MC is coupled between the source terminal of the driving transistor MDRV and the power supply terminal for providing the power supply voltage ELVDD, and is controlled by a control signal S4.

[0096] In the pixel circuit 70, the reset input terminal VPAD2 for receiving the initial voltage VINT is different from the data input terminal VPAD for receiving the display data VDATA. The input transistor MIN at the data input terminal VPAD can be turned on in the scanning phase to receive the display data VDATA, and the input transistor MIN2 at the reset input terminal VPAD2 can be turned on in the reset phase to receive the initial voltage VINT.

[0097] Figure 8is a waveform diagram of related signals and voltages of the pixel circuit 70, which shows the waveforms of the control signals S1-S4, the light emitting control signal EM, the voltage of the data input terminal VPAD, the voltage of the reference node VC, and the gate voltage VG of the driving transistor MDRV. Since the pixel circuit 70 has a reset input terminal VPAD2 different from the data input terminal VPAD, the data input terminal VPAD can continuously provide the display data VDATA, and the initial voltage VINT is provided through the reset input terminal VPAD2.

[0098] Fig. 9 FIG. 7 shows the operation of the pixel circuit 70 in phase P1 (i.e., the reset phase). Figure 8 and Fig. 9 The cutoff transistor MC controlled by the control signal S4 is turned off in phase P1 to cut off the leakage current during the initialization operation. In addition, the cutoff transistor MC should be turned on in phase P4 (i.e., the light-emitting phase) so that the driving current ILED can be output to the light-emitting component L2 to make the light-emitting component emit light.

[0099] In the pixel circuit 20, the reset transistor MR2 is not connected to the anode of the light emitting component L2 through the light emitting control transistor MEM. Therefore, in the reset phase, the light emitting control transistor MEM located on the current path through the driving transistor MDRV and the light emitting component L2 can be turned off to cut off the leakage current. In other words, the light emitting control transistor MEM can be used as a cut-off transistor. In contrast, in the pixel circuit 70, the path for transmitting the initial voltage VINT to the light emitting component L2 includes the input transistor MIN2, the reset transistor MR1, the offset control transistor MAZ and the light emitting control transistor MEM, and these transistors should be turned on in the reset phase to smoothly initialize the light emitting component L2. In this example, the offset control transistor MAZ can be used as a reset transistor in the reset phase to be coupled to the light emitting component L2 through the light emitting control transistor MEM. Therefore, the cut-off transistor MC should be provided in the pixel circuit 70, and the cut-off transistor MC should be turned off in the reset phase to cut off the current path through the driving transistor MDRV when the initial voltage VINT is received to eliminate the leakage current, while preventing the initial voltage VINT received by the light emitting component L2 from being offset.

[0100] Fig.101 is a schematic diagram of a pixel circuit 100 of a display screen according to an embodiment of the present invention. The structure of the pixel circuit 100 is similar to that of the pixel circuit 70, so signals or components with similar functions are represented by the same symbols. The difference between the pixel circuit 100 and the pixel circuit 70 is that the pixel circuit 100 includes a reset transistor MR2 coupled between the anode of the light emitting element L2 and the gate terminal of the driving transistor MDRV, similar to the implementation of the pixel circuit 20. In addition, the truncation transistor MC of the pixel circuit 70 is omitted in the pixel circuit 100.

[0101] Fig.11 1 is a waveform diagram of related signals and voltages of the pixel circuit 100, which shows the waveforms of the control signals S1-S3, the light emitting control signal EM, the voltage of the data input terminal VPAD, the voltage of the reference node VC, and the gate voltage VG of the driving transistor MDRV. Similarly, since the pixel circuit 70 has a reset input terminal VPAD2 different from the data input terminal VPAD, the data input terminal VPAD can continuously provide the display data VDATA, and the initial voltage VINT is provided through the reset input terminal VPAD2.

[0102] Fig.12 FIG. 2 shows the operation of the pixel circuit 100 in phase P1 (i.e., the reset phase). Fig.11 and Fig.12 In phase P1, the offset control transistor MAZ and the light emitting control transistor MEM are both turned off, so there is no current conduction path between the power supply terminal and the light emitting element L2, and there is no current conduction path between the power supply terminal and the reset input terminal VPAD2. Therefore, there is no leakage current path during the reset operation, and no additional cutoff transistor MC is required. The other operation modes of the pixel circuit 100 are similar to the aforementioned pixel circuits and are not described in detail here.

[0103] It is worth noting that the purpose of the present invention is to propose a new pixel circuit that can be used to eliminate the offset caused by the threshold voltage of the driving transistor on the organic light emitting diode panel. Those skilled in the art can make modifications or changes accordingly, but are not limited to this. For example, in the above-mentioned embodiments, the transistors in the pixel circuit are all P-type metal oxide semiconductor transistors; but in other embodiments, N-type metal oxide semiconductor transistors (NMOS transistors) or a combination of N-type and P-type metal oxide semiconductor transistors can also be used to implement a similar architecture, and the level and initial voltage of the control signal can be modified accordingly. In the embodiments proposed in this specification, a pixel circuit structure of two capacitors C1 and C2 is used, but the present invention is not limited to this; in other embodiments, capacitor C2 can be omitted and only C1 can be retained to realize a pixel circuit structure of a single capacitor. In addition, the above-mentioned embodiments can be applied to thin film transistor technology to be implemented on the glass substrate of the display screen, and can also be applied to complementary metal oxide semiconductor technology to be implemented in an integrated circuit. In addition, the pixel circuit of the present invention can be applied to various self-luminous panels, including organic light emitting diode panels, mini-LED panels, micro-LED panels, and micro organic light emitting diode panels, but not limited to this.

[0104] The present invention proposes some pixel circuit structures, in which the reset transistor can be set in any and feasible way to realize the initialization of the driving transistor and the light-emitting component. As long as a first reset transistor is coupled between the reset input terminal and the gate terminal of the driving transistor and the first reset transistor can be turned on during the reset phase, the first reset transistor can be used to initialize the driving transistor. As long as a second reset transistor is coupled between the reset input terminal and the light-emitting component and the second reset transistor can be turned on during the reset phase, the second reset transistor can be used to initialize the light-emitting component. The following embodiments illustrate other possible architectures that can be used to implement the reset transistor in the pixel circuit of the present invention.

[0105] Fig.13 1 is a schematic diagram of a pixel circuit 130 of a display screen according to an embodiment of the present invention. The structure of the pixel circuit 130 is similar to that of the pixel circuit 20, so signals or components with similar functions are represented by the same symbols. The difference between the pixel circuit 130 and the pixel circuit 20 is that in the pixel circuit 130, the reset transistor MR2 is directly connected between the reset / data input terminal VPAD and the anode of the light-emitting element L2, rather than being coupled between the gate terminal of the drive transistor MDRV and the light-emitting element L2.

[0106] In the pixel circuit 20, the reset transistor MR2 is coupled to the reset / data input terminal VPAD through the input transistor MIN (and also through the reset transistor MR1). In this case, the signal path for transmitting the initial voltage VINT to the light-emitting element L2 includes three switches respectively composed of the input transistor MIN, the reset transistor MR1 and the reset transistor MR2. These switches are all turned on in the reset phase, but in the actual circuit, each turned-on switch has a parasitic resistance, thereby generating a resistance-capacitance delay (RC delay). The resistance-capacitance delay increases the time taken for the anode voltage of the light-emitting element L2 to reach its target initial voltage VINT, thereby reducing the operating speed of the pixel circuit and reducing the refresh rate that can be achieved by the display screen.

[0107] In contrast, in the pixel circuit 130, the left end of the reset transistor MR2 is directly connected to the reset / data input terminal VPAD without passing through any other transistors or switches. In this case, the signal path for transmitting the initial voltage VINT to the light-emitting component L2 only includes a single switch composed of the reset transistor MR2. This embodiment can minimize the resistance and capacitance delays on the signal path to reduce the time required for the light-emitting component L2 to be initialized. Therefore, the structure of the pixel circuit 130 can achieve faster operation speed and higher panel refresh rate.

[0108] Fig.14 1 is a schematic diagram of a pixel circuit 140 of a display screen according to an embodiment of the present invention. The structure of the pixel circuit 140 is similar to that of the pixel circuit 130, so signals or components with similar functions are represented by the same symbols. The difference between the pixel circuit 140 and the pixel circuit 130 is that in the pixel circuit 140, the reset transistor MR1 is directly connected between the reset / data input terminal VPAD and the gate terminal of the drive transistor MDRV, rather than being coupled between the reference node VC and the gate terminal of the drive transistor MDRV.

[0109] In the pixel circuit 20 or 130, the reset transistor MR1 is coupled to the reset / data input terminal VPAD through the input transistor MIN. In this case, the signal path for transmitting the initial voltage VINT to the gate terminal of the driving transistor MDRV includes two switches respectively formed by the input transistor MIN and the reset transistor MR1. These switches are turned on in the reset phase, but in the actual circuit, each turned-on switch has a parasitic resistance, thereby generating a resistance-capacitance delay, which increases the time taken for the gate voltage of the driving transistor MDRV to reach its target initial voltage VINT, thereby reducing the operating speed of the pixel circuit and reducing the refresh rate that can be achieved by the display screen.

[0110] In contrast, in the pixel circuit 140, the left end of the reset transistor MR1 is directly connected to the reset / data input terminal VPAD without passing through any other transistors or switches. In this case, the signal path for transmitting the initial voltage VINT to the drive transistor MDRV only includes a single switch formed by the reset transistor MR1. This embodiment can minimize the resistance and capacitance delays on the signal path to reduce the time required for the drive transistor MDRV to be initialized.

[0111] Furthermore, in the pixel circuit 140, the reset transistor MR1 used to initialize the driving transistor MDRV is directly connected between the reset / data input terminal VPAD and the gate terminal of the driving transistor MDRV, and the reset transistor MR2 used to initialize the light-emitting element L2 is directly connected between the reset / data input terminal VPAD and the anode of the light-emitting element L2. In this way, the signal path for initialization is simplified, and therefore, the structure of the pixel circuit 140 can achieve optimal efficiency in consideration of the operating speed of the reset phase of the display screen.

[0112] The detailed operation of the pixel circuits 130 and 140 and their related signal waveforms are similar to those of the pixel circuit 20. Those skilled in the art can refer to the above paragraphs and Figure 3 and Figures 4A to 4D The operation of the pixel circuits 130 and 140 can be inferred from the description of FIG. 1 , which will not be described here for simplicity.

[0113] It is worth noting that the various pixel circuit embodiments proposed in this specification can be combined with each other in any manner to achieve the initialization of the driving transistor and the light-emitting component. For example, the data input terminal can be used as a reset input terminal to provide an initial voltage in the reset stage, or the initial voltage can also be received by a reset input terminal different from the data input terminal. For the reset transistor (such as MR1) used to initialize the driving transistor, one end can be coupled to the gate terminal of the driving transistor, and the other end can be coupled to the reset input terminal through an input transistor or directly connected to the reset input terminal. For the reset transistor (such as MR2) used to initialize the light-emitting component, one end can be coupled to the anode of the light-emitting component through a light-emitting control transistor or directly connected to the anode of the light-emitting component, and the other end can be coupled to the gate terminal of the driving transistor to further couple to the reset input terminal through another reset transistor and / or input transistor, coupled to a reference node to further couple to the reset input terminal through an input transistor, or directly connected to the reset input terminal. If the signal path for initializing the light emitting component passes through the light emitting control transistor, the light emitting control transistor should be turned on during the reset phase, so a cutoff transistor can be provided to cut off the leakage current path from the power supply end to the light emitting component and / or the reset input end. The above implementations and variations can be selectively utilized to achieve various pixel structure variations of the embodiments of the present invention.

[0114] The following paragraphs also describe several possible pixel structures. Fig.15 1 is a schematic diagram of a pixel circuit 150 of a display screen according to an embodiment of the present invention. In the pixel circuit 150, the reset transistor MR1 is coupled between the reference node VC and the gate terminal of the driving transistor MDRV. The offset control transistor MAZ and the light emitting control transistor MEM can also be used as reset transistors, which are turned on in the reset phase to transmit the initial voltage VINT to the light emitting element L2. Therefore, a cutoff transistor MC should be set on the current path of the driving transistor MDRV, which is turned off in the reset phase to avoid leakage current.

[0115] Fig.16 FIG. 1 is a schematic diagram of another pixel circuit 160 of a display screen according to an embodiment of the present invention. In the pixel circuit 160, the reset transistor MR1 is directly connected to the reset / data input terminal VPAD without passing through any other transistors. Similarly, the offset control transistor MAZ and the light emitting control transistor MEM can also be used as reset transistors, which are turned on during the reset phase to transmit the initial voltage VINT to the light emitting element L2. The pixel circuit 160 is also provided with a cutoff transistor MC to avoid leakage current.

[0116] Fig.17 Schematic diagram of another pixel circuit 170 of a display screen according to an embodiment of the present invention. In the pixel circuit 170, the reset transistor MR2 is connected between the reset / data input terminal VPAD and the anode of the light emitting component L2 to transmit the initial voltage VINT to the light emitting component L2. The offset control transistor MAZ and the light emitting control transistor MEM are turned on in the reset phase to transmit the initial voltage VINT from the light emitting component L2 to the gate terminal of the driving transistor MDRV in the reset phase. In other words, the offset control transistor MAZ and the light emitting control transistor MEM can also be used as reset transistors to initialize the driving transistor MDRV, so other reset transistors (such as MR1) in the above-mentioned embodiments can be omitted. Since the light emitting control transistor MEM should be turned on in the reset phase, it is necessary to set a cutoff transistor MC and turn it off in the reset phase to avoid leakage current.

[0117] In summary, the present invention proposes a pixel circuit that can be used to eliminate the offset caused by the critical voltage of the driving transistor. The operation of the pixel circuit includes a reset phase, in which the driving transistor and the light-emitting component are initialized at the same time. The initial voltage used to initialize the driving transistor and the light-emitting component can be received from a reset input terminal, and the reset input terminal can be the same as a data input terminal used to provide display data, or can be different from the data input terminal. A first reset transistor can be coupled between the reset input terminal and the driving transistor to transmit the initial voltage to the gate terminal of the driving transistor. In one or more embodiments, the first reset transistor can be connected in parallel with the capacitor used to couple the display data. A second reset transistor can be coupled between the reset input terminal and the light-emitting component to transmit the initial voltage to the anode of the light-emitting component. In one or more embodiments, a cutoff transistor can be set to avoid leakage current during the reset phase. The first reset transistor and the second reset transistor can be set and connected in any and feasible manner to achieve initialization of the driving transistor and the light-emitting component.

[0118] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A pixel circuit of a display screen, characterized in that: include: a light emitting component; a driving transistor having a gate terminal; A capacitor, comprising: a first terminal coupled to the gate terminal of the driving transistor; and a second terminal coupled to a reset input terminal of the pixel circuit; a first reset transistor, comprising: a first terminal coupled to the gate terminal of the driving transistor; and a second terminal coupled to the reset input terminal; and a second reset transistor, comprising: a first end coupled to the light emitting component; and A second terminal is coupled to the reset input terminal.

2. The pixel circuit according to claim 1, wherein: The reset input terminal is a data input terminal for receiving display data.

3. The pixel circuit according to claim 1, wherein: The reset input terminal is different from a data input terminal for receiving a display data.

4. The pixel circuit according to claim 1, wherein: The first reset transistor is coupled to the reset input terminal through an input transistor.

5. The pixel circuit according to claim 1, wherein: The first reset transistor is directly connected to the reset input terminal.

6. The pixel circuit according to claim 1, wherein: The second reset transistor is coupled to the reset input terminal through an input transistor.

7. The pixel circuit according to claim 1, wherein: The second reset transistor is directly connected to the reset input terminal.

8. The pixel circuit according to claim 1, wherein: The second reset transistor is coupled to the light emitting element through a light emitting control transistor.

9. The pixel circuit according to claim 1, wherein: The second reset transistor is directly connected to the light emitting element.

10. The pixel circuit according to claim 1, wherein: The first reset transistor forms a signal path for transmitting an initial voltage to the driving transistor to initialize the driving transistor.

11. The pixel circuit according to claim 1, wherein: The second reset transistor forms a signal path for transmitting an initial voltage to the light emitting element to initialize the light emitting element.

12. The pixel circuit according to claim 1, wherein: An initial voltage initializes the driving transistor through the first reset transistor, and initializes the light emitting component through the second reset transistor.

13. The pixel circuit according to claim 1, wherein: An initial voltage is transmitted to the gate terminal of the driving transistor through the first reset transistor, and a display data is coupled to the gate terminal of the driving transistor through the capacitor.

14. The pixel circuit according to claim 1, wherein: Also includes: A cutoff transistor is coupled to the driving transistor and is used to cut off a current path passing through the driving transistor when an initial voltage for initializing the driving transistor or the light emitting element is received.

15. A pixel circuit of a display screen, characterized in that: include: a light emitting component; a driving transistor having a gate terminal for driving the light emitting element; a capacitor coupled between a reset input terminal of the pixel circuit and the gate terminal of the driving transistor; a first reset transistor, coupled between the reset input terminal and the gate terminal of the driving transistor, for initializing the driving transistor; and a second reset transistor, coupled between the reset input terminal and the light emitting element, for initializing the light emitting element; The driving transistor and the light emitting element are initialized simultaneously.

16. The pixel circuit according to claim 15, characterized in that: The driving transistor and the light emitting element are initialized by receiving the same initial voltage.

17. The pixel circuit according to claim 16, wherein: The initial voltage is received from a data input terminal for receiving a display data.

18. The pixel circuit according to claim 16, wherein: The initial voltage is received from a reset input terminal which is different from a data input terminal for receiving a display data.

19. The pixel circuit according to claim 16, wherein: The first reset transistor forms a signal path for transmitting the initial voltage to the driving transistor to initialize the driving transistor.

20. The pixel circuit according to claim 19, characterized in that: The signal path for transmitting the initial voltage to the driving transistor includes only a single switch.

21. The pixel circuit according to claim 16, wherein: The second reset transistor forms a signal path for transmitting the initial voltage to the light emitting element to initialize the light emitting element.

22. The pixel circuit according to claim 21, characterized in that: The signal path for transmitting the initial voltage to the light emitting element includes only a single switch.

23. A pixel circuit of a display screen, characterized in that: include: a light emitting component; a driving transistor having a gate terminal for driving the light emitting element; a capacitor coupled between a reset input terminal of the pixel circuit and the gate terminal of the driving transistor; a first reset transistor coupled between the reset input terminal and the gate terminal of the driving transistor; and a second reset transistor coupled between the reset input terminal and the light emitting element; Wherein, the first reset transistor is connected in parallel with the capacitor.

24. The pixel circuit according to claim 23, characterized in that: An initial voltage is transmitted to the gate terminal of the driving transistor through the first reset transistor, and a display data is coupled to the gate terminal of the driving transistor through the capacitor.

25. The pixel circuit according to claim 23, characterized in that: A first terminal of the first reset transistor and a first terminal of the capacitor are coupled to the reset input terminal through an input transistor.

26. The pixel circuit according to claim 25, characterized in that: A second terminal of the first reset transistor and a second terminal of the capacitor are directly connected to the gate terminal of the driving transistor.

27. A pixel circuit of a display screen, characterized in that: include: a light emitting component; a driving transistor having a gate terminal for driving the light emitting element; a capacitor coupled between a reset input terminal of the pixel circuit and the gate terminal of the driving transistor; a first reset transistor coupled between the reset input terminal and the gate terminal of the driving transistor; a second reset transistor coupled between the reset input terminal and the light emitting element; as well as A cutoff transistor is coupled to the driving transistor and is used to cut off a current path passing through the driving transistor when an initial voltage for initializing the driving transistor or the light emitting element is received.

28. The pixel circuit according to claim 27, characterized in that: The cutoff transistor includes a light-emitting control transistor coupled between the driving transistor and the light-emitting element.

29. The pixel circuit according to claim 28, characterized in that: The second reset transistor is directly connected to the light emitting element instead of being connected through the light emitting control transistor.

30. The pixel circuit according to claim 27, wherein: The cutoff transistor is coupled between the driving transistor and a power supply terminal.

31. The pixel circuit according to claim 30, characterized in that: The second reset transistor is coupled to the light emitting element through a light emitting control transistor.

32. The pixel circuit according to claim 27, wherein: The cutoff transistor is turned off during a reset phase when the initial voltage is received, and is turned on during a light emitting phase when the light emitting element emits light.

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