Display panel and display device

Abstract

The invention relates to a display panel and a display device, and belongs to the technical field of display. The display panel comprises a pixel circuit and a light-emitting element; the monitoring module and the compensation module are electrically connected with the data line, a part of a display area of the display panel is a low-gray-scale picture in a one-frame display period, and a data voltage value transmitted on the data line jumps into a first data voltage at the display time of the low-gray-scale picture; the maintenance time of the first data voltage detected by the monitoring module is the same as the maintenance time of the compensation voltage transmitted to the data line by the compensation module; the time interval between the time when the bias voltage control signal line transmits the enable signal to the control end of the bias voltage adjusting module, the starting time when the data voltage value jumps to the first data voltage and the starting time when the compensation module transmits the compensation voltage to the data line is the same as the time interval between the time when the bias voltage control signal line transmits the enable signal and the starting time when the data voltage value jumps to the first data voltage. The display device comprises a driving circuit board and the display panel. The structure of the panel does not need to be changed, and the display quality when the low-gray-scale picture is displayed can be effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Compared with liquid crystal displays (LCDs), organic light emitting diodes (OLEDs) have the characteristics of self-luminescence, fast response, wide color gamut, large viewing angle, high brightness, etc., and can be used to make thin display devices and flexible display devices. They have gradually become the focus of research in the current display technology field, and are increasingly being used in the field of high-performance displays. Organic light emitting diodes require current drive. When used in the display field, the driving transistor in the pixel circuit is controlled to provide a driving current to the organic light emitting diode so that the organic light emitting diode emits light, and a stable driving current needs to be provided to the organic light emitting diode to ensure the display performance in the application. Therefore, pixel circuit design is the core technical content of OLED displays and has important research significance.

[0003] In the process of driving and displaying, the display device of the prior art will inevitably have mutual coupling between signals due to the design of the pixel circuit structure itself in the display panel. In particular, when a certain signal jumps, the probability of the driving signal close to it being coupled by the jump signal is greatly increased, which is easy to affect the display quality. In the existing design, the signal coupling problem in the circuit structure is improved by changing the design of the pixel circuit, such as adding a shielding structure, etc., but this design method easily complicates the circuit structure of the panel, which is not conducive to the production and cost control of the panel.

[0004] Therefore, providing a display panel and a display device that can effectively improve the display quality without changing the structure of the panel itself is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] In order to solve the above technical problems, the present disclosure provides a display panel and a display device to solve the problem that the display quality of the display device in the prior art cannot be effectively guaranteed.

[0006] The present disclosure provides a display panel, comprising a plurality of electrically connected pixel circuits and light-emitting elements; the pixel circuit comprises an electrically connected driving module, a first reset module, a data writing module and a bias voltage regulating module;

[0007] The display panel includes a plurality of first reset signal lines, a plurality of data lines and a plurality of bias control signal lines; a first end of the first reset module is electrically connected to the first reset signal line, and a second end of the first reset module is electrically connected to the anode of the light emitting element; a control end of the bias adjustment module and a control end of the first reset module are both electrically connected to the bias control signal line, a first end of the data writing module and a first end of the bias adjustment module are both electrically connected to the first end of the driving module, and a second end of the data writing module is electrically connected to the data line;

[0008] In the pixel circuit, in a direction perpendicular to the light emitting surface of the display panel, the first reset signal line, the data line, and the anode of the light emitting element at least partially overlap;

[0009] It also includes a monitoring module and a compensation module, both of which are electrically connected to the data line;

[0010] In a display period of a frame of the display panel, part of the display area of ​​the display panel is a low grayscale picture, and during the display time of the low grayscale picture, the data voltage value transmitted on the data line jumps to the first data voltage;

[0011] The monitoring module detects that the first data voltage is maintained for a time period of A, and then the compensation module transmits a compensation voltage to the data line, and the compensation voltage is maintained for a time period of A;

[0012] The time interval for the bias control signal line to transmit the enable signal to the control end of the bias adjustment module is B, and the time interval between the starting moment when the data voltage value transmitted on the data line jumps to the first data voltage and the starting moment when the compensation module transmits the compensation voltage to the data line is B.

[0013] Based on the same inventive concept, the present disclosure further provides a display device, which includes a driving circuit board and the above-mentioned display panel, and the driving circuit board is electrically connected to the above-mentioned display panel.

[0014] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0015] The display panel provided by the present disclosure is provided with data lines electrically connected to the monitoring module and the compensation module respectively. When a low grayscale image is displayed in a partial display area of ​​the display panel, the monitoring module monitors the jump of the first data voltage transmitted on the data line to realize the low grayscale display image, so that the voltage coupled to the anode of the light-emitting element is compensated back by the compensation voltage provided by the compensation module, and if the time interval for the bias control signal line to transmit the enable signal to the control end of the bias adjustment module is set to B, then the moment B after the moment when the data line first jumps to the first data voltage is the starting moment when the compensation module transmits the compensation voltage to the data line, and the maintenance time A of the first data voltage to realize the low grayscale display image is the same as the maintenance time A of the compensation voltage, so that the compensation module can compensate the data voltage at the accurate position where the black block copy phenomenon occurs without changing the design structure of the panel itself and saving production costs, thereby ensuring the direct compensation effect of the compensation module on the data voltage on the data line, and effectively improving the display quality of the display panel when displaying low grayscale images. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0019] Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure of a pixel circuit and a light-emitting element;

[0020] Figure 3 yes Figure 1 A schematic diagram of the film structure of a first reset signal line, a data line and an anode of a light-emitting element in a partial area of ​​a sub-pixel region;

[0021] Figure 4 It is a schematic diagram of a situation in which a low-brightness picture displayed on a display panel is copied and displayed in the prior art;

[0022] Figure 5 It is a schematic diagram of the compensation timing of the compensation module of the display panel provided by the embodiment of the present invention for the data line transmission signal;

[0023] Figure 6yes Figure 1 A schematic diagram of another electrical connection structure of a pixel circuit and a light emitting element;

[0024] Figure 7 yes Figure 1 A schematic diagram of another electrical connection structure of a pixel circuit and a light emitting element;

[0025] Figure 8 yes Figure 7 A working timing diagram of a pixel circuit;

[0026] Fig. 9 is a schematic diagram of a planar structure of a display device provided by an embodiment of the present invention;

[0027] Fig.10 Schematic diagram of another planar structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0029] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0030] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure of a pixel circuit and a light-emitting element, a display panel 000 provided in this embodiment includes a plurality of electrically connected pixel circuits 10 and light-emitting elements 20; the pixel circuit 10 includes an electrically connected driving module 101, a first reset module 102, a data writing module 103 and a bias adjustment module 104;

[0031] The display panel 000 includes a plurality of first reset signal lines REF1, a plurality of data lines S, and a plurality of bias control signal lines SP1; a first end of a first reset module 102 is electrically connected to the first reset signal line REF1, and a second end of the first reset module 102 is electrically connected to an anode of a light emitting element 20; a control end of a bias regulating module 104 and a control end of the first reset module 102 are both electrically connected to the bias control signal line SP1, a first end of a data writing module 103 and a first end of the bias regulating module 104 are both electrically connected to a first end of a driving module 101, and a second end of the data writing module 103 is electrically connected to the data line S;

[0032] In the pixel circuit 10, in a direction perpendicular to the light emitting surface of the display panel 000, the first reset signal line REF1, the data line S, and the anode of the light emitting element 20 at least partially overlap;

[0033] It also includes a monitoring module 30 and a compensation module 40, both of which are electrically connected to the data line S;

[0034] In a frame display cycle of the display panel 000, a portion of the display area AA of the display panel 000 is a low grayscale picture. During the display time of the low grayscale picture, the data voltage value transmitted on the data line S jumps to the first data voltage Vdata1;

[0035] The monitoring module 30 detects that the first data voltage Vdata1 is maintained for a time period of A, and the compensation module 40 transmits a compensation voltage ΔV to the data line S, and the compensation voltage ΔV is maintained for a time period of A;

[0036] The time interval for the bias control signal line SP1 to transmit the enable signal Vsp1 to the control end of the bias adjustment module 104 is B, and the time interval between the starting time t1 when the data voltage value transmitted on the data line S jumps to the first data voltage Vdata1 and the starting time t2 when the compensation module 40 transmits the compensation voltage ΔV to the data line S is B.

[0037] Specifically, the display panel 000 provided in this embodiment may be an organic light-emitting display panel, or may be other display panels that control the driving module 101 in the pixel circuit 10 to provide a driving current so that the light-emitting element 20 emits light. The light-emitting element 20 in this embodiment may be an organic light-emitting diode, or in some other optional embodiments, the light-emitting element 20 may also be a micro light-emitting diode or a sub-millimeter light-emitting diode, which is not limited in this embodiment. This embodiment takes the display panel 000 as an organic light-emitting diode display panel as an example for illustration. Optionally, the display panel 000 in this embodiment may include a plurality of sub-pixels 00, and the light-emitting colors of the light-emitting elements 00 in the sub-pixels 00 of different colors may be different, thereby realizing color display of the display panel 000. Further optionally, the multiple sub-pixels 00 in this embodiment can be arranged in an array, that is, the multiple sub-pixels 00 are arranged along the first direction X to form sub-pixel rows, the multiple sub-pixel rows are arranged along the second direction Y, the multiple sub-pixels 00 are arranged along the second direction Y to form sub-pixel columns, and the multiple sub-pixel columns are arranged along the first direction X to form an array-arranged sub-pixel 00 structure; wherein the first direction X and the second direction Y can be understood as intersecting or being perpendicular to each other in a direction parallel to the plane where the display panel 000 is located. Or in some other optional embodiments, the multiple sub-pixels 00 can also be arranged in other ways, which is not limited in this embodiment. Figure 1 The arrangement of multiple sub-pixels 00 in an array is used as an example for illustration. The display panel 000 of this embodiment includes multiple electrically connected pixel circuits 10 and light-emitting elements 20, that is, one sub-pixel 00 may include an electrically connected pixel circuit 10 and a light-emitting element 20, and the pixel circuit 10 is used to control the light-emitting element 20 to emit light. Since the light-emitting element 20 in the organic light-emitting diode display panel can generally be an organic light-emitting diode, which is a current-driven element, it is necessary to set a corresponding pixel circuit 10 to provide a driving current for the light-emitting element 20 so that the light-emitting element 20 can emit light.

[0038] like Figure 1 As shown, in the layout structure of the display panel 000, it is generally necessary to set up multiple signal lines providing different types of driving signals. For example, the display panel 000 of this embodiment may at least include multiple first reset signal lines REF1, multiple data lines S and multiple bias control signal lines SP1, wherein the first reset signal line REF1 is used to provide the first reset signal Vref1 to the first reset module 102 of each sub-pixel 00 when the first reset module 102 is turned on, the data line S is used to provide the data voltage value Vdata to the data writing module 103 of each sub-pixel 00 when the data writing module 103 is turned on, and the bias control signal line SP1 is used to provide the bias control signal Vsp1 to the control end of the bias adjustment module 104 of each sub-pixel 00 to control whether the bias adjustment module 104 is turned on or not.

[0039] It is understandable that the types of signal lines included in the display panel 000 in this embodiment are only examples. In specific implementations, the signal lines provided in the display panel 000 include but are not limited to these, and may also include other driving signal lines, which are not described in detail in this embodiment.

[0040] like Figure 2As shown, the pixel circuit 10 of the present embodiment at least includes an electrically connected driving module 101, a first reset module 102, a data writing module 103 and a bias adjustment module 104; wherein, the first end of the first reset module 102 is electrically connected to the first reset signal line REF1, and the second end of the first reset module 102 is electrically connected to the anode of the light-emitting element 20. When the first reset module 102 is turned on, the first reset signal line REF1 is used to provide the first reset signal Vref1 to the first end of the first reset module 102 of each sub-pixel 00, and the second end of the first reset module 102 is electrically connected to the anode of the light-emitting element 20, that is, the first reset signal line REF1 is used to reset the anode of the light-emitting element 20 when the first reset module 102 is turned on, thereby improving the residual of the data signal of the previous frame, improving the afterimage phenomenon, and enhancing the display effect of the display panel 000. The control end of the bias adjustment module 104 and the control end of the first reset module 102 are both electrically connected to the bias control signal line SP1. The bias control signal Vsp1 provided by the bias control signal line SP1 can jointly control whether the first reset module 102 and the bias adjustment module 104 are turned on or off, which is beneficial to reduce the number of signal lines in the panel and simplify the panel design. The first end of the data writing module 103 and the first end of the bias regulating module 104 are both electrically connected to the first end of the driving module 101, and the second end of the data writing module 103 is electrically connected to the data line S. When the data writing module 103 is turned on, the data voltage value Vdata provided on the data line S at that moment can be written into the driving module 101. When the bias regulating module 104 is turned on under the control of the bias control signal Vsp1 provided by the bias control signal line SP1, the bias regulating module 104 can perform bias regulation on the driving module 101. For example, the second end of the bias regulating module 104 can be electrically connected to the bias regulation signal line DVH, and the bias regulation signal line DVH is used to provide a bias regulation signal Vbias. When the bias regulation module 104 is turned on, the bias regulation signal The bias adjustment signal Vbias provided by the line DVH is transmitted to the driving module 101 through the bias adjustment module 104. The driving module 101 generally includes a driving transistor DT. The bias adjustment signal Vbias can be used to adjust the bias state of the driving transistor DT, so that the driving transistor DT is reverse biased, and the first pole (i.e., the first end of the driving module 101) and the second pole (i.e., the second end of the driving module 101) of the driving transistor DT are reversed, so as to weaken the degree of ion polarization inside the driving transistor DT and reduce the threshold voltage of the driving transistor DT. The threshold voltage of the driving transistor DT is adjusted by biasing the driving transistor DT to compensate for the threshold voltage drift problem caused by the hysteresis effect of the driving transistor due to the forward bias state of the driving transistor DT.

[0041] It is understandable that this embodiment Figure 2The electrical connection structure of each pixel circuit 10 and the light-emitting element 20 in the display panel 000 is only illustrated by way of example. In a specific implementation, the pixel circuit 10 may also include other structures, such as a control module for threshold compensation, a control module for controlling the light emission of the light-emitting element 20, etc. This embodiment is not described in detail here. For details, please refer to the circuit structure of the organic light-emitting diode display panel in the related technology, or refer to the description of the subsequent embodiments for understanding.

[0042] like Figure 1 As shown, the layout structure of the display panel 000 of this embodiment may include at least a plurality of first reset signal lines REF1, a plurality of data lines S and a plurality of bias control signal lines SP1. The above signal lines may be made by using different conductive film layers in the film structure of the display panel 000. This embodiment does not limit the film layer positions of the above signal lines. For details, please refer to the film layer structure of the panel in the related art for understanding. Figure 1 As shown, in this embodiment, the overall extension direction of the first reset signal line REF1 (it can be understood that Figure 1 The direction of the signal line is only a schematic diagram. In actual production, the signal line in the panel is not necessarily a straight line, and may have certain bends and different thicknesses. The specific production is based on the panel film layer space) as the second direction Y, the overall extension direction of the data line S is the second direction Y, and the overall extension direction of the bias control signal line SP1 is the first direction X. Or in some other optional embodiments, the overall extension direction of the first reset signal line REF1 can also be the first direction X. In this embodiment, Figure 1 It is only an example. It is understandable that in order to clearly illustrate the electrical connection relationship between the pixel circuit and the signal line, Figure 1 The data line S, the first reset signal line REF1 and the light emitting element 20 in the embodiment do not overlap each other. However, in the actual film layer manufacturing of the panel, in order to minimize the layout space of the pixel circuit and the signal wiring, the structures of different conductive film layers will inevitably overlap to a certain extent. For details, please refer to the subsequent explanations for understanding. Figure 1 It is only for the purpose of clearly illustrating the electrical connection relationship between the pixel circuit and the signal line.

[0043] like Figure 1 and Figure 3 As shown, Figure 3 yes Figure 1Schematic diagram of the film structure of the first reset signal line, data line and anode of the light-emitting element in a sub-pixel area in a partial area. For the design structure of the area where the pixel circuit 10 of a sub-pixel 00 is located, in the direction Z perpendicular to the light-emitting surface of the display panel 000, the film structure of the display panel 000 may include a substrate 01, a transistor array layer 02, a pixel definition layer 03 and a light-emitting function layer 04. The substrate 01 serves as a carrier, and the transistor array layer is used to set the transistor structure included in each module in the pixel circuit 10. The light-emitting function layer 04 may include the anode 201, the light-emitting layer 202 and the cathode 203 of the light-emitting element 20. The opening 03K of the pixel definition layer 03 is used to set the light-emitting layer 202 of the light-emitting element 20. It can be understood that the film structure of the display panel 000 of this embodiment includes but is not limited to this Figure 3 The structure shown in the figure can be set according to the actual panel design during specific implementation. Figure 3 It is only for illustrating the position structure of the first reset signal line REF1, the data line S, and the anode 201 of the light emitting element 20 in the design area where a sub-pixel 00 is located. In this embodiment, for the design structure of the area where the pixel circuit 10 of a sub-pixel 00 is located, in the direction Z perpendicular to the light emitting surface of the display panel 000, the first reset signal line REF1, the data line S, and the anode 201 of the light emitting element 20 at least partially overlap.

[0044] When the pixel circuit 10 structure of the display panel 000 generally includes the above structure, when the display panel is driven to display, for example, when a low-brightness picture (such as a black block) is displayed in a part of the display area within a frame time, the data voltage value Vdata transmitted on the data line S in the same frame jumps to display the first data voltage of low brightness, and the bias control signal Vsp1 on the bias control signal line SP1 for controlling whether the first reset module 102 and the bias adjustment module 104 in the display panel 000 are turned on or off is provided by the gate drive circuit (not shown in the figure) cascaded in the frame area of ​​the display panel, and the shift registers in the gate drive circuit are cascaded, and are refreshed from the top to the bottom of the display panel in one frame time. Taking the new as an example, the waveforms of different sub-pixel rows in the same frame time are different, similar to the waveforms of the bias control signal Vsp1 of adjacent rows all moving forward, and the time period for the data voltage value transmitted on the data line S in a frame to jump to the first data voltage displaying low brightness is fixed. Therefore, there will inevitably be a time period in which the time when the data voltage value Vdata transmitted on the data line S jumps to the first data voltage displaying low brightness and the time when the bias control signal Vsp1 controls the first reset module 102 and the bias adjustment module 104 to be turned on (that is, the time when the bias control signal Vsp1 is the enable signal of the first reset module 102 and the bias adjustment module 104) coincides within the one frame time. Therefore, during the overlap time, because the first reset signal line REF1 and the data line S are arranged in the upper and lower film layers in the layout structure of the display panel 000, the first reset signal line REF1 and the data line S are easily coupled to each other. The low-potential first reset signal Vref1 (low-potential because it is necessary to reset the anode of the light-emitting element) provided by the first reset signal line REF1 is coupled to the data line S, so that the potential transmitted on the data line S decreases, and the anode 201 of the light-emitting element 20 passes through the data line S. Figure 3 As shown, the anode potential of the light-emitting element 20 will also be affected and lower, causing the actual light-emitting brightness of the light-emitting element 20 to be darker than the normal brightness it should emit, that is, the originally displayed low-brightness image (such as a black block) is copied in other display areas of the panel, such as Figure 4 As shown, Figure 4 The present invention is a schematic diagram of a situation in which a low-brightness image displayed by a display panel is duplicated in the prior art, resulting in an unexpected display effect and affecting the display quality.

[0045] like Figure 1-Figure 3 , Figure 5 As shown, Figure 51 is a timing diagram of compensation of the compensation module of the display panel provided by the embodiment of the present invention for the data line transmission signal. In order to solve the above technical problems, the display panel 000 provided by the present embodiment also includes a monitoring module 30 and a compensation module 40. The monitoring module 30 and the compensation module 40 are both electrically connected to the data line S. It should be noted that the structure of the monitoring module 30 and the compensation module 40 in the present embodiment is only an example. For example, the monitoring module 30 and the compensation module 40 can be set in the non-display area of ​​the display panel 000, such as the frame area, or can also be separately integrated in a circuit chip and bound to the panel, or can also be set to other structures. In specific implementation, the position and structure of the monitoring module 30 and the compensation module 40 include but are not limited to this, and can also be other settings. It is only necessary to ensure that the monitoring module 30 and the compensation module 40 are both electrically connected to the data line S. The monitoring module 30 of the present embodiment is used to detect the data voltage value Vdata transmitted on the data line S, and the compensation module 40 is used to compensate for the transmission signal on the data line S. Specifically, during a frame display cycle of the display panel 000, a portion of the display area AA of the display panel 000 is a low grayscale image, such as a portion of the display area AA is displayed as a black block image. During the display time of the low grayscale image, the data voltage value transmitted on the data line S jumps to the first data voltage Vdata1. The first data voltage Vdata1 is the data voltage value required for the low brightness display image. At this time, the monitoring module 30 detects that the maintenance time of the first data voltage Vdata1 is A, and the compensation module 40 transmits the compensation voltage ΔV (such as Figure 5 , it can be understood that the compensation voltage ΔV is not the timing of normal transmission on the data line S, but is compensated and superimposed on the data line S by the compensation module 40, so it is indicated by a dotted line. Since the monitoring module 30 detects that the maintenance time of the first data voltage Vdata1 is A, the compensation module 40 controls the maintenance time of the compensation voltage ΔV to be A, that is, the compensation module 40 controls the maintenance time of the compensation voltage ΔV to be the same as the maintenance time of the first data voltage Vdata1 detected by the monitoring module 30, so as to ensure the compensation module 40 has a data voltage compensation effect on the data line S. The starting time t2 when the compensation module 40 transmits the compensation voltage ΔV to the data line S is associated with the time interval when the bias control signal line SP1 transmits the enable signal Vsp1 to the control end of the bias adjustment module 104. Specifically, the time interval when the bias control signal line SP1 transmits the enable signal Vsp1 to the control end of the bias adjustment module 104 (the enable signal Vsp1 is the bias control signal Vsp1 that the bias control signal line SP1 controls the bias adjustment module 104 and the first reset module 102 to be turned on) is B, wherein, Figure 5SP1(1) in the figure represents the bias control signal line corresponding to the first sub-pixel row, and SP1(n) represents the bias control signal line corresponding to the last sub-pixel row. For the same sub-pixel row, the first conduction of the bias adjustment module 104 and the first reset module 102 is the first reset module 102 resetting the anode of the light-emitting element 20, and the bias adjustment module 104 performs the bias adjustment on the driving module 101 for the first time, and the second conduction is the second bias adjustment on the driving module 101 by the bias adjustment module 104. Therefore, the time interval between the two times is the time interval B for the bias control signal line SP1 to transmit the enable signal Vsp1 to the control end of the bias adjustment module 104. The time interval B is a known constant. In this embodiment, the compensation module 40 transmits the compensation voltage ΔV to the data line S. The starting time of the data line S can have the following relationship: the starting time t1 when the data voltage value transmitted on the data line S jumps to the first data voltage Vdata1 and the starting time t2 when the compensation module 40 transmits the compensation voltage ΔV to the data line S, and the time interval between the two is also B, that is, the time interval B between the moment when the data line S first jumps to the first data voltage Vdata1 is the starting time when the compensation module 40 transmits the compensation voltage ΔV to the data line S, so that the compensation module 40 can compensate the data voltage at the exact position where the black block copy phenomenon occurs, effectively improving the display quality of the display panel 000 when displaying low grayscale images.

[0046] Optionally, when the display panel 000 is driven, the first time the bias regulating module 104 and the first reset module 102 are turned on is when the first reset module 102 resets the anode of the light emitting element 20, and the bias regulating module 104 performs bias regulation on the driving module 101 for the first time. At this time, the bias control signal line SP1 transmits the enable signal Vsp1 to the control end of the bias regulating module 104, which can be selected as 2 pulses (such as Figure 5 As shown) or multiple pulses, high-precision frequency conversion can be achieved. The second conduction of the bias adjustment module 104 and the first reset module 102 only needs to ensure that the bias adjustment module 104 is always open, and the bias adjustment signal Vbias provided by the bias adjustment signal line DVH can be transmitted to the driving module 101 through the bias adjustment module 104 to adjust the bias state of the driving transistor DT. Therefore, the bias control signal line SP1 at this time transmits the enable signal Vsp1 to the control end of the bias adjustment module 104, which can be selected as 1 pulse.

[0047] The display panel 000 provided in this embodiment is provided with a data line S which is electrically connected to the monitoring module 30 and the compensation module 40 respectively. When a low grayscale image is displayed in a partial display area of ​​the display panel 000, the monitoring module 30 monitors the jump of the first data voltage Vdata1 transmitted on the data line S for realizing the low grayscale display image, so that the voltage coupled to the anode 201 of the light-emitting element 20 is compensated back by the compensation voltage ΔV provided by the compensation module 40, and it is set that if the time interval of the bias control signal line SP1 transmitting the enable signal Vsp1 to the control end of the bias adjustment module 104 is B, the first data voltage Vdata1 on the data line S is increased. The moment B after the first jump to the first data voltage Vdata1 is the starting moment when the compensation module 40 transmits the compensation voltage ΔV to the data line S, and the maintenance time of the first data voltage Vdata1 for realizing the low grayscale display image is the same as the maintenance time of the compensation voltage ΔV. Therefore, there is no need to change the design structure of the panel itself, saving production costs, while realizing that the compensation module 40 compensates for the data voltage at the exact position where the black block copy phenomenon occurs, ensuring the direct compensation effect of the compensation module 40 on the data voltage on the data line S, and effectively improving the display quality of the display panel 000 when displaying low grayscale images.

[0048] In some optional embodiments, please refer to Figure 1-Figure 5 and Figure 6 , Figure 6 yes Figure 1 Another schematic diagram of the electrical connection structure of the pixel circuit and the light-emitting element, in this embodiment, the pixel circuit 10 further includes a first light-emitting control module 105, a second light-emitting control module 106, a threshold compensation module 107, and a second reset module 108;

[0049] A first end of the second reset module 108 is electrically connected to the second reset signal line REF2, a second end of the second reset module 108 is electrically connected to the control end of the driving module 101, and a control end of the second reset module 108 is electrically connected to the first scan signal line SN1;

[0050] A first end of the threshold compensation module 107 is electrically connected to the control end of the driving module 101, a second end of the threshold compensation module 107 is electrically connected to the second end of the driving module 101, and a control end of the threshold compensation module 107 is connected to the second scanning signal line SN2;

[0051] A first end of the first light emitting control module 105 is electrically connected to the first power signal line PVDD, a second end of the first light emitting control module 105 is electrically connected to the first end of the driving module 101, a first end of the second light emitting control module 106 is electrically connected to the second end of the driving module 101, a second end of the second light emitting control module 106 is electrically connected to the anode of the light emitting element 20, a cathode of the light emitting element 20 is electrically connected to the second power signal line PVEE, and a control end of the first light emitting control module 105 and a control end of the second light emitting control module 106 are electrically connected to a light emitting control signal line EM;

[0052] The control end of the data writing module 103 is electrically connected to the third scanning signal line SP;

[0053] A second terminal of the bias regulation module 104 is electrically connected to the bias regulation signal line DVH.

[0054] This embodiment explains the electrical connection relationship of the module structure that the pixel circuit 10 in the sub-pixel 00 of the display panel 000 may specifically include. In this embodiment, the driving transistor DT is electrically connected to the data writing module 103, the threshold compensation module 107 and the bias adjustment module 104, and the first electrode of the driving transistor DT is electrically connected to the data writing module 103 and the bias adjustment module 104 respectively. The driving transistor DT is used to generate a driving current, wherein the first electrode of the driving transistor DT can be understood as the source of the driving transistor DT, and the second electrode of the driving transistor DT can be understood as the drain of the driving transistor DT, or the first electrode of the driving transistor DT can be understood as the drain of the driving transistor DT, and the second electrode of the driving transistor DT can be understood as the source of the driving transistor DT, and this embodiment does not limit this. The second end of the data writing module 103 is electrically connected to the data line S. The data writing module 103 is turned on under the control of the third scanning signal Vsp provided by the third scanning signal line SP, and the data voltage value Vdata is transmitted to the second end of the data writing module 103 through the data line S. The first end of the data writing module 103 is electrically connected to the first electrode of the driving transistor DT. The data writing module 103 is used to provide the data voltage value Vdata to the driving transistor DT. The threshold compensation module 107 is connected between the gate of the driving transistor DT and the second electrode of the driving transistor DT. The threshold compensation module 107 is provided by the second scanning signal V SN2The threshold compensation module 107 is used to detect and compensate for the deviation of the threshold voltage of the driving transistor DT, and provide the deviation of the compensated threshold voltage and the data signal provided by the data line S to the driving transistor DT to achieve threshold compensation for the driving transistor DT. The threshold compensation module 107 provided in this embodiment can improve the display unevenness caused by the difference in the threshold voltage of the driving transistor DT caused by the manufacturing process and the threshold voltage drift of the driving transistor DT caused by transistor aging. The second reset module 108 is provided on the first scanning signal line SN1. SN1 The second reset signal line REF2 is turned on under control, and the second reset signal Vref2 provided by the second reset signal line REF2 can reset the gate of the driving transistor DT (ie, the N1 node) and refresh the gate potential of the driving transistor DT in the previous frame.

[0055] When the light emitting element 20 emits light, the first light emitting control module 105 and the second light emitting control module 106 provide a light emitting control signal V through the light emitting control signal line EM. EM A conductive path is formed among the first power signal line PVDD, the first light-emitting control module 105, the driving transistor DT, the second light-emitting control module 106, the light-emitting element 20, and the second power signal line PVEE, and a driving current is provided to the light-emitting element 20 to control the light-emitting element 20 to emit light.

[0056] Optional, such as Figure 6 and Figure 7 As shown, Figure 7 yes Figure 1A schematic diagram of another electrical connection structure of a pixel circuit and a light-emitting element, wherein a driving module 101 includes a driving transistor DT, a first reset module 102 includes a first transistor M1, a data writing module 103 includes a second transistor M2, a bias adjustment module 104 includes a third transistor M3, a first light-emitting control module 105 includes a fourth transistor M4, a second light-emitting control module 106 includes a fifth transistor M5, a threshold compensation module 107 includes a sixth transistor M6, and a second reset module 108 includes a seventh transistor M7, wherein, further optionally, the second reset module 108 and the threshold compensation module 107 include metal oxide transistors, that is, the sixth transistor M6 and the seventh transistor M7 are metal oxide transistors, such as N-type metal oxide transistors. The driving module 101, the first reset module 102, the data writing module 103, the bias regulating module 104, the first light-emitting control module 105 and the second light-emitting control module 106 respectively include low-temperature polysilicon transistors, that is, the driving transistor DT, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are all low-temperature polysilicon transistors, such as P-type low-temperature polysilicon transistors. In this embodiment, the sixth transistor M6 and the seventh transistor M7 connected to the control end of the driving module 101, that is, the gate of the driving transistor DT are N-type metal oxide transistors, and the remaining first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the driving transistor DT are all P-type low-temperature polysilicon transistors. Since the metal oxide transistor has a low leakage current in the off state, the influence of the leakage current on the gate potential of the driving transistor DT can be reduced, thereby stabilizing the gate voltage of the driving transistor DT, improving the working stability of the driving transistor DT, and then ensuring the stability of the driving current, which is conducive to enabling the display panel 000 of this embodiment to ensure the uniformity of the light-emitting brightness of the light-emitting element 20. In particular, when the display panel 000 realizes low-frequency driving display, the display time of a frame is long, so the time that the potential of the driving transistor DT needs to be maintained is also long. If the transistor connected to the gate of the driving transistor DT is a low-temperature polysilicon transistor, it is easy to cause obvious flickering by the leakage of the transistor connected to the gate of the driving transistor DT due to the large off-state leakage of the low-temperature polysilicon transistor. Therefore, this embodiment sets the sixth transistor M6 and the seventh transistor M7 as N-type metal oxide transistors, and utilizes their small off-state leakage characteristics, so that the potential of the gate of the driving transistor DT can be maintained for a long time when the display panel 000 realizes low-frequency driving display, thereby improving the flickering phenomenon during low-frequency driving and improving the display effect.

[0057] Further optionally, the pixel circuit 10 also includes a storage capacitor C, one end of the storage capacitor C is connected to the first power signal line PVDD, and the other end of the storage capacitor C is connected to the gate of the driving transistor DT. The storage capacitor C is used to stabilize the potential of the gate of the driving transistor DT, which is beneficial for the driving transistor DT to remain turned on.

[0058] In some optional embodiments, please refer to Figure 7 and Figure 8 , Figure 8 yes Figure 7 A working timing diagram of the pixel circuit in the embodiment, in the sub-pixel 00 provided in this embodiment, the working process of the pixel circuit 10 at least includes a first bias adjustment stage T1, a reset stage T2, a threshold compensation and data writing stage T3, a second bias adjustment stage T4, and a light emitting stage T5;

[0059] In the first bias regulation stage T1, that is, before resetting the gate of the driving transistor DT, the bias control signal line SP1 is fed with a low level bias control signal Vsp1 to control the third transistor M3 of the bias regulation module 104 to turn on, and the second scanning signal line SN2 is fed with a high level second scanning signal V SN2When the sixth transistor M6 of the control threshold compensation module 107 is turned on, the bias adjustment signal Vbias provided by the bias adjustment signal line DVH is transmitted to the gate (i.e., the N1 node) of the driving transistor DT through the third transistor M3 and the sixth transistor M6, and the bias state of the driving transistor DT is adjusted for the first time, so that the driving transistor DT is reverse biased, the first pole and the second pole of the driving transistor DT are reversed, the degree of ion polarization inside the driving transistor DT is weakened, and the threshold voltage of the driving transistor DT is reduced. The threshold voltage of the driving transistor DT is adjusted by biasing the driving transistor DT to compensate for the threshold voltage drift problem caused by the hysteresis effect of the driving transistor due to the forward bias state of the driving transistor DT. Optionally, the bias adjustment signal Vbias can be a DC positive voltage signal. Since the bias adjustment signal Vbias is a relatively high positive voltage value, that is, no matter what the picture displayed in the previous frame is, before resetting the gate of the driving transistor DT and writing the current picture, the driving transistor DT needs to undergo a writing of the bias adjustment signal Vbias, so that the sub-pixel 00 experiences a same writing of the bias adjustment signal Vbias before resetting the gate of the driving transistor DT, and the written bias adjustment signal Vbias is a relatively high positive voltage value, so that a larger instantaneous current can flow through the driving transistor DT. This current can adjust the bias defect problem inside the driving transistor DT, and can improve the hysteresis characteristics of the driving transistor DT, thereby reducing the bias effect of the previous frame display picture, so that the state of the driving transistor DT when writing the current display picture is closer to the preset state, thereby reducing the bias difference of the driving transistor DT when the current frame and the previous frame display pictures are displayed, improving the threshold drift problem of the driving transistor DT, and enhancing the display effect.

[0060] At this time, the bias control signal line SP1 inputs a low-level bias control signal Vsp1, which can also control the first transistor M1 of the first reset module 102 to be turned on. The first reset signal line REF1 provides a first reset signal Vref1 which resets the anode of the light-emitting element 20 through the first transistor M1, so that the anode of the light-emitting element 20 is initialized, thereby improving the residual data signal of the previous frame, improving the afterimage phenomenon, and enhancing the display effect of the display panel 000.

[0061] In the reset phase T2, the first scanning signal line SN1 is fed with a high-level first scanning signal V SN1 The seventh transistor M7 of the second reset module 108 is controlled to be turned on, and the second reset signal Vref2 provided by the second reset signal line REF2 resets the gate of the driving transistor DT (ie, the N1 node), and refreshes the gate potential of the driving transistor DT in the previous frame.

[0062] It can be understood that, in a part of the time period of the reset phase T2, the first scanning signal line SN1 is fed with a high-level first scanning signal V SN1 The second scanning signal line SN2 is fed with a high level second scanning signal V SN2 The time overlap is beneficial to improving the hysteresis problem of the driving transistor DT during the reset phase T2.

[0063] In the threshold compensation and data writing stage T3, the third scanning signal line SP is fed with a low-level third scanning signal Vsp to control the second transistor M2 of the data writing module 103 to be turned on, and the second scanning signal line SN2 is fed with a high-level second scanning signal V SN2 The sixth transistor M6 of the threshold compensation module 107 is controlled to be turned on, and the threshold-compensated data voltage value Vdata provided by the data line S is transmitted to the gate of the driving transistor DT through the second transistor M2, the driving transistor DT, and the sixth transistor M6, so as to perform threshold compensation on the driving transistor DT and self-compensate for the deviation of the threshold voltage of the driving transistor DT.

[0064] In the second bias adjustment stage T4, the bias control signal line SP1 inputs a low-level bias control signal Vsp1 to control the third transistor M3 of the bias adjustment module 104 to turn on, and the bias adjustment signal Vbias provided by the bias adjustment signal line DVH is transmitted to the first electrode (i.e., the N2 node) of the driving transistor DT through the third transistor M3, thereby adjusting the bias state of the driving transistor DT for the second time.

[0065] In the light-emitting stage T4, the light-emitting control signal line EM is fed with a low-level light-emitting control signal V EM The fourth transistor M4 of the first light-emitting control module 105 is controlled to be turned on, the fifth transistor M5 of the second light-emitting control module 106 is turned on, the driving transistor DT generates a driving current under the control of its gate voltage, and a conductive path is formed among the first power signal line PVDD, the fourth transistor M4, the driving transistor DT, the fifth transistor M5, the light-emitting element 20, and the second power signal line PVEE. The driving current is provided to the light-emitting element 20 to control the light-emitting element 20 to emit light.

[0066] It should be noted that, in specific implementation, the connection structure of the pixel circuit 10 of this embodiment includes but is not limited to the above structure and driving sequence, and may also be other connection structures and driving methods, which are not limited in this embodiment.

[0067] In some optional embodiments, please continue to refer to Figure 1-Figure 5 In this embodiment, the value of the first reset signal Vref1 transmitted by the first reset signal line REF1 is inversely proportional to the value of the compensation voltage ΔV.

[0068] This embodiment explains that since the first reset signal line REF1 and the data line S in the layout structure of the display panel 000 are arranged in the upper and lower film layers, the first reset signal line REF1 and the data line S are prone to signal coupling. The low-potential first reset signal Vref1 provided by the first reset signal line REF1 is coupled to the data line S, causing the potential transmitted on the data line S to decrease. The anode 201 of the light-emitting element 20 will pass under the data line S, and the anode potential of the light-emitting element 20 will also be affected and lower, causing the actual light-emitting brightness of the light-emitting element 20 to be darker than the brightness it should normally emit, affecting the display quality. Therefore, the compensation module 40 set in this embodiment directly compensates the data voltage on the data line S. The size of the compensation voltage ΔV is related to the degree of coupling. The greater the signal coupling degree, the larger the compensation value needs to be, and the smaller the coupling degree, the smaller the compensation value. The degree of signal coupling is affected by the low-potential first reset signal Vref1 provided by the first reset signal line REF1. The lower the low-potential first reset signal Vref1 provided by the first reset signal line REF1, the more strongly the data line S of the upper and lower film layers is coupled, so that the potential transmitted on the data line S drops more. The data line S will pass under the anode of the light-emitting element 20, so the anode potential of the light-emitting element 20 is also affected and is lower. When the compensation module 40 does not make compensation, the luminous brightness of the light-emitting element 20 is dimmer than the normal brightness. Therefore, when the monitoring module 30 is provided in this embodiment to monitor the jump of the first data voltage Vdata1 transmitted on the data line S to realize the low grayscale display screen, so that the voltage coupled to the anode 201 of the light-emitting element 20 is compensated back by the compensation voltage ΔV provided by the compensation module 40, the value of the compensation voltage ΔV that the compensation module 40 needs to provide is also larger. Therefore, in this embodiment, the value of the first reset signal Vref1 transmitted by the first reset signal line REF1 is inversely proportional to the value of the compensation voltage ΔV. The lower the low-potential first reset signal Vref1 provided by the first reset signal line REF1, the larger the value of the compensation voltage ΔV that the compensation module 40 needs to provide. The higher the low-potential first reset signal Vref1 provided by the first reset signal line REF1, the smaller the value of the compensation voltage ΔV that the compensation module 40 needs to provide. This allows the compensation module 40 to compensate for the data voltage with higher accuracy at the exact location where the black block copy phenomenon occurs, thereby ensuring the direct compensation effect of the compensation module 40 on the data voltage on the data line S, and effectively improving the display quality of the display panel 000 when displaying low grayscale images.

[0069] In some optional embodiments, please continue to refer to Figure 1-Figure 5In this embodiment, during the maintenance time A of the compensation voltage ΔV, before the compensation module 40 transmits the compensation voltage ΔV to the data line S, the data voltage value Vdata originally transmitted on the data line S is the second data voltage Vdata2, and the second data voltage Vdata2 is less than the first data voltage Vdata1.

[0070] This embodiment explains that within a frame display cycle of the display panel 000, a part of the display area AA of the display panel 000 is a low grayscale image, such as a part of the display area AA is displayed as a black block image. During the display time of the low grayscale image, the data voltage value transmitted on the data line S jumps to the first data voltage Vdata1, and the first data voltage Vdata1 is the data voltage value required for the low-brightness display image. During the maintenance time A of the compensation voltage ΔV, before the compensation module 40 transmits the compensation voltage ΔV to the data line S, that is, during the scanning period in the prior art when black block copying is prone to occur under a frame of image scanning, the data voltage value Vdata originally transmitted on the data line S is the second data voltage Vdata2, and the second data voltage Vdata2 is less than the first data voltage Vdata1, that is, the second data voltage Vdata2 is a data voltage that does not jump, thereby enabling the remaining area of ​​the low grayscale display image to be a non-black block display area of ​​the same brightness.

[0071] Optionally, within the maintenance time A of the compensation voltage ΔV, after the compensation module 40 transmits the compensation voltage ΔV to the data line S, the compensation voltage ΔV is superimposed on the data voltage value originally transmitted on the data line S to form a third data voltage Vdata3, and the third data voltage Vdata3 is less than the second data voltage Vdata2, that is, if the first data voltage Vdata1 is a data voltage value required for a low-brightness display image to be a high level, then within the maintenance time A of the compensation voltage ΔV, before the compensation module 40 transmits the compensation voltage ΔV to the data line S, that is, during the scanning period in the prior art when black block copying is prone to occur under a frame of image scanning, the second data voltage Vdata2 originally transmitted on the data line S is a very small level or 0, or a voltage value approximately equal to 0, then after the compensation module 40 transmits the compensation voltage ΔV to the data line S, the compensation voltage ΔV is superimposed on the data voltage value originally transmitted on the data line S. The third data voltage Vdata3 is superimposed, and the third data voltage Vdata3 is a smaller voltage value after a compensation voltage ΔV is superimposed on the second data voltage Vdata2. If the first data voltage Vdata1 is a high level data voltage value required for low-brightness display of the picture, and the scanning period during which black block copying is prone to occur under the scanning of the previous frame is not compensated, the second data voltage Vdata2 originally transmitted on the data line S is a very small level or 0, or a voltage value approximately equal to 0, then after the compensation voltage ΔV is superimposed on the second data voltage Vdata2, the third data voltage Vdata3 transmitted on the data line S at this time is a low level, which is equivalent to the compensation voltage ΔV directly lowering the transmission signal value on the data line S, thereby ensuring that the luminous brightness of the area where black block copying may originally occur is improved, and the brightness will not be darker than the normal brightness due to signal coupling.

[0072] In some optional embodiments, please refer to Figure 1-Figure 8 and Fig. 9 , Fig. 9: is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. The display device 111 may be a mobile phone, or may be a computer, a television, a car display device or other display device 111 with a display function, and the present invention does not specifically limit this. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention. For details, reference may be made to the specific description of the display panel 000 in the above embodiments, and this embodiment will not be repeated here. The display device 111 of this embodiment includes a driver circuit board IC and the display panel 000 of the above embodiment. The driver circuit board IC is electrically connected to the display panel 000. The driver circuit board IC may be a display driver chip (Display Driver Integrated Circuit, DDIC). The driver circuit board IC is mainly used to control the display panel 000, drive the display panel 000 through an electrical signal, transmit video data, cooperate with the display panel 000 to achieve lightness, flexibility and foldability, and provide a wide color gamut and high-fidelity display signal.

[0073] Optionally, the driver circuit board IC is electrically connected to the display panel 000 by binding with a flexible circuit board. It is understandable that the present embodiment does not limit the electrical connection method between the driver circuit board IC and the display panel 000, and the specific understanding can be made by referring to the binding method between the driver circuit board IC and the display panel 000 in the related art. It is understandable that the final structure of the display device 111 can be a structure in which the driver circuit board IC is located on the backlight side of the display panel 000 by bending the flexible circuit board, thereby minimizing the overall size of the display device 111 and avoiding the driver circuit board IC from occupying the space of the device.

[0074] Optional, such as Figure 1-Figure 5 , Fig.10 As shown, Fig.10: is another schematic diagram of the planar structure of the display device provided by an embodiment of the present invention. The monitoring module 30 and the compensation module 40 electrically connected to the data line S in this embodiment can be integrated into the driving circuit board IC; the driving circuit board IC controls the compensation module 40 to transmit the compensation voltage ΔV to the data line S to maintain the time A, and the driving circuit board IC controls the time interval B between the starting time t1 when the data voltage value transmitted on the data line S jumps to the first data voltage Vdata1 and the starting time t2 when the compensation module 40 transmits the compensation voltage ΔV to the data line S. By integrating the monitoring module 30 and the compensation module 40 electrically connected to the data line S into the driving circuit board IC, the frame layout space of the display panel 000 can be saved, which is conducive to realizing the narrow frame design of the panel, and the monitoring module 30 and the compensation module 40 can also work better with the driving circuit board IC to achieve the direct compensation effect of the data voltage on the data line S.

[0075] Optionally, the driving circuit board IC in this embodiment is electrically connected to the data line S. Specifically, a data signal output pin may be provided on the driving circuit board IC, and a data voltage value is provided for the data line S in the display panel 000 through the driving circuit board IC. The driving circuit board IC is electrically connected to the data line S, and the data voltage on the data line S is completely provided by the output of the driving circuit board IC. Therefore, the monitoring module 30 in the driving circuit board IC can identify the maintenance time A of the data voltage value on the data line S jumping to the first data voltage Vdata1, thereby ensuring the compensation effect of the compensation module 40 on the data voltage value on the data line S, thereby improving the display quality.

[0076] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0077] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: It comprises a plurality of electrically connected pixel circuits and light-emitting elements; the pixel circuit comprises an electrically connected driving module, a first reset module, a data writing module and a bias voltage regulating module; The display panel includes a plurality of first reset signal lines, a plurality of data lines and a plurality of bias control signal lines; a first end of the first reset module is electrically connected to the first reset signal line, and a second end of the first reset module is electrically connected to the anode of the light-emitting element; a control end of the bias adjustment module and a control end of the first reset module are both electrically connected to the bias control signal line, a first end of the data writing module and a first end of the bias adjustment module are both electrically connected to the first end of the driving module, and a second end of the data writing module is electrically connected to the data line; In the pixel circuit, in a direction perpendicular to the light emitting surface of the display panel, the first reset signal line, the data line, and the anode of the light emitting element at least partially overlap; It also includes a monitoring module and a compensation module, wherein the monitoring module and the compensation module are both electrically connected to the data line; In a frame display cycle of the display panel, part of the display area of ​​the display panel is a low grayscale picture, and during the display time of the low grayscale picture, the data voltage value transmitted on the data line jumps to the first data voltage; The monitoring module detects that the maintenance time of the first data voltage is A, then the compensation module transmits a compensation voltage to the data line, and the maintenance time of the compensation voltage is A; The time interval for the bias control signal line to transmit the enable signal to the control end of the bias adjustment module is B, and the time interval between the starting moment when the data voltage value transmitted on the data line jumps to the first data voltage and the starting moment when the compensation module transmits the compensation voltage to the data line is B.

2. The display panel according to claim 1, characterized in that: The pixel circuit further includes a first light emitting control module, a second light emitting control module, a threshold compensation module, and a second reset module; The first end of the second reset module is electrically connected to the second reset signal line, the second end of the second reset module is electrically connected to the control end of the driving module, and the control end of the second reset module is electrically connected to the first scan signal line; The first end of the threshold compensation module is electrically connected to the control end of the driving module, the second end of the threshold compensation module is electrically connected to the second end of the driving module, and the control end of the threshold compensation module is connected to the second scanning signal line; The first end of the first light-emitting control module is electrically connected to the first power signal line, the second end of the first light-emitting control module is electrically connected to the first end of the driving module, the first end of the second light-emitting control module is electrically connected to the second end of the driving module, the second end of the second light-emitting control module is electrically connected to the anode of the light-emitting element, the cathode of the light-emitting element is electrically connected to the second power signal line, and the control end of the first light-emitting control module and the control end of the second light-emitting control module are electrically connected to the light-emitting control signal line; The control end of the data writing module is electrically connected to the third scanning signal line; The second end of the bias regulation module is electrically connected to the bias regulation signal line.

3. The display panel according to claim 2, characterized in that: The second reset module and the threshold compensation module include metal oxide transistors.

4. The display panel according to claim 2, characterized in that: The driving module, the first resetting module, the data writing module, the bias regulating module, the first light emitting control module and the second light emitting control module respectively include low temperature polysilicon transistors.

5. The display panel according to claim 1, characterized in that: The value of the first reset signal transmitted by the first reset signal line is in inverse proportion to the value of the compensation voltage.

6. The display panel according to claim 1, characterized in that: During the maintenance time A of the compensation voltage, before the compensation module transmits the compensation voltage to the data line, the data voltage value originally transmitted on the data line is a second data voltage, and the second data voltage is less than the first data voltage.

7. The display panel according to claim 6, characterized in that: During the maintenance time A of the compensation voltage, after the compensation module transmits the compensation voltage to the data line, the compensation voltage is superimposed on the data voltage value originally transmitted on the data line to form a third data voltage, and the third data voltage is less than the second data voltage.

8. A display device, characterized in that: It comprises a driving circuit board and the display panel according to any one of claims 1 to 7, wherein the driving circuit board is electrically connected to the display panel.

9. According to the display device of claim 8, the monitoring module and the compensation module are integrated in the driving circuit board; the driving circuit board controls the maintenance time of the compensation module transmitting the compensation voltage to the data line, and the driving circuit board controls the time interval between the starting moment when the data voltage value transmitted on the data line jumps to the first data voltage and the starting moment when the compensation module transmits the compensation voltage to the data line. 10 . The display device according to claim 9 , wherein the driving circuit board is electrically connected to the data line.

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