A kind of incorporation in-signal conversion circuit and digital microfluidic chip

Abstract

This application discloses a parallel-in serial-out signal conversion circuit, relating to the field of digital microfluidics technology, and in particular, a parallel-in serial-out signal conversion circuit and a digital microfluidic chip, which are applied in a digital microfluidic chip. The circuit includes: a driver terminal, a first clock terminal, a second clock terminal, an output terminal, a parallel-in selection module, and a register output module. The register output module is connected to the parallel-in selection module, the driver terminal, the second clock terminal, and the output terminal, respectively. The driver terminal is used to connect to the driving voltage. It inherits the excellent performance of traditional GOA circuits and expands their functions, possessing a preset function that can load data into registers in parallel. All preset terminals transmit data simultaneously, resulting in a high data transfer rate.

Description

Technical Field

[0001] This application relates to the field of digital microfluidics technology, and in particular to a parallel-input serial-output signal conversion circuit and a digital microfluidics chip. Background Technology

[0002] In existing technologies, GOA (Gate Driver on Array) can be used to implement the line-by-line scanning driving function of liquid crystal panels. In traditional active matrix liquid crystal displays, the line scanning signal is implemented by an external integrated circuit. However, by using a GOA circuit, the integrated circuits related to scanning drive are saved, thereby reducing the manufacturing cost of the liquid crystal display. The GOA circuit has two basic functions: first, it outputs the gate scan drive signal to drive the gate lines in the panel, turning on the TFTs in the display area to charge the pixels; second, it has a shift register function, where after one gate scan drive signal is output, the next gate scan drive signal is output through clock control, and so on.

[0003] However, existing GOA circuits cannot implement preset data functions, which limits their use in microfluidic chips. They cannot load data into registers in parallel, resulting in low transmission efficiency. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a signal conversion circuit that can load data into registers in parallel and has high transmission efficiency.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] According to one aspect of the present invention, a parallel-in serial-out signal conversion circuit is provided, applied in a digital microfluidic chip, comprising: a driving terminal, a first clock terminal, a second clock terminal, an output terminal, a parallel-in selection module, and a register output module; the register output module is connected to the parallel-in selection module, the driving terminal, the second clock terminal, and the output terminal respectively; the driving terminal is used to receive a driving voltage; the first clock terminal is used to receive a first clock signal; the second clock terminal is used to receive a second clock signal; the parallel-in selection module includes an input terminal, an enable terminal, and a preset terminal, and further includes a first transistor, a second transistor, a third transistor, and a sixth transistor; the drain of the first transistor is connected to the input terminal, the drain of the second transistor is connected to the preset terminal, the control electrode of the second transistor is connected to the enable terminal, and the drain and control electrode of the third transistor are connected to the driving terminal.

[0007] Specifically, the selection module also includes a fourth transistor; the drain of the fourth transistor is connected to the source of the third transistor and the control electrode of the first transistor; the control electrode of the fourth transistor is connected to the enable terminal; the source of the sixth transistor is individually connected to the register output module; and the source of the fourth transistor is grounded.

[0008] More specifically, the sources of the first and second transistors are connected to the drain of the sixth transistor; the control electrode of the first transistor is connected to the drain of the fourth transistor.

[0009] The above-mentioned register output module includes a register capacitor; the first end of the register capacitor is connected to the source of the sixth transistor, and the second end of the register capacitor is connected to the output terminal.

[0010] Furthermore, the register output module also includes a fifth transistor, a seventh transistor, and a tenth transistor; the control electrode and drain of the fifth transistor are connected to the drive terminal; the source of the fifth transistor is connected to the drain of the tenth transistor; the drain of the seventh transistor is connected to the second clock terminal; the control electrode of the tenth transistor is connected to the source of the sixth transistor; and the source of the tenth transistor is grounded.

[0011] Furthermore, the register output module also includes a ninth transistor and an eleventh transistor; the control electrode of the eleventh transistor is connected to the drain of the tenth transistor; the drain of the eleventh transistor is connected to the control electrode of the ninth transistor and the control electrode of the seventh transistor.

[0012] Furthermore, the sources of the tenth, eleventh, and ninth transistors are grounded; the drain of the ninth transistor and the source of the seventh transistor are connected to the second terminal of the register capacitor.

[0013] The above also includes a reset module; the reset module is connected to the register output module, and the reset module is equipped with a reset signal receiving terminal.

[0014] Furthermore, the reset module includes an eighth transistor; the control electrode of the eighth transistor is connected to the reset signal receiving terminal; the drain of the eighth transistor is connected to the second terminal of the register capacitor.

[0015] According to another aspect of the present invention, a digital microfluidic chip is provided, which includes a plurality of parallel-in serial-out units, wherein the parallel-in serial-out units include the above-described parallel-in serial-out signal conversion circuit.

[0016] The beneficial effects of the present invention are as follows: The parallel input-serial output signal conversion circuit of this application inherits the excellent performance of the traditional GOA circuit and expands its functions. It has a preset function, which can put data into the register in parallel; each preset terminal transmits at the same time, the data transmission rate is high, the transmission speed is fast, and the signal width range of parallel transmission is larger, with low requirements on the format of the transmitted signal. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a parallel-in serial-out signal conversion circuit according to an embodiment of this application;

[0019] Figure 2 This application describes the signal source setup and output waveform of a parallel-to-serial signal conversion circuit according to an embodiment of the present application. Figure 1 ;

[0020] Figure 3 This application describes the signal source setup and output waveform of a parallel-to-serial signal conversion circuit according to an embodiment of the present application. Figure 2 ;

[0021] Figure 4 This is a schematic diagram of the parallel-in serial-out unit according to an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of a five-stage cascaded circuit with parallel input and serial output according to an embodiment of this application;

[0023] Figure 6 This is a waveform diagram of the cascaded circuit signal source according to an embodiment of this application;

[0024] Figure 7 This is a waveform diagram of the preset terminal and serial output of the cascaded circuit in an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0027] In the description of this invention, unless otherwise explicitly defined, terms such as "setup" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0028] In the description of this invention, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0029] Example 1

[0030] like Figure 1 and Figure 4 As shown, a parallel-in serial-out signal conversion circuit is built into the parallel-in serial-out unit and applied in a digital microfluidic chip. The parallel-in serial-out signal conversion circuit includes: a driver terminal, a first clock terminal, a second clock terminal, an output terminal, a parallel selection module, a register output module, and a reset module.

[0031] The register output module is connected to the parallel selection module, the reset module, the driver terminal, the second clock terminal, and the output terminal, respectively.

[0032] The driver terminal is used to connect the driver signal VDD; the first clock terminal is used to connect the first clock signal CK; the second clock terminal is used to connect the second clock signal XCK; and the output terminal is used to output the output signal OUT.

[0033] The reset module is connected to the register output module, and the reset module is equipped with a reset signal receiving terminal for receiving the reset signal RESET.

[0034] The parallel selection module includes an input terminal, an enable terminal, and a preset terminal. It also includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a sixth transistor M6. The drain of the first transistor M1 is connected to the input terminal; the drain of the second transistor M2 is connected to the preset terminal; the control electrode of the second transistor M2 is connected to the enable terminal; the drain and control electrode of the third transistor M3 are connected to the drive terminal. The drain of the fourth transistor M4 is connected to the source of the third transistor M3 and the control electrode of the first transistor M1; the control electrode of the fourth transistor M4 is connected to the enable terminal; the source of the sixth transistor M6 is individually connected to the register output module; and the source of the fourth transistor M4 is grounded. The sources of the first transistor M1 and the second transistor M2 are connected to the drain of the sixth transistor M6; and the control electrode of the first transistor M1 is connected to the drain of the fourth transistor M4.

[0035] The input terminal is used to receive the input signal IN, the enable terminal is used to receive the enable signal EN, and the preset terminal is used to receive the preset signal SET.

[0036] Specifically, the register output module includes a register capacitor C1; the first terminal of the register capacitor C1 is connected to the source of the sixth transistor M6, and the second terminal of the register capacitor C1 is connected to the output terminal.

[0037] More specifically, the register output module also includes the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11.

[0038] The control electrode and drain of the fifth transistor M5 are connected to the drive terminal; the source of the fifth transistor M5 is connected to the drain of the tenth transistor M10; the drain of the seventh transistor M7 is connected to the second clock terminal.

[0039] The control electrode of the tenth transistor M10 is connected to the source of the sixth transistor M6; the source of the tenth transistor M10 is grounded. The control electrode of the eleventh transistor M11 is connected to the drain of the tenth transistor M10; the drain of the eleventh transistor M11 is connected to the control electrodes of the ninth transistor M9 and the seventh transistor M7. The sources of the tenth transistor M10, the eleventh transistor M11, and the ninth transistor M9 are grounded; the drain of the ninth transistor M9 and the source of the seventh transistor M7 are connected to the second terminal of the register capacitor C1.

[0040] More specifically, the reset module includes an eighth transistor M8; the control electrode of the eighth transistor M8 is connected to the reset signal receiving terminal; the drain of the eighth transistor M8 is connected to the second terminal of the register capacitor C1.

[0041] In this embodiment, transistors M1 to M11 are all amorphous silicon thin-film transistors, and the register capacitor C1 is a 12pF register capacitor. The drain of the first transistor M1 is controlled by the input signal IN; the drain of the second transistor M2 is controlled by the preset signal SET, and the gate is controlled by the enable signal EN; the drain and gate of the third transistor M3 are controlled by the drive signal VDD; the gate of the fourth transistor M4 is controlled by the enable signal EN; the drain and gate of the fifth transistor M5 are controlled by the drive signal VDD; the gate of the sixth transistor M6 is controlled by the first clock signal CK; the drain of the seventh transistor M7 is controlled by the second clock signal XCK, and the source outputs the signal OUT; the gate of the eighth transistor M8 is controlled by the reset signal RESET.

[0042] Specific working principle, such as Figure 2 and Figure 3 As shown:

[0043] 1. Incorporate selection module

[0044] When the signal EN is high, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on, and the first transistor M1 is turned off. At this time, the preset signal SET becomes the input signal of the circuit. When the signal EN is low, the first transistor M1 and the third transistor M3 are turned on, and the second transistor M2 and the fourth transistor M4 are turned off. At this time, the input signal IN becomes the input signal of the circuit.

[0045] 2. Registered Output Module

[0046] Stage ①: The input signal (referring to the drain of the sixth transistor M6) is high. At this time, the first clock signal CK is high and the second clock signal XCK (external clock) is low. The sixth transistor M6 is turned on and the register capacitor C1 stores the input signal.

[0047] Phase 2: The input signal (referring to the drain of the sixth transistor M6) is low. At this time, the first clock signal CK is low, the second clock signal XCK is high, the seventh transistor M7 is turned on, the register capacitor C1 outputs the registered signal, making the output signal OUT high.

[0048] Stage 3: The input signal (referring to the drain of the sixth transistor M6) is high. At this time, the first clock signal CK is high and the second clock signal XCK is low. The sixth transistor M6, the ninth transistor M9, and the eleventh transistor M11 are turned on, which is beneficial for capacitor discharge. The seventh transistor M7 is turned off, and the output signal OUT is low.

[0049] 3. Reset Module

[0050] When the reset signal RESET is high, the eighth transistor M8 is turned on, and the output signal OUT is low.

[0051] Depend on Figure 3 Simulation results show that when the preset signal SET and the first clock signal CK are both high, the circuit shifts and outputs a high-level signal. This type of GOA parallel-to-serial unit circuit can freely set the input signal and realize the signal shifting and registering function.

[0052] According to another aspect of the present invention, a digital microfluidic chip is provided, which includes a plurality of parallel-in serial-out units, wherein the parallel-in serial-out units include the above-described parallel-in serial-out signal conversion circuit.

[0053] In this embodiment, as Figure 5 As shown, this is a five-stage cascaded circuit with parallel input and serial output. Each parallel input / serial output unit is connected to the same enable signal EN, drive signal VDD, reset signal RESET, first clock signal CK, and second clock signal XCK. Each parallel input / serial output unit is connected to its corresponding preset signal SET. Figure 5 (SET1 to SET5 in the series); and the output of the preceding parallel-in serial-out unit is connected to the input of the subsequent parallel-in serial-out unit. Through Figure 6 and Figure 7 As can be seen, when the preset terminals SET of the parallel input are intermittent pulses, the units influence each other, and the shift register signal can be output serially. This signal, with parallel input and serial output, can be used not only for GOA (Getting Over Ahead) but also for transmitting detection signals.

[0054] In summary, the parallel input / serial output signal conversion circuit and digital microfluidic chip of this application inherit the excellent performance of traditional GOA circuits and expand their functions. It has a preset function, which can put data into the register in parallel; each preset terminal transmits data simultaneously, with high data transmission rate, fast transmission speed, and a wider range of parallel transmission signal width, and low requirements for the format of the transmitted signal.

[0055] If the integrated units described in this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0056] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A parallel-in serial-out signal conversion circuit, applied in a digital microfluidic chip, characterized in that, include: Driver terminal, first clock terminal, second clock terminal, output terminal, parallel selection module, register output module, and reset module; The register output module is connected to the parallel selection module, the driver terminal, the second clock terminal, and the output terminal, respectively. The driving terminal is used to connect the driving voltage; The first clock terminal is used to receive a first clock signal; the second clock terminal is used to receive a second clock signal. The parallel selection module includes an input terminal, an enable terminal, and a preset terminal, and the parallel selection module further includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a sixth transistor; The drain of the first transistor is connected to the input terminal, the drain of the second transistor is connected to the preset terminal, the control terminal of the second transistor is connected to the enable terminal, the drain and control terminal of the third transistor are connected to the drive terminal, the sources of the first and second transistors are connected to the drain of the sixth transistor, the drain of the fourth transistor is connected to the source of the third transistor and the control terminal of the first transistor, the control terminal of the fourth transistor is connected to the enable terminal, the source of the fourth transistor is grounded, and the source of the sixth transistor is individually connected to the register output module. The register output module further includes a register capacitor, the first end of which is connected to the source of the sixth transistor, and the second end of which is connected to the output terminal. The reset module is connected to the register output module, and the reset module is provided with a reset signal receiving terminal. The reset module includes an eighth transistor, the control terminal of the eighth transistor is connected to the reset signal receiving terminal, and the drain of the eighth transistor is connected to the second terminal of the register capacitor.

2. The parallel-in serial-out signal conversion circuit according to claim 1, characterized in that: The register output module also includes a fifth transistor, a seventh transistor, and a tenth transistor; The control electrode and drain of the fifth transistor are connected to the driving terminal; the source of the fifth transistor is connected to the drain of the tenth transistor. The drain of the seventh transistor is connected to the second clock terminal; The control electrode of the tenth transistor is connected to the source electrode of the sixth transistor; the source electrode of the tenth transistor is grounded.

3. The parallel-in serial-out signal conversion circuit according to claim 2, characterized in that: The register output module also includes a ninth transistor and an eleventh transistor; The control electrode of the eleventh transistor is connected to the drain electrode of the tenth transistor; The drain of the eleventh transistor is connected to the control electrode of the ninth transistor and the control electrode of the seventh transistor.

4. The parallel-in serial-out signal conversion circuit according to claim 3, characterized in that: The sources of the tenth transistor, the eleventh transistor, and the ninth transistor are grounded; The drain of the ninth transistor and the source of the seventh transistor are connected to the second terminal of the register capacitor.

5. A digital microfluidic chip, characterized in that, include: A plurality of parallel-in serial-out units, wherein the parallel-in serial-out units include a parallel-in serial-out signal conversion circuit as described in any one of claims 1 to 4.

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