Signal generation structure and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and in particular to a signal generating structure and a memory, wherein the signal generating structure comprises: a pulse generating circuit, which generates a pulse signal based on a clock signal, wherein the pulse width in the pulse signal is equal to the period of the clock signal; a period detecting circuit, which generates a digital detection signal based on the pulse signal, wherein the value of the digital detection signal is a multiple of the pulse width of the pulse signal to a preset period; a processing circuit, which obtains the period of the clock signal based on the digital detection signal and generates a delay control signal corresponding to the period of the clock signal; a signal generating circuit, which delays a first initial signal based on the delay control signal to generate a second initial signal, and generates a column address selection signal based on the first initial signal and the second initial signal, flips the column selection signal to a valid level based on the valid edge of the first initial signal, and flips the column selection signal to an invalid level based on the valid edge of the second initial signal.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a signal generating structure and a memory. Background Art

[0002] The signal width of the column select signal (CSL) in dynamic random access memory (DRAM) often determines the edge issues of many array core timings.

[0003] The stability of the CSL signal is affected by factors such as operating pressure, operating voltage, and operating temperature. During the actual use of the CSL signal generation circuit, the operating voltage and operating temperature are unstable. Therefore, the pulse width of the CSL signal fluctuates widely. If the actual pulse width of the CSL signal is insufficient relative to the preset pulse width, or the pulse width of the CSL signal is too long relative to the preset pulse width, data reading and writing may fail, that is, the efficiency of the CSL signal is low.

[0004] The stability of the CSL signal affects the performance of the memory to a certain extent. How to reduce the influence of factors such as temperature, voltage and temperature on the CSL signal, that is, to improve the stability of the CSL signal, is an urgent problem to be solved. Summary of the Invention

[0005] Embodiments of the present disclosure provide a signal generating structure and a memory to generate a stable column address strobe signal.

[0006] An embodiment of the present disclosure provides a signal generating structure for generating a column address selection signal, including: a pulse generating circuit, configured to generate a pulse signal based on a clock signal, wherein the pulse width in the pulse signal is equal to the period of the clock signal; a period detection circuit, configured to generate a digital detection signal based on the pulse signal, wherein the value of the digital detection signal is a multiple of the pulse width of the pulse signal to a preset period; a processing circuit, configured to obtain the period of the clock signal based on the digital detection signal, and generate a delay control signal corresponding to the period of the clock signal; a signal generating circuit, configured to delay a first initial signal based on the delay control signal to generate a second initial signal, and generate a column address selection signal based on the first initial signal and the second initial signal, wherein the column selection signal is flipped to a valid level based on the valid edge of the first initial signal, and the column selection signal is flipped to an invalid level based on the valid edge of the second initial signal.

[0007] The signal length of the column selection address signal generated by the signal generating structure is determined by the size of the delay control signal. The delay control signal (related to the frequency / period of the clock signal) is a digital signal. Compared with the analog signal realized only by a fixed delay circuit, its stability is less affected by the working pressure, working voltage and working temperature, making the signal length of the generated column selection address signal more stable.

[0008] Optionally, the pulse generating circuit includes: a delay unit, whose input end is used to receive a drive signal, and the drive signal is used to start the pulse generating circuit; a first inverter, whose input end is connected to the output end of the delay unit; a first AND logic circuit, whose first input end is used to receive the drive signal, and whose second input end is connected to the output end of the first inverter; a first D trigger, whose input end is connected to the output end of the first AND logic circuit, whose clock end is used to receive a clock signal, and whose output end is used to output a pulse signal.

[0009] Optionally, the signal generating structure further includes: a frequency processing circuit, configured to generate a clock signal based on an external clock signal, wherein the clock signal is a divided signal of the external clock signal, and the division ratio is set to: so that the frequency of the clock signal meets the frequency recognition range of the period detection circuit.

[0010] Optionally, the frequency processing circuit includes: n cascaded stages of D flip-flops, the input end of each stage of the D flip-flop being used to receive the inverted signal outputted by the output end, where n is an integer greater than 1; the clock end of the first stage of the D flip-flop being used to receive an external clock signal CLK, the clock end of the i-th stage of the D flip-flop being connected to the inverted output end of the i-1-th stage of the D flip-flop, 2≤i≤n, wherein the output end of the i-th stage of the D flip-flop outputs the i-th clock signal; a selector having n input ends, each input end correspondingly connected to the output end of one of the n stages of the D flip-flops, a control end being used to receive a clock selection signal, and an output end being used to output the clock signal, the selector being configured to output the i-th clock signal whose frequency satisfies the frequency recognition range of the period detection circuit as the clock signal based on the clock selection signal.

[0011] Optionally, the period detection circuit includes: an oscillation circuit, configured to oscillate based on a pulse signal to generate an oscillation signal of a preset period; a counting circuit, configured to count the number of oscillations of the oscillation signal within a pulse width time in the pulse signal, and generate a digital detection signal based on the number of oscillations.

[0012] Optionally, the oscillation circuit includes: a ring oscillator formed by cascading m stages of second inverters, where m is an odd number greater than 1; the period detection circuit also includes: a selection circuit, arranged in the ring oscillator, configured to adjust the number of connected stages of the second inverters in the ring oscillator.

[0013] Optionally, the processing circuit includes: a first processing unit, which obtains the period of the external clock signal based on the digital detection signal and a preset formula, wherein the preset formula is related to the preset period of the oscillation signal, the delay of the second inverter of each stage, and the multiplier setting of the frequency division signal; a second processing unit, which is configured to generate a delay control signal based on the period of the external clock signal and the preset delay correspondence; the preset delay correspondence indicates the correspondence between the period of the external clock signal and the number of delay cycles required to generate the column address selection signal.

[0014] Optionally, the signal generating circuit includes: a delay unit configured to delay the first initial signal based on a delay control signal to generate a second initial signal; and a merging unit configured to generate a column selection signal based on the first initial signal and the second initial signal.

[0015] Optionally, the delay control signal includes k delay control sub-signals, and the delay unit includes: a cascade of k-level shift register circuits, the input end of the first-level shift register circuit is used to receive the first initial signal, the input end of the q-th-level shift register circuit is connected to the output end of the q-1-th-level shift register circuit, 2≤q≤k, and the output end of the last-level shift register circuit is used to output the second initial signal; each shift register circuit is also used to receive an external clock signal and a corresponding delay control sub-signal.

[0016] Optionally, the delay unit further includes: a delayer, the input end of the delayer is connected to the output end of the last stage shift register circuit, and the delayer is configured to delay the signal input to the delayer for a preset time; a merging unit is configured to generate a column selection signal based on the first initial signal and the delayed second initial signal output by the delayer.

[0017] Optionally, when the delay control sub-signal is a valid signal, the shift register circuit corresponding to the delay control sub-signal performs a one-clock cycle delay on the signal received at its input terminal.

[0018] Optionally, the merging unit includes: a first SR latch based on a NOR gate, the S end of the first SR latch is used to receive the first initial signal, the R end is used to receive the second initial signal, and the output end is used to output the column address selection signal.

[0019] Optionally, the merging unit includes: a second SR latch based on a NAND gate, the S end of the second SR latch is used to receive the second initial signal, the R end is used to receive the first initial signal, and the output end is used to output the column address selection signal.

[0020] Optionally, the shift register circuit includes: a first P-type transistor, a first terminal serving as the input end of the shift register circuit, and a second terminal connected to the input end of the third inverter and the output end of the fourth inverter; a first N-type transistor, a first terminal serving as the input end of the shift register circuit, and a second terminal connected to the input end of the third inverter and the output end of the fourth inverter; a first AND gate, a first input end for receiving a corresponding delay control sub-signal, a second input end for receiving an inverted signal of an external clock signal, and an output end connected to the control end of the first P-type transistor; a first NAND gate, a first input end for receiving a corresponding delay control sub-signal, a second input end for receiving an inverted signal of an external clock signal, and an output end connected to the control end of the first N-type transistor; a second P-type transistor, a first terminal connected to the output end of the third inverter and the input end of the fourth inverter, and a second terminal connected to the fifth inverter a second N-type transistor, a first terminal connected to the output end of the third inverter and the input end of the fourth inverter, and a second terminal connected to the input end of the fifth inverter and the output end of the sixth inverter; a second AND gate, a first input end for receiving the corresponding delay control sub-signal, a second input end for receiving the external clock signal, and an output end connected to the control end of the second P-type transistor; a second NAND gate, a first input end for receiving the corresponding delay control sub-signal, a second input end for receiving the external clock signal, and an output end connected to the control end of the second N-type transistor; a third P-type transistor, a first terminal for receiving the power supply voltage, a control end for receiving the shift reset signal, and a second terminal connected to the input end of the fifth inverter and the output end of the sixth inverter; the output end of the fifth inverter and the input end of the sixth inverter serve as the output end of the shift register circuit.

[0021] Another embodiment of the present disclosure further provides a memory, comprising the signal generating structure provided by the above embodiment, to generate a stable column address strobe signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A schematic diagram of a signal generating structure provided in one embodiment of the present disclosure;

[0024] Figure 2An exemplary diagram of the working principle of a signal generating structure provided in one embodiment of the present disclosure;

[0025] Figure 3 A schematic structural diagram of a pulse generating circuit provided in one embodiment of the present disclosure;

[0026] Figure 4 An exemplary diagram of the working principle of a pulse generating circuit provided in one embodiment of the present disclosure;

[0027] Figure 5 A schematic structural diagram of a signal generating structure including a frequency processing circuit provided in one embodiment of the present disclosure;

[0028] Figure 6 A schematic structural diagram of a frequency processing circuit provided in one embodiment of the present disclosure;

[0029] Figure 7 A schematic diagram of the structure of a period detection circuit provided in one embodiment of the present disclosure;

[0030] Figure 8 A schematic structural diagram of an oscillation circuit provided in one embodiment of the present disclosure;

[0031] Figure 9 A schematic diagram of the structure of a processing circuit provided in one embodiment of the present disclosure;

[0032] Figure 10 A schematic structural diagram of a signal generating circuit provided in one embodiment of the present disclosure;

[0033] Figure 11 A schematic structural diagram of a delay unit provided in one embodiment of the present disclosure;

[0034] Figure 12 A schematic structural diagram of a shift register circuit provided in one embodiment of the present disclosure;

[0035] Figure 13 A schematic structural diagram of a first SR latch provided in one embodiment of the present disclosure;

[0036] Figure 14 A schematic diagram of the working principle of a first SR latch provided in one embodiment of the present disclosure;

[0037] Figure 15 A schematic structural diagram of a delay unit including a delay device provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] As can be seen from the background technology, the stability of the column select signal (CSL) is affected by factors such as operating pressure, operating voltage and operating temperature. During the actual use of the CSL signal generation circuit, the operating voltage and operating temperature are unstable. Therefore, the pulse width of the CSL signal fluctuates widely, and the stability of the CSL signal affects the performance of the memory to a certain extent.

[0039] An embodiment of the present disclosure provides a signal generating structure to generate a stable column address strobe signal.

[0040] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0041] Figure 1 This is a schematic diagram of the signal generation structure provided in this embodiment. Figure 2 This is an example diagram of the working principle of the signal generating structure provided in this embodiment. Figure 3 A schematic diagram of the structure of the pulse generating circuit provided in this embodiment, Figure 4 This is an example diagram of the working principle of the pulse generating circuit provided in this embodiment. Figure 5 A schematic diagram of a signal generating structure including a frequency processing circuit provided in this embodiment, Figure 6 This is a schematic diagram of the structure of the frequency processing circuit provided in this embodiment. Figure 7 This is a schematic diagram of the structure of the period detection circuit provided in this embodiment, Figure 8 A schematic diagram of the structure of the oscillation circuit provided in this embodiment, Figure 9 A schematic diagram of the structure of the processing circuit provided in this embodiment, Figure 10 This is a schematic diagram of the structure of the signal generating circuit provided in this embodiment. Figure 11 This is a schematic diagram of the structure of the delay unit provided in this embodiment. Figure 12 A schematic diagram of the structure of the shift register circuit provided in this embodiment is shown in FIG. Figure 13 This is a schematic diagram of the structure of the first SR latch provided in this embodiment, Figure 14 Schematic diagram of the working principle of the first SR latch provided in this embodiment, Figure 15 The structure diagram of the delay unit including the delay device provided in this embodiment is as follows. The signal generating structure provided in this embodiment is described in detail with reference to the accompanying drawings, as follows:

[0042] refer to Figure 1 , a signal generating structure for generating a column address strobe signal CSL, comprising:

[0043] The pulse generating circuit 101 is configured to generate a pulse signal Pluse based on the clock signal CLKx; wherein the pulse width of the pulse signal Pluse is equal to the period of the clock signal CLKx. Figure 4 , the pulse width of the pulse signal Pluse is equal to the time interval between two adjacent rising edges or two adjacent falling edges of the clock signal CLKx; it should be noted that, Figure 4 In the example, the pulse signal Pluse is based on the rising edge transition of the clock signal CLKx, which does not constitute a limitation to this embodiment; in other examples, the pulse signal Pluse can also be set to be based on the falling edge transition of the clock signal CLKx.

[0044] The period detection circuit 102 is configured to generate a digital detection signal Output based on the pulse signal Pluse; the value of the digital detection signal Output is the ratio of the pulse width of the pulse signal Pluse to a preset period. In one example, assuming the pulse width of the pulse signal Pluse is 500 ns, when the preset period is 50 ns, the ratio of the pulse width of the pulse signal Pluse to the preset period is 10, i.e., the value of the digital detection signal Output is 10, which is converted to a binary signal of "0001010". When the preset period is 100 ns, the ratio of the pulse width of the pulse signal Pluse to the preset period is 5, i.e., the value of the digital detection signal Output is 5, which is converted to a binary signal of "00000101".

[0045] It should be noted that in the above example, the digital detection signal Output is an 8-bit binary signal, which is used as an example for illustrative explanation and does not constitute a limitation of this example. In specific applications, the actual data length of the digital detection signal Output is set based on the multiplication range of the preset period by the pulse width of the possible pulse signal Pluse.

[0046] The processing circuit 103 is configured to obtain a period of the clock signal CLKx based on the digital detection signal Output, and generate a delay control signal for the period of the clock signal CLKx.

[0047] The signal generating circuit 104 is configured to delay the first initial signal based on the delay control signal to generate a second initial signal, and generate a column selection address signal CSL based on the first initial signal and the second initial signal; wherein the column selection address signal CSL is flipped to a valid level based on the valid edge of the first initial signal, and is flipped to an invalid level based on the valid edge of the second initial signal. Specifically, referring to Figure 2 Combined with Figure 1 The signal generating circuit 104 delays the first initial signal to generate a second initial signal. The specific number of delay cycles is controlled based on the delay control signal, that is, the delay control signal determines the ratio of the signal length of the generated column selection address signal CSL to the clock signal CLKx.

[0048] It should be noted that, based on the generation principle of the column address selection signal CSL provided in this embodiment, if the column address selection signal CSL is generated based on the rising edge of the first initial signal and the rising edge of the second initial signal, the signal length of the column address selection signal CSL is: the number of cycles represented by the delay control signal x*the period of the clock signal CLKx; if the column address selection signal CSL is generated based on the rising edge of the first initial signal and the falling edge of the second initial signal, the signal length of the column address selection signal CSL is: the number of cycles represented by the delay control signal x*the period of the clock signal CLKx+the pulse width of the first initial signal; if the column address selection signal CSL is generated based on the falling edge of the first initial signal and the rising edge of the second initial signal, the signal length of the column address selection signal CSL is: the number of cycles represented by the delay control signal x*the period of the clock signal CLKx-the pulse width of the first initial signal; if the column address selection signal CSL is generated based on the falling edge of the first initial signal and the falling edge of the second initial signal, the signal length of the column address selection signal CSL is: the number of cycles represented by the delay control signal x*the period of the clock signal CLKx. in, Figure 2 For example, the column address strobe signal CSL is generated based on the rising edge of the first initial signal and the rising edge of the second initial signal. Those skilled in the art can generate the column address strobe signal CSL based on the above description. Figure 2 Based on this, a timing diagram under other column address strobe signal CSL generation conditions is obtained.

[0049] It should also be noted that in some embodiments, a delay circuit may be provided in the circuit generating the second initial signal to adjust the length of the column address strobe signal CSL by a fixed delay corresponding to the delay circuit. Specifically, if the column address strobe signal CSL is generated based on the rising edge of the first initial signal and the rising edge of the second initial signal, the signal length of the column address strobe signal CSL is: the number of cycles represented by the delay control signal x*the period of the clock signal CLKx+the fixed delay corresponding to the delay circuit; if the column address strobe signal CSL is generated based on the rising edge of the first initial signal and the falling edge of the second initial signal, the signal length of the column address strobe signal CSL is: the number of cycles represented by the delay control signal x *The period of the clock signal CLKx + the pulse width of the first initial signal + the fixed delay corresponding to the delay circuit; if the column address selection signal CSL is generated based on the falling edge of the first initial signal and the rising edge of the second initial signal, the signal length of the column address selection signal CSL is: the number of periods represented by the delay control signal x * the period of the clock signal CLKx - the pulse width of the first initial signal + the fixed delay corresponding to the delay circuit; if the column address selection signal CSL is generated based on the falling edge of the first initial signal and the falling edge of the second initial signal, the signal length of the column address selection signal CSL is: the number of periods represented by the delay control signal x * the period of the clock signal CLKx + the fixed delay corresponding to the delay circuit.

[0050] In addition, for the first initial signal, the first initial signal is generated based on the read / write command of the memory; in a specific application, if the signal length of the generated column address selection signal CSL is not related to the pulse width of the first initial signal, the first initial signal can be set to a signal of any pulse width; if the signal length of the generated column address selection signal CSL is related to the pulse width of the first initial signal, the pulse width of the first initial signal is set based on the column address selection signal CSL to be generated.

[0051] For the signal generating structure provided in this embodiment, the signal length of the generated column selection address signal CSL is determined by the size of the delay control signal (related to the frequency / period of the clock signal). As a digital signal, the delay control signal is less affected by the operating pressure, operating voltage and operating temperature than the analog signal implemented only by a fixed delay circuit, so that the signal length of the generated column selection address signal CSL is relatively stable.

[0052] For the pulse generating circuit 101, refer to Figure 3The pulse generating circuit 101 includes: a delay unit 202, whose input end is used to receive a driving signal, and the driving signal is used to start the pulse generating circuit 101; a first inverter 201, whose input end is connected to the output end of the delay unit 202; a first AND logic circuit 201, whose first input end is used to receive the driving signal, and whose second input end is connected to the output end of the first inverter 211; a first D flip-flop 203, whose input end is connected to the output end of the first AND logic circuit 201, whose clock end is used to receive a clock signal CLKx, and whose output end is used to output a pulse signal Pluse.

[0053] Regarding the driving signal, in some embodiments, the driving signal may be an enable signal generated by a test mode MRS command of the memory; in other embodiments, the driving signal may be a read / write enable signal generated by a read / write command of the memory.

[0054] refer to Figure 4 When the driving signal is valid, that is, the first input terminal A1 of the first AND logic circuit 201 is input at a high level, and the second input terminal A2 inputs the inverted signal of the delayed driving signal. At this time, the first AND logic circuit 201 generates a driving pulse B based on the driving signal. The pulse width of the driving pulse B is the delay length of the delay unit 202, which is used to instruct the first D flip-flop 203 to jump to a high level next time. When the first D flip-flop 203 receives the valid edge of the clock signal CLKx, the output signal jumps to a high level based on the driving pulse B; when the first D flip-flop 203 receives the next valid edge of the clock signal CLKx, since the driving pulse B is at a low level at this time, the output signal of the first D flip-flop 203 jumps to a low level, that is, a pulse signal Pluse is generated, and the pulse width of the pulse signal Pluse is equal to the period of the clock signal CLKx.

[0055] It should be noted that in other examples, the drive signal can also be set to be active low. In this case, the first AND logic circuit can be replaced with a corresponding NAND logic circuit to generate the same drive pulse. In addition, the pulse width of the drive pulse B generated by the first AND logic circuit 201 must be less than one clock cycle of the clock signal CLKx, that is, the delay of the delay unit 202 is less than one clock cycle of the clock signal CLKx. In actual use, for the first D flip-flop 203, the active level of the drive pulse B may not be sampled solely by the rising edge of the clock signal CLKx. In an actual circuit, the drive pulse B can be sampled simultaneously by the rising edges of the clock signal CLKx and the inverted signal CLKx- of the clock signal CLKx. Then, a logical operation is performed on the two sampling results to generate the pulse signal Pluse.

[0056] In some embodiments, reference Figure 5The signal generating structure further includes: a frequency processing circuit 110, which is configured to generate a clock signal CLKx based on the external clock signal CLK, wherein the clock signal CLKx is a frequency-divided signal of the external clock signal CLK, and the frequency-divided ratio is set so that the frequency of the clock signal CLKx satisfies the frequency recognition range of the period detection circuit 102. Specifically, the period detection circuit 102 has a recognizable frequency range. When the pulse signal Pluse satisfies this frequency range, the pulse signal Pluse can be recognized by the period detection circuit 102. When the frequency of the pulse signal Pluse is too high and exceeds the recognition range of the period detection circuit 102, the pulse signal Pluse cannot be recognized. Therefore, it is necessary to perform frequency-dividing processing on the external clock signal CLK with a higher frequency so that the frequency of the recognized clock signal CLKx satisfies the recognizable frequency range of the period detection circuit 102. The clock signal CLKx is a frequency-divided signal of the external clock signal CLK, that is, the frequency of the clock signal CLKx is smaller than the frequency of the external clock signal CLK, and the period is larger.

[0057] For the frequency processing circuit 110, in some embodiments, reference Figure 6 The frequency processing circuit 110 includes: n-stage cascaded D flip-flops, the input terminal D of each stage D flip-flop is used to receive the inverted signal output by the output terminal Q, n is an integer greater than 1; the clock terminal Ck of the first stage D flip-flop is used to receive the external clock signal CLK, the clock terminal Ck of the i-th stage D flip-flop is connected to the inverted output terminal of the i-1-th stage D flip-flop, 2≤i≤n, wherein the output terminal of the i-th stage D flip-flop outputs the i-th clock signal. It should be noted that for Figure 6 For example, the input terminal D of each stage of the D flip-flop is used to receive the inverted signal output by the output terminal Q. In a specific implementation, it can be set that the input terminal of each stage of the D flip-flop is connected to the inverting output terminal; in addition, the clock terminal Ck of the i-th stage D flip-flop is connected to the inverting output terminal of the i-1-th stage D flip-flop. In a specific implementation, it can be set that the clock terminal Ck of the i-th stage D flip-flop is the output terminal of the inverter, and the input terminal of the inverter is connected to the non-inverting output terminal of the i-1-th stage D flip-flop.

[0058] The selector 120 has n input terminals, each input terminal corresponding to the output terminal of one of the n-stage D flip-flops, a control terminal for receiving a clock selection signal, and an output terminal for outputting the clock signal CLKx. The selector 120 is configured to output the i-th clock signal whose frequency meets the frequency recognition range of the period detection circuit 102 as the clock signal CLKx based on the clock selection signal.

[0059] for Figure 6For example, the first D flip-flop outputs the first clock signal CLK1, the second D flip-flop outputs the second clock signal CLK2, the third D flip-flop outputs the third clock signal CLK3, and the fourth D flip-flop outputs the fourth clock signal CLK4, wherein the period of the second clock signal CLK2 is twice that of the first clock signal CLK1, the period of the third clock signal CLK3 is twice that of the second clock signal CLK2, and the period of the fourth clock signal CLK4 is twice that of the third clock signal CLK3. It should be noted that Figure 6 The frequency processing circuit 110 composed of 4 cascaded D flip-flops is used as an example for illustration, i.e., n=4, which does not constitute a limitation of this embodiment. In specific applications, the number of D flip-flops can be set according to the need to divide the external clock signal CLK by a multiple.

[0060] Continue to refer Figure 6 In some embodiments, the clock terminal Ck of the first-stage D flip-flop is connected to the output terminal of the AND logic circuit, and the first input terminal of the AND logic circuit is used to receive the external clock signal CLK, and the second input terminal is used to receive the enable signal, so that the frequency processing circuit 110 can be started based on the enable signal control, saving energy consumption of the frequency processing circuit 110; in addition, the reset terminal RN of each stage of the D flip-flop is also used to receive a reset signal to reset the frequency processing circuit 110 through the reset signal.

[0061] For the period detection circuit 102, refer to Figure 7 In some embodiments, the period detection circuit 102 includes: an oscillation circuit 301, configured to oscillate based on the pulse signal Pluse to generate an oscillation signal with a preset period; a counting circuit 302, configured to count the number of oscillations of the oscillation signal within the pulse width time of the pulse signal Pluse, and generate a digital detection signal Output based on the number of oscillations.

[0062] Continue to refer Figure 7 In some embodiments, the oscillation circuit 301 is further configured to receive a second enable signal, so that the period detection circuit 102 can be activated based on the second enable signal, thereby reducing energy consumption of the period detection circuit 102. In some embodiments, the second enable signal can be an enable signal generated by a test mode MRS command of the memory; in other embodiments, the second enable signal can be a read / write enable signal generated by a read / write command of the memory.

[0063] In one example, refer to Figure 8The oscillation circuit 301 includes: a ring oscillator composed of m stages of second inverters in cascade, where m is an odd number greater than 1; the period detection circuit 102 also includes: a selection circuit 303, which is provided in the ring oscillator and is configured to adjust the number of connected stages of the second inverters in the ring oscillator. It should be noted that Figure 8 The number of inverter stages shown in the example is only used to illustrate the oscillation circuit 301 and does not constitute a limitation on the oscillation circuit 301 .

[0064] For the processing circuit 103, refer to Figure 9 In some embodiments, the processing circuit 103 includes: a first processing unit 401, which obtains the period of the external clock signal CLK based on the digital detection signal Output and a preset formula, where the preset formula is related to the preset period of the oscillation signal, the delay of the second inverter of each stage, and the multiplier setting of the frequency division signal; a second processing unit 402, which is configured to generate a delay control signal based on the period of the external clock signal CLK and a preset delay correspondence relationship; the preset delay correspondence relationship indicates the correspondence between the period of the external clock signal CLK and the number of delay cycles required to generate the column address selection signal CSL.

[0065] For the first processing unit 401, in one example, assuming that the oscillation period of the ring oscillator in the oscillation circuit 301 is 500 ps, ​​or the period of the oscillation signal generated by the oscillation circuit 301 is 500 ps, ​​and the digital detection signal Output<8:0> output by the period detection circuit 102 is "000100000". The preset formula in the first processing unit 401 is set to: Output<8:3>*500 ps + output<2:0>*500 ps / 10. In this case, the pulse width of the pulse signal can be calculated to be 2 ns, that is, the period of the clock signal CLKx is 2 ns. Then, based on the frequency division ratio set by the frequency processing circuit 110, the specific period of the clock signal CLK can be obtained. It should be noted that the above description of the preset formula is only used by those skilled in the art to understand the working principle of the first processing unit 401 and does not constitute a limitation of the first processing unit 401. In other embodiments, due to different oscillation periods of the oscillation circuit 301, the setting parameters of the preset formula in the first processing unit 401 are also different.

[0066] For the second processing unit 402, in DDR5, the target length of the column address strobe signal CSL is greater than or equal to 3 ns. To generate a column address strobe signal CSL with a signal length of 3 ns in all cases, it needs to be generated with the period of the clock signal CLKx or the external clock signal CLK. The formula is CSL = delay control signal * clock signal CLKx / period of the external clock signal CLK. In one example, refer to the setting method in Table 1 below:

[0067] Table 1: Comparison of the clock signal CLKx period, delay control signal, and column address strobe signal CSL signal length when the preset delay is not included

[0068] The period of the clock signal CLKx Delay control signal The generated column address strobe signal CSL signal length 0.682ns 5 0.682*5=3.410ns 0.625ns 5 0.625*5=3.125ns 0.556ns 6 0.556*6=3.336ns 0.500ns 6 0.500*6=3.000ns 0.455ns 7 0.455*7=3.185ns 0.417ns 8 0.417*8=3.336ns 0.385ns 8 0.385*8=3.080ns 0.357ns 9 0.357*9=3.213ns 0.334ns 9 0.334*9=3.000ns

[0069] It should be noted that Table 1 uses the period of the clock signal CLKx as an example to illustrate how the second processing unit 402 obtains the delay control signal. In other embodiments, the delay control signal can also be obtained based on the external clock signal CLK. In this case, the delay control signal = the delay control signal obtained based on the clock signal CLKx * the frequency division ratio of the frequency processing circuit 110. In some embodiments, the circuit generating the column address strobe signal CSL also includes a delay circuit for performing a preset delay on the first initial signal. Specifically, the preset delay is used to fine-tune the generation time of the second initial signal. Because the delay controlled by the delay control signal is a digital signal adjustment, the adjustment speed is fast, but the accuracy of the adjusted delay is not high. Therefore, an analog signal fine-tuning of the preset delay is added to improve the accuracy of the signal length of the generated column address strobe signal CSL. In this case, the signal length of the generated column address strobe signal CSL also includes the preset delay time. In this case, CSL = delay control signal * clock signal CLKx / period of the external clock signal CLK + preset delay. In one example, assuming the preset delay is 0.5 ns, refer to the setting method in Table 2 below:

[0070] Table 2: Comparison of the period of the clock signal CLKx, the delay control signal, and the length of the column address strobe signal CSL when the preset delay is included

[0071] The period of the clock signal CLKx Delay control signal Preset delay The generated column address strobe signal CSL signal length 0.682ns 4 0.5ns 0.682*4+0.5=3.23ns 0.625ns 4 0.5ns 0.625*4+0.5=3.00ns 0.556ns 5 0.5ns 0.556*5+0.5=3.28ns 0.500ns 5 0.5ns 0.500*5+0.5=3.00ns 0.455ns 6 0.5ns 0.455*6+0.5=3.23ns 0.417ns 6 0.5ns 0.417*6+0.5=3.00ns 0.385ns 7 0.5ns 0.385*7+0.5=3.19ns 0.357ns 7 0.5ns 0.357*7+0.5=3.00ns 0.334ns 8 0.5ns 0.334*8+0.5=3.17ns

[0072] It should be noted that Table 2 uses the period of the clock signal CLKx as an example to illustrate the manner in which the second processing unit 402 obtains the delay control signal. In other embodiments, the delay control signal can also be obtained based on the external clock signal CLK. In this case, the delay control signal = the delay control signal obtained based on the clock signal CLKx * the frequency division ratio of the frequency processing circuit 110.

[0073] It should also be noted that, for the second processing unit 402, the second processing unit 402 is set based on the above table, and the second processing unit directly decodes and obtains the delay control signal based on the period of the acquired clock signal CLKx. Figure 10The signal generating circuit 104 includes: a delay unit 501, which is configured to delay the first initial signal based on a delay control signal to generate a second initial signal; wherein the delay control signal is used to control the number of cycles of the first initial signal. If the delay control signal is used to represent the number of cycles of the external clock signal CLK, the delay of the first initial signal is set based on the external clock signal CLK; if the delay control signal is used to represent the number of cycles of the clock signal CLKx, the delay of the first initial signal is set based on the clock signal CLKx; a merging unit 502, which is configured to generate a column address select signal CSL based on the valid edge of the first initial signal and the valid edge of the second initial signal.

[0074] For the delay unit 501, refer to Figure 11 , used to implement the corresponding relationship in Table 1, the delay control signal includes k delay control sub-signals, and the delay unit 501 includes: a cascade of k-stage shift register circuits 600, the input end of the first-stage shift register circuit 600 is used to receive the first initial signal, the input end of the q-th-stage shift register circuit 600 is connected to the output end of the q-1-th-stage shift register circuit 600, 2≤q≤k, and the output end of the last-stage shift register circuit 600 is used to output the second initial signal; each shift register circuit 600 is further used to receive an external clock signal CLK or a clock signal CLKx, and a corresponding delay control sub-signal.

[0075] Specifically, when the delay control sub-signal is valid, the shift register circuit 600 corresponding to the delay control sub-signal aligns the signal received at the input terminal and performs a one-clock-cycle delay. When the delay control sub-signal is invalid, the shift register circuit 600 corresponding to the delay control sub-signal directly outputs the input signal. More specifically, if the clock received by the shift register circuit 600 is the external clock signal CLK, the one-clock-cycle delay is one cycle of the external clock signal CLK; if the clock received by the shift register circuit 600 is the clock signal CLKx, the one-clock-cycle delay is one cycle of the clock signal CLKx.

[0076] For the shift register circuit 600, refer to Figure 12The shift register circuit 600 includes: a first P-type transistor P101, a first terminal of which serves as an input terminal of the shift register circuit 600, and a second terminal of which is connected to the input terminal of the third inverter 803 and the output terminal of the fourth inverter 804; a first N-type transistor N101, a first terminal of which serves as an input terminal of the shift register circuit 600, and a second terminal of which is connected to the input terminal of the third inverter 803 and the output terminal of the fourth inverter 804; a first AND gate 810, a first input terminal of which is used to receive a corresponding delay control sub-signal, and a second input terminal of which is used to receive an external The inverted signal of the clock signal CLK or the inverted signal of the missing signal CLKx, the output end of which is connected to the control end of the first P-type transistor P101; the first NAND gate 860, the first input end of which is used to receive the corresponding delay control sub-signal, the second input end of which is used to receive the inverted signal of the external clock signal CLK or the inverted signal of the missing signal CLKx, the output end of which is connected to the control end of the first N-type transistor N101; the second P-type transistor P102, the first terminal of which is connected to the output end of the third inverter 803 and the input end of the fourth inverter 804, the second The first terminal of the second N-type transistor N102 is connected to the output terminal of the third inverter 803 and the input terminal of the fourth inverter 804, and the second terminal is connected to the input terminal of the fifth inverter 805 and the output terminal of the sixth inverter 806; the first input terminal of the second AND gate 820 is used to receive the corresponding delay control sub-signal, the second input terminal is used to receive the external clock signal CLK or the clock signal CLKx, and the output terminal is connected to the control terminal of the second P-type transistor P102 ; The second NAND gate 870, the first input end is used to receive the corresponding delay control sub-signal, the second input end is used to receive the external clock signal CLK or the clock signal CLKx, and the output end is connected to the control end of the second N-type transistor N102; the third P-type transistor P103, the first terminal is used to receive the power supply voltage VDD, the control end is used to receive the shift reset signal RSTB, and the second terminal is connected to the input end of the fifth inverter 805; the output end of the fifth inverter 505 and the input end of the sixth inverter serve as the output end of the shift register circuit 600.

[0077] Regarding the merging unit 502, in one example, the merging unit 502 includes: a first SR latch based on a NOR gate, wherein the S terminal of the first SR latch is used to receive the first initial signal, the R terminal is used to receive the second initial signal, and the output terminal is used to output the column address selection signal CSL. Figure 13The first SR latch includes: a first OR logic circuit 531, a first input end of which is connected to the output end of the second OR logic circuit 532, a second input end of which serves as the R end of the first SR latch to receive the second initial signal, and an output end for outputting the column address selection signal CSL; a second OR logic circuit 532, a first input end of which is connected to the output end of the first OR logic circuit 531, and a second input end of which serves as the S end of the first SR latch to receive the first initial signal.

[0078] Specifically, the S terminal of the first SR latch is used as the "1" terminal. When the S terminal receives a high level, the output terminal of the first SR latch is pulled high; the R terminal of the first SR latch is used as the "0" terminal. When the R terminal receives a low level, the output terminal of the first SR latch is pulled high or low. At this time, the merging unit 502 generates the column address selection signal CSL based on the first initial signal and the second initial signal. Figure 14 .

[0079] In another example, based on the second SR latch formed by a NAND gate, the S terminal of the second SR latch is used to receive the second initial signal, the R terminal is used to receive the first initial signal, and the output terminal is used to output the column address selection signal CSL.

[0080] In another example, refer to Figure 15 , used to implement the correspondence in Table 2, the delay unit 501 also includes: a delayer 601, the input end of the delayer 601 is connected to the output end of the last-stage shift register circuit 600, and the delayer 601 is configured to delay the signal input to the delayer 601 for a preset time; at this time, the merging unit 502 is configured to generate a column address selection signal CSL based on the first initial signal and the delayed second initial signal output by the delayer 601.

[0081] Specifically, in one example, the merging unit 502 includes a first SR latch configured based on a NOR gate, wherein the S terminal of the first SR latch is used to receive the first initial signal, the R terminal is used to receive the delayed second initial signal output by the delayer 601, and the output terminal is used to output the column address selection signal CSL. In another example, the second SR latch is configured based on a NAND gate, wherein the S terminal of the second SR latch is used to receive the delayed second initial signal output by the delayer 601, the R terminal is used to receive the first initial signal, and the output terminal is used to output the column address selection signal CSL.

[0082] For the signal generating structure provided in this embodiment, the signal length of the generated column selection address signal CSL is determined by the size of the delay control signal (related to the frequency / period of the clock signal). As the delay control signal is a digital signal, its stability is less affected by the operating pressure, operating voltage and operating temperature, so that the signal length of the generated column selection address signal CSL is relatively stable.

[0083] It should be noted that the features disclosed in the signal generating structures provided in the above embodiments can be arbitrarily combined without conflict to obtain new signal generating structure embodiments.

[0084] Another embodiment of the present disclosure provides a memory, comprising the signal generating structure provided by the above embodiment, to generate a stable column address strobe signal.

[0085] Specifically, for the signal generating structure, the signal length of the generated column selection address signal CSL is determined by the size of the delay control signal (related to the frequency / period of the clock signal). As a digital signal, the delay control signal is less affected by the operating pressure, operating voltage and operating temperature than the analog signal realized only by a fixed delay circuit, so that the signal length of the generated column selection address signal CSL is relatively stable.

[0086] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0087] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A signal generating structure for generating a column address strobe signal, characterized in that: include: a pulse generating circuit configured to generate a pulse signal based on a clock signal, wherein a pulse width in the pulse signal is equal to a period of the clock signal; a period detection circuit configured to generate a digital detection signal based on the pulse signal, wherein a value of the digital detection signal is a ratio of a pulse width of the pulse signal to a preset period; a processing circuit configured to obtain a period of the clock signal based on the digital detection signal and generate a delay control signal corresponding to the period of the clock signal; The signal generating circuit is configured to delay the first initial signal based on a delay control signal to generate a second initial signal, and generate the column address selection signal based on the first initial signal and the second initial signal, wherein the column address selection signal is flipped to a valid level based on a valid edge of the first initial signal, and the column address selection signal is flipped to an invalid level based on a valid edge of the second initial signal.

2. The signal generating structure according to claim 1, wherein: The pulse generating circuit comprises: A delay unit, whose input end is used to receive a driving signal, wherein the driving signal is used to start the pulse generating circuit; a first inverter, an input end of which is connected to the output end of the delay unit; a first AND logic circuit, wherein the first input terminal is used to receive the driving signal, and the second input terminal is connected to the output terminal of the first inverter; The first D flip-flop has an input end connected to the output end of the first AND logic circuit, a clock end for receiving the clock signal, and an output end for outputting the pulse signal.

3. The signal generating structure according to claim 1 or 2, characterized in that: Also includes: The frequency processing circuit is configured to generate the clock signal based on the external clock signal, wherein the clock signal is a divided signal of the external clock signal, and the frequency division ratio is set to: so that the frequency of the clock signal meets the frequency recognition range of the period detection circuit.

4. The signal generating structure according to claim 3, characterized in that: The frequency processing circuit includes: n-stage cascaded D flip-flops, wherein the input terminal of each stage of the D flip-flop is used to receive the inverted signal output by the output terminal, where n is an integer greater than 1; the clock terminal of the first-stage D flip-flop is used to receive the external clock signal CLK, the clock terminal of the i-th stage D flip-flop is connected to the inverting output terminal of the i-1-th stage D flip-flop, where 2≤i≤n, and the output terminal of the i-th stage D flip-flop outputs the i-th clock signal; The selector has n input terminals, each input terminal corresponding to the output terminal of one of the n-level D flip-flops, the control terminal is used to receive a clock selection signal, and the output terminal is used to output the clock signal. The selector is configured to output the i-th clock signal whose frequency meets the frequency recognition range of the period detection circuit as the clock signal based on the clock selection signal.

5. The signal generating structure according to claim 3, characterized in that: The period detection circuit comprises: an oscillation circuit configured to oscillate based on the pulse signal to generate an oscillation signal with a preset period; The counting circuit is configured to count the number of oscillations of the oscillation signal within a pulse width time in the pulse signal, and generate the digital detection signal based on the number of oscillations.

6. The signal generating structure according to claim 5, characterized in that: include: The oscillation circuit comprises: a ring oscillator formed by cascading m stages of second inverters, where m is an odd number greater than 1; The period detection circuit further includes: a selection circuit, which is provided in the ring oscillator and configured to adjust the number of connected stages of the second inverter in the ring oscillator.

7. The signal generating structure according to claim 6, characterized in that: The processing circuit includes: a first processing unit, configured to obtain a period of the external clock signal based on the digital detection signal and a preset formula, wherein the preset formula is related to a preset period of the oscillation signal, a delay of each stage of the second inverter, and a multiplication factor setting of the frequency division signal; The second processing unit is configured to generate the delay control signal based on the period of the external clock signal and the preset delay correspondence; the preset delay correspondence indicates the correspondence between the period of the external clock signal and the number of delay cycles required to generate the column address selection signal.

8. The signal generating structure according to claim 3, characterized in that: The signal generating circuit comprises: a delay unit, configured to delay the first initial signal based on a delay control signal to generate the second initial signal; The merging unit is configured to generate the column address strobe signal based on the first initial signal and the second initial signal.

9. The signal generating structure according to claim 8, characterized in that: The delay control signal includes k delay control sub-signals, and the delay unit includes: A cascade of k-stage shift register circuits, wherein an input end of a first-stage shift register circuit is used to receive the first initial signal, an input end of a q-th-stage shift register circuit is connected to an output end of a q-1-th-stage shift register circuit, where 2≤q≤k, and an output end of a last-stage shift register circuit is used to output a second initial signal; Each of the shift register circuits is further configured to receive the external clock signal and a corresponding one of the delay control sub-signals.

10. The signal generating structure according to claim 9, characterized in that: The delay unit further includes: a delayer, wherein an input end of the delayer is connected to an output end of the last-stage shift register circuit, and the delayer is configured to delay a signal input to the delayer for a preset time; The merging unit is configured to generate the column address strobe signal based on the first initial signal and the delayed second initial signal output by the delayer.

11. The signal generating structure according to claim 9 or 10, characterized in that: When the delay control sub-signal is a valid signal, the shift register circuit corresponding to the delay control sub-signal performs a one-clock cycle delay on the signal received at its input terminal.

12. The signal generating structure according to any one of claims 8 to 10, characterized in that: The merging unit includes: a first SR latch based on a NOR gate, an S terminal of the first SR latch is used to receive the first initial signal, an R terminal is used to receive the second initial signal, and an output terminal is used to output the column address selection signal.

13. The signal generating structure according to any one of claims 8 to 10, characterized in that: The merging unit includes: a second SR latch based on a NAND gate, the S end of the second SR latch is used to receive the second initial signal, the R end is used to receive the first initial signal, and the output end is used to output the column address selection signal.

14. The signal generating structure according to claim 9, characterized in that: The shift register circuit includes: a first P-type transistor, having a first terminal serving as an input terminal of the shift register circuit and a second terminal connected to an input terminal of the third inverter and an output terminal of the fourth inverter; a first N-type transistor, having a first terminal serving as an input terminal of the shift register circuit and a second terminal connected to the input terminal of the third inverter and the output terminal of the fourth inverter; a first AND gate, having a first input terminal for receiving the corresponding delay control sub-signal, a second input terminal for receiving the inverted signal of the external clock signal, and an output terminal connected to the control terminal of the first P-type transistor; a first NAND gate, having a first input terminal for receiving the corresponding delay control sub-signal, a second input terminal for receiving the inverted signal of the external clock signal, and an output terminal connected to the control terminal of the first N-type transistor; a second P-type transistor, having a first terminal connected to the output of the third inverter and the input of the fourth inverter, and a second terminal connected to the input of the fifth inverter and the output of the sixth inverter; a second N-type transistor, having a first terminal connected to the output of the third inverter and the input of the fourth inverter, and a second terminal connected to the input of the fifth inverter and the output of the sixth inverter; a second AND gate, having a first input terminal for receiving the corresponding delay control sub-signal, a second input terminal for receiving the external clock signal, and an output terminal connected to the control terminal of the second P-type transistor; a second NAND gate, having a first input terminal for receiving the corresponding delay control sub-signal, a second input terminal for receiving the external clock signal, and an output terminal connected to the control terminal of the second N-type transistor; a third P-type transistor, having a first terminal for receiving a power supply voltage, a control terminal for receiving a shift reset signal, and a second terminal connected to the input terminal of the fifth inverter and the output terminal of the sixth inverter; The output end of the fifth inverter and the input end of the sixth inverter serve as the output end of the shift register circuit.

15. A memory, characterized in that: The invention comprises the signal generating structure according to any one of claims 1 to 14.

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