Embedded memory device and integrated circuit having same

Abstract

An embedded memory device and an integrated circuit having the same are disclosed. The embedded memory device includes: a hold voltage supply circuit outputting a hold voltage in response to a hold activation signal; and a plurality of array voltage supply circuits that output respective array voltages to respective bit cells. Each of the plurality of array voltage supply circuits includes: an array switch providing a hold voltage as a corresponding array voltage in response to a hold activation signal; a power switch providing a power voltage as the corresponding array voltage in response to a power gate activation signal; and an auxiliary circuit that compensates for the respective array voltage during a write operation or a read operation.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2023-0073590 filed on June 8, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0002] The present disclosure relates to embedded memory devices and more particularly to embedded memory devices and integrated circuits having embedded memory devices. Background Art

[0003] Typically, a diode retention circuit is a circuit used in a static random access memory (SRAM). Typically, a diode retention circuit is configured by connecting a diode between each inverter and a power supply terminal. The diode serves to maintain the data between the power supply and the inverter. The diode retention circuit is used to improve data retention in the SRAM. The diode provides a reverse voltage so that the data can be retained even when the power is cut off or a fault occurs, thereby improving the stability of the SRAM cell and preventing data loss. The diode retention circuit is an important factor in ensuring data retention while significantly reducing the power consumption of the SRAM. The circuit allows the SRAM to maintain accurate data even when the power is restored or the fault is cleared. Summary of the invention

[0004] In general, in some aspects, the disclosed subject matter is directed to embedded memory devices in which variations in retention circuits may be reduced, integrated circuits having embedded memory devices, and methods of operating embedded memory devices.

[0005] One or more embodiments provide an embedded memory device, an integrated circuit having the embedded memory device, and a method of operating the embedded memory device, in which a time to enter a hold operation and a time to enter a normal operation mode can be optimally varied according to a size of the embedded memory device generated by a memory compiler.

[0006] According to some embodiments, an embedded memory device includes: a retention voltage supply circuit that outputs a retention voltage in response to a retention activation signal; and a plurality of array voltage supply circuits that output corresponding array voltages to corresponding bit cells. The plurality of array voltage supply circuits each include: an array switch that provides the retention voltage as a corresponding array voltage in response to the retention activation signal; a power switch that provides a power voltage as the corresponding array voltage in response to a power gate activation signal; and an auxiliary circuit for compensating the corresponding array voltage during a write operation or a read operation.

[0007] According to some embodiments, an embedded memory device includes: a first cell array, a second cell array, a third cell array, and a fourth cell array; a first row decoder disposed in the first cell array and the second cell array; a second row decoder disposed in the third cell array and the fourth cell array; a first array voltage supply circuit that provides a first array voltage to the first cell array; a second array voltage supply circuit that provides a second array voltage to the second cell array; a third array voltage supply circuit that provides a third array voltage to the third cell array; a fourth array voltage supply circuit that provides a fourth array voltage to the fourth cell array; and a retention diode controller that controls the first array voltage supply circuit to the fourth array voltage supply circuit to share a retention voltage in a retention operation mode.

[0008] According to some embodiments, an integrated circuit includes: at least one processor; and a memory device storing data required for operation of the at least one processor. The memory device includes: a plurality of memory banks having a plurality of bit cells connected between word lines and bit lines; an array voltage supply circuit providing an array voltage corresponding to each of the plurality of memory banks; and a retention diode controller controlling the array voltage supply circuit to share a retention voltage in a retention operation mode.

[0009] According to some embodiments, a method of operating an integrated circuit includes: setting a hold time for entering a retention mode of operation from a normal operation mode according to a memory size using an RC delay; and setting a recovery time for entering a normal operation mode from the retention mode of operation according to the memory size. In the retention mode of operation, a retention voltage of an array voltage supply circuit is shared. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The features of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a diagram illustrating an example of an embedded memory device 10 according to some embodiments;

[0012] Figure 2 is a diagram showing that according to some embodiments Figure 1 A diagram of an example of a bit cell 12 shown in FIG.

[0013] Figure 3 is a diagram illustrating an example of an array voltage management circuit 100 according to some embodiments;

[0014] Figure 4 is a diagram showing that according to some embodiments Figure 3 A diagram of an example operation timing of the memory device shown in;

[0015] Figure 5 is a diagram illustrating an example of an embedded memory device 200 according to some embodiments;

[0016] Figure 6 is a diagram showing that according to some embodiments Figure 5 A diagram of an example of an array voltage supply circuit 241 shown in FIG.

[0017] Figure 7 is a diagram showing that according to some embodiments Figure 5 A diagram of an example of a holding diode controller 250 is shown in FIG.

[0018] Figure 8 is a diagram illustrating an example operation of generating switching signals PD_IO and RETD_IO of the holding diode controller 250 according to some embodiments;

[0019] Fig. 9 is a diagram illustrating an example of a voltage control circuit 300 according to some embodiments;

[0020] Fig.10 is a flowchart illustrating an example method of operating an integrated circuit according to some embodiments; and

[0021] Fig.11 is a diagram illustrating an example of a system on chip (SOC) according to some embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0023] The embedded memory device, the integrated circuit having the embedded memory device and the method of operating the embedded memory device according to some embodiments of the present invention can reduce the leakage current in the diode retention mode by reducing the array voltage when performing the retention operation on the memory of various sizes generated by the memory compiler. Therefore, during the transition from the diode retention mode to the standby mode, the data of the embedded memory device can be well maintained.

[0024] The embedded memory device can be applied to a memory device using array voltage (VDDA) collapse write assist by equipping it with an array switch (MPAS), and the embedded memory device can reduce diode variation by sharing the diode drain voltage between sub-arrays. In the embedded memory device, by using a metal RC (resistance-capacitance) delay intersecting an input-output line instead of an inverter delay, an optimized diode retention mode transition time can be provided according to the size of a memory instance (such as the number of bits per word or input / output (I / O)).

[0025] Figure 1 is a diagram showing an example of an embedded memory device 10 according to some embodiments. Figure 1 , the embedded memory device 10 includes a cell array 11 , a column driver 13 , a sense amplifier circuit (S / A) 14 , a row driver 15 , and a control logic 16 .

[0026] The embedded memory device 10 may receive an address ADDR, a clock CLK, a command CMD, and write data W_DATA. For example, the embedded memory device 10 may receive a command CMD ("write command") indicating a write operation, an address ADDR ("write address") to which the write data W_DATA will be stored, and the write data W_DATA, and the write data W_DATA may be stored in a target area corresponding to the write address of the cell array 11. In addition, the embedded memory device 10 may receive a command CMD ("read command") indicating a read and an address ADDR ("read address") in which the read data R_DATA is stored, and the read data R_DATA stored in the target area corresponding to the read address of the cell array 11 may be output externally.

[0027] The cell array 11 includes a plurality of bit cells 12. In the cell array 11, the plurality of bit cells 12 may be arranged at regular intervals. The plurality of bit cells 12 may be provided at points where word lines WL and bit lines BL intersect. In detail, the plurality of bit cells 12 may be connected to at least one of the plurality of word lines WL, respectively, and may be connected to at least one of the plurality of bit lines BL.

[0028] Each of the plurality of bit cells 12 may be a memory cell. In some embodiments, each of the plurality of bit cells 12 is a volatile memory cell. For example, each of the plurality of bit cells 12 may be a static random access memory (SRAM) cell. For example, each of the plurality of bit cells 12 may be a dual-port SRAM (DPSRAM) cell capable of performing a write operation and a read operation simultaneously. In some embodiments, each of the bit cells 12 may be a non-volatile memory cell (such as a flash memory or a resistive random access memory (RRAM)).

[0029] In some embodiments, the cell array 11 is divided into a plurality of sub-arrays. In this case, the bit cell 12 may not be disposed at the boundary of the sub-array. The number of word lines (WL) / bit lines (BL) included in each sub-array may be the same or different from each other. The embedded memory device 10 may be implemented to perform an access operation on at least one of the sub-arrays.

[0030] The column driver 13 may be connected to the cell array 11 through a plurality of bit lines BL. The column driver 13 may be implemented to select at least one bit line from among the plurality of bit lines BL based on a column address Y_ADD. The column driver 13 may select at least one of the plurality of sub-arrays based on a sub-array address S_ADD. The sub-array address S_ADD may be an address based on a row address X_ADD. For example, the column driver 13 may select a bit line and a complementary bit line included in the sub-array based on the column address Y_ADD and the sub-array address S_ADD. In this case, the bit line and the complementary bit line may be connected to at least one of the plurality of bit cells 12. When the column driver 13 selects a bit line and a complementary bit line, a plurality of bit cells 12 connected to the bit line and the complementary bit line may be selected.

[0031] The column driver 13 may perform a read operation or a write operation based on the control signal CTR. The column driver 13 senses a current or a voltage received through the plurality of bit lines BL, thereby identifying a value stored in a bit cell 12 connected to an activated word line among the plurality of bit cells 12, and outputs read data R_DATA based on the identified value.

[0032] In addition, the column driver 13 applies a current or a voltage to the plurality of bit lines BL based on the write data W_DATA, and may write a value into a bit cell connected to the activated word line among the plurality of bit cells 12. According to some embodiments, the column driver 13 includes a read circuit that performs a read operation and a write circuit that performs a write operation. The column driver 13 may include a bit line precharge circuit that precharges the plurality of bit lines BL.

[0033] The sense amplifier circuit (S / A) 14 may be implemented to output read data R_DATA by amplifying a difference between signals output from the column driver 13 .

[0034] The row driver 15 may be connected to the cell array 11 through a plurality of word lines WL. The row driver 15 may be implemented to activate at least one word line among the plurality of word lines WL based on a row address X_ADD. When the row driver 15 selects at least one word line among the plurality of word lines WL based on the row address X_ADD, a bit cell 12 connected to the activated word line among the plurality of bit cells 12 may be selected.

[0035] The control logic 16 may receive an address ADDR, a clock CLK, a command CMD, and write data W_DATA, and may be implemented to generate a row address X_ADD, a column address Y_ADD, a subarray address S_ADD, and a control signal CTR. For example, the control logic 16 may identify a read command by decoding the command CMD, and generate a row address X_ADD, a column address Y_ADD, a subarray address S_ADD, and a control signal CTR to read the read data R_DATA from the cell array 11. In addition, the control logic 16 may identify a write command by decoding the command CMD, and generate a row address X_ADD, a column address Y_ADD, a subarray address S_ADD, and a control signal CTR to write the write data W_DATA to the cell array 11.

[0036] The embedded memory device 10 according to some embodiments further includes an array voltage management circuit. The array voltage management circuit may include a power switch (or power switch transistor) MPPS, a transistor diode MPD, a diode switch (or diode switch transistor) MPDS, and an array switch (or array switch transistor) MPAS, wherein the power switch MPPS is used to supply the array voltage VDDA to the cell array 11, the diode switch MPDS is turned on when the diode is held, and the array switch MPAS is connected to the array voltage VDDA separated from each column (e.g., independent). In some embodiments, the array switch MPAS, the transistor diode MPD, and the diode switch MPDS are connected in series. In some embodiments, the array switch MPAS-transistor diode MPD-diode switch MPDS connected in series to the power switch MPPS are connected in parallel. In some embodiments, the drain of the transistor diode MPD is shared between sub-arrays. In some embodiments, the gate signal generators of the power switch MPPS, the transistor diode MPD, and the array switch MPAS are implemented using input / output metal RC delays.

[0037] The embedded memory device 10 according to some embodiments uses a transistor diode MPD in a diode hold mode to reduce the array voltage VDDA to an external cell power supply voltage (external cell VDD; VDDCE), thereby reducing leakage current of the memory cell. The embedded memory device 10 according to some embodiments can be applied to an array to which VDDA collapse write assist is applied.

[0038] In the embedded memory device 10, diode variations can be reduced by sharing the diode drain voltage not only within a subarray but also between subarrays or banks. In addition, the embedded memory device 10 uses metal RC delays instead of delay chains, thereby providing a mode transition time optimized for the size of the memory instance.

[0039] Figure 2 is a diagram showing that according to some embodiments Figure 1 FIG. 1 is a diagram of an example of a bit cell 12 shown in FIG. Figure 2 The bit cell 12 includes a first pass transistor PG1, a second pass transistor PG2, a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, and a second pull-down transistor PD2.

[0040] In some embodiments, the first and second pass transistors PG1 and PG2 and the first and second pull-down transistors PD1 and PD2 are N-type transistors, and the first and second pull-up transistors PU1 and PU2 may be P-type transistors.

[0041] In some embodiments, the first and second pass transistors PG1 and PG2 and the first and second pull-down transistors PD1 and PD2 are N-channel metal oxide semiconductor field effect transistors (MOSFETs), and the first and second pull-up transistors PU1 and PU2 may be P-channel MOSFETs (PFETs).

[0042] In some embodiments, the first pull-up transistor PU1 and the first pull-down transistor PD1 constitute a first inverter IV1, and the second pull-up transistor PU2 and the second pull-down transistor PD2 constitute a second inverter IV2. In detail, the drain terminal of the first pull-up transistor PU1 may be connected to the drain terminal of the first pull-down transistor PD1, and the gate of the first pull-up transistor PU1 may be electrically connected to the gate of the first pull-down transistor PD1. The power supply voltage VDD may be applied to the source terminal of the first pull-up transistor PU1, and the ground voltage VSS may be applied to the source terminal of the first pull-down transistor PD1. Therefore, the first pull-up transistor PU1 and the first pull-down transistor PD1 may constitute a first inverter IV1.

[0043] Similarly, the drain terminal of the second pull-up transistor PU2 may be connected to the drain terminal of the second pull-down transistor PD2, and the gate of the second pull-up transistor PU2 may be electrically connected to the gate of the second pull-down transistor PD2. The power supply voltage VDD may be applied to the source terminal of the second pull-up transistor PU2, and the ground voltage VSS may be applied to the source terminal of the second pull-down transistor PD2. Therefore, the second pull-up transistor PU2 and the second pull-down transistor PD2 may constitute a second inverter IV2. The gate of the first pull-up transistor PU1 and the gate of the first pull-down transistor PD1 connected to each other may correspond to the input terminal of the first inverter IV1, and the first node N1 connected to the drain terminal of the first pull-up transistor PU1 and the drain terminal of the first pull-down transistor PD1 may correspond to the output terminal of the first inverter IV1. The gate of the second pull-up transistor PU2 and the gate of the second pull-down transistor PD2 connected to each other may correspond to the input terminal of the second inverter IV2, and the second node N2 connected to the drain terminal of the second pull-up transistor PU2 and the drain terminal of the second pull-down transistor PD2 may correspond to the output terminal of the second inverter IV2.

[0044] In some embodiments, the first inverter IV1 and the second inverter IV2 are connected in a latch structure. In detail, the gate of the first pull-up transistor PU1 and the gate of the first pull-down transistor PD1 may be connected to the second node N2, and the gate of the second pull-up transistor PU2 and the gate of the second pull-down transistor PD2 may be connected to the first node N1. One end of the first transfer transistor PG1 may be connected to the first node N1, and the other end of the first transfer transistor PG1 may be connected to the bit line BL. One end of the second transfer transistor PG2 may be connected to the second node N2, and the other end of the second transfer transistor PG2 may be connected to the complementary bit line BLb. The gate of the first transfer transistor PG1 and the gate of the second transfer transistor PG2 may be connected to the word line WL.

[0045] The bit cell 12 may write logic data through the first node N1 and the second node N2 using the word line WL, the bit line BL, and the complementary bit line BLb, or may read logic data through the first node N1 and the second node N2.

[0046] Figure 3 is a diagram illustrating an array voltage management circuit 100 according to some embodiments.

[0047] Reference Figure 3 , the array voltage management circuit 100 includes array voltage supply circuits 121 to 12Y that provide array voltages VDDA[1] to VDDA[Y], and a holding voltage supply circuit 130, where Y is an integer greater than 1.

[0048] The first array voltage supply circuit 121 may include an array voltage switch ASW, a power switch PSW, and an auxiliary circuit 121 - 1 .

[0049] The array voltage switch ASW is connected to the shared hold voltage supply circuit 130 and may be implemented to provide a first array voltage VDDA[1] corresponding to a hold voltage (or diode hold voltage) VRETD in a hold operation mode (or, hold operation or hold mode).

[0050] The power switch PSW may be implemented to provide a first array voltage VDDA[1] corresponding to the power supply voltage VDD in a normal operation mode (or, normal operation or normal mode).

[0051] The auxiliary circuit 121 - 1 may be implemented to provide a corresponding first array voltage VDDA[ 1 ] in a write operation or a read operation.

[0052] The array voltage supply circuits 12I to 12Y may be implemented identically or similarly to each other.

[0053] The holding voltage supply circuit 130 may include a diode switch DSW and a holding circuit 131. The diode switch DSW may be implemented to provide a power supply voltage VDD to the holding circuit 131 in a holding operation mode. In some embodiments, the diode switch DSW may include a P-channel metal oxide semiconductor (PMOS) transistor. In some embodiments, the array voltage switch ASW, the power switch PSW, or both the array voltage switch ASW and the power switch PSW may include a PMOS transistor. The holding circuit 131 may include at least one diode. In this case, the diode may be implemented as a transistor diode.

[0054] The embedded memory device 10 may provide a retention operation and a power-off operation, wherein the retention operation reduces the array voltage VDDA to a minimum voltage VMIN that can maintain data to significantly reduce leakage while maintaining memory data, and the power-off operation is used to disconnect the power supplied to the array voltage VDDA without maintaining data. In some embodiments, the embedded memory device 10 selectively operates or enters the retention operation and the power-off operation as needed.

[0055] When entering the retention operation, after the retention switches (e.g., the diode switch DSW and the array voltage switch ASW) are closed, the power switch PSW is turned off to properly save the data, and thus the array voltage VDDA can always be greater than the minimum voltage VMIN. In addition, when entering the normal mode from the retention operation mode, since the power switch PSW is first closed and then the retention switches DSW and ASW are turned off, the drop of the array voltage VDDA can be prevented.

[0056] The auxiliary circuit 121-1 for controlling the array voltage VDDA can be used to assist the write operation and the read operation of the memory. Since the memory device having a column multiplexer (MUX) structure should control the array voltage VDDA of only the selected column, the array voltage VDDA is separated for each column.

[0057] Since a general memory device includes a separate holding circuit for each column, the holding / recovery time varies greatly. Meanwhile, the embedded memory device 10 according to some embodiments uses a holding voltage supply circuit 130 shared by the columns, and therefore, the influence of time fluctuations can be significantly reduced. The embedded memory device 10 according to some embodiments can provide a shared holding voltage supply circuit 130 to reduce the variation of the holding / recovery time even when the array voltage VDDA is separated for each column.

[0058] Figure 4 is a diagram showing that according to some embodiments Figure 3 FIG. 1 is a diagram showing the operation timing of the memory device shown in FIG. Figure 4 As shown in , the array voltage VDDA can be adjusted by controlling the power gate activation signal PG_EN and the retention activation signal RET_EN.

[0059] For example, in the hold mode of operation (e.g. Figure 4 In the "maintain" state, the power gate activation signal PG_EN has a low level, and the retention activation signal RET_EN has a high level. At this time, the array voltage VDDA can maintain the minimum voltage VMIN. Figure 4 As shown in RET is the time used to enter the hold operation.

[0060] In addition, in normal operating mode (e.g. Figure 4 In the "normal" state, the power gate activation signal PG_EN has a high level, and the retention activation signal RET_EN has a low level. At this time, the array voltage VDDA can maintain the power supply voltage VDD. Figure 4 As shown in REC is the time used to return to normal operation.

[0061] In addition, in power-down mode (for example, Figure 4 In the case of "power-off" in the embodiment, the power gate activation signal PG_EN has a low level, and the retention activation signal RET_EN has a low level. At this time, the array voltage VDDA can maintain the ground voltage GND.

[0062] The memory device 10 according to some embodiments provides a retention time t for entering a retention operation. RET and the recovery time t for returning to normal operationREC , and can therefore have the best time (t RET , t REC ), the retention operation varies according to the various sizes of the memory device 10 generated by the SRAM compiler.

[0063] One or more features of the above-described embodiments are applicable to embodiments of a memory device including a plurality of cell arrays.

[0064] Figure 5 is a diagram illustrating an embedded memory device 200 according to some embodiments. Figure 5 , the embedded memory device 200 includes a plurality of cell arrays 211 , 212 , 213 , and 214 , row decoders 221 and 222 (eg, central decoders XDEC1 221 and XDEC2 222 ), array voltage supply circuits 241 , 242 , 243 , and 244 , and a holding diode controller 250 .

[0065] Each of the array voltage supply circuits 241, 242, 243, and 244 has a structure in which an array switch MPAS is added between the array voltage VDDA and the drain of the transistor diode MPD. Each of the array voltage supply circuits 241, 242, 243, and 244 turns off the array switch MPAS when performing a VDDA collapse operation, and can thus be prevented from being affected by the transistor diode MPD. On the other hand, in each of the array voltage supply circuits 241, 242, 243, and 244, the source voltage of the array switch MPAS (e.g., the diode holding voltage VRETD) instead of the array voltage VDDA can be shared by all columns.

[0066] like Figure 5 As shown in , when central decoders XDEC1 and XDEC2 are used, the source voltage VRETD can be shared between the left input output (IO) and the right IO. In addition, when two memory banks (e.g., memory bank 1 and memory bank 2) are used, the source voltage VRETD can be shared between the memory banks. Therefore, the diode variation can be significantly reduced by sharing a relatively large number of transistor diodes MPD.

[0067] Additionally, layout optimization may be relatively easy by disposing the diode switch MPDS and the transistor diode MPD in only one region between two memory banks without inserting the diode switch MPDS and the transistor diode MPD for each memory bank.

[0068] In the embedded memory device 200 according to some embodiments, even when each column has a separate array voltage VDDA, the embedded memory device 200 can be implemented so that the array switch MPAS is inserted between the array voltage VDDA and the drain node of the diode to have a shared holding circuit (e.g., a diode), and the diode holding voltage VRETD can be shared within the SRAM array. In some embodiments, by sharing the diode holding voltage VRETD between both sides of the holding diode controller 250 and / or between memory banks in the SRAM array, diode variation can be significantly reduced.

[0069] Figure 6 is a diagram showing that according to some embodiments Figure 5 241 is a diagram of an array voltage supply circuit 241 shown in FIG. Figure 6 , the array voltage supply circuit 241 includes power switch transistors MPPS<1:4>, MPPS<5:8>, . . . , MPPS <y-3:y>, diode switch transistor MPDS <1> 、MPDS <2> 、……、MPDS <y 4>, diode transistor MPD <1> 、MPD <2> 、……、MPD <y 4>, and array switch transistors MPAS<1:4>, MPAS<5:8>, ..., MPAS <y-3:y>In some implementations, at least one of the power switch transistor MPPS, the diode switch transistor MPDS, the diode transistor MPD, and the array switch transistor MPAS may include a PMOS transistor.

[0070] When VDDA collapse write assist is used to improve the writability of the embedded memory device 200, the array voltage VDDA (eg, array voltages VDDA<1:4>, VDDA<5:8>, . . . , ... <y-3:y>) can be separated for each column to collapse the array voltage VDDA for only the selected columns.

[0071] Figure 7 is a diagram showing that according to some embodiments Figure 5 FIG. 2 is a diagram of a holding diode controller 250 shown in FIG. Figure 7 , the holding diode controller 250 receives the holding signal RET and the power activation signal PDE, and can be implemented to output a combined signal of the holding signal RET and the power activation signal PDE as two switch signals PD_IO and RETD_IO (e.g., the power-off signal PD_IO and the holding diode activation signal RETD_IO) by using RC delay. It should be understood that Figure 7 The logic circuit of the holding diode controller 250 shown in FIG. 2 is only an example.

[0072] Conventional retention diode controllers use a chain of inverters to generate fixed delays used in non-overlapping signal generators. In contrast, retention diode controller 250 according to some embodiments may be implemented using RC delays of metal wiring that become longer as the number of columns of an SRAM instance increases. Thus, retention diode controller 250 may generate a t delay that becomes larger as the number of SRAM columns increases. RET and t REC The two switching signals PD_IO and RETD_IO.

[0073] Figure 8 is a diagram illustrating an operation of generating switching signals PD_IO and RETD_IO of the holding diode controller 250 according to some embodiments.

[0074] In the embedded memory device 200, when transitioning from normal operation to retention operation, the diode switch MPDS farthest from the retention diode controller 250 is turned on, and by generating a power-off signal PD_IO using a subsequent retention diode activation signal RETD_IO to turn off the diode switch MPDS, a stable retention voltage VRET input can be ensured.

[0075] In addition, when the embedded memory device 200 transitions from the retention operation to the normal operation, by turning on the farthest located power switch MPPS and using the returned signal PD_IO, recovery may be stably performed by generating the signal RETD_IO to turn off the diode switch MPDS.

[0076] In an embedded memory device according to some embodiments, t RET and t REC In detail, the embedded memory device 200 according to some embodiments can track and generate metal wiring that becomes longer due to the number of IOs. When designing an SRAM compiler, it is necessary to set the t RET and t REC Compared to a method designed to be constant, an embedded memory device according to some embodiments may provide a smaller t due to fewer IOs being used. RET and t REC .

[0077] Fig. 9 is a diagram showing a voltage control circuit 300 according to some embodiments. Fig. 9 , the voltage control circuit 300 includes an array voltage supply circuit 341 and a holding diode controller 350 .

[0078] The array voltage supply circuit 341 and Figure 6 The array voltage supply circuit 241 is implemented similarly, and may also include a write assist circuit (eg, write assist <1:4>, write assist <5:8>, . . . , write assist <y-3:y>). Maintaining diode controller 350 and Figure 7 The holding diode controller 250 is similarly implemented and may also include a transistor that provides the holding voltage VRETD in response to the switching signal MPREF.

[0079] Fig.10 is a flow chart illustrating a method of operating an integrated circuit according to some embodiments. Figures 1 to 10 , the method of operating the integrated circuit is as follows. The retention time is set according to the size of the SRAM using RC delay (S110). In this case, the SRAM size can be determined by the SRAM compiler. The retention time can be determined using a shared diode. Thereafter, a recovery time corresponding to the size of the SRAM is set (S120).

[0080] In some embodiments, the memory size is set in the memory compiler. In some embodiments, in the normal operation mode, the power gate activation signal is maintained at a high level, and the hold activation signal may be maintained at a low level. In some embodiments, in the hold operation mode, the power gate activation signal is maintained at a low level, and the hold activation signal may be maintained at a high level. In some embodiments, in the power-off mode, the power gate activation signal is maintained at a low level, and the hold activation signal may be maintained at a low level.

[0081] Fig.11 1 is a diagram illustrating a system on chip (SOC) according to some embodiments. The SOC 1000 is an embodiment of a complex functional block (such as intellectual property (IP)) that performs various functions on a single chip, and a bit cell set according to some embodiments may be included in a corresponding functional block of the SOC 1000.

[0082] Reference Fig.11 , the SOC 1000 includes a modem 1200, a display controller 1300, a memory device 1400, an external memory controller 1500, a central processing unit (CPU) 1600, a transaction unit 1700, a power management integrated circuit (PMIC) 1800, and a graphics processing unit (GPU) 1900. The respective functional blocks of the SOC 1000 may communicate with each other through a system bus 1100. The CPU 1600, which may control the overall operation of the SOC 1000, may control the operations of the other functional blocks 1200, 1300, 1400, 1500, 1700, 1800, and 1900.

[0083] The modem 1200 may demodulate a signal received from outside the SOC 1000 or modulate a signal generated inside the SOC 1000 and transmit the signal externally. The display controller 1300 may transmit data generated inside the SOC 1000 to a display by controlling a display (or display device) outside the SOC 1000.

[0084] The memory device 1400 may include a non-volatile memory (such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM). The memory device 1400 may also include a volatile memory (such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a mobile DRAM, a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power DDR (LPDDR) SDRAM, a graphic DDR (GDDR) SDRAM, and a Rambus dynamic random access memory (RDRAM). As described with reference to Figures 1 to 10 As described above, the memory device 1400 may be implemented as an embedded memory device that shares a retention circuit.

[0085] The external memory controller 1500 may control an operation of transmitting and receiving data from an external integrated circuit connected to the SOC 1000. For example, a program or data stored in the external integrated circuit may be provided to the CPU 1600 or the GPU 1900 under the control of the external memory controller 1500.

[0086] The transaction unit 1700 may monitor data transactions of the respective functional blocks, and the PMIC 1800 may control power supplied to the respective functional blocks according to control of the transaction unit 1700 .

[0087] The GPU 1900 may execute program instructions related to graphic processing. The GPU 1900 may receive graphic data through the external memory controller 1500, and may also transmit the graphic data processed by the GPU 1900 to the outside of the SOC 1000 through the external memory controller 1500.

[0088] The device described above can be implemented as a hardware component, a software component, or a combination of a hardware component and a software component. For example, the device and components described in the example embodiment can be implemented using one or more general-purpose computers or special-purpose computers and processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors, or any other device that can execute instructions and respond. The processing device can run an operating system (OS) and one or more software applications running on the operating system. The processing device can also access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, sometimes a processing device is described, but those skilled in the art will understand that the processing device may include multiple processing elements or multiple types of processing elements. For example, the processing device may include multiple processors, or a processor and a controller. In addition, other processing configurations are feasible, such as parallel processors.

[0089] Software may include computer programs, codes, instructions, or a combination of one or more of them, and may configure a processing device to operate as needed or to command the processing device independently or collectively. Software or data may be embodied in any tangible machine, component, physical device, virtual device, computer storage medium, or device to interpret instructions or data by or to provide instructions or data to the processing device. Software may be distributed on networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer readable media.

[0090] Typically, a memory structure specifies definitions of circuit elements and data defining rules for combining these circuit elements to create a memory instance. The specific requirements of the memory instance are input into the memory compiler as input parameters through a graphical user interface (GUI). For example, the input parameters may specify various aspects of the desired memory instance that define the selection of various optional features (such as power gate features, the size of the memory array, the reuse placement of the memory array, and the built-in self-test (BIST) mode to be supplied, etc.). In addition, the memory compiler creates the desired memory instance based on the memory structure and the input parameters. The memory compiler according to some embodiments includes the required components for the shared retention circuit. A general-purpose computer that can be used to perform the memory compilation operations described above can be used to create such a memory instance.

[0091] Embodiments of the present disclosure may be used for diodes and diode control of SRAM compilers. In some embodiments, an SRAM compiler diode hold mode is provided, and the hold and recovery time may be optimized. In some embodiments, even in an SRAM using a VDDA crash write assist circuit, a diode hold mode is provided by diode sharing between subarrays using a relatively small size diode. According to some embodiments, optimal hold and recovery time may be provided in SRAMs of various sizes generated by a compiler. In an embedded memory device according to some embodiments, a switch may be inserted between a diode and VDDA. An embedded memory device according to some embodiments may share a source voltage VRETD of a diode with both sides of control. In an embedded memory device according to some embodiments, a diode is inserted in only one IO region between cell arrays in a 2-memory body structure, and a diode source voltage VRETD is shared between memory bodies. An embedded memory device according to some embodiments includes a diode controller and a switch group providing both a power-off mode and a hold mode. An embedded memory device according to some embodiments may include a diode controller using an RC delay through metal wiring, which becomes longer according to the number of columns (IO) during the transition from a hold mode to a normal mode. An embedded memory device according to some embodiments may include a diode controller using an RC delay through a metal wiring that becomes longer according to the number of columns (IOs) when transitioning from a normal mode to a retention mode.

[0092] As described above, in an embedded memory device, an integrated circuit having the embedded memory device, and a method of operating the embedded memory device according to some embodiments, leakage of a memory cell is reduced using a PMOS diode in a retention operation mode.

[0093] In an embedded memory device, an integrated circuit having the embedded memory device, and a method of operating the embedded memory device according to some embodiments, retention fluctuation may be reduced by sharing a diode drain voltage between sub-arrays or between memory banks.

[0094] An embedded memory device, an integrated circuit having an embedded memory device, and a method of operating an embedded memory device according to some embodiments may use metal RC delays to provide a mode transition time optimized for the size of the memory instance.

[0095] Although the present disclosure includes many specific implementation details, these should not be interpreted as limitations on the scope of protection that can be claimed. Specific features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in a specific combination and even initially claimed as such, in some cases, one or more features from a combination may be removed from the combination, and a combination may point to a sub-combination or a variation of a sub-combination.

[0096] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of some embodiments as defined by the appended claims. < / y> < / y>

Claims

1. An embedded memory device, include: a sustain voltage supply circuit configured to output a sustain voltage in response to a sustain activation signal; as well as A plurality of array voltage supply circuits are configured to output a plurality of array voltages to a plurality of bit cells, respectively. Wherein, each of the plurality of array voltage supply circuits comprises: an array switch configured to provide a hold voltage as a corresponding array voltage in response to a hold activation signal, a power switch configured to provide a power supply voltage as the corresponding array voltage in response to a power gate activation signal, and The auxiliary circuit is configured to compensate the corresponding array voltage during a write operation or a read operation.

2. The embedded memory device according to claim 1, in, The holding voltage supply circuit includes: a hold switch configured to connect to the power terminal in response to a hold activation signal; and The holding circuit is connected between the holding switch and the plurality of array voltage supply circuits.

3. The embedded memory device according to claim 2, in, The holding switch includes a P-channel metal oxide semiconductor transistor.

4. The embedded memory device according to claim 2, in, The holding circuit includes a transistor diode.

5. The embedded memory device according to claim 2, in, The array switch, the power switch, or both the array switch and the power switch include P-channel metal oxide semiconductor transistors.

6. The embedded memory device according to claim 1, in, In the hold operation mode, the array switch of each array voltage supply circuit is configured to receive a hold activation voltage at a high level, and the power switch of each array voltage supply circuit is configured to receive a power gate activation signal at a low level.

7. The embedded memory device according to claim 1, in, In a normal operation mode, the array switch of each array voltage supply circuit is configured to receive a hold activation signal at a low level, and the power switch of each array voltage supply circuit is configured to receive a power gate activation signal at a high level.

8. The embedded memory device according to claim 1, in, In the power-off mode, the array switch of each array voltage supply circuit is configured to receive a hold activation signal at a low level, and the power switch of each array voltage supply circuit is configured to receive a power gate activation signal at a low level.

9. The embedded memory device according to any one of claims 1 to 8, further comprising: include: a holding diode controller configured to generate a holding activation signal and a power gate activation signal, Therein, the holding voltage is shared between two sides of a holding diode controller and / or shared between multiple memory banks.

10. The embedded memory device according to any one of claims 1 to 8, in, The holding voltage supply circuit is provided in a region between the first memory bank and the second memory bank.

11. An embedded memory device, include: a first unit array, a second unit array, a third unit array, and a fourth unit array; A first row decoder is disposed in the first cell array and the second cell array; A second row decoder is arranged in the third unit array and the fourth unit array; a first array voltage supply circuit configured to provide a first array voltage to a first cell array; a second array voltage supply circuit configured to provide a second array voltage to a second cell array; a third array voltage supply circuit configured to provide a third array voltage to a third cell array; a fourth array voltage supply circuit configured to provide a fourth array voltage to a fourth cell array; as well as The holding diode controller is configured to control the first array voltage supply circuit to the fourth array voltage supply circuit to share the holding voltage in the holding operation mode.

12. The embedded memory device according to claim 11, in, The first to fourth array voltage supply circuits are configured to each provide an individual array voltage for at least one column.

13. The embedded memory device according to claim 11, in, The first array voltage supply circuit to the fourth array voltage supply circuit each include: at least one power switch transistor connected to the power terminal in response to the power-off signal; at least one diode switching transistor connected to the power supply terminal in response to a hold signal; at least one diode transistor connected to the drain of the at least one diode switch transistor and having a drain outputting a holding voltage; and At least one array switch transistor is connected to the drain of the at least one diode transistor in response to a hold signal.

14. The embedded memory device according to claim 13, in, At least one of the at least one power switch transistor, the at least one diode switch transistor, the at least one diode transistor, and the at least one array switch transistor comprises a P-channel metal oxide semiconductor transistor.

15. The embedded memory device according to claim 13, in, The retention diode controller generates a power-off signal and a retention signal using resistance-capacitance delay of metal wiring that varies according to the number of columns of the memory instance.

16. An integrated circuit, include: at least one processor; as well as a memory device configured to store data for operation of the at least one processor, Wherein, the memory device comprises: A plurality of memory banks having a plurality of bit cells connected between a plurality of word lines and a plurality of bit lines, a plurality of array voltage supply circuits configured to respectively provide a plurality of array voltages corresponding to the plurality of memory banks, and A holding diode controller is configured to control the plurality of array voltage supply circuits to share a holding voltage in a holding operation mode.

17. The integrated circuit according to claim 16, in, Each of the plurality of array voltage supply circuits comprises: at least one power switch transistor connected to the power terminal in response to the power-off signal; at least one diode switching transistor connected to the power supply terminal in response to a hold signal; at least one diode transistor connected to the drain of the at least one diode switch transistor and having a drain outputting a holding voltage; and At least one array switch transistor is connected to the drain of the at least one diode transistor in response to a hold signal.

18. The integrated circuit according to claim 17, in, Each of the plurality of array voltage supply circuits further includes a write assist circuit configured to compensate an array voltage during a write operation.

19. The integrated circuit according to claim 17, in, The holding diode controller is configured to output a holding signal and a power-off signal by combining one or more of a holding activation signal, a holding diode activation signal, and a power-off activation signal.

20. The integrated circuit according to claim 17, in, The retention diode controller is configured to output a retention signal and a power-off signal to have a resistance-capacitance delay that is variable according to an instance size of the memory.

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