Manufacturing method of power semiconductor device

Abstract

The invention discloses a manufacturing method of a power semiconductor device, which comprises the following steps of: etching on a semiconductor substrate to form a gate trench, and then integrally forming an oxide layer on the surface of the semiconductor substrate; polycrystalline silicon is deposited and filled in the groove; carrying out a global CMP grinding process, grinding the polycrystalline silicon on the surface of the semiconductor substrate until the surface of the oxide layer is reached, and removing all the polycrystalline silicon on the surface; performing an oxide layer etching process to remove an oxide layer possibly existing on the surface of the polycrystalline silicon; and carrying out a polycrystalline silicon etching process, and continuously carrying out over-etching on the polycrystalline silicon to ensure that the polycrystalline silicon on the surface is completely etched. According to the method, the global CMP process is carried out after the polycrystalline silicon deposition is completed, and then the surface of the polycrystalline silicon is etched by adopting the dry etching process for reducing the etching amount, so that the etching residue is eliminated, the process duration is shortened, and the etching loss of the gate dielectric layer is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices and process manufacturing, and in particular to a method for manufacturing a power semiconductor device. Background Art

[0002] In power semiconductor devices, the gate-source drive current IGSS failure analysis of a low-voltage SGT (separate gate trench device) product shows residual defects in the gate polysilicon, such as Figure 1 As shown in the figure, polysilicon remains in the surface area of ​​the trench, forming defects. The reason for the analysis is that impurities fall on the substrate surface during the deposition and etching of the gate polysilicon, resulting in the etching of the impurity area being blocked by the impurities when etching the polysilicon layer, causing the polysilicon etching to fail. After the etching is completed, the polysilicon that should have been etched away remains, forming defects, which is the main factor causing the failure of IGSS.

[0003] The existing etching process for polysilicon mainly forms a groove on the substrate and grows an oxide film, then deposits polysilicon to fill the groove and cover the surface of the substrate, and then back-etches the polysilicon. Back-etching adopts a dry etching process, firstly performs a preliminary etching (Breakthrough), mainly etching with CF4 etching gas for 10 to 18 seconds to remove a small amount of silicon oxide that may exist on the surface of the polysilicon, and then performs a main etching process, the etching gas is Cl2 / SF6 / He, the main etching step etches polysilicon, the etching rate is relatively fast, and then Cl2 / HBr / He etching gas is used for endpoint detection etching, and finally, the etching gas Cl2 / HBr is used in an oxygen atmosphere to perform an over-etching process to ensure that the polysilicon is etched cleanly. Since the main etching process step and the etching endpoint detection step have a large amount of etching and a long process time, defects are easily generated. The etching process still cannot ensure that the polysilicon in the groove is etched cleanly, and in some cases, polysilicon residues are caused, causing the prepared device to fail. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a power semiconductor device.

[0005] In order to solve the above problems, the present invention provides a method for manufacturing a power semiconductor device, comprising the following process steps: Etching a gate trench of a power semiconductor device on a semiconductor substrate, and then forming an oxide layer on the entire surface of the semiconductor substrate; Depositing a layer of polysilicon in the trench, wherein the polysilicon completely fills the trench and covers the surface of the semiconductor substrate; Performing a global CMP grinding process to grind the polysilicon on the surface of the semiconductor substrate until the oxide layer surface is reached, and all the polysilicon on the surface is removed; Performing an oxide layer etching process to remove the oxide layer that may exist on the surface of the polysilicon; The polysilicon etching process is performed to continue over-etching the polysilicon to ensure that the surface polysilicon is etched cleanly.

[0006] Furthermore, the semiconductor substrate includes a silicon substrate, a silicon germanium substrate, a gallium nitride substrate, and a silicon carbide substrate.

[0007] Furthermore, the oxide layer etching process uses CF4 gas for etching, and the process time is 3 to 10 seconds.

[0008] Furthermore, the polysilicon etching process adopts a dry etching process.

[0009] Furthermore, the polysilicon is over-etched, and the etching gas atmosphere adopts a mixed gas of Cl2, HBr and O2 to ensure that the surface polysilicon is etched cleanly.

[0010] Furthermore, after the polysilicon is overetched, the surface polysilicon depression is controlled within 1000Å.

[0011] The manufacturing method of the power semiconductor device described in the present invention directly performs a global CMP process to grind and remove all the polysilicon on the surface after the polysilicon deposition is completed, and then etches the surface of the polysilicon using a dry etching process with a reduced etching amount. In this way, the polysilicon in the internal area of ​​the chip can be etched cleanly, and at the same time, steps with long etching cycles such as the main etching process and the endpoint detection etching process in the traditional process are omitted, thereby reducing the process time and reducing the etching loss of the gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of defects caused by polysilicon residue after the existing polysilicon etching process is completed.

[0013] Figure 2 It is the IGSS failure curve diagram of the device completed under the existing process.

[0014] Figures 3 to 5 It is a schematic diagram of the process steps of the present invention.

[0015] Figure 6 It is a comparison diagram of IGSS failure curves of devices under the existing process and the process of the present invention.

[0016] Figure 7 Flow chart of the process steps of the present invention. DETAILED DESCRIPTION

[0017] The following is a specific implementation of the present invention in conjunction with the accompanying drawings, and the technical solutions in the present invention are clearly and completely described, but the present invention is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0018] The present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layers and zones may be exaggerated, and the same reference numerals represent the same elements from beginning to end. In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0019] The present invention provides a method for manufacturing a power semiconductor device, comprising the following process steps: A semiconductor substrate is provided, and the material of the semiconductor substrate is not limited, including common silicon substrates, silicon germanium substrates, gallium nitride substrates, silicon carbide substrates, etc. A conventional gate process is performed on the semiconductor substrate 1, including etching to form a gate trench of a power semiconductor device, and then forming an oxide layer 2 on the entire surface of the semiconductor substrate; and selectively forming a shielding gate structure at the bottom of the trench.

[0020] An isolation dielectric layer is formed in the trench, and a layer of polysilicon 3 is deposited in the trench. The polysilicon completely fills the trench and covers the surface of the semiconductor substrate. The polysilicon is used to make the gate of the power semiconductor device.

[0021] After the polysilicon deposition for making the gate is completed, a global CMP grinding process is performed to globally grind the polysilicon 3 on the surface of the semiconductor substrate in the active area, and the grinding stops at the surface of the oxide layer 2 to remove all the polysilicon on the substrate surface.

[0022] The oxide layer etching process is mainly a dry etching process, using CF4 etching gas for etching, and the process time is 3 to 10 seconds to remove the small amount of oxide layer that may exist on the surface of the polysilicon. Because polysilicon may undergo a natural oxidation process, a small amount of silicon oxide is formed on the surface of the polysilicon. These possible silicon oxides are removed by the etching process. The etching amount of this etching step is very small, and the impact on the surface oxide layer of the substrate area is very small. This etching step is basically the same as the conventional process preparatory etching (Breakthrough). The main difference is that the process of the present invention further compresses the process time from the 10 to 18 seconds of the conventional process to 3 to 10 seconds, with a typical value of 5 seconds, saving half of the working hours, and also reducing the etching loss of the gate oxide layer. Compared with the conventional process, the etching loss can be controlled at about 50Å.

[0023] Then, the polysilicon over-etching process is performed. The polysilicon over-etching process adopts a dry etching process to continue over-etching the polysilicon to ensure that the surface polysilicon is etched cleanly. The etching gas atmosphere adopts a mixed gas of Cl2, HBr and O2. After the polysilicon is over-etched, the surface polysilicon depression is controlled within 1000Å, and the local area in the chip active area, such as the gate polysilicon at the source end polysilicon connection step, can be further etched clean.

[0024] After the above process steps, it can be ensured that the polysilicon is removed cleanly without residue. Compared with the traditional process, the present invention first uses the CMP grinding process to perform global grinding to remove the polysilicon on the surface of the substrate after the polysilicon is deposited, and then uses the optimized dry etching process to control the gate polysilicon depression within 1000AÅ, ensuring that the polysilicon in the small space area is etched cleanly. The present invention improves the gate polysilicon process of the power MOS device, eliminates the main etching process and the etching endpoint detection process steps in the traditional process, reduces the dry etching amount of polysilicon, improves the gate polysilicon etching residual defects, and can significantly reduce the probability of product IGSS failure. After actual measurement, the IGSS failure rate is significantly reduced after the implementation of the process of the present invention. Figure 7 As shown, the left side of the dotted line in the figure is the IGSS failure rate curve of the existing process, and the right side of the dotted line is the failure rate curve of the process of the present invention, and the improvement effect is obvious.

[0025] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a power semiconductor device, Features: The process steps include: Etching a gate trench of a power semiconductor device on a semiconductor substrate, and then forming an oxide layer on the entire surface of the semiconductor substrate; Depositing and filling the gate trench with polysilicon, wherein the polysilicon completely fills the trench and covers the surface of the semiconductor substrate; Performing a global CMP grinding process to grind the polysilicon on the surface of the semiconductor substrate until the oxide layer surface is reached, and all the polysilicon on the surface is removed; Performing an oxide layer etching process to remove the oxide layer that may exist on the surface of the polysilicon; The polysilicon etching process is performed to continue over-etching the polysilicon to ensure that the surface polysilicon is etched cleanly.

2. The method for manufacturing a power semiconductor device according to claim 1, Features: The semiconductor substrate includes a silicon substrate, a silicon germanium substrate, a gallium nitride substrate, and a silicon carbide substrate.

3. The method for manufacturing a power semiconductor device according to claim 1, Features: The oxide layer etching process adopts CF 4 The etching process is carried out by gas, and the process time is 3 to 10 seconds.

4. The method for manufacturing a power semiconductor device according to claim 1, Features: The polysilicon etching process adopts a dry etching process.

5. The method for manufacturing a power semiconductor device according to claim 1, Features: The polysilicon is over-etched, and the etching gas atmosphere is Cl 2 , HBr and O 2 A mixed gas is used to ensure that the surface polysilicon is etched cleanly.

6. The method for manufacturing a power semiconductor device according to claim 1, Features: After the polysilicon is overetched, the surface polysilicon depression is controlled within 1000Å.

7. The power semiconductor device according to claim 1, Features: The gate trench can selectively form a shielding gate at the bottom of the trench, then deposit an isolation dielectric layer, and then form a device gate at the top of the gate trench.

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