Transistor and forming method thereof

Abstract

Gate isolation processes (e.g., gate-to-source / drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and a gate spacer of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure; forming a gate isolation liner partially filling the CGI opening along the side wall of the gate electrode; and forming a gate isolation layer over the gate isolation liner that fills a remaining portion of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. The dielectric constant of the gate isolation layer is smaller than that of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer. The embodiment of the invention also relates to a transistor and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to transistors and methods of forming the same. Background Art

[0002] The electronics industry is experiencing a growing demand for smaller and faster electronic devices that can simultaneously support more increasingly complex and sophisticated functions. Therefore, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance and low-power integrated circuits (ICs). To date, these goals have been achieved to a large extent by reducing the size of semiconductor ICs (e.g., minimum component size) and thereby improving production efficiency and reducing associated costs. However, such miniaturization has brought greater complexity to semiconductor manufacturing processes. Therefore, achieving continued progress in semiconductor ICs and devices requires similar progress in semiconductor manufacturing processes and technology.

[0003] Recently, multi-gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling; reducing off-state current; and reducing short channel effect (SCE). One such multi-gate device that has been introduced is the all-around gate transistor (GAA). GAA devices are named for the gate structure, which can extend around the channel region and provide access to the channel on two or four sides. GAA devices are compatible with traditional complementary metal oxide semiconductor (CMOS) processes, and their structure allows them to be aggressively scaled down while maintaining gate control and mitigating SCE. GAA devices provide channels in silicon nanowires / nanosheets. However, the manufacture of GAA components integrated around nanowires / nanosheets can be challenging. For example, although current approaches have been satisfactory in many aspects, there is still a need for continued improvement. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a transistor, comprising: forming a gate stack above a semiconductor layer, wherein the gate stack includes a gate electrode disposed above a gate dielectric, wherein the gate stack is disposed between a first epitaxial source / drain and a second epitaxial source / drain; etching the gate dielectric to expose the sidewalls of the gate electrode; forming a gate isolation pad along the exposed sidewalls of the gate electrode; and forming a source / drain contact to the first epitaxial source / drain.

[0005] Other embodiments of the present application provide a method for forming a transistor, comprising: forming a channel layer above a substrate; forming a gate structure above the channel layer by the following steps: forming a gate spacer; forming a gate dielectric layer above the channel layer, wherein the gate dielectric layer is arranged along the sidewalls of the gate spacer; and forming a gate electrode layer above the gate dielectric layer; recessing the gate dielectric layer to expose the sidewalls of the gate electrode layer; and forming a liner to cover the exposed sidewalls of the gate electrode layer.

[0006] Some other embodiments of the present application provide a transistor, comprising: a semiconductor layer, arranged between a first epitaxial source / drain and a second epitaxial source / drain; a gate structure, arranged above the semiconductor layer, wherein the gate structure comprises a gate stack and a gate spacer arranged along the sidewall of the gate stack, wherein: the gate stack comprises a gate electrode arranged above a high-k gate dielectric, wherein the high-k gate dielectric is arranged along a lower portion of the sidewall of the gate electrode, and the high-k gate dielectric is arranged between the gate spacer and the lower portion of the sidewall of the gate electrode; and a gate isolation pad, arranged along an upper portion of the sidewall of the gate electrode, wherein the gate isolation pad is arranged above the gate spacer and the high-k gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1A is a perspective view showing a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0009] Figure 1B is a perspective view showing a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0010] Figure 1C is a perspective view showing a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0011] Figure 1D-1 and Figure 1D-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0012] Figure 1E-1 and Figure 1E-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0013] Figure 1F is a perspective view showing a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0014] Figure 1F-1 and Figure 1F-2 According to some embodiments of the present disclosure Figure 1F Cross-sectional view of a semiconductor structure.

[0015] Figure 1G is a perspective view showing a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0016] Figure 1G-1 and Figure 1G-2 According to some embodiments of the present disclosure Figure 1G Cross-sectional view of a semiconductor structure.

[0017] Figure 1G-3 According to some embodiments of the present disclosure Figure 1G-2 A magnified view of the diagram is shown to show more details.

[0018] Figure 1H-1 and Figure 1H-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0019] Fig. 1I is a perspective view showing a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0020] Figure 1I-1 and Figure 1I-2 According to some embodiments of the present disclosure Fig. 1I Cross-sectional view of a semiconductor structure.

[0021] Figure 1I-3 According to some embodiments of the present disclosure Figure 1I-2 A magnified view of the diagram is shown to show more details.

[0022] Figure 1J is a perspective view showing a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0023] Figure 1J-1 and Figure 1J-2 According to some embodiments of the present disclosure Figure 1J Cross-sectional view of a semiconductor structure.

[0024] Figure 2A-1 and Figure 2A-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0025] Figure 2B-1 and Figure 2B-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0026] Figure 2C is a perspective view showing a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0027] Figure 2C-1 and Figure 2C-2 According to some embodiments of the present disclosure Figure 2C Cross-sectional view of a semiconductor structure.

[0028] Figure 2C-3 According to some embodiments of the present disclosure Figure 2C-2 A magnified view of the diagram is shown to show more details.

[0029] Figure 2D-1 and Figure 2D-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0030] Figure 3 Some embodiments of the present disclosure are shown Figure 2C-3 Modification of the semiconductor structure.

[0031] Figure 4A-1 and Figure 4A-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0032] Figure 4B-1 and Figure 4B-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0033] Figure 5A-1 and Figure 5A-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0034] Figure 5B-1 and Figure 5B-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0035] Figure 5C-1 and Figure 5C-2 is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0036] Figure 5D-1 and Figure 5D-2is a cross-sectional view illustrating a formed semiconductor structure at an intermediate stage according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. The specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted and formed, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be directly contacted. In addition, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "under", "upward", "downward", "top", "bottom" and their derivatives (e.g., "horizontally", "downward", "upward", etc.) are used to easily understand the relationship between one component and another component of the disclosed embodiments. Spatial relative terms are intended to cover different orientations of devices including components. In addition, when describing a numerical value or a numerical range with "about", "approximately", etc., as understood by those of ordinary skill in the art, the term is intended to cover a numerical value within a reasonable range taking into account the changes inherent in the manufacturing period. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the values, the values ​​or ranges of values ​​encompass a reasonable range including the described values, such as within + / - 10% of the described values. For example, a material layer having a thickness of "about 5 nm" may encompass a size range from 4.5 nm to 5.5 nm, where the manufacturing tolerance associated with the deposited material layer known to those of ordinary skill in the art is + / - 10%. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0038] Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. It should be understood that additional operations may be provided before, during, and after the method, and that some of the operations described may be replaced or eliminated for other embodiments of the method.

[0039] The nanostructure transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channels, nanoribbon FETs, all-around gate (GAA) transistor structures) can be patterned by any suitable method. For example, the structure can be patterned using one or more lithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines lithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0040] Embodiments of semiconductor structures and methods for forming semiconductor structures are provided. The method includes recessing a gate dielectric layer to expose a top gate electrode layer. Thus, the size of the top portion of the final gate stack can be reduced, and the spacing between the contact plug and the final gate stack can be increased. Thus, the reliability of the resulting semiconductor device can be improved. In addition, the overlap window of the photolithography process for forming the contact opening can be relaxed, which can facilitate the scaling down of the gate-to-gate spacing.

[0041] Figures 1A to 1J-2 is a schematic diagram showing the formation of a semiconductor structure 100 at various intermediate stages according to some embodiments of the present disclosure. Figure 1A is a perspective view of the semiconductor structure 100 after forming the active region 104 and the isolation structure 110 according to some embodiments of the present disclosure.

[0042] According to some embodiments, a semiconductor structure 100 is provided, such as Figure 1A According to some embodiments, the semiconductor structure 100 includes a substrate 102 and an active region 104 as well as an isolation structure 110 over the substrate 102 .

[0043] In order to better understand the semiconductor structure, an XYZ coordinate reference is provided in the drawings of the embodiments of the present disclosure. The X-axis and the Y-axis are generally oriented in a lateral (or horizontal) direction parallel to the main surface of the substrate 102. The Y-axis is lateral to (e.g., substantially perpendicular to) the X-axis. The Z-axis is generally oriented in a vertical direction perpendicular to the main surface (or XY plane) of the substrate 102.

[0044] The substrate 102 may be part of a semiconductor wafer, a semiconductor chip (or die), etc. In some embodiments, the substrate 102 is a silicon substrate. In some embodiments, the substrate 102 includes: an elemental semiconductor, such as germanium; a compound semiconductor, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In addition, the substrate 102 may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement features.

[0045] According to some embodiments, the active region 104 extends in the X direction. According to some embodiments, the active region 104 has a longitudinal axis parallel to the X direction. In some embodiments, the active region 104 is also referred to as a fin or fin structure. According to some embodiments, each of the active regions 104 is defined as a number of channel regions and a number of source / drain regions, wherein the channel regions and the source / drain regions are arranged alternately. In the disclosed embodiments, the source / drain refers to the source and / or drain. It should be noted that in the disclosed embodiments, the source and drain are interchangeable and their structures are substantially the same. The X direction may also be referred to as the channel extension direction. The current of the resulting semiconductor device (i.e., the nanostructure transistor) flows in the X direction through the channel. The gate structure or gate stack will be formed to have a longitudinal axis parallel to the Y direction and extend above the channel region of the active region 104. The Y direction may also be referred to as the gate extension direction.

[0046] According to some embodiments, each of the active regions 104 includes a lower fin element 104L surrounded by an isolation structure 110 and an upper fin element formed by an epitaxial stack including alternating first semiconductor layers 106 and second semiconductor layers 108. According to some embodiments, the formation of the active region 104 includes forming an epitaxial stack over the substrate 102 using an epitaxial growth process. The epitaxial stack may be formed by depositing a first semiconductor layer 106 on the substrate 102; depositing a second semiconductor layer 108 on the first semiconductor layer 106; and repeating a cycle of depositing the semiconductor layers 106 and 108 several times. According to some embodiments, the first semiconductor layer 106 and the second semiconductor layer 108 are alternately stacked. The epitaxial growth process may be molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE), or another suitable technique.

[0047] In some embodiments, the first semiconductor layer 106 is made of a first semiconductor material, and the second semiconductor layer 108 is made of a second semiconductor material having a different composition than the first semiconductor material. According to some embodiments, the first semiconductor material for the first semiconductor layer 106 has a different lattice constant than the second semiconductor material for the second semiconductor layer 108. In some embodiments, the first semiconductor material and the second semiconductor material have different oxidation rates and / or etching selectivities. In some embodiments, the first semiconductor layer 106 is made of SiGe, wherein the percentage of germanium (Ge) in the SiGe is in the range from about 20 atomic % to about 50 atomic %, and the second semiconductor layer 108 is made of pure silicon or substantially pure silicon. In some embodiments, the first semiconductor layer 106 is Si 1-x Ge x (where x is greater than about 0.3) or Ge (x=1.0), and the second semiconductor layer 108 is Si or Si 1-y Ge y , where y is less than about 0.4, and x>y.

[0048] According to some embodiments, the first semiconductor layer 106 is configured as a sacrificial layer and will be removed to form a gap to accommodate the gate material. According to some embodiments, the second semiconductor layer 108 will form a nanostructure (e.g., a nanowire or nanosheet) that extends laterally between the source / drain components and serves as a channel for the resulting semiconductor device (such as a nanostructure transistor). As used herein, the term "nanostructure" refers to a semiconductor layer having a cylindrical, bar, and / or sheet shape. According to some embodiments, a gate stack (not shown) that wraps the nanostructure will be formed across the nanostructure. Although in Figure 1A Three first semiconductor layers 106 and three second semiconductor layers 108 are shown in FIG. 1 , but the number is not limited to three, and may be two or four, and less than ten.

[0049] In some embodiments, the thickness of each of the first semiconductor layers 106 is in a range from about 3 nm to about 20 nm, such as about 4 nm to about 12 nm. In some embodiments, the thickness of each of the second semiconductor layers 108 is in a range from about 3 nm to about 20 nm, such as about 4 nm to about 12 nm. The thickness of the second semiconductor layer 108 may be greater than, equal to, or less than the thickness of the first semiconductor layer 106, which may depend on the amount of gate material to be filled in the space where the first semiconductor layer 106 is removed.

[0050] According to some embodiments, the formation of active region 104 further includes patterning the epitaxial stack and the underlying substrate 102 using photolithography and etching processes to form trenches and active region 104 protruding from between the trenches. According to some embodiments, the portion of substrate 102 protruding from between the trenches serves as a lower fin element 104L of active region 104. According to some embodiments, the remaining portion of the epitaxial stack (including first semiconductor layer 106 and second semiconductor layer 108) serves as an upper fin element of active region 104.

[0051] According to some embodiments, the isolation structure 110 is formed to surround the lower fin element 104L of the active region 104, such as Figure 1A According to some embodiments, the isolation structure 110 is configured to electrically isolate the active region 104 of the semiconductor structure 100 and is also referred to as a shallow trench isolation (STI) feature.

[0052] According to some embodiments, the formation of the isolation structure 110 includes forming an insulating material to overfill the trench. In some embodiments, the insulating material is made of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, the insulating material is deposited using CVD (such as flowable CVD (FCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), or high aspect ratio process (HARP)), atomic layer deposition (ALD), another suitable technique, or a combination thereof.

[0053] According to some embodiments, a planarization process is performed on the insulating material to remove the portion of the insulating material located above the active region 104. The planarization may be a chemical mechanical polishing (CMP), an etch back process, or a combination thereof. According to some embodiments, the insulating material is then recessed by an etching process (such as dry plasma etching and / or wet chemical etching) until the sidewalls of the upper fin elements of the active region 104 are exposed. According to some embodiments, the remaining insulating material serves as an isolation structure 110.

[0054] Figure 1B is a perspective view of the semiconductor structure 100 after forming a dummy gate structure 112 and a spacer layer 117 according to some embodiments of the present disclosure.

[0055] According to some embodiments, a dummy gate structure 112 is formed across the active region 104 and the isolation structure 110, such as Figure 1B. According to some embodiments, the dummy gate structure 112 is configured as a sacrificial structure and will be replaced by the final gate stack. In some embodiments, the dummy gate structure 112 extends in the Y direction. According to some embodiments, the dummy gate structure 112 has a longitudinal axis parallel to the Y direction. According to some embodiments, the dummy gate structure 112 surrounds the channel region of the active region 104.

[0056] According to some embodiments, each of the dummy gate structures 112 includes a dummy gate dielectric layer 114 and a dummy gate electrode layer 116 formed over the dummy gate dielectric layer 114. Figure 1B . In some embodiments, the dummy gate dielectric layer 114 is conformally formed along the upper fin elements of the active region 104. In some embodiments, the dummy gate dielectric layer 114 is made of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO and / or HfAlO. In some embodiments, the dielectric material is deposited using ALD, CVD, thermal oxidation, physical vapor deposition (PVD), another suitable technique, or a combination thereof.

[0057] In some embodiments, the dummy gate electrode layer 116 is made of a semiconductor material such as polysilicon or polysilicon germanium. In some embodiments, the material for the dummy gate electrode layer 116 is deposited using CVD, ALD, another suitable technique, or a combination thereof. In some embodiments, the formation of the dummy gate structure 112 includes: globally and conformally depositing a dielectric material for the dummy gate dielectric layer 114 over the semiconductor structure 100; depositing a material for the dummy gate electrode layer 116 over the dielectric material; planarizing the material for the dummy gate electrode layer 116; and patterning the material for the dummy gate electrode layer 116 and the dielectric material into the dummy gate structure 112.

[0058] According to some embodiments, the patterning process includes forming a patterned mask including hard mask layers 113 and 115 over the material for dummy gate electrode layer 116. According to some embodiments, hard mask layer 113 may be a silicon nitride layer, and hard mask layer 115 may be a silicon oxide layer. According to some embodiments, the patterned mask corresponds to and overlaps with the channel region of active region 104. According to some embodiments, the material for dummy gate dielectric layer 114 and dummy gate electrode layer 116 that is not covered by the patterned mask is etched away until the top surface of active region 104 and isolation structure 110 is exposed.

[0059] According to some embodiments, a spacer layer 117 is formed over the semiconductor structure 100, such as Figure 1B. In some embodiments, the spacer layer 117 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, the spacer layer 117 is made of a low-k dielectric material having a dielectric constant (k) less than 10. For example, the dielectric constant value of the gate spacer layer 118 can be lower than the k value of silicon oxide (SiO), such as less than 4.2, equal to or less than about 3.9, such as in a range from about 3.5 to about 3.9. The spacer layer 117 is deposited using ALD, CVD (such as PECVD, LPCVD or HARP), another suitable technique, or a combination thereof.

[0060] Figure 1C is a perspective view of the semiconductor structure 100 after forming a gate spacer layer 118 , a semiconductor isolation structure 120 , a dielectric isolation structure 122 , an inner spacer layer 124 , and source / drain features 126 according to some embodiments of the present disclosure.

[0061] According to some embodiments, an etching process is performed on the spacer layer 117. According to some embodiments, a vertical portion of the spacer layer 117 located on the opposite side of the dummy gate structure 112 remains to form a gate spacer layer 118, such as Figure 1C As shown in . According to some embodiments, the gate spacer layer 118 is used to offset subsequently formed source / drain features and separate the source / drain features from the gate structure. The gate spacer layer 118 may also be referred to as a top spacer layer.

[0062] According to some embodiments, source / drain features 126 are formed in and / or over source / drain regions of active region 104, such as Figure 1C . According to some embodiments, the formation of the source / drain features 126 includes recessing the source / drain regions of the active region 104 using the dummy gate structure 112 and the gate spacer layer 118 as a mask to form source / drain recesses on opposite sides of the dummy gate structure 112 (where the source / drain features 126 will be formed). According to some embodiments, the source / drain recesses may extend into the lower fin element 104L. In some embodiments, the recessing process includes an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, or wet chemical etching, or a combination thereof.

[0063] Thereafter, according to some embodiments, an etching process is performed to recess the first semiconductor layer 106 of the active region 104 laterally from the source / drain recesses to form notches, and then an internal spacer layer 124 is formed in the notches, such as Figure 1C. According to some embodiments, the inner spacer layer 124 is formed adjacent to the recessed side of the first semiconductor layer 106. In some embodiments, the inner spacer layer 124 is located between adjacent second semiconductor layers 108 and between the lowermost second semiconductor layer 108 and the lower fin element 104L. In some embodiments, the inner spacer layer 124 extends directly below the gate spacer layer 118.

[0064] In some embodiments, the inner spacer layer 124 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and / or oxygen-doped silicon carbon nitride (Si(O)CN). In some embodiments, the inner spacer layer 124 is made of a low-k dielectric material having a dielectric constant lower than 10. For example, the dielectric constant value of the inner spacer layer 124 can be lower than the k value of silicon oxide (SiO), such as lower than 4.2, equal to or lower than about 3.9, such as in a range from about 3.5 to about 3.9.

[0065] In some embodiments, the formation of the inner spacer layer 124 includes: depositing a dielectric material for the inner spacer layer 124 over the semiconductor structure 100 to overfill the notch; and then etching away a portion of the dielectric material located outside the notch. According to some embodiments, the portion of the inner spacer layer 124 remaining in the notch serves as the inner spacer layer 124.

[0066] According to some embodiments, the semiconductor isolation feature 120 is formed in the source / drain recesses on the lower fin element 104L using an epitaxial growth process, such as Figure 1C The epitaxial growth process may be MBE, MOCVD or VPE, another suitable technique or a combination thereof. In some embodiments, the semiconductor isolation component 120 is made of an undoped epitaxial material, such as intrinsic silicon, intrinsic silicon germanium and / or another suitable semiconductor material. For example, the impurities (or n-type dopants and / or p-type dopants) in the semiconductor isolation component 120 have a relative humidity of less than about 10 14 cm -3 In some other embodiments, the semiconductor isolation feature 120 is doped with a dopant having an opposite conductivity type to that of the source / drain feature 126 .

[0067] Thereafter, according to some embodiments, a dielectric isolation feature 122 is formed in the source / drain recesses on the semiconductor isolation feature 120 and on the isolation structure 110, such as Figure 1C. In some embodiments, the semiconductor isolation feature 120 and the dielectric isolation feature 122 are configured to block a leakage path of a bottom planar transistor formed by the lower fin element 104L. In some embodiments, the dielectric isolation feature 122 is made of silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN) and / or oxygen-doped silicon carbon nitride (Si(O)CN).

[0068] In some embodiments, the formation of the dielectric isolation member 122 includes: depositing a dielectric material for the dielectric isolation member 122 over the semiconductor structure 100; and etching back the dielectric material. In some embodiments, the semiconductor isolation member 120 is made of undoped silicon, and the dielectric isolation member 122 is made of silicon oxide. In some embodiments, forming the semiconductor isolation member 120 can reduce the difficulty of the deposition and etching back processes for forming the dielectric isolation member 122.

[0069] According to some embodiments, source / drain features 126 are then grown in source / drain recesses 120 from the exposed surface of second semiconductor layer 108 using an epitaxial growth process, such as Figure 1C . The epitaxial growth process may be MBE, MOCVD or VPE, another suitable technique or a combination thereof. In some embodiments, the source / drain feature 126 abuts the inner spacer layer 124 and the second semiconductor layer 108. In some embodiments, the source / drain feature 126 has a small planar surface. In some other embodiments, the source / drain feature 126 may have a curved surface in some other embodiments.

[0070] In some embodiments, the source / drain feature 126 is made of any suitable semiconductor material for an n-type semiconductor device or a p-type semiconductor device. In some embodiments, the source / drain feature 126 is doped. The concentration of the dopant in the source / drain feature 126 is in the range of about 1×10 19 cm -3 About 6×10 21 cm -3 According to some embodiments, an annealing process may be performed on the semiconductor structure 100 to activate dopants in the source / drain features 126 .

[0071] In some embodiments, where the active region 104 is to be formed as an N-type nanostructure device (such as an n-channel nanostructure transistor), the source / drain component 126 is made of a semiconductor material, such as SiP, SiAs, SiCP, SiC, Si, GaAs, another suitable semiconductor material, or a combination thereof. In some embodiments, the source / drain component 126 is doped with an n-type dopant during the epitaxial growth process. For example, the n-type dopant can be phosphorus (P) or arsenic (As). For example, the source / drain component 126 can be epitaxially grown Si doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain component and / or doped with arsenic to form a silicon:arsenic (Si:As) source / drain component.

[0072] In some embodiments, where the active region 104 is to be formed as a P-type nanostructure device (such as a P-channel nanostructure transistor), the source / drain features 126 are made of a semiconductor material, such as SiGe, Si, GaAs, another suitable semiconductor material, or a combination thereof. In some embodiments, the source / drain features 126 are doped with a p-type dopant during the epitaxial growth process. For example, the p-type dopant can be boron (B) or BF2. For example, the source / drain features 126 can be epitaxially grown SiGe doped with boron (B) to form a silicon germanium:boron (SiGe:B) source / drain feature.

[0073] Figure 1D-1 and Figure 1D-2 is a cross-sectional view corresponding to line YY and line XX of a semiconductor after forming a contact etch stop layer (CESL) 128 and a first interlayer dielectric layer (ILD) 130 according to some embodiments.

[0074] Line XX lies in a plane parallel to the longitudinal axis of active region 104 (ie, X direction) and passes through active region 104. Line YY lies in a plane parallel to the longitudinal axis of the gate structure (ie, Y direction) and crosses the source / drain regions of active region 104.

[0075] According to some embodiments, a contact etch stop layer 128 is formed over the semiconductor structure 100 to cover the source / drain features 126, such as Figure 1D-1 and Figure 1D-2 According to some embodiments, a contact etch stop layer 128 is further formed along and covers the sidewalls of the gate spacer layer 118 and the top surface of the dielectric isolation structure 122 .

[0076] In some embodiments, the contact etch stop layer 128 is made of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxynitride (SiOC), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, the contact etch stop layer 128 is made of a low-k dielectric material having a dielectric constant less than 10. In some embodiments, the dielectric material for the contact etch stop layer 128 is deposited globally and conformally over the semiconductor structure 100 using CVD (such as LPCVD, PECVD, HDP-CVD, or HARP), ALD, another suitable method, or a combination thereof.

[0077] Thereafter, according to some embodiments, a first interlayer dielectric layer 130 is formed over the contact etch stop layer 128, such as Figure 1D-1 and Figure 1D-2 . According to some embodiments, the first interlayer dielectric layer 130 overfills the space between the dummy gate structures 112. In some embodiments, the first interlayer dielectric layer 130 is made of a dielectric material, such as undoped silicate glass (USG), doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG) and / or another suitable dielectric material. In some embodiments, the contact etch stop layer 128 is made of a low-k dielectric material having a dielectric constant lower than 10 (such as lower than 4.2).

[0078] In some embodiments, the first interlayer dielectric layer 130 and the contact etch stop layer 128 are made of different materials and have a large difference in etching selectivity. For example, the contact etch stop layer 128 is a silicon nitride layer, and the first interlayer dielectric layer 130 is a silicon oxide layer. In some embodiments, the dielectric material for the first interlayer dielectric layer 130 is deposited using a technique such as CVD (such as HDP-CVD, PECVD, HARP or FCVD), another suitable technique, or a combination thereof. According to some embodiments, the dielectric material for the contact etch stop layer 128 and the first interlayer dielectric layer 130 above the top surface of the pseudo gate electrode layer 116 is removed using a technique such as CMP.

[0079] Figure 1E-1 and Figure 1E-2 is a cross-sectional view of the semiconductor corresponding to line YY and line XX after forming gate trench 134 and gap 136 , according to some embodiments.

[0080] According to some embodiments, the dummy gate structure 112 is removed using an etching process to form a gate trench 134 between the gate spacer layer 118, such as Figure 1E-2. In some embodiments, the gate trench 134 exposes the channel region of the active region 104. In some embodiments, the gate trench 134 also exposes the sidewalls of the gate spacer layer 118 facing the channel region. In some embodiments, the etching process includes one or more etching processes. For example, when the dummy gate electrode layer 116 is made of polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode layer 116. For example, plasma dry etching, dry chemical etching and / or wet etching can be used thereafter to remove the dummy gate dielectric layer 114.

[0081] Then, according to some embodiments, an etching process is performed on the first semiconductor layer 106 of the active region 104 to form a gap 136, such as Figure 1E-2 . The inner spacer layer 124 can be used as an etch stop layer in the etching process, which can protect the source / drain features 126 from damage. In some embodiments, the etching process includes a selective wet etching process, such as an APM (e.g., ammonium hydroxide-hydrogen peroxide-water mixture) etching process. In some embodiments, the wet etching process uses an etchant such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine pyrocatechol (EDP), and / or potassium hydroxide (KOH) solution.

[0082] According to some embodiments, gaps 136 are formed between adjacent second semiconductor layers 108 and between the lowermost second semiconductor layer 108 and the lower fin element 104L. In some embodiments, gaps 136 also expose sidewalls of the inner spacer layer 124 facing the channel region.

[0083] According to some embodiments, after one or more etching processes, four main surfaces of the second semiconductor layer 108 are exposed. According to some embodiments, the exposed second semiconductor layer 108 forms a nanostructure. According to some embodiments, the nanostructures 108 are vertically stacked and spaced apart from each other. According to some embodiments, the nanostructures 108 are used as a channel layer of a resulting semiconductor device (e.g., a nanostructure transistor, such as a GAA transistor). In some embodiments, a trimming process may be performed on the nanostructure 108 to shape the profile of the nanostructure 108, such as rounding the corners of the nanostructure 108.

[0084] Figure 1F is a perspective view of the semiconductor structure 100 after forming a final gate stack 138 according to some embodiments of the present disclosure. Figure 1F-1 and Figure 1F-2 According to some embodiments, Figure 1F A cross-sectional view taken along line YY and line XX.

[0085] According to some embodiments, a final gate stack 138 is formed in the gate trench 134 and the gap 136, thereby encapsulating the nanostructure 108, such as Figure 1F and Figure 1F-2 In some embodiments, the final gate stack 138 extends in the Y direction. According to some embodiments, the final gate stack 138 has a longitudinal axis parallel to the Y direction. In some embodiments, according to some embodiments, each of the final gate stacks 138 includes an interface layer 140, a gate dielectric layer 142, and a metal gate electrode layer 144, as shown in FIG. Figure 1F and Figure 1F-2 as shown in .

[0086] According to some embodiments, the interface layer 140 is formed on the exposed surface of the nanostructure 108 and the exposed top surface of the lower fin element 104L. According to some embodiments, the interface layer 140 wraps the nanostructure 108. In some embodiments, the interface layer 140 is made of chemically formed silicon oxide. In some embodiments, the interface layer 140 is nitrogen-doped silicon oxide. In some embodiments, the interface layer 140 is formed using one or more cleaning processes, such as including ozone (O3), ammonium hydroxide-hydrogen peroxide-water mixture and / or hydrochloric acid-hydrogen peroxide-water mixture. According to some embodiments, the semiconductor material from the nanostructure 108 and the lower fin element 104L is oxidized to form the interface layer 140.

[0087] According to some embodiments, the gate dielectric layer 142 is conformally formed along the interface layer 140 to wrap the nanostructure 108. According to some embodiments, the gate dielectric layer 142 is also conformally formed along the sidewalls of the gate spacer layer 118 facing the channel region. According to some embodiments, the gate dielectric layer 142 is also conformally formed along the sidewalls of the inner spacer layer 124 facing the channel region.

[0088] The gate dielectric layer 142 may be a high-k dielectric layer. In some embodiments, the high-k dielectric layer is a dielectric material having a high dielectric constant (k value), for example, greater than 10, such as greater than 20, such as greater than 30. In some embodiments, the high-k dielectric layer includes hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, Al2O3, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), a combination thereof, or another suitable material. The high-k dielectric layer may be deposited using ALD, PVD, CVD, and / or another suitable technique.

[0089] According to some embodiments, the metal gate electrode layer 144 is formed to overfill the gate trench 134 and the remaining portion of the gap 136. In some embodiments, the metal gate electrode layer 144 is made of more than one conductive material, such as a metal, a metal alloy, a conductive metal oxide and / or a metal nitride, another suitable conductive material, and / or a combination thereof. For example, the metal gate electrode layer 144 can be made of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Re, Ir, Co, Ni, another suitable conductive material, or a multilayer thereof.

[0090] The metal gate electrode layer 144 may be a multi-layer structure having various combinations of a diffusion barrier layer, a work function layer having a selected work function to enhance device performance (e.g., threshold voltage) for an n-channel FET or a p-channel FET, a capping layer to prevent oxidation of the work function layer, a glue layer to bond the work function layer to the next layer, and a metal filling layer to reduce the overall resistance of the gate stack and / or another suitable layer. The metal gate electrode layer 144 may be formed using ALD, PVD, CVD, electron beam evaporation, or another suitable technique.

[0091] The top nanostructure 108 is denoted as 108_1. Figure 1F-2 . According to some embodiments, a portion of the metal gate electrode layer 144 formed above the topmost nanostructure 108_1 between the gate spacer layers 118 is referred to as a top gate electrode layer TG. According to some embodiments, a portion of the metal gate electrode layer 144 formed below the topmost nanostructure 108_1 between the inner spacer layers 124 is referred to as an inner gate electrode layer IG. According to some embodiments, the inner gate electrode layer IG is located between the nanostructures 108 and between the bottommost nanostructure 108 and the lower fin element 104L.

[0092] According to some embodiments, a planarization process such as CMP may be performed on the semiconductor structure 100 to remove materials of the gate dielectric layer 142 and the metal gate electrode layer 144 formed on a top surface of the first interlayer dielectric layer 130 .

[0093] The final gate stack 138 engages the channel region so that current can flow between the source / drain features 126 during operation. The final gate stack 138 wrapping the nanostructure 108 combines with adjacent source / drain features 126 to form a nanostructure transistor, for example, an n-channel nanostructure transistor and / or a p-channel nanostructure transistor.

[0094] Figure 1G is a perspective view of the semiconductor structure 100 after an etching process according to some embodiments of the present disclosure. Figure 1G-1 and Figure 1G-2According to some embodiments, Figure 1G A cross-sectional view taken along line YY and line XX. Figure 1G-3 yes Figure 1G-2 A magnified image is shown to show more details.

[0095] According to some embodiments, an etching process is performed on the semiconductor structure 100 to recess the gate spacer layer 118 and the gate dielectric layer 142 along the vertical portion of the sidewall of the gate spacer layer 118, such as Figure 1G to Figure 1G-3 . According to some embodiments, during the etching process, the first interlayer dielectric layer 130 and the contact etch stop layer 128 are also recessed along the vertical portion of the gate spacer layer 118. According to some embodiments, a trench 145 is formed between the top gate electrode layer TG and the recessed first interlayer dielectric layer 130 (as well as the contact etch stop layer 128 and the source / drain features 126).

[0096] In some embodiments, the etching process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching or wet chemical etching, and / or a combination thereof. In some embodiments, the etching process is performed without an additional patterned mask. In some embodiments, a mask layer (not shown) may be formed to cover the metal gate electrode layer 144.

[0097] According to some embodiments, the vertical portion of the contact etch stop layer 128 along the gate spacer layer 118 is completely removed during the etching process, thereby exposing a portion 126S of the surface of the source / drain feature 126, such as Figure 1G-3 In some other embodiments, the vertical portion of the contact etch stop layer 128 along the gate spacer layer 118 may be partially removed, and the surface of the source / drain feature 126 remains completely covered by the contact etch stop layer 128 .

[0098] According to some embodiments, after the etching process, a top surface 142T of the recessed gate dielectric layer 142 is lower than a top surface 118T of the recessed gate spacer layer 118. In some other embodiments, a top surface 142T of the recessed gate dielectric layer 142 may be substantially flush with a top surface 118T of the recessed gate spacer layer 118.

[0099] According to some embodiments, the gate dielectric layer 142 above the topmost nanostructure 108_1 includes a vertical portion 142A formed along the sidewalls of the gate spacer layer 118 and a horizontal portion 142B formed along the top surface of the topmost nanostructure 108_1. Due to the growth on surfaces with different surface characteristics, the vertical portion 142A and the horizontal portion 142B of the gate dielectric layer 142 can have different crystalline characteristics. For example, in some embodiments, during the deposition process, the high-k dielectric material of the gate dielectric layer 142 is formed on an amorphous surface provided by the gate spacer layer 118 and a crystalline surface provided by the interface layer 140 (and the nanostructure 108 below). Therefore, the vertical portion 142A is mainly amorphous and the horizontal portion 142B is mainly crystalline, and therefore they have different etching selectivities in the etching process used to recess the gate dielectric layer 142.

[0100] According to some embodiments, as etching proceeds vertically downward from the top of vertical portion 142A toward horizontal portion 142B, the etching rate gradually slows down due to the increased crystallinity of the high-k dielectric material of gate dielectric layer 142. That is, according to some embodiments, the etching rate for etching the lower portion of vertical portion 142A is slower than the etching rate for etching the upper portion of vertical portion 142A. Therefore, according to some embodiments, horizontal portion 142B of gate dielectric layer 142 can be used as an etching stop layer in the etching process.

[0101] In some embodiments, the etching process stops at the bottom portion of the vertical portion 142A. Figure 1G-2 and Figure 1G-3 . According to some embodiments, in some other embodiments, etching may eventually self-stop on horizontal portion 142B having high crystallinity. Therefore, according to some embodiments, due to the different etching selectivities between vertical portion 142A and horizontal portion 142B of gate dielectric layer 142, the etching process for recessing gate dielectric layer 142 may be better controlled. According to some embodiments, horizontal portion 142B of gate dielectric layer 142 remains covering the top surface of topmost nanostructure 108_1, thereby preventing the channel region from being oxidized.

[0102] In some embodiments, the recessed gate dielectric layer 142 has a height H1 above the topmost nanostructure 108_1. In some embodiments, the height H1 is in a range from about 1 nm to about 10 nm.

[0103] According to some embodiments, top surface 118T of recessed gate spacer layer 118 is lower than top 126T of source / drain feature 126 and top surface 128T of contact etch stop layer 128. According to some embodiments, top surface 130T of recessed first interlayer dielectric layer 130 is lower than top surface 144T of metal gate electrode layer 144.

[0104] Because the thickness of the gate dielectric layer 142 is relatively thin (e.g., about 1-2 nm), the process difficulty of etching the dielectric layer (e.g., substantially anisotropic, vertical etching) may be relatively high without recessing the gate spacer layer 118 and the contact etch stop layer 128. Therefore, by recessing the gate spacer layer 118 and the contact etch stop layer 128, the gate dielectric layer 142 may be etched vertically and laterally, thereby reducing the process difficulty of recessing the gate dielectric layer 142.

[0105] According to some embodiments, during the etching process, an upper portion of the sidewall 144S of the top gate electrode layer TG is exposed from the recessed gate dielectric layer 142. After the etching process, the top gate electrode layer TG includes an upper portion 144A protruding from the gate dielectric layer 142 and a lower portion 144B nested in the gate dielectric layer 142, as shown in FIG. Figure 1G-3 as shown in .

[0106] In some embodiments, the upper portion 144A of the top gate electrode layer TG exposed from the recessed gate dielectric layer 142 is laterally recessed by a distance D. In some embodiments, the distance D is in the range of from about 1 nm to about 2 nm. The recessed top gate electrode layer TG can improve the leakage risk between the top gate electrode layers, and the contact plug formed subsequently may be higher. This will be discussed in detail later. In some other embodiments, the upper portion of the sidewall 144S of the top gate electrode layer TG is not laterally recessed.

[0107] In some embodiments, a connection surface 144S1 connecting between the sidewall of the upper portion 144A and the sidewall of the lower portion 144B may be curved (eg, concave). In some embodiments, the connection surface 144S1 may be linearly inclined.

[0108] In some embodiments, the upper portion 144A of the top gate electrode layer TG has a dimension D1 in the X direction, and the dimension D1 is in a range from about 3 nm to about 15 nm. In some embodiments, the lower portion 144B of the top gate electrode layer TG has a dimension D2 in the X direction, and the dimension D2 is in a range from about 5 nm to about 15 nm. In some embodiments, the dimension D1 is smaller than the dimension D2. In some other embodiments, the dimension D1 of the upper portion 144A is substantially equal to the dimension D2 of the lower portion 144B.

[0109] In some embodiments, the ratio (D1 / D2) of dimension D1 to dimension D2 is in a range from about 0.6 to about 1. If the ratio (D1 / D2) is too small, the risk of collapse or swing of the top gate electrode layer TG may increase. In some embodiments, the final gate stack 138 has a critical dimension D3 in the X direction in a range from 10 nm to about 20 nm.

[0110] Figure 1H-1 and Figure 1H-2 is a cross-sectional view corresponding to line YY and line XX of the semiconductor after forming the liner layer 146 and the filling layer 148 according to some embodiments.

[0111] According to some embodiments, a liner layer 146 is formed over the semiconductor structure 100, such as Figure 1H-1 and Figure 1H-2 . According to some embodiments, the liner 146 extends along the top surface 144T and the upper portion of the sidewall 144S of the top gate electrode layer TG, and covers the top surface 144T and the upper portion of the sidewall 144S of the top gate electrode layer TG. According to some embodiments, the liner 146 also extends along the top surface 118T of the gate spacer layer 118 and the top surface 142T of the gate dielectric layer 142, and covers the top surface 118T of the gate spacer layer 118 and the top surface 142T of the gate dielectric layer 142. According to some embodiments, liner 146 also extends along and covers exposed portions 126S of the surface of source / drain feature 126, exposed side surfaces of contact etch stop layer 128, and top surface 130T and side walls of first interlayer dielectric layer 130.

[0112] According to some embodiments, upper portion 144A of top gate electrode layer TG is surrounded by and in direct contact with liner 146 , while lower portion 144B of top gate electrode layer TG is surrounded by and in direct contact with gate dielectric layer 142 .

[0113] In some embodiments, the liner 146 is made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiOC), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, the liner 146 is made of a low-k dielectric material having a dielectric constant less than 10. In some embodiments, the dielectric material for the liner 146 is deposited globally and conformally over the semiconductor structure 100 using CVD (such as LPCVD, PECVD, HDP-CVD, or HARP), ALD, another suitable method, or a combination thereof. In some embodiments, the thickness of the liner 146 is in a range from about 3 nm to about 10 nm. In some embodiments, the thickness of the liner 146 is greater than the thickness of the gate dielectric layer 142.

[0114] According to some embodiments, a filling layer 148 is formed over the liner layer 146, such as Figure 1H-1 and Figure 1H-2 As shown in . According to some embodiments, the filling layer 148 overfills the space between the top gate electrode layers TG. In some embodiments, the filling layer 148 is made of a dielectric material, such as silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, the filling layer 148 is made of a low-k dielectric material having a dielectric constant lower than 10. In some embodiments, the k value of the filling layer 148 can be lower than the k value of silicon oxide (SiO), such as lower than 4.2, equal to or lower than about 3.9, such as in a range from about 3.5 to about 3.9. In some embodiments, the filling layer 148 is deposited using a technique such as CVD (such as HDP-CVD, PECVD, HARP, or FCVD), another suitable technique, or a combination thereof.

[0115] In some embodiments, the filling layer 148 and the liner 146 are made of different materials and have a large difference in etching selectivity. In some embodiments, the dielectric constant of the filling layer 148 is lower than the dielectric constant of the liner 146. In an embodiment where the liner 146 is a silicon nitride layer and the filling layer 148 is a silicon oxide layer, the liner 146 can prevent the upper portion 144A of the top gate electrode layer TG from being oxidized, thereby reducing the risk of adversely affecting the threshold voltage of the resulting semiconductor device.

[0116] Fig. 1I is a perspective view of the semiconductor structure 100 after a planarization process according to some embodiments of the present disclosure. Figure 1I-1 and Figure 1I-2 According to some embodiments, Fig. 1IA cross-sectional view taken along line YY and line XX. Figure 1I-3 yes Figure 1I-2 A magnified view of the diagram is shown to show more details.

[0117] According to some embodiments, a planarization process is performed on the semiconductor structure 100 to expose the top gate electrode layer TG, such as Figure 1I to Figure 1I-3 As shown in . According to some embodiments, the planarization process may be a CMP or an etch-back process. According to some embodiments, the planarization process is performed to thin down the top gate electrode layer TG until the top gate electrode layer TG has a desired height.

[0118] In some embodiments, a portion of the filling layer 148 located above the first interlayer dielectric layer 130 and a portion of the liner 146 along the top surface 130T of the first interlayer dielectric layer 130 are also removed, thereby exposing the top surface 130T of the first interlayer dielectric layer 130. Figure 1I-3 as shown in .

[0119] According to some embodiments, after the planarization process, the top surface 144T of the top gate electrode layer TG, the top surface 146T of the liner 146, the top surface 148T of the filling layer 148, and the top surface 130T of the first interlayer dielectric layer 130 are substantially coplanar, as shown in FIG. Figure 1I-3 as shown in .

[0120] In some embodiments, the top gate electrode layer TG has a height H2 (in the Z direction) above the topmost nanostructure 108_1 together with the gate dielectric layer 142. In some embodiments, the height H2 is in a range from about 10 nm to about 30 nm. In some embodiments, the ratio (H1 / H2) of the height H1 to the height H2 is in a range from about 0.05 to about 0.5. If the ratio (H1 / H2) is too large (e.g., greater than 0.5), the risk of leakage between the top gate electrode layer and the subsequently formed contact plug may be high. This will be discussed in detail later.

[0121] Figure 1J is a perspective view of the semiconductor structure 100 after forming an etch stop layer 150 , a second interlayer dielectric layer 152 , and a contact plug 154 according to some embodiments of the present disclosure. Figure 1J-1 and Figure 1J-2 According to some embodiments, Figure 1J A cross-sectional view taken along line YY and line XX.

[0122] According to some embodiments, an etch stop layer 150 is formed over the semiconductor structure 100, such as Figure 1J to Figure 1J-2. In some embodiments, the etch stop layer 150 is made of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, the dielectric material for the etch stop layer 150 is deposited using CVD (such as LPCVD, PECVD, HDP-CVD, or HARP), ALD, another suitable method, or a combination thereof.

[0123] According to some embodiments, a second interlayer dielectric layer 152 is formed over the etch stop layer 150, such as Figure 1J to Figure 1J-2 . In some embodiments, the second interlayer dielectric layer 152 is made of a dielectric material, such as USG, BPSG, FSG, PSG, BSG, or another suitable dielectric material. In some embodiments, the second interlayer dielectric layer 152 and the etch stop layer 150 are made of different materials and have a large difference in etching selectivity. In some embodiments, the etch stop layer 150 is made of silicon nitride and the second interlayer dielectric layer 152 is made of silicon oxide. In some embodiments, the second interlayer dielectric layer 152 is deposited using a technique such as CVD (such as HDP-CVD, PECVD, HARP, or FCVD), another suitable technique, or a combination thereof.

[0124] According to some embodiments, a contact plug 154 is formed through the second interlayer dielectric layer 152, the etch stop layer 150, the first interlayer dielectric layer 130, and the contact etch stop layer 128. Figure 1J-1 to Figure 1J-2 According to some embodiments, contact plug 154 is bonded on and electrically connected to source / drain feature 126 .

[0125] In some embodiments, the formation of the contact plug 154 includes patterning the semiconductor structure 100 using photolithography and etching processes to form contact openings (where the contact plug 154 is to be formed) until the source / drain features 126 are exposed. The etching process may include dry etching, such as reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma (ICP) etching, capacitively coupled plasma (CCP) etching, another suitable method, or a combination thereof.

[0126] According to some embodiments, a deposition process and an etch-back process are used to form contact pad 156 along the sidewall of the contact opening. In some embodiments, contact pad 156 is made of an insulating material such as a dielectric material (e.g., SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, SiN, HfSi, or SiO); or undoped silicon (Si).

[0127] A silicide layer 158 is formed on the exposed surface of the source / drain feature 126. In some embodiments, the silicide layer 158 is made of WSi, NiSi, TiSi and / or CoSi. In some embodiments, the formation of the silicide layer 158 includes depositing a metal material and subsequently one or more annealing processes. According to some embodiments, the semiconductor material (e.g., Si) from the source / drain feature 126 reacts with the metal material to form the silicide layer 158. The unreacted metal material is then removed, for example, using wet etching.

[0128] Afterwards, according to some embodiments, one or more conductive materials for contact plug 154 are deposited to overfill the contact opening. In some embodiments, one or more conductive materials are deposited to overfill the contact opening using CVD, PVD, electron beam evaporation, ALD, electroplating (ECP), chemical deposition (ELD), another suitable method, or a combination thereof. The one or more conductive materials on the upper surface of second interlayer dielectric layer 152 are planarized using, for example, CMP.

[0129] The contact plug 154 may have a multilayer structure. For example, a barrier / adhesion layer (not shown) may be optionally deposited along the sidewalls and bottom surface of the contact opening. The barrier / adhesion layer may be made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), another suitable material, or a combination thereof. A metal bulk layer is then deposited on the barrier / adhesion layer (if formed) to fill the remaining portion of the contact opening. In some embodiments, the metal bulk layer is made of one or more conductive materials having low resistance and good gap filling capability, for example, cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), rhodium (Rh), iridium (Ir), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), another suitable metal material, or a combination thereof.

[0130] As the scale of semiconductor devices continues to shrink, one of the design challenges of semiconductor devices is to reduce the gate-to-gate pitch P, such as Figure 1J-2Scaling of the gate-to-gate pitch P may be achieved by reducing the critical dimension D3 of the final gate stack 138 , the critical dimension D4 of the contact plug 154 , and / or the spacing between the final gate stack 138 and the contact plug 154 .

[0131] However, the reduction in the critical dimension of the gate stack (or dummy gate structure) may reduce the gap filling capability of the metal gate electrode material, thereby adversely affecting the threshold voltage of the resulting semiconductor device. The reduction in the critical dimension of the contact plug may reduce the contact plug's bonding area on the source / drain feature, thereby increasing the resistance of the resulting semiconductor device.

[0132] In addition, the reduction of the spacing between the gate stack and the contact plug is limited by the capabilities of the lithography process used to form the contact opening (e.g., the stacking window). In the instance where the contact plug is offset toward the final gate stack, the risk of leakage between the top gate electrode layer and the contact plug may be significantly increased because the gate dielectric layer 142 may contain conductive materials (e.g., titanium) and / or crystal defects and may be conductive to serve as a leakage path. The location most susceptible to leakage may be on the top surface of the top gate electrode layer because this is the closest spacing between the gate stack and the contact plug.

[0133] According to some embodiments of the present disclosure, after forming the final gate stack 138, the gate dielectric layer 142 is recessed so as to reduce the size of the top portion of the final gate stack 138 (i.e., substantially equal to the size D1 of the upper portion 144A of the top gate electrode layer TG) without reducing the gap filling capability of the metal gate electrode material, and thus the interval S between the contact plug 154 and the final gate stack 138 can be increased. That is, because the gate dielectric layer 142, which can serve as a leakage path, is recessed, the window for electrical isolation between the contact plug 154 and the final gate stack 138 can be increased.

[0134] When the contact plug 154 is offset toward the final gate stack 138, the risk of leakage between the top gate electrode layer TG and the contact plug 154 may not increase significantly. Therefore, the reliability of the resulting semiconductor device (e.g., the window of time-dependent dielectric breakdown (TDDB)) can be improved. In addition, the overlay window of the photolithography process for forming the contact opening 150 can be relaxed, which can promote the reduction of the gate-to-gate spacing.

[0135] Furthermore, according to some embodiments, upper portion 144A of top gate electrode layer TG is surrounded by liner 146, which has a lower dielectric constant than gate dielectric layer 142 and better electrical isolation than gate dielectric layer 142. Therefore, according to some embodiments, parasitic capacitance between top gate electrode layer TG and contact plug 154 may be reduced, thereby improving performance (e.g., speed) of the resulting semiconductor device.

[0136] It should be understood that the semiconductor structure 100 may undergo further CMOS processes to form various features over the semiconductor structure, such as multi-layer interconnect structures (eg, conductive vias, metal lines, inter-metal dielectric layers, passivation layers, etc.).

[0137] Figure 2A-1 to Figure 2D-2 is a schematic diagram showing the formation of a semiconductor structure 200 at various intermediate stages according to some embodiments of the present disclosure. Figure 2A-1 to Figure 2D-2 An embodiment similar to Figures 1A to 1J-2 The embodiment of the present invention differs in that the first interlayer dielectric layer 130 and the contact etch stop layer 128 are heavily recessed in the etching process for recessing the gate spacer layer 118 and the gate dielectric layer 142.

[0138] Figure 2A-1 and Figure 2A-2 is a cross-sectional view corresponding to line YY and line XX of the semiconductor structure 200 after an etching process according to some embodiments.

[0139] According to some embodiments, continue from Figure 1G to Figure 1G-3 , an etching process is performed on the semiconductor structure 200 to recess the gate spacer layer 118 and the gate dielectric layer, such as Figure 2A-1 and Figure 2A-2 . According to some embodiments, vertical portion 142A of gate dielectric layer 142 is substantially completely removed, and the etching process stops on horizontal portion 142B of gate dielectric layer 142, due to the high crystallinity of horizontal portion 142B. According to some embodiments, gate spacer layer 118 above topmost nanostructure 108_1 is removed, so that topmost nanostructure 108_1 is exposed from trench 145.

[0140] According to some embodiments, sidewalls 144S of the top gate electrode layer TG are completely exposed from the gate dielectric layer 142. According to some embodiments, a top surface 142T of the gate dielectric layer 142 is substantially flush with a bottom surface of the top gate electrode layer TG.

[0141] The second topmost nanostructure 108 is denoted as 108_2. Figure 2A-1 The topmost nanostructure 108_1 and the second topmost nanostructure 108_2 are shown in FIG. Figure 2A-11 are shown as dashed lines, indicating that they are behind or in front of the cross-sectional view. According to some embodiments, the contact etch stop layer 128 and the first interlayer dielectric layer 130 are also recessed and etched to a position located a distance D5 below the top surface of the topmost nanostructure 108_1, thereby exposing the upper portion of the surface of the source / drain feature 126. In some embodiments, the distance D5 is less than about 30 nm.

[0142] In some embodiments, a top surface 128T of the contact etch stop layer 128 and a top surface 130T of the first interlayer dielectric layer 130 are substantially flush with or higher than a top surface of the second topmost nanostructure 108_2 .

[0143] Figure 2B-1 and Figure 2B-2 is a cross-sectional view of the semiconductor structure 200 corresponding to line YY and line XX after forming the liner layer 146 and the filling layer 148 according to some embodiments.

[0144] According to some embodiments, a liner 146 is formed over the semiconductor structure 200, and a second interlayer dielectric layer 148 is formed over the liner 146. Figure 2B-1 and Figure 2B-2 . According to some embodiments, the liner 146 extends along the top surface 144T and the sidewall 144S of the top gate electrode layer TG and covers the top surface 144T and the sidewall 144S of the top gate electrode layer TG. According to some embodiments, the liner 146 also extends along the upper portion of the surface of the source / drain feature 126 and covers the upper portion of the surface of the source / drain feature 126.

[0145] According to some embodiments, liner 146 also covers the top surface of topmost nanostructure 108_1 and top surface 142T of gate dielectric layer 142. According to some embodiments, liner 146 also covers top surface 128T of contact etch stop layer 128 and top surface 130T and sidewalls of first interlayer dielectric layer 130.

[0146] Figure 2C is a perspective view of the semiconductor structure 200 after a planarization process according to some embodiments of the present disclosure. Figure 2C-1 and Figure 2C-2 According to some embodiments, Figure 2C A cross-sectional view taken along line YY and line XX. Figure 2C-3 yes Figure 2C-2 A magnified image is shown to show more details.

[0147] According to some embodiments, a planarization process is performed on the semiconductor structure 200 to expose the top gate electrode layer TG, such as Figure 2C to Figure 2C-3According to some embodiments, after the planarization process, the top surface 144T of the top gate electrode layer TG, the top surface 146T of the liner 146, and the top surface 148T of the filling layer 148 are substantially coplanar, as shown in FIG. Figure 2C-3 as shown in .

[0148] In some embodiments, the height H1 of the gate dielectric layer 142 above the topmost nanostructure 108_1 is in a range from about 1 nm to about 2 nm. In some embodiments, the top gate electrode layer TG has a height H2 in a range from about 10 nm to about 30 nm. In some embodiments, the ratio of the height H1 to the height H2 (H1 / H2) is in a range from about 0.05 to about 0.1. Because the vertical portion of the gate dielectric layer 142 above the topmost nanostructure 108_1 is completely removed, the leakage risk between the top gate electrode layer and the contact plug can be further reduced.

[0149] Figure 2D-1 and Figure 2D-2 is a cross-sectional view of the semiconductor structure 200 corresponding to line YY and line XX after forming an etch stop layer 150 , a second interlayer dielectric layer 152 , and a contact plug 154 according to some embodiments.

[0150] According to some embodiments, an etch stop layer 150 is formed over the semiconductor structure 200, a second interlayer dielectric layer 152 is formed over the etch stop layer 150, and a contact plug 154 is formed through the second interlayer dielectric layer 152, the etch stop layer 150, the filling layer 148, and the liner 146. Figure 2D-1 and Figure 2D-2 as shown in .

[0151] Figure 3 Some embodiments of the present disclosure are shown Figure 2C-3 Modification of the semiconductor structure. Figure 3 An embodiment similar to Figure 2A-1 to Figure 2D-2 , except that after the etching process for recessing the gate spacer layer 118 and the gate dielectric layer 142, the gate spacer layer 118 has a portion remaining on the top surface of the topmost nanostructure 108_1.

[0152] Figure 4A-1 to Figure 4B-2 is a cross-sectional view illustrating the formation of a semiconductor structure 300 at various intermediate stages according to some embodiments of the present disclosure. Figure 4A-1 to Figure 4B-2 An embodiment similar to Figures 1A to 1J-2 The embodiment of the present invention is different in that the filling layer 148 and the liner layer 146 remain on the first interlayer dielectric layer 130 after the planarization process.

[0153] Figure 4A-1 and Figure 4A-2A cross-sectional view corresponding to line YY and line XX of the semiconductor structure 300 after a planarization process is shown in accordance with some embodiments.

[0154] According to some embodiments, continue from Figure 1I to Figure 1I-2 , a planarization process is performed on the semiconductor structure 300 to expose the top gate electrode layer TG, such as Figure 4A-1 and Figure 4A-2 In some embodiments, after the planarization process, the filling layer 148 and the liner 146 remain above the top surface 130T of the first interlayer dielectric layer 130. According to some embodiments, the top surface 144T of the top gate electrode layer TG, the top surface 146T of the liner 146, and the top surface 148T of the filling layer 148 are substantially coplanar, as shown in FIG. Figure 4A-2 as shown in .

[0155] Figure 4B-1 and Figure 4B-2 A cross-sectional view corresponding to line YY and line XX of the semiconductor structure 300 is shown after forming an etch stop layer 150 , a second interlayer dielectric layer 152 , and a contact plug 154 , according to some embodiments.

[0156] According to some embodiments, an etch stop layer 150 is formed over the semiconductor structure 300, a second interlayer dielectric layer 152 is formed over the etch stop layer 150, and a contact plug 154 is formed through the second interlayer dielectric layer 152, the etch stop layer 150, the filling layer 148, the liner 146, the first interlayer dielectric layer 130, and the contact etch stop layer 128. Figure 4B-1 and Figure 4B-2 as shown in .

[0157] Figure 5A-1 to Figure 5D-2 4 is a cross-sectional view illustrating the formation of a semiconductor structure 400 at various intermediate stages according to some embodiments of the present disclosure. Figure 5A-1 to Figure 5D-2 An embodiment similar to Figures 1A to 1J-2 , except that a top surface 128T of the etch stop layer 128 is exposed in the etching process for recessing the gate spacer layer 118 and the gate dielectric layer 142.

[0158] Figure 5A-1 and Figure 5A-2 A cross-sectional view corresponding to line YY and line XX of the semiconductor structure 400 is shown after an etching process in accordance with some embodiments.

[0159] According to some embodiments, continue from Figure 1G to Figure 1G-3 , an etching process is performed on the semiconductor structure 400 to recess the gate spacer layer 118 and the gate dielectric layer, such as Figure 5A-1 and Figure 5A-2According to some embodiments, during the etching process, a portion of the first interlayer dielectric layer 130 located above the contact etch stop layer 128 is removed, thereby exposing a top surface 128T of the contact etch stop layer 128 .

[0160] Figure 5B-1 and Figure 5B-2 A cross-sectional view corresponding to line YY and line XX of the semiconductor structure 400 is shown after forming a liner layer 146 and a filling layer 148 in accordance with some embodiments.

[0161] According to some embodiments, a liner 146 is formed over the semiconductor structure 400, and a second interlayer dielectric layer 148 is formed over the liner 146. Figure 5B-1 and Figure 5B-2 According to some embodiments, liner 146 extends along and covers top surface 144T and sidewall 144S of top gate electrode layer TG and top surface 128T of contact etch stop layer 128 .

[0162] Figure 5C-1 and Figure 5C-2 A cross-sectional view corresponding to line YY and line XX of the semiconductor structure 400 after a planarization process is shown in accordance with some embodiments.

[0163] According to some embodiments, a planarization process is performed on the semiconductor structure 400 to expose the top gate electrode layer TG, such as Figure 5C-1 and Figure 5C-2 According to some embodiments, in some embodiments, after the planarization process, the top surface 144T of the top gate electrode layer TG, the top surface 146T of the liner 146, and the top surface 148T of the filling layer 148 are substantially coplanar, as shown in FIG. Figure 5C-2 as shown in .

[0164] Figure 5D-1 and Figure 5D-2 A cross-sectional view corresponding to line YY and line XX of the semiconductor structure 400 is shown after forming an etch stop layer 150 , a second interlayer dielectric layer 152 , and a contact plug 154 , according to some embodiments.

[0165] According to some embodiments, an etch stop layer 150 is formed over the semiconductor structure 400, a second interlayer dielectric layer 152 is formed over the etch stop layer 150, and a contact plug 154 is formed through the second interlayer dielectric layer 152, the etch stop layer 150, the filling layer 148, the liner 146, and the contact etch stop layer 128. Figure 5D-1 and Figure 5D-2 as shown in .

[0166] As described above, the method for forming a semiconductor structure includes recessing the gate dielectric layer 142 to expose the top gate electrode layer TG. Therefore, the size of the top portion of the final gate stack 138 can be reduced, and thus the spacing S between the contact plug 154 and the final gate stack 138 can be increased. Therefore, the reliability of the resulting semiconductor device can be improved. In addition, the overlap window of the photolithography process for forming the contact opening 150 can be relaxed, which can promote the reduction of the gate-to-gate spacing.

[0167] Furthermore, the top gate electrode layer TG is at least partially surrounded by the liner 146, which has a lower dielectric constant than the gate dielectric layer 142 and better electrical isolation than the gate dielectric layer 142. Therefore, according to some embodiments, the parasitic capacitance between the top gate electrode layer TG and the contact plug 154 can be reduced, thereby improving the performance of the resulting semiconductor device.

[0168] Resistance-capacitance (RC) delay has become a significant challenge as reduced geometries are implemented to achieve ICs with faster operating speeds (e.g., by reducing the distance that electrical signals propagate), thereby offsetting some of the advantages achieved by shrinking and limiting further shrinking of ICs. RC delay generally represents the delay in the speed of electrical signals through an IC caused by the product of resistance (R) (i.e., the resistance of a material to the flow of electric current) and capacitance (C) (i.e., the ability of a material to store charge). Therefore, it is desirable to reduce resistance and capacitance to reduce RC delay and optimize the performance of shrunken ICs. As IC technology expands to sub-20nm technology nodes, reduced critical dimensions (e.g., gate length, gate pitch, fin pitch, size of vias, size of metal lines, via pitch, metal line pitch, etc.) lead to increased parasitic capacitance, and therefore increased RC delay, which can no longer be ignored when designing shrunken ICs. For transistors, parasitic capacitance may come from gate-to-source / drain capacitance and gate-to-source / drain contact capacitance. The material separating the gate stack of a transistor from its source / drain features (e.g., gate spacers and / or high-k gate dielectrics) and source / drain contacts (e.g., gate spacers, high-k gate dielectrics, interlayer dielectric (ILD) layers, etc.) can increase or decrease gate-to-source / drain capacitance and gate-to-source / drain contact capacitance, and thus increase or decrease the total parasitic capacitance of the transistor. Therefore, efforts to reduce the total parasitic capacitance of a transistor are generally directed to reducing the dielectric constant of the material separating the gate stack from the source / drain features and / or source / drain contacts.

[0169] The disclosed embodiments recognize that the high-k gate dielectric of the gate stack (which is typically implemented to improve transistor performance) also contributes to the total parasitic capacitance of the transistor. The contribution of the high-k gate dielectric to parasitic capacitance (such as the parasitic capacitance between the gate electrode and the source / drain contacts) is becoming increasingly prevalent and detrimental in transistors at scaled technology nodes. In addition, the conductive sidewall portions of the high-k gate dielectric (such as those formed along the sidewalls of the gate electrode) may undesirably create a conductive path between the gate electrode and the source / drain contacts, which may degrade transistor performance. In addition, time-dependent dielectric breakdown (TBBD) considerations may constrain the distance / spacing between the gate stack and the source / drain contacts, which may be further limited by the overlap window corresponding to the lithography process used to form the source / drain contact openings, in which the source / drain contacts are formed. This constraint on reducing the distance / spacing between the gate stack and the source / drain contacts limits further IC scaling.

[0170] The disclosed embodiments provide for removing sidewall portions of high-k gate dielectrics and / or recessing sidewall portions of high-k gate dielectrics to solve such problems and / or improve contact gate isolation (e.g., isolation between a gate electrode and a source / drain contact), thereby improving transistor performance. In some embodiments, a gate structure includes a gate stack and a gate spacer disposed along a sidewall of the gate stack, and the gate stack includes a gate electrode disposed above the high-k gate dielectric. The high-k gate dielectric may wrap around the gate electrode. For example, the high-k gate dielectric has a sidewall portion located between the sidewalls of the gate electrode and the gate spacer and a bottom portion located between the gate electrode and the semiconductor layer (e.g., a channel). The contact gate isolation process may include: recessing the sidewall portions of the high-k gate dielectric and the gate spacer (e.g., by etching) to form a contact gate isolation (CGI) opening that exposes the sidewall of the gate electrode; forming a gate isolation liner that partially fills the CGI opening along the sidewall of the gate electrode; and forming a gate isolation layer that fills the remaining portion of the CGI opening above the gate isolation liner. The gate isolation liner and the gate isolation layer may form a CGI structure over the gate spacer and / or the high-k gate dielectric, and the gate isolation liner may be disposed between the gate spacer and the sidewall of the gate electrode. The gate isolation liner and the gate isolation layer each include a dielectric material having a dielectric constant less than the dielectric constant of the high-k gate dielectric, such as a dielectric material having a dielectric constant less than about 8. In some embodiments, the gate isolation liner and the gate isolation layer each include a dielectric material including silicon and oxygen, nitrogen, carbon, or a combination thereof. In some embodiments, the dielectric constant of the gate isolation layer is less than the dielectric constant of the gate isolation liner. In some embodiments, the gate isolation liner includes nitrogen, which may prevent and / or reduce oxidation of the gate electrode.

[0171] In some embodiments, the sidewall portion of the high-k gate dielectric has an amorphous structure, and the bottom portion of the high-k gate dielectric has a crystalline structure. In such embodiments, the etching process for recessing the high-k gate dielectric can have different etching selectivities relative to the sidewall portion of the high-k gate dielectric and the bottom portion of the high-k gate dielectric, so that the etching process can stop when reaching the bottom portion of the high-k gate dielectric. Therefore, the sidewall portion of the high-k gate dielectric can be easily removed relative to the bottom portion of the high-k gate dielectric, which can prevent and / or minimize damage to the underlying semiconductor layer (i.e., the underlying channel). In some embodiments, the recess / etch partially removes the sidewall portion of the high-k gate dielectric, the sidewall portion of the high-k gate dielectric covers the lower portion of the sidewall of the gate electrode, and the gate isolation liner covers the upper portion of the sidewall of the gate electrode. In some embodiments, the recess / etch completely removes the sidewall portion of the high-k gate dielectric, and the gate isolation liner covers the sidewall of the gate electrode. In some embodiments, the recessing / etching reduces the width of the gate electrode (eg, the gate electrode may be laterally etched such that the gate electrode has a top width that is smaller than a bottom width).

[0172] In some embodiments, the recess / etching reduces the thickness of the ILD layer and / or the contact etch stop layer (CESL). In such embodiments, the gate isolation liner and / or the gate isolation layer may be formed above the top surface of the ILD layer and / or the top surface of the CESL. In some embodiments, the ILD layer is removed after the high-k gate dielectric and / or gate spacer is recessed / etched and before the gate isolation liner and / or the gate isolation layer are formed. In such embodiments, the gate isolation liner and / or the gate isolation layer may be formed above the CESL, and a portion of the CESL may be formed above the epitaxial source / drain. In some embodiments, the recess / etching may remove a portion of the ILD layer and / or the CESL located above the top surface of the epitaxial source / drain. In such embodiments, the gate isolation liner and / or the gate isolation layer may be formed above the epitaxial source / drain.

[0173] Embodiments of semiconductor structures and methods for forming the same may be provided. The method for forming the semiconductor structure includes: recessing a gate dielectric layer to expose a gate electrode layer; forming a liner to cover an exposed sidewall of a gate stack. Thus, the size of a top portion of the gate stack may be reduced. Thus, an overlay window of a photolithography process for forming a contact opening may be relaxed, which may facilitate a reduction in gate-to-gate spacing.

[0174] In some embodiments, a method for forming a semiconductor structure is provided. The method includes: forming a channel layer above a substrate; forming a gate spacer layer above the channel layer; forming a gate dielectric layer along the sidewalls of the gate spacer layer and the top surface of the channel layer; forming a gate electrode layer above the gate dielectric layer to fill the grooves between the gate spacer layers; recessing the gate dielectric layer to expose the sidewalls of the gate electrode layer; and forming a liner to cover the sidewalls of the gate electrode layer exposed from the gate dielectric layer. In some embodiments, the dielectric constant of the liner is lower than the dielectric constant of the gate dielectric layer. In some embodiments, the method further includes: recessing the gate electrode layer laterally when recessing the gate dielectric layer. In some embodiments, the channel layer includes a plurality of nanostructures stacked vertically and spaced apart from each other.

[0175] In some embodiments, the method further comprises forming a filling layer above the liner. The filling layer is made of a material different from the liner. In some embodiments, the method further comprises: planarizing the filling layer and the liner until a top surface of the gate electrode layer is exposed. In some embodiments, the method further comprises: recessing the gate spacer layer when recessing the gate dielectric layer. After recessing the gate spacer layer and the gate dielectric layer, a top surface of the gate dielectric layer is lower than a top surface of the gate spacer layer.

[0176] In some embodiments, the method further comprises: forming a source / drain feature adjacent to the channel layer; forming a contact etch stop layer over the source / drain feature; forming an interlayer dielectric layer over the contact etch stop layer; and recessing the interlayer dielectric layer and the contact etch stop layer when recessing the gate dielectric layer. In some embodiments, after recessing the interlayer dielectric layer and the contact etch stop layer, a top surface of the contact etch stop layer is lower than a top of the source / drain feature.

[0177] In some embodiments, the gate dielectric layer includes a vertical portion along the sidewalls of the gate spacer layer, and recessing the gate dielectric layer includes etching an upper portion of the vertical portion of the gate dielectric layer at a first etch rate and etching a lower portion of the vertical portion of the gate dielectric layer at a second etch rate that is slower than the first etch rate.

[0178] In some embodiments, a method for forming a semiconductor structure is provided. The method includes: forming a dummy gate structure above an active region; forming a source / drain component adjacent to the active region; forming an interlayer dielectric layer above the source / drain component; and replacing the dummy gate structure with a gate stack. The gate stack includes a gate dielectric layer located above a gate electrode layer. The method also includes: etching the interlayer dielectric layer and the gate dielectric layer to expose an upper portion of the gate electrode layer; and forming a filling layer along the upper portion of the gate electrode layer. In some embodiments, the method also includes: forming a contact plug through the filling layer on the source / drain component. In some embodiments, the contact plug also penetrates the interlayer dielectric layer. In some embodiments, the method also includes forming a contact etch stop layer to cover the source / drain component. The interlayer dielectric layer is formed above the contact etch stop layer, and etching the interlayer dielectric layer and the gate dielectric layer may include removing the interlayer dielectric layer to expose the top surface of the contact etch stop layer. The contact plug may also penetrate the contact etch stop layer.

[0179] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a plurality of nanostructures located above a substrate; a source / drain component adjacent to the plurality of nanostructures; a gate dielectric layer located above the topmost nanostructure in the nanostructures; a gate electrode layer located above the gate dielectric layer; and a liner located above the gate dielectric layer. The liner includes a first portion along the sidewall of the gate electrode layer and in direct contact with the sidewall of the gate electrode layer. In some embodiments, the dielectric constant of the liner is lower than the dielectric constant of the gate dielectric layer. In some embodiments, the semiconductor structure also includes a contact etch stop layer covering the source / drain component and an interlayer dielectric layer above the contact etch stop layer. The liner includes a second portion along the sidewall of the interlayer dielectric layer and in direct contact with the sidewall of the interlayer dielectric layer. In some embodiments, a portion of the surface of the source / drain component is covered by the liner and in direct contact with the liner. In some embodiments, a portion of the top surface of the topmost nanostructure is covered by the liner and in direct contact with the liner. In some embodiments, the semiconductor structure also includes a filling layer above the liner. The top surface of the filling layer can be substantially flush with the top surface of the interlayer dielectric layer. In some embodiments, the gate electrode layer includes an upper portion surrounded by the liner layer and a lower portion surrounded by the gate dielectric layer. The upper portion of the gate electrode layer may be narrower than the lower portion of the gate electrode layer.

[0180] Some embodiments of the present application provide a method for forming a transistor, comprising: forming a gate stack above a semiconductor layer, wherein the gate stack includes a gate electrode disposed above a gate dielectric, wherein the gate stack is disposed between a first epitaxial source / drain and a second epitaxial source / drain; etching the gate dielectric to expose the sidewalls of the gate electrode; forming a gate isolation pad along the exposed sidewalls of the gate electrode; and forming a source / drain contact to the first epitaxial source / drain.

[0181] In some embodiments, the method further includes: forming gate spacers along sidewalls of the gate stack, wherein the gate dielectric is located between the gate spacers and the sidewalls of the gate electrode; and etching the gate spacers when etching the gate dielectric.

[0182] In some embodiments, etching the gate dielectric and etching the gate spacers form a gap, the gate isolation liner partially fills the gap, and the method further includes forming a gate isolation layer to fill a remaining portion of the gap.

[0183] In some embodiments, etching the gate spacer exposes the first epitaxial source / drain, the second epitaxial source / drain, or both, wherein the gate isolation liner is formed on the first epitaxial source / drain, the second epitaxial source / drain, or both.

[0184] In some embodiments, the method further includes forming a first dielectric layer before etching the gate dielectric and before etching the gate spacers, wherein the first dielectric layer includes an interlayer dielectric (ILD) layer disposed over a contact etch stop layer (CESL).

[0185] In some embodiments, etching the gate dielectric and etching the gate spacers form a gap between the sidewalls of the gate electrode and the first dielectric layer, and the gate isolation liner partially fills the gap, and the method further includes forming a second dielectric layer to fill the remaining portion of the gap.

[0186] In some embodiments, the method further includes etching the first dielectric layer while etching the gate spacers.

[0187] In some embodiments, etching the gate spacer and etching the first dielectric layer exposes the first epitaxial source / drain, the second epitaxial source / drain, or both, wherein the gate isolation pad is formed on the first epitaxial source / drain, the second epitaxial source / drain, or both.

[0188] In some embodiments, etching the gate dielectric reduces a width of the gate electrode.

[0189] Other embodiments of the present application provide a method for forming a transistor, comprising: forming a channel layer above a substrate; forming a gate structure above the channel layer by the following steps: forming a gate spacer; forming a gate dielectric layer above the channel layer, wherein the gate dielectric layer is arranged along the sidewalls of the gate spacer; and forming a gate electrode layer above the gate dielectric layer; recessing the gate dielectric layer to expose the sidewalls of the gate electrode layer; and forming a liner to cover the exposed sidewalls of the gate electrode layer.

[0190] In some embodiments, the method further includes: forming a filling layer above the liner, wherein a composition of the filling layer is different from a composition of the liner; and performing a planarization process on the filling layer and the liner, wherein the planarization process exposes the gate electrode layer.

[0191] In some embodiments, the method further comprises recessing the gate spacer when recessing the gate dielectric layer, wherein after recessing the gate spacer and recessing the gate dielectric layer, a top surface of the gate dielectric layer is lower than a top surface of the gate spacer.

[0192] In some embodiments, the method further includes: forming a source / drain feature adjacent to the channel layer; forming a contact etch stop layer above the source / drain feature; forming an interlayer dielectric layer above the contact etch stop layer; and recessing the interlayer dielectric layer and the contact etch stop layer when recessing the gate dielectric layer.

[0193] In some embodiments, the method further includes: laterally recessing the gate electrode layer when recessing the gate dielectric layer.

[0194] Some other embodiments of the present application provide a transistor, comprising: a semiconductor layer, arranged between a first epitaxial source / drain and a second epitaxial source / drain; a gate structure, arranged above the semiconductor layer, wherein the gate structure comprises a gate stack and a gate spacer arranged along the sidewall of the gate stack, wherein: the gate stack comprises a gate electrode arranged above a high-k gate dielectric, wherein the high-k gate dielectric is arranged along a lower portion of the sidewall of the gate electrode, and the high-k gate dielectric is arranged between the gate spacer and the lower portion of the sidewall of the gate electrode; and a gate isolation pad, arranged along an upper portion of the sidewall of the gate electrode, wherein the gate isolation pad is arranged above the gate spacer and the high-k gate dielectric.

[0195] In some embodiments, a width of a lower portion of the gate electrode is greater than a width of an upper portion of the gate electrode.

[0196] In some embodiments, the gate isolation liner extends below a top surface of the gate spacer, wherein a portion of the gate isolation liner is located between the gate spacer and the lower portion of the sidewall of the gate electrode.

[0197] In some embodiments, the transistor further includes: an interlayer dielectric layer disposed above the first epitaxial source / drain and the second epitaxial source / drain, wherein the gate isolation liner physically contacts the interlayer dielectric layer.

[0198] In some embodiments, the transistor further includes: a gate isolation layer disposed above the gate isolation pad and wrapped by the gate isolation pad.

[0199] In some embodiments, the dielectric constant of the gate isolation layer is smaller than the dielectric constant of the gate isolation liner.

[0200] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of forming a transistor, comprising: forming a gate stack over the semiconductor layer, wherein the gate stack includes a gate electrode disposed over a gate dielectric, wherein the gate stack is disposed between a first epitaxial source / drain and a second epitaxial source / drain; etching the gate dielectric to expose sidewalls of the gate electrode; forming a gate isolation liner along the exposed sidewall of the gate electrode; and Source / drain contacts are formed to the first epitaxial source / drain.

2. The method according to claim 1, further comprising: forming gate spacers along sidewalls of the gate stack, wherein the gate dielectric is located between the gate spacers and the sidewalls of the gate electrode; and The gate spacers are etched while the gate dielectric is being etched.

3. The method according to claim 2, wherein: The gate dielectric is etched and the gate spacer is etched to form a gap, the gate isolation liner partially fills the gap, and the method further includes forming a gate isolation layer to fill a remaining portion of the gap.

4. The method according to claim 2, wherein: The gate spacers are etched to expose the first epitaxial source / drain, the second epitaxial source / drain, or both, wherein the gate isolation liner is formed on the first epitaxial source / drain, the second epitaxial source / drain, or both.

5. The method according to claim 2, further comprising: A first dielectric layer is formed before etching the gate dielectric and before etching the gate spacers, wherein the first dielectric layer includes an interlayer dielectric (ILD) layer disposed over a contact etch stop layer (CESL).

6. The method according to claim 5, wherein: Etching the gate dielectric and etching the gate spacers form a gap between the sidewall of the gate electrode and the first dielectric layer, and the gate isolation liner partially fills the gap, and the method further includes forming a second dielectric layer to fill a remaining portion of the gap.

7. The method according to claim 5, further comprising: The first dielectric layer is etched while etching the gate spacers.

8. The method according to claim 7, wherein: Etching the gate spacers and etching the first dielectric layer exposes the first epitaxial source / drain, the second epitaxial source / drain, or both, wherein the gate isolation liner is formed on the first epitaxial source / drain, the second epitaxial source / drain, or both.

9. A method of forming a transistor, comprising: forming a channel layer over the substrate; A gate structure is formed above the channel layer by the following steps: forming a gate spacer; forming a gate dielectric layer over the channel layer, wherein the gate dielectric layer is disposed along sidewalls of the gate spacer; and forming a gate electrode layer over the gate dielectric layer; recessing the gate dielectric layer to expose sidewalls of the gate electrode layer; and A liner layer is formed to cover the exposed sidewalls of the gate electrode layer.

10. A transistor comprising: A semiconductor layer is disposed between the first epitaxial source / drain and the second epitaxial source / drain; A gate structure is disposed above the semiconductor layer, wherein the gate structure includes a gate stack and a gate spacer disposed along a sidewall of the gate stack, wherein: The gate stack includes a gate electrode disposed over a high-k gate dielectric, wherein the high-k gate dielectric is disposed along a lower portion of a sidewall of the gate electrode and the high-k gate dielectric is disposed between the gate spacers and the lower portion of the sidewall of the gate electrode; and A gate isolation liner is disposed along an upper portion of a sidewall of the gate electrode, wherein the gate isolation liner is disposed over the gate spacer and the high-k gate dielectric.

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