Systems, devices, and methods for nanowires for semiconductor packages

Abstract

Systems, devices, and methods for nanowires for semiconductor packages are provided herein. The semiconductor package may include a die attached to a substrate. The cover may also be attached to the substrate. The die includes a die nanowire, and the cap includes a cap nanowire. The nanowires may be formed over the entirety of the die or in a pattern. The cover may have a corresponding or symmetric overlay or pattern. In a semiconductor package, a die nanowire is coupled with a lid nanowire to provide improved heat dissipation, etc.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to nanowires for semiconductors, and more particularly to heat dissipation in a semiconductor package using nanowires. Background Art

[0002] A semiconductor package may include a die or chip enclosed under a lid or cap. The lid acts as a heat sink to dissipate heat. A thermal interface material (TIM) may be used between the die and the lid to help dissipate heat from the die to the lid. The TIM may degrade over time, including shrinking from the edges of the coverage applied by the TIM between the die and the lid. This shrinkage reduces the efficiency of heat dissipation. In addition, the shrinkage in the TIM coverage further concentrates heat in locations that are still covered by the TIM, thereby absorbing heat unevenly (compared to uncovered locations), which may further concentrate heat and accelerate degradation.

[0003] New systems, apparatus, and methods for semiconductor packaging are needed. The inventors have discovered many improvements in existing techniques and processes that are the subject of the embodiments described herein. Through hard work, ingenuity, and innovation, many of these deficiencies, challenges, and problems have been addressed by developing solutions included in the embodiments of the present disclosure, some examples of which are described in detail herein. Summary of the invention

[0004] Various embodiments described herein relate to systems, apparatus, and methods for nanowires in semiconductor packaging.

[0005] According to some embodiments of the present disclosure, an example semiconductor package is provided. The semiconductor package may include: a substrate; a die including a first side of the die and a second side of the die, wherein the first side of the die includes a formation of multiple die nanowires, wherein the second side of the die is coupled to the substrate; a lid including a first side of the lid facing the die, wherein the first side of the lid includes a formation of multiple lid nanowires; and wherein at least one formation of the die nanowire is coupled to at least one formation of the lid nanowire.

[0006] In some embodiments, the cover is composed of a cover top portion and a plurality of cover side portions, and the cover top portion is coupled to the cover side portions by glue.

[0007] In some embodiments, the at least one of the formations of the plurality of die nanowires is coupled to at least one of the formations of the plurality of cap nanowires, and wherein the coupling is aligned with a shared common axis.

[0008] In some embodiments, at least one of the plurality of die nanowire formations is coupled to at least one of the plurality of cap nanowire formations, and wherein the coupling is misaligned, wherein the at least one of the plurality of die nanowire formations has a different axis than the at least one of the plurality of cap nanowire formations.

[0009] In some embodiments, the formation of the plurality of cap nanowires covers a first portion of the first side of the cap that is not the entirety of the first side of the cap.

[0010] In some embodiments, the formation of the plurality of die nanowires covers a first portion of the first side of the die that is not the entirety of the first side of the die.

[0011] In some embodiments, the first portion of the first side of the die covered by the formation of the plurality of die nanowires includes coverage of at least one die hotspot.

[0012] In some embodiments, the formation of the plurality of die nanowires is in a first pattern, wherein the formation of the plurality of cap nanowires is in a second pattern, and wherein the first pattern and the second pattern are complementary patterns.

[0013] In some embodiments, in addition to covering the die, the first side of the cover also covers one or more circuits.

[0014] In some embodiments, the formation of the plurality of cap nanowires is only on a first portion of the cap associated with the die.

[0015] According to some embodiments of the present disclosure, an example method is provided. The method may be a method of manufacturing a semiconductor package, comprising: growing a formation of a plurality of die nanowires on a first side of a die; growing a formation of a plurality of cover nanowires on a first side of a cover; attaching the die to a substrate; attaching the cover to the substrate, including coupling the formation of the plurality of die nanowires to the formation of the plurality of cover nanowires.

[0016] In some embodiments, the cover includes a cover top portion and a plurality of cover side portions, and the cover top portion is coupled to the cover side portions by glue.

[0017] In some embodiments, at least one formation of die nanowires is coupled to at least one formation of cap nanowires, and the coupling is aligned with a shared common axis.

[0018] In some embodiments, the formation of at least one die nanowire is offset coupled to the formation of at least one cap nanowire, wherein the formation of the at least one die nanowire has a different axis than the formation of the at least one cap nanowire.

[0019] In some embodiments, the formation of the plurality of cap nanowires covers a first portion of the first side of the cap that is not the entirety of the first side of the cap.

[0020] In some embodiments, the formation of the plurality of die nanowires covers a first portion of the first side of the die that is not the entirety of the first side of the die.

[0021] In some embodiments, the first portion of the first side of the die covered by the formation of the plurality of die nanowires includes coverage of at least one die hotspot.

[0022] In some embodiments, the formation of the plurality of die nanowires is in a first pattern, wherein the formation of the plurality of cap nanowires is in a second pattern, and wherein the first pattern and the second pattern are complementary patterns.

[0023] In some embodiments, the first side of the cover covers one or more circuits in addition to the die.

[0024] In some embodiments, the formation of the plurality of cap nanowires is located only on a first portion of the cap associated with the die.

[0025] The above overview is provided only for the purpose of summarizing some example embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it will be understood that the above embodiments are merely examples and should not be construed as limiting the scope or spirit of the present disclosure in any way. It will also be understood that in addition to those embodiments summarized here, the scope of the present disclosure also includes many potential embodiments, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Having thus generally described certain example embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0027] Figure 1A illustrates a cross-sectional view of an example block diagram of a semiconductor package with a detached lid according to one or more embodiments of the present disclosure;

[0028] Figure 1B illustrates a cross-sectional view of an example block diagram of a semiconductor package with an attached lid according to one or more embodiments of the present disclosure;

[0029] Figure 2A-2C A cross-sectional diagram illustrating an example block diagram of a cap nanowire and a die nanowire according to one or more embodiments of the present disclosure;

[0030] Figure 3A-3Dillustrates a diagram of an example block diagram of a die and a lid according to one or more embodiments of the present disclosure;

[0031] Figure 4A , 4B illustrates a cross-sectional view of an example block diagram of a cover having a separated top and sides according to one or more embodiments of the present disclosure;

[0032] Figure 5 illustrates a flow chart of operations for manufacturing an exemplary semiconductor package according to one or more embodiments of the present disclosure;

[0033] Figure 6 A flowchart illustrating operations for fabricating an exemplary die in accordance with one or more embodiments of the present disclosure; and

[0034] Figure 7 A flow chart illustrating operations for manufacturing an exemplary cover in accordance with one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0035] Some embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. In fact, the various embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0036] As used herein, the term "comprising" means including but not limited to, and should be interpreted in the manner commonly used in the patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and consisting essentially of.

[0037] The phrases "in various embodiments," "in one embodiment," "according to one embodiment," "in some embodiments," etc. generally indicate that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, these phrases do not necessarily refer to the same embodiment).

[0038] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0039] If the specification states that a component or feature "may", "could", "might", "should", "would", "preferably", "likely", "usually", "optionally", "for example", "often", or "might" (or other such language) be included or have a property, then that particular component or feature is not required to be included or have that property. Such components or features may be optionally included in some embodiments, or may also be excluded.

[0040] The term "circuit" as used herein with respect to components of a system or device should be understood to include specific hardware configured to perform the functions associated with the specific circuits described herein. The term "circuit" should be broadly understood to include hardware, and in some embodiments, software for configuring the hardware. For example, in some embodiments, a "circuit" may include processing circuits, communication circuits, input / output circuits, and the like. In some embodiments, other elements may provide or supplement the functionality of a particular circuit.

[0041] Summary

[0042] The present disclosure relates to systems, devices and methods for semiconductor packaging that use nanowires for improved thermal management. Heat generated by a die during thermal cycling may cause degradation or failure of a semiconductor package or components and / or circuits in the semiconductor package. Dissipating heat from the semiconductor package improves the performance and life of the semiconductor package.

[0043] A semiconductor package may include a die coupled to a substrate and a cover coupled to the substrate, the cover covering the die and other components and / or circuits of the semiconductor package. Nanowires may be formed on the die and on the cover, respectively, so that when the die and the cover are each coupled to the substrate, the die nanowires are coupled to the cover nanowires. The die nanowires and the cover nanowires may be grown in a plurality of formations, which may present a pattern. The corresponding formations of the die nanowires and the cover nanowires may be aligned and coupled. When coupled, the die nanowires form mechanical and electrical contact with the cover nanowires, which allows them to couple and allows for improved heat dissipation. An example of a semiconductor package is a ball grid array, which may then be mounted to or used in an electronic device or another system.

[0044] The nanowires can be arranged in a pattern that includes a first pattern on the die and a second (complementary) pattern on the lid. An example pattern can be a ring or a series of rings. Alternatively, the pattern can be based on a characteristic of the die, such as the location of one or more hot spots. The location of the hot spot can have a nanowire associated with the hot spot that is configured to conduct heat away from the hot spot. The pattern can also have one or more portions of the pattern that do not include nanowires (e.g., spaces between formations of nanowires).

[0045] Nanowires improve reliability as well as thermal performance. Given that semiconductor packages utilize TIMs, nanowires as described herein can result in improved thermal dissipation of heat that is an order of magnitude or more greater than using TIMs. Even if misaligned, the formation of nanowires provides increased thermal dissipation compared to semiconductor packages using TIMs.

[0046] Example Systems and Devices

[0047] Embodiments of the present disclosure herein include systems and devices for nanowires for semiconductor packaging as described herein, which can be implemented in various embodiments. Exemplary embodiments include a semiconductor package having a lid and a die, wherein the lid nanowires are grown on the lid and the die nanowires are grown on the die. When the lid is attached to a substrate to which the die is attached, the lid nanowires are coupled to the die nanowires. The coupled lid nanowires and die nanowires allow for improved heat dissipation of the semiconductor package, among other things.

[0048] Figure 1A A cross-sectional view of an example block diagram of a semiconductor package with a separated lid according to one or more embodiments of the present disclosure is illustrated. The semiconductor package 100 may include a die 110, a lid 120, and a substrate 130. The lid 120 is illustrated as being separated from the substrate 130. The lid 120 separated from the substrate 130 illustrates the lid nanowires 122A-D separated from the die nanowires 112A-D.

[0049] The die 110 has a first side 114A facing the lid 120 and a second side 114B facing the substrate 130. The first side 114A of the die 110 has a formation 112A-D of a plurality of nanowires. The second side 114B of the die 110 has a plurality of solder balls 116, copper pillars, etc., that couple the die 110 to the substrate 130. For example, the solder balls can be coupled to one or more signal pads 136A-C of the substrate. The nanowires on the die 110 are die nanowires. It will be understood that some of the figures illustrate solder balls 116, and alternative embodiments may use copper pillars, etc.

[0050] The lid 120 may include a top portion and a plurality of side portions. The top portion may have a first face 124A facing the die 110 and the substrate 120. The top portion 124A of the lid 120 may have a formation 122A-122D of a plurality of nanowires. The nanowires on the lid 120 are lid nanowires. The lid may be a plated metal core. For example, the lid 120 may have a copper core board with another metal to prevent the copper from being oxidized.

[0051] The formation of nanowires (e.g., 112A-112D, 122A-122D) may include several nanowires grown together. Although the drawings may illustrate the formation of nanowires 112 as including a few nanowires, it should be understood that the drawings are not to scale and the number of nanowires in the formation of nanowires 112 may be based on the area of ​​the formation of nanowires 112 on the die 110. The nanowires may be made of a metal such as copper.

[0052] For example, the substrate 130 may be a laminate substrate, and the substrate 130 may include one or more signal pads 136 and / or other circuits. The cover 120 may be attached to the substrate 130 to cover one or more other circuits (e.g., ICs, electrical components, etc.) in addition to the signal pads 136. The use of nanowires to dissipate the heat generated by the die 110 may also provide an improvement in their lifespan by reducing the temperature to which these other circuits are exposed. A solder mask may cover the substrate 130 and be removed in various operations, such as at the location where the solder balls 116 are connected and when the solder balls 116 are connected. In various embodiments, the substrate 130 may be a wafer or panel from which the semiconductor package 100 is to be separated. For example, a plurality of semiconductor packages 100 may be manufactured together before being separated from a common wafer or panel.

[0053] Figure 1B A cross-sectional view of an example block diagram of a semiconductor package with an attached lid according to one or more embodiments of the present disclosure is illustrated. When the lid 120 is attached to the substrate 130, the die nanowires are coupled to the lid nanowires. As shown, the first formation 112A of the die nanowires is coupled to the first formation 122A of the lid nanowires; the second formation 112B of the die nanowires is coupled to the second formation 122B of the lid nanowires; the third formation 112C of the die nanowires is coupled to the third formation 122C of the lid nanowires; and the fourth formation 112D of the die nanowires is coupled to the fourth formation 122D of the lid nanowires. In various embodiments, when the lid 120 is attached to the substrate 130, the distance from the first side 124A of the lid to the first side 114A of the die can be 50 microns. In various embodiments, the lid 120 can be attached to the substrate 130 with glue.

[0054] Figure 2A-2CA cross-sectional view of an example block diagram of a cover nanowire and a die nanowire according to one or more embodiments of the present disclosure is illustrated. Specifically, a formation 112 of the die nanowire and a formation 122 of the cover nanowire are illustrated. The formation 112 of the die nanowire may have a first height 122H on a first axis 212, and the formation 122 of the cover nanowire may also have the same or different height 222H on a second axis 222. The axis may be referred to as a central axis. The width of the formation of nanowires (e.g., 112, 212) may be 5 to 10 microns wide, but even if the coupling misalignment of the formation of nanowires (where the axis of the cover nanowire is not aligned with the axis of the die nanowire) allows improved heat dissipation. The distance or gap between the die and the cover of the semiconductor package may be less than the first height 122H and the second height 222H, so that when the cover 120 is attached to the substrate 130, the cover nanowire 122 will be in contact with the die nanowire 112 to form a mechanical connection and an electrical connection.

[0055] Figure 2A A cross-sectional view of an example block diagram of a formation of die nanowires 112 separated from a formation of cap nanowires 122 according to one or more embodiments of the present disclosure is shown. As shown, when the formation of die nanowires 112 is separated from the formation of cap nanowires 122, axes 212 and 222 are aligned. When the formation of die nanowires 112 and the formation of cap nanowires 122 are coupled, the nanowires will couple to create a mechanical connection as well as an electrical connection.

[0056] Figure 2B A cross-sectional diagram of an example block diagram of a formation of die nanowires 112 coupled to a formation of cap nanowires 122 with axes 212 aligned with 222 according to one or more embodiments of the present disclosure is illustrated. When axes 212 and 222 are aligned, the coupling may allow for maximum heat transfer through the coupling.

[0057] Figure 2C A cross-sectional view of an example block diagram of separation of the formation 112 of die nanowires from the formation 122 of cap nanowires in accordance with one or more embodiments of the present disclosure is illustrated with misalignment of the axes 212 and 222. When the axes 212 and 222 are misaligned, but still coupled as shown, heat transfer through misaligned coupling is still improved.

[0058] Figure 3A-3DA view of an example block diagram of a die and a lid according to one or more embodiments of the present disclosure is illustrated. The die 110 and the lid 120 can have a pattern of nanowires. The pattern of nanowires on the lid 120 can be on a first portion of the lid 120 associated with the die 110. The size of the first portion of the lid 120 can be determined based on the size of the first side 114A of the die 110. The pattern of nanowires can be formed by the formation of die nanowires 112 and / or the formation of lid nanowires 122. Figure 3A-3D Each of the embodiments of the present invention illustrates a die (e.g., 310A-310D) and a cover (e.g., 320A-320D). The cover (e.g., 320A-320D) is larger than the die and can include a cover portion (e.g., 326A-326D) with dimensions corresponding to the dimensions of the die (e.g., 310A-310D). The die and cover portion can be matched in size so that the die nanowires connect to the cover nanowires, including having a symmetrical pattern on each. In various embodiments, the pattern can have nanowires at locations on the die that have one or more hot spots.

[0059] Figure 3A The invention comprises a die 310A having nanowires covering the entire die 310A, and Figure 3A Also included is a cover 320A having a first portion 326A, with nanowires covering the entirety of the first portion 326A.

[0060] Figure 3B including a die 310B having nanowires in a pattern of four squares, and Figure 3B Also included is a cover 320B having a first portion 326B having nanowires in a matching pattern of four squares.

[0061] Figure 3C including a tube core 320C, the tube core 320C having nanowires in a donut-shaped pattern, and Figure 3C Also included is a cover 320C having a first portion 326C having a matching pattern of nanowires in a donut shape.

[0062] Figure 3D The invention comprises a tube core 310D, the tube core 310D has nanowires in rectangular and square patterns, and Figure 3D Also included is a cover 320D having a first portion 326D having nanowires in a matching pattern of rectangles and squares. The patterns on the die and covers 310D and 320D match so that when the cover 320D is flipped over to cover the die 310D, the patterns will align.

[0063] The patterns on the die and the lid may include areas and / or portions that are cleared to not have nanowires. Such areas and / or portions may be cleared because the die may include circuits and / or areas or portions that do not generate heat to be dissipated or do not generate as much heat to be dissipated.

[0064] Figure 4A , 4B A cross-sectional view of an example block diagram of a lid with a separated top and side according to one or more embodiments of the present disclosure is illustrated. In various embodiments, the lid 400 may include a top portion 442 and a plurality of side portions 444A, 444B. It will be understood that the lid 420 may have a side for each of its outer sides, such as having four side portions 444 for a lid 420 having a square shape. Thus, after the nanowires have been formed on the top portion of the lid, the lid may be assembled from the corresponding portions of the lid. In various embodiments, the nanowires may be formed using a deposition liquid that may be removed by centrifugal force by rotating the top portion of the lid. Thus, in various embodiments, assembling the lid using portions may allow for an easier way to form the nanowires. It will be understood that the lid 420 may have a shape different from a square, such as a rectangle or a shape having more or less than four sides.

[0065] Figure 4A The cap side portions 444A, 444B are shown separated from the top portion 442. The top portion may have formations 122A-D of cap nanowires formed on the cap top portion 442 prior to attaching the cap side portions 444A, 444B.

[0066] Figure 4B A cover 420 is illustrated having a cover top portion 442 attached to side portions 444A, 444B. The attachment may use an adhesive, such as glue.

[0067] It should be readily appreciated that the embodiments of the systems and apparatus described herein may be configured in various additional and alternative ways besides those explicitly described herein.

[0068] Example Method

[0069] Figure 5 A flow chart illustrating operations for fabricating an exemplary semiconductor package in accordance with one or more embodiments of the present disclosure is illustrated.

[0070] At operation 502, a die nanowire is created on the die. Figure 6 The various operations described create die nanowires 112 on die 110 .

[0071] At operation 504, a cap nanowire is created on the cap. Figure 7 The various operations described create die nanowires 112 on die 110 .

[0072] At operation 506, the die is attached to the substrate. Attaching the die 110 to the substrate 130 may include placing the die 110 in alignment with the substrate 130 such that the solder balls 116 on the second side 114B of the die 110 are aligned with the signal pads 136 on the first side 134A of the substrate 134. If the substrate 130 includes a solder mask over the signal pads 134, such as to prevent oxidation of the metal of the signal pads 134, the solder mask may be removed to allow the solder balls 116 to couple to the signal pads 134. Once placed, the die 110 and the substrate 130 may be coupled by melting the solder. An underfill material may be applied to fill the space around the solder and between the die 110 and the solder 130. For example, the underfill may be an epoxy that fills the space between the die 110 and the substrate 130 by capillary action.

[0073] In various embodiments, placing the die 110 may include flipping the die 110 so that the second side 114B of the die 110 faces the first side of the substrate 130. This may include picking up the die 110 with a flip chip fixture. In order to use a flip chip fixture, the die 110 may need to be rigid enough so as not to crack due to the thickness of the die 110. In various embodiments, the formation 112 of die nanowires may provide increased rigidity. This may include a pattern of die nanowires 112 covering the entirety or a majority of the die 110.

[0074] At operation 508, the lid is attached to the substrate, thereby coupling the die nanowires and the lid nanowires. Attaching the lid to the substrate includes aligning the formation of the lid nanowires with its corresponding die nanowire formation. This may include aligning complementary and / or symmetrical nanowire patterns on the die 110 and the lid 120. The lid 120 may be placed onto the substrate 130, and the formation of the lid nanowires is brought to the formation of the die nanowires. The lid 120 may be attached to the substrate 130 by glue. In various embodiments, the attachment by glue may include depositing glue around the substrate 130 at locations where the side portions of the lid 120 contact the substrate 130. The semiconductor package may then be heated to, for example, 150-200 degrees Celsius to cure the glue. In addition, pressure may be applied to the semiconductor package or the portion of the semiconductor package having the nanowires to anneal the die nanowires with the lid nanowires. Annealing and curing of the glue may occur simultaneously, or may occur at separate times, such as sequentially.

[0075] Figure 6A flow chart of operations for manufacturing an exemplary die according to one or more embodiments of the present disclosure is illustrated. Creating die nanowires 112 on die 110 may include preparing die 110 from multiple dies on a wafer, panel, or the like. For example, the wafer may be bumped to add solder bumps and may be ground to a desired thickness. The wafer may need to be attached to a handler after grinding to allow for handling of the wafer. For example, the solder bumps are on the second side 114B of the die, and the die nanowires 112 will grow on the first side 114A of the die 110, so the wafer is processed by at least flipping the wafer to expose the first side 114A of the die 110 for growing the formation of the die nanowires 112.

[0076] At operation 602, the second side of the wafer is bumped. Multiple dies may be prepared together on a wafer including die 110. Bumping the bottom side of the wafer including second side 114B with solder bumps creates solder balls 116A.

[0077] At operation 604, a first side of the wafer is ground. The wafer may have a standard size that may require a reduced thickness for semiconductor packaging. The wafer including die 110 may be ground to a first thickness. In various embodiments, the grinding may include flipping the wafer and performing a top surface grinding to remove a portion of the wafer.

[0078] At operation 606, a handler is attached to the wafer. The wafer including the die 110 may require increased rigidity for handling after being ground to a reduced thickness. A front handler can be applied to the face of the wafer where the bumps are formed. The front handler can be a first material (e.g., a heat-deactivated glue or a tape with glue) that can add rigidity while absorbing the topology of the solder bumps. The handler can be a temporary layer that can be removed later. Additionally or alternatively, a sawing tape can be added to the wafer for use in a subsequent singulation step that includes sawing individual dies from the wafer. If a handler of the first material is added, the handler can be disengaged to add the sawing tape to one or more portions of the wafer.

[0079] At operation 608, a nanowire seed layer is applied to the first side of the die. The nanowire seed layer is applied to the top portion of the wafer (including the first side 114A of the die 110), and may be applied over the entirety of the die 110, or may be applied in one or more patterns. This may create a pattern, such as growing nanowires on hot spots or heat dissipation target areas. In various embodiments, the die 110 is part of a wafer, and the nanowire seed layer may be applied simultaneously.

[0080] At operation 610, die nanowires are grown from the nanowire seed layer. Die nanowires 112 are grown on the first side 114A of the die 110 from the nanowire seed layer. The growth of the nanowires may include one or more electroplating operations. The growth of the nanowires may also include applying a photoresist layer. The photoresist layer may have one or more openings, or one or more openings may be created therein after applying the photoresist layer. The nanowires may grow in the openings of the photoresist layer. These openings may be formed into one or more patterns, which may allow the nanowires to grow in one or more patterns. In various embodiments, the die 110 is part of a wafer, and multiple dies having nanowires may be grown simultaneously.

[0081] In embodiments where multiple dies are part of a wafer, the dies 110 may be separated from the wafer by one or more singulation operations. This may include sawing the wafer using a saw along a sawing tape applied to the wafer.

[0082] Figure 7 A flow chart of operations for fabricating an exemplary lid according to one or more embodiments of the present disclosure is illustrated. Creating lid nanowires 122 on lid 120 may include applying a nanowire seed layer to lid 120 and growing lid nanowires from the seed layer. In various embodiments where lid 420 includes a top portion 442 that is separate from side portions 444, one or more lid top portions 442 may be prepared by growing lid nanowires 122 on top portion 442 before the corresponding side portions 444 are attached to (one or more) top portions 442. Then, after lid nanowires 122 have been grown on top portion 442, the corresponding lid side portions 444 are attached to lid top portion 442.

[0083] At operation 702, a nanowire seed layer is applied to the lid. The lid 120 may include applying the nanowire seed layer, which may include covering all areas of the lid in a pattern, or removing one or more portions of the seed layer after applying the seed layer. In various embodiments, the pattern may have the seed layer applied in one or more shapes. In various embodiments, the pattern may have the seed layer applied only to hot spots.

[0084] At operation 704, cap nanowires are grown from the nanowire seed layer. The nanowires are generated on the nanowire seed layer, which may include electroplating. The growth of the nanowires may also include applying a photoresist layer. The photoresist layer may have one or more openings, or one or more openings may be created therein after applying the photoresist layer. The nanowires may be grown in the openings of the photoresist. These openings may be formed into one or more patterns, which may allow the nanowires to grow in one or more patterns.

[0085] At operation 706, the side portion of the cover is attached to the top portion of the cover. In various embodiments where the cover has multiple portions, subsequent steps may include attaching one or more side portions of the cover to the portion of the cover having the nanowires. For example, the attachment may be accomplished using one or more glues.

[0086] Summarize

[0087] The operations and / or functions of the present disclosure have been described herein, such as in flow charts. Although the operations and / or functions are illustrated in a particular order in the accompanying drawings, this should not be understood as requiring that such operations and / or functions be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed to achieve the desired results. In some cases, it may also be advantageous to perform the operations and / or functions in an alternative order. In some cases, the actions detailed in the claims can be performed in a different order and still achieve the desired results. Therefore, although specific embodiments of the subject matter have been described, other embodiments are also within the scope of the subsequent claims.

[0088] Although this specification contains many specific embodiments and implementation details, these should not be interpreted as limitations on the scope of any disclosed or potentially claimed content, but rather as descriptions of features specific to a particular disclosed specific embodiment. Certain features described herein in the context of a separate embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although in the above description features may be described as acting in the form of certain combinations, even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a variant of a sub-combination or a sub-combination.

[0089] Although this detailed description sets forth certain embodiments of the present disclosure, the appended claims cover other embodiments of the invention that differ from the described embodiments according to various modifications and improvements.

[0090] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim, it is not intended that the claim be interpreted pursuant to 35 USC §112, paragraph 6.

Claims

1. A semiconductor package, comprising: substrate; a die comprising a first side of the die and a second side of the die, wherein the first side of the die comprises a formation of a plurality of die nanowires, wherein the second side of the die is coupled to a substrate; a lid comprising a first side of the lid facing the die, wherein the first side of the lid comprises a formation of a plurality of lid nanowires; and Wherein at least one formation of die nanowires is coupled to at least one formation of cap nanowires. 2 . The semiconductor package according to claim 1 , wherein the lid comprises a lid top portion and a plurality of lid side portions, and the lid top portion is coupled to the lid side portions by glue.

3. The semiconductor package of claim 1, wherein the at least one of the formations of the plurality of die nanowires is coupled to at least one of the formations of the plurality of cap nanowires, and wherein the coupling is aligned with a shared common axis.

4. The semiconductor package of claim 1 , wherein at least one of the formations of the plurality of die nanowires is coupled to at least one of the formations of the plurality of cap nanowires, and wherein the coupling is misaligned, wherein the at least one of the formations of the plurality of die nanowires has a different axis than the at least one of the formations of the plurality of cap nanowires. 5 . The semiconductor package of claim 1 , wherein the formation of the plurality of cap nanowires covers a first portion of the first side of the cap, the first portion not being the entire first side of the cap.

6. The semiconductor package of claim 1, wherein the formation of the plurality of die nanowires covers a first portion of the first side of the die that is not the entirety of the first side of the die.

7. The semiconductor package of claim 6, wherein the first portion of the first face of the die covered by the formation of the plurality of die nanowires comprises covering of at least one die hotspot.

8. The semiconductor package of claim 1, wherein the formation of the plurality of die nanowires is in a first pattern, wherein the formation of the plurality of cap nanowires is in a second pattern, and wherein the first pattern and the second pattern are complementary patterns.

9. The semiconductor package of claim 1, wherein the first side of the cover covers one or more circuits in addition to the die.

10. The semiconductor package of claim 9, wherein the formation of the plurality of cap nanowires is only on a first portion of the cap associated with the die.

11. A method for manufacturing a semiconductor package, comprising: growing a formation of a plurality of die nanowires on a first side of the die; growing a formation of a plurality of cap nanowires on a first side of the cap; attaching the die to the substrate; Attaching the cap to the substrate includes coupling the formation of the plurality of die nanowires to the formation of the plurality of cap nanowires. 12 . The method of manufacturing a semiconductor package according to claim 11 , wherein the cover comprises a cover top portion and a plurality of cover side portions, and the cover top portion is coupled to the cover side portions by glue.

13. The method of manufacturing a semiconductor package of claim 11, wherein at least one formation of die nanowires is coupled to at least one formation of cap nanowires, and wherein the coupling is aligned with a shared common axis.

14. The method of manufacturing a semiconductor package according to claim 11, wherein the formation of at least one die nanowire coupled to the formation of at least one cap nanowire is offset, wherein the formation of the at least one die nanowire has a different axis than the formation of the at least one cap nanowire. 15 . The method of manufacturing a semiconductor package according to claim 11 , wherein the formation of the plurality of cap nanowires covers a first portion of the first surface of the cap, the first portion not being the entire first surface of the cap.

16. The method of manufacturing a semiconductor package according to claim 11, wherein the formation of the plurality of die nanowires covers a first portion of the first side of the die, the first portion not being the entire first side of the die.

17. The method of manufacturing a semiconductor package of claim 16, wherein the first portion of the first face of the die covered by the formation of the plurality of die nanowires includes covering of at least one die hotspot.

18. The method of manufacturing a semiconductor package according to claim 11, wherein the formation of the plurality of die nanowires is in a first pattern, wherein the formation of the plurality of cap nanowires is in a second pattern, and wherein the first pattern and the second pattern are complementary patterns.

19. The method of manufacturing a semiconductor package according to claim 11, wherein the first side of the cover covers one or more circuits in addition to the die.

20. The method of manufacturing a semiconductor package of claim 19, wherein the formation of the plurality of cap nanowires is located only on a first portion of the cap associated with the die.

Images