On-die flexure control apparatus and method

Abstract

The subject of the invention is an on-die flexure control apparatus and method. An electronic device and an associated method are disclosed. An electronic device is shown that includes a semiconductor die and a patterned layer connected to a backside of the die. The electronic device is shown to include a pattern of elements across the patterned layer, the pattern of elements differing across the backside of the die. The electronic device is further shown to include a compliant filler within the element in the patterned layer.

Description

Technical Field

[0001] Embodiments described herein generally relate to semiconductor devices. More specifically, the present disclosure relates to techniques for mitigating die warpage. Background Art

[0002] Semiconductor die cooling is an important issue in electronic devices. Thermally conductive and / or heat dissipating materials are used to improve die cooling. Some thermally conductive materials have different coefficients of thermal expansion (CTE). When laminated to a semiconductor die, the difference in CTE can cause die warping, which can lead to many technical problems.

[0003] It would be desirable to provide apparatus and methods that reduce or eliminate die warpage while also maintaining effective die cooling. Apparatus and methods that address these and other technical challenges are described. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the figures, the same numerals may describe similar components in different views, which are not necessarily drawn to scale. The same numerals with different letter suffixes may represent different instances of similar components. The figures generally illustrate the various embodiments discussed in this document by way of example and not by way of limitation.

[0005] Figure 1 An isometric view of a semiconductor device according to some example embodiments is shown.

[0006] Figure 2 A side view of a semiconductor device according to some example embodiments is illustrated.

[0007] Figure 3 A side view of a semiconductor device according to some example embodiments is illustrated.

[0008] Figure 4 Semiconductor devices according to some example embodiments are illustrated.

[0009] Figure 5 Another semiconductor device according to some example embodiments is illustrated.

[0010] Fig. 6A An unpatterned layer of a semiconductor device according to some example embodiments is illustrated.

[0011] Figure 6B A patterned layer of a semiconductor device according to some example embodiments is illustrated.

[0012] Figure 6C Another patterned layer of a semiconductor device according to some example embodiments is illustrated.

[0013] Figure 7 A flowchart of a method of manufacturing a semiconductor device according to some example embodiments is shown.

[0014] Figure 8 Systems that may combine electronic devices with patterned layers and methods according to some example embodiments are shown. DETAILED DESCRIPTION

[0015] The following description and drawings fully illustrate specific embodiments to enable those skilled in the art to implement them. Other embodiments may incorporate structural, logical, electrical, process and other changes. Parts and features of some embodiments may be included in those of other embodiments or replace those of other embodiments. The embodiments set forth in the claims include all available equivalents of those claims.

[0016] Figure 1 A top view of a semiconductor device 100 according to some example embodiments is shown. The semiconductor device 100 includes a semiconductor die 102 such as a processor die, a memory die, a graphics die, a controller die, etc. A patterned layer 108 coupled to the die 102 is shown. In one example, the patterned layer 108 forms a direct interface with the die 102. The direct interface provides thermal conduction with a minimum distance for heat propagation. In one example, the patterned layer 108 is connected to the die 102 and includes one or more intervening layers between the die 102 and the patterned layer 108.

[0017] In one example, the patterned layer 108 is formed of a single piece of thermally conductive material such as a metal. In one example, the patterned layer 108 is formed of copper. Other materials for the patterned layer 108 include, but are not limited to, aluminum, silver, gold, nickel, diamond, aluminum nitride, silicon carbide, or a combination of two or more of these materials, such as a copper and diamond composite.

[0018] In one example, a physical deposition technique such as evaporation, sputtering, etc. is used to form the patterned layer 108 on the die 102. Other techniques for forming the patterned layer 108 are possible, including but not limited to chemical deposition, or laminating a separate sheet onto the die 102. The different formation techniques will be detectable in the final product, for example, sputtering and evaporation will form a unique grain pattern in the bulk material as a result of the technique used. Other formation methods will also be detectable in the final product, for example, by cross-sectioning and microscopic inspection.

[0019] exist Figure 1In one example, the patterned layer 108 includes a pattern of elements 104 that form grooves in the patterned layer 108. In one example, the pattern of elements 104 includes a constant spacing in the X direction on the patterned layer 108. In one example, the pattern of elements 104 includes a constant spacing in the Y direction on the patterned layer 108. In one example, the pattern of elements 104 includes a constant spacing in both the X direction and the Y direction on the patterned layer 108. The pattern of elements 104 can be different across the back side of the die 110. Variations in the pattern of elements 104 can be used to adjust stresses in the patterned layer 108 and improve or eliminate warping due to differences in thermal expansion coefficients in the materials.

[0020] In one example, the patterned layer 108 may be comprised of a thickness between 50 μm and 500 μm. Figure 2 As shown in more detail in , the pattern of elements 104 may extend through the entire thickness of patterned layer 108. Figure 1 , the pattern of elements 104 can consist of straight lines extending across the length and width of the back side of the tube core 110. The pattern of elements 104 can consist of other forms or shapes, such as angled lines, arc patterns or arc segments included in the pattern, sinusoidal patterns, "wavy" patterns, triangular patterns, and others. The pattern of elements 104 can be formed by laser ablation. The pattern of elements 104 can be formed using a tube core cutting (die-saw). Another method of forming the pattern of elements 104 includes, but is not limited to, etching, such as photolithography using a mask.

[0021] Figure 2 illustrates a side view of patterned layer 208, similar to that from Figure 1 The patterned layer 108. Figure 2 , the patterned layer 208 includes a plurality of grooves 204. In some embodiments, the patterned layer 208 includes a pattern 206 of groove-forming elements 204. Although the grooves 204 are shown as having square bottoms, other forms of grooves are also within the scope of the invention, such as triangular or circular bottoms.

[0022] As described above, in one example, the pattern 206 differs across the patterned layer 208 . Figure 2Three different widths 205 are shown. Depth 207 may also vary between elements 204 of pattern 206. In one example, depth 209 extends across the entire thickness of patterned layer 208. In other embodiments, element 204 may extend across only a portion of patterned layer 208. Variations and combinations of different widths 205, depths 207, spacing intervals 211, etc. may be used to tailor thermal expansion effects within different XY locations in patterned layer 208. These variations may mitigate or eliminate warping due to differences in thermal expansion coefficients in materials, such as between silicon and copper.

[0023] Element 104 may include the following Figure 6C In one example, including a compliant filler will allow a degree of compression, thereby allowing portions of patterned layer 208 adjacent to element 204 to expand and contract without causing warping. Including a compliant filler further provides the advantage of preventing unwanted particles from invading element 204 that could jam element 204 and reduce the available expansion and contraction motion. An example of such a possibility includes the subsequent use of a thermal interface grease or other material that may include suspended particles. Including a compliant filler in element 204 of pattern 206 facilitates the use of a thermal interface grease while also preventing suspended particles from the thermal interface grease from invading element 204 in pattern 206.

[0024] In one example, the compliant fill within elements 204 of pattern 206 further includes thermally conductive particles in a distribution that is effective in thermal conduction, but not so dense as to restrict thermal expansion and contraction of adjacent elements 204. In such an example, the compliant fill may assist in thermal conduction, but will be compliant enough not to add to die warpage.

[0025] Figure 3 A side view of a semiconductor device 300 is shown. The device 300 includes a die 310 and a patterned layer 308. Figure 3 The patterned layer 308 includes a pattern of element 304 similar to the pattern 206 of element 204. Figure 3 In the example of FIG. 3 , an intermediate layer 312 is included between the die 310 and the patterned layer 308 .

[0026] In one embodiment, the die 310 is connected to the patterned layer 308 via an intermediate layer 312. Although one intermediate layer 312 is shown, more than one intermediate layer may be included as long as heat can be sufficiently conducted from the die 310 to the patterned layer 308. In some embodiments, the intermediate layer 312 may optionally be used between the die 310 and the patterned layer 308, for example as a diffusion barrier or as a buffer layer. The intermediate layer 312 may be used in some embodiments to protect the die 310 during the formation of the element 304 (e.g., when die cutting is used to form the element 304). Other methods in which the intermediate layer 312 may provide protection include laser ablation, etching, etc.

[0027] The intermediate layer 312 may include titanium, nickel, vanadium, gold, or one or more combinations of these or other materials. Other thermally conductive materials are also within the scope of the invention. In one embodiment, the thickness of the intermediate layer 312 is between 10 nm and 500 nm.

[0028] Figure 4 One example of a semiconductor device 400 according to some example embodiments is illustrated. Figure 4 The device 400 includes a first die 410 coupled to a substrate 402. A first underfill 403 may be included around a first solder connection 404, although the invention is not so limited. One or more secondary dies 420 are shown coupled to a top surface of the first die 410. A second underfill 423 may be included around a second solder connection 424, although the invention is not so limited. Figure 4 In the example of , the encapsulant 422 is included, and the encapsulant 422 at least partially covers the secondary tube core 420. Figure 4 In the example of FIG. 4 , the secondary die 420 and the encapsulant 422 form a horizontal top surface 432 that facilitates the formation of the patterned layer 430. In one example, the patterned layer 430 includes a pattern of elements 434 as described in other examples above. The pattern including the elements 434 mitigates or eliminates warping due to differences in the coefficients of thermal expansion in the materials while still providing thermal dissipation of heat from the dies 410, 420 through the patterned layer 430.

[0029] In one example, patterned layer 430 may include a thermally conductive material. Patterned layer 430 may further include a pattern of elements 434 forming grooves. The pattern of elements 434 may be different in size, shape, length, and width. In one embodiment, patterned layer 430 may be composed of a pattern of elements 434 forming grooves with a constant pitch in the XY direction. In another example, patterned layer 430 may be composed of a thickness between 50 μm and 500 μm. The pattern of elements 434 may extend across the entire thickness of patterned layer 430.

[0030] Figure 5 One example of a semiconductor device 500 according to some example embodiments is illustrated. Figure 5 The device 500 includes a first die 510 coupled to a substrate 502. A first underfill 503 may be included around a first solder connection 504, although the invention is not so limited. One or more secondary dies 520 are shown coupled to a top surface of the first die 510. Figure 5 In an example, the secondary die 520 is coupled to the top surface of the first die 510 using a bonding technique such as a solid state reaction between materials to form a bond. In one example, the bond 524 includes an intermetallic compound, although the invention is not so limited. Other example configurations of the bond between the secondary die 520 and the first die 510 include a solder connection.

[0031] In an embodiment, the connection of the first die 510 to the (one or more) secondary die 520 can be made by using a copper pad. In an embodiment, such a connection (e.g., a copper pad) is surrounded by an inorganic dielectric. For example, such an inorganic dielectric can be a combination of silicon oxide or other similar materials.

[0032] exist Figure 5 In the example of , the encapsulant 522 is included, and the encapsulant 522 at least partially covers the secondary tube core 520. Figure 5 In the example shown, encapsulant 522 completely covers the top surface of secondary die 520 . Figure 5 The device 500 further includes a structural block 540. In one example, the structural block 540 includes silicon, although other materials are within the scope of the invention. The inclusion of the structural block 540 provides a level of mechanical strength to the device 500 to help resist any damage due to the fragility of the thin components. Figure 5 The example further includes a horizontal top surface that facilitates the formation of the patterned layer 530. In one example, the patterned layer 530 includes a pattern of elements 534 as described in other examples above. The pattern including elements 534 mitigates or eliminates warping due to differences in coefficients of thermal expansion in the materials while still providing thermal dissipation of heat from the dies 510, 520 through the seal 522 and the structural block 540 and ultimately through the patterned layer 530.

[0033] Fig. 6A A non-patterned heat conductive structure of a semiconductor device according to some example embodiments is described. Fig. 6A As shown in FIG. 6 , the embodiment includes a silicon structure 620 and a thermally conductive layer 606. Fig. 6AIn one embodiment, the thermally conductive layer 606 forms a direct interface 622 with the silicon structure 620, although the invention is not so limited. As noted in the above examples, an intermediate layer may be included between the silicon structure 620 and the thermally conductive layer 606 as long as there is still sufficient thermal conduction between the silicon structure 620 and the thermally conductive layer 606. In one example, the silicon structure 620 includes a die. In one example, the silicon structure 620 includes a structural block, such as from Figure 5 The structural block 540.

[0034] Figure 6B The formation of element 604 in the pattern of elements is shown. Fig. 6A Recesses are formed in the thermally conductive layer 606 to form the patterned layer 630. In some embodiments, as depicted, the elements 604 can extend across the entire thickness of the patterned layer 630. However, in some embodiments, the elements 604 can extend across only a portion of the thickness of the patterned layer 630. As noted in the examples above, variations across the surface of the thermally conductive layer 606 can be utilized to form a pattern of the elements 604 to form the patterned layer.

[0035] Figure 6C Explains from Figure 6B The patterned layer 630 is formed by a plurality of layers of a plurality of substrates. Figure 6C Examples include compliant fillers 640 within element 604. Compliant fillers 640 may include thermally conductive particles 642. Examples of thermally conductive particles 642 include, but are not limited to, zinc oxide nanoparticles, copper nanoparticles, nanodiamonds, graphene, or silver nanoparticles. Although nanoparticles indicate a favorable size scale, other sizes of particles 642 suitable for element 604 are also within the scope of the invention. Element 604 may include compliant fillers 640 to assist in heat conduction. In the example shown, compliant fillers 640 include a matrix material and may also include conductive particles 642 as described above. Examples of matrix materials include, but are not limited to, polymer materials. An example polymer material includes silicone, although the invention is not so limited. Solid but flexible compliant materials include advantages over grease or oil materials because they resist the aggregation of unwanted particles that may be caught within element 604 while still maintaining sufficient compliance to allow expansion and contraction of patterned layer 630 to resist warping.

[0036] Figure 7 An example flow chart of a method of manufacturing a semiconductor device is shown. In operation 702, a thermally conductive layer is coupled to a die. In operation 704, at least one patterned recess element is formed in the thermally conductive layer. In operation 706, the at least one patterned recess is filled with a compliant filler, and in operation 708, the die is connected to a semiconductor substrate.

[0037] In one example, an apparatus as described in the present disclosure has reduced warpage, especially during temperature fluctuations. One advantage of reduced warpage includes more reliable die testing. After manufacturing, dies are often tested to ensure that they are operating as expected. By detecting defective dies early, bad dies can be discarded before being incorporated into a higher level apparatus such as the system 800 described below. This can provide significant cost savings because if a bad die is found later in manufacturing, a more expensive system, such as the die itself, may need to be scrapped.

[0038] During one example of die testing, the die is probed and exposed to different temperature environments to stress the die and assess how robust the die is when subjected to temperature changes. Warping during die probing can cause good dies to fail simply because the probe failed to make contact with the die, not because the die itself is bad. By reducing warping at the die level, probing operation reliability is improved.

[0039] Figure 8 A system-level schematic diagram is illustrated, depicting an example of an electronic device (e.g., system) that may include a patterned layer and the methods described above. In one embodiment, system 800 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet computer, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular phone, a mobile computing device, a smart phone, an Internet appliance, or any other type of computing device. In some embodiments, system 800 includes a system-on-chip (SOC) system.

[0040] In one embodiment, the processor 810 has one or more processing cores 812 and 812N, where 812N represents the Nth processing core within the processor 810, where N is a positive integer. In one embodiment, the system 800 includes multiple processors including 810 and 805, wherein the processor 805 has logic similar to or the same as the logic of the processor 810. In some embodiments, the processing core 812 includes, but is not limited to, pre-fetch logic for fetching instructions, decoding logic for decoding instructions, execution logic for executing instructions, and the like. In some embodiments, the processor 810 has a cache memory 816 for caching instructions and / or data for the system 800. The cache memory 816 can be organized into a hierarchical structure including one or more levels of cache memory.

[0041] In some embodiments, the processor 810 includes a memory controller 814 that is operable to perform functions that enable the processor 810 to access and communicate with a memory 830 including a volatile memory 832 and / or a non-volatile memory 834. In some embodiments, the processor 810 is coupled to the memory 830 and the chipset 820. The processor 810 may also be coupled to a wireless antenna 878 to communicate with any device configured to transmit and / or receive wireless signals. In one embodiment, the interface of the wireless antenna 878 operates according to, but is not limited to, the IEEE 802.11 standard and its related series, Home Plug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0042] In some embodiments, the volatile memory 832 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. The non-volatile memory 834 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0043] Memory 830 stores instructions and information to be executed by processor 810. In one embodiment, memory 830 may also store temporary variables or other intermediate information while processor 810 is executing instructions. In the illustrated embodiment, chipset 820 is connected to processor 810 via point-to-point (PtP or PP) interfaces 817 and 822. Chipset 820 enables processor 810 to connect to other elements in system 800. In some embodiments of the example system, interfaces 817 and 822 are configured to communicate with processor 810 in accordance with a plurality of communication protocols such as TCP, HTTP, HTTPS, or other protocols. In some embodiments, the present invention may operate with a PtP communication protocol such as QuickPath Interconnect (QPI), etc. In other embodiments, a different interconnect may be used.

[0044] In some embodiments, the chipset 820 is operable to communicate with the processors 810, 805, the display device 840, and other devices including a bus bridge 872, a smart TV 876, an I / O device 874, a non-volatile memory 860, a storage medium (such as one or more mass storage devices) 862, a keyboard / mouse 864, a network interface 866, and various forms of consumer electronics 877 (such as PDAs, smart phones, tablet computers, etc.). In one embodiment, the chipset 820 is coupled to these devices through an interface 824. The chipset 820 can also be coupled to a wireless antenna 878 to communicate with any device configured to transmit and / or receive wireless signals. In one example, any combination of components in the chipset can be separated by a continuous flexible shield as described in the present disclosure.

[0045] The chipset 820 is connected to a display device 840 via an interface 826. The display 840 may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, the processor 810 and the chipset 820 are combined into a single SOC. In addition, the chipset 820 is connected to one or more buses 850 and 855 that interconnect various system elements such as I / O devices 874, non-volatile memory 860, storage media 862, keyboard / mouse 864, and network interface 866. The buses 850 and 855 may be interconnected together via a bus bridge 872.

[0046] In one embodiment, the mass storage device 862 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash drive, or any other form of computer data storage medium. In one embodiment, the network interface 866 is implemented by any type of well-known network interface standard, including but not limited to an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect (PCI) express interface, a wireless interface, and / or any other suitable type of interface. In one embodiment, the wireless interface operates according to, but is not limited to, the IEEE 802.11 standard and its related series, Home Plug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0047] Although Figure 8The modules shown in the figure are depicted as independent blocks within the system 800, but the functions performed by some of these blocks may be integrated within a single semiconductor circuit or the functions performed by some of these blocks may be implemented using two or more independent integrated circuits. For example, although the cache memory 816 is depicted as a separate block within the processor 810, the cache memory 816 (or selected aspects of 816) may be incorporated into the processing core 812.

[0048] To better illustrate the methods and apparatus disclosed herein, a non-limiting list of examples is provided here:

[0049] Example 1 includes a semiconductor device. The semiconductor device includes a semiconductor substrate, a tube core connected to the semiconductor substrate, and a patterned layer connected to the back side of the tube core. The patterned layer includes a thermally conductive material. The patterned layer includes a pattern of elements that form a groove, wherein the pattern of the elements is different across the back side of the tube core.

[0050] Example 2 includes the semiconductor device of Example 1, further comprising at least one thermally conductive interlayer between the die and the patterned layer.

[0051] Example 3 includes the semiconductor device of any of Examples 1-2, wherein the thermally conductive material includes metal.

[0052] Example 4 includes the semiconductor device of any of Examples 1-3, wherein the metal includes copper.

[0053] Example 5 includes the semiconductor device of any of Examples 1-4, wherein the thermally conductive material includes diamond.

[0054] Example 6 includes the semiconductor device of any of Examples 1-5, wherein elements in the pattern of elements extend across an entire width of the die.

[0055] Example 7 includes the semiconductor device of any of Examples 1-6, wherein elements in the pattern of elements include arc-shaped geometries.

[0056] Example 8 includes the semiconductor device of any of Examples 1-7, wherein the recess includes a compliant fill.

[0057] Example 9 includes the semiconductor device of any of Examples 1-8, wherein the compliant filler includes thermally conductive particles.

[0058] Example 10 includes the semiconductor device of any of Examples 1-9, wherein a thickness of the patterned layer is between 50 μm and 500 μm.

[0059] Example 11 is a semiconductor device. The semiconductor device includes a semiconductor substrate and a base die connected to the semiconductor substrate, wherein one or more secondary dies are coupled to a back side of the base die. The semiconductor device includes a patterned layer connected to the back side of the semiconductor device. The patterned layer includes a thermally conductive material. The patterned layer includes a pattern of elements forming a groove, wherein the pattern of the elements is different across the back side of the semiconductor device.

[0060] Example 12 includes the semiconductor device of Example 11, wherein the patterned layer forms a direct interface with one or more secondary dies.

[0061] Example 13 includes the semiconductor device of any of Examples 11-12, further comprising a silicon structure over the one or more secondary dies, wherein the patterned layer forms a direct interface with the silicon structure.

[0062] Example 14 includes the semiconductor device of any of Examples 11-13, wherein the dielectric material includes a polymer molding material.

[0063] Example 15 includes the semiconductor device of any of Examples 11-14, wherein the dielectric material includes silicon oxide glass.

[0064] Example 16 includes the semiconductor device of any of Examples 11-15, wherein the recess includes a compliant fill.

[0065] Example 17 includes the semiconductor device of any of Examples 11-16, wherein the compliant filler includes thermally conductive particles.

[0066] Example 18 is a method of manufacturing a semiconductor device. The method includes: coupling a thermally conductive layer to a die; forming at least one patterned recess element in the thermally conductive layer; filling the at least one patterned recess with a compliant filler; and connecting the die to a semiconductor substrate.

[0067] Example 19 includes the method of Example 18, wherein forming at least one patterned recess feature comprises laser ablation.

[0068] Example 20 includes the method of any of Examples 18-19, further comprising probing the die to test for manufacturing defects before attaching the die to the semiconductor substrate.

[0069] Throughout this specification, multiple instances can implement components, operations or structures described as single instances. Although the individual operations of one or more methods are described and described as independent operations, one or more operations in the individual operations can be performed simultaneously, and it is not required to perform the operations in the order described. The structure and functionality presented as independent components in the example configuration can be implemented as a combined structure or component. Similarly, the structure and functionality presented as a single component can be implemented as an independent component. These and other changes, modifications, additions and improvements belong to the scope of the subject matter in this article.

[0070] Although an overview of the inventive subject matter has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of the embodiments of the present disclosure. Such embodiments of the inventive subject matter may be referred to herein, individually or collectively, as the term "invention" merely for convenience and in the case where more than one is actually disclosed, it is not intended to actively limit the scope of the present application to any single disclosure or inventive concept.

[0071] The embodiments described herein are described in sufficient detail to enable those skilled in the art to implement the disclosed teachings. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of the present disclosure. Therefore, the detailed description is not to be construed in a limiting sense, and the scope of the various embodiments is limited only by the appended claims, together with the full scope of equivalents to which such claims are entitled.

[0072] As used herein, the term "or" may be interpreted in the sense of either including or excluding. In addition, multiple instances may be provided for resources, operations, or structures described herein as single instances. In addition, the boundaries between various resources, operations, modules, engines, and data stores are somewhat arbitrary, and specific operations are described in the context of specific illustrative configurations. Other allocations of functionality are foreseeable and may fall within the scope of various embodiments of the present disclosure. Typically, structures and functionality presented as independent resources in the example configurations may be implemented as combined structures or resources. Similarly, structures and functionality presented as single resources may be implemented as independent resources. These and other changes, modifications, additions, and improvements fall within the scope of embodiments of the present disclosure as represented by the appended claims. The specification and drawings are therefore to be viewed in an illustrative, rather than a restrictive, sense.

[0073] For purposes of explanation, the foregoing description has been described with reference to specific example embodiments. However, the illustrative discussion above is not intended to be exhaustive or to limit the possible example embodiments to the precise forms disclosed. In light of the above teachings, many modifications and variations are possible. The exemplary embodiments have been selected and described in order to best explain the principles involved and their practical application, thereby enabling others skilled in the art to best utilize the various example embodiments with various modifications as are suitable for the particular use contemplated.

[0074] It will also be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact without departing from the scope of this example embodiment. Both the first contact and the second contact are contacts, but they are not the same contact.

[0075] The terms used in the description of the exemplary embodiments herein are only for the purpose of describing the specific exemplary embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, as used in the description of the exemplary embodiments and the attached examples, the singular forms "a", "an" and "the" are intended to also include the plural forms. It will also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising" when used in this specification specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0076] As used herein, the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if [a stated condition or event] is detected" may be interpreted to mean "upon the determination" or "in response to the determination" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

Claims

1. A semiconductor device comprising: Semiconductor substrate; a die connected to the semiconductor substrate; as well as A patterned layer of thermally conductive material connected to the back side of the die, wherein the patterned layer includes a pattern of elements that form recesses, wherein the pattern of elements differs across the back side of the die. 2 . The semiconductor device of claim 1 , further comprising at least one thermally conductive interlayer between the die and the patterned layer.

3. The semiconductor device according to claim 1, wherein: The thermally conductive material includes metal.

4. The semiconductor device according to claim 3, wherein: The metal includes copper.

5. The semiconductor device according to claim 1, wherein: The thermally conductive material includes diamond.

6. The semiconductor device according to claim 1, wherein: Elements in the pattern of elements extend across the entire width of the die.

7. The semiconductor device according to claim 1, wherein: Elements in the pattern of elements include arcuate geometric shapes.

8. The semiconductor device according to claim 1, wherein: The groove includes a compliant filler.

9. The semiconductor device according to claim 8, wherein: The compliant filler includes thermally conductive particles.

10. The semiconductor device according to claim 1, wherein The thickness of the patterned layer is between 50 μm and 500 μm.

11. A semiconductor device comprising: Semiconductor substrate; a base die connected to the semiconductor substrate; one or more secondary dies coupled to a back side of the base die; a dielectric material encapsulating the one or more secondary dies; as well as A patterned layer connected to the back side of the semiconductor device, the patterned layer being composed of a thermally conductive material, wherein the patterned layer includes a pattern of elements forming recesses, wherein the pattern of elements differs across the back side of the semiconductor device.

12. The semiconductor device according to claim 11, wherein: The patterned layer forms a direct interface with the one or more secondary dies.

13. The semiconductor device of claim 11, further comprising a silicon structure over the one or more secondary dies, wherein: The patterned layer forms a direct interface with the silicon structure.

14. The semiconductor device according to claim 11, wherein: The dielectric material includes a polymer molding material.

15. The semiconductor device according to claim 11, wherein: The dielectric material includes silica glass.

16. The semiconductor device according to claim 11, wherein: The groove includes a compliant filler.

17. The semiconductor device according to claim 16, wherein: The compliant filler includes thermally conductive particles.

18. A method for manufacturing a semiconductor device, comprising: coupling a thermally conductive layer to the die; forming at least one patterned recessed element in the thermally conductive layer; filling the at least one patterned groove with a compliant filler; as well as The die is connected to a semiconductor substrate.

19. The method of claim 18, wherein: Forming at least one patterned recessed feature includes laser ablation.

20. The method of claim 18, further comprising: The die is probed to test for manufacturing defects prior to attaching the die to the semiconductor substrate.

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