System and method for coupling integrated circuit die

Abstract

The invention relates to systems and methods for coupling integrated circuit dies. A circuit system includes a support device having interconnected conductors. The circuitry also includes first, second, and third integrated circuits mounted on the support device. An interconnect conductor couples the first integrated circuit to the third integrated circuit. The second integrated circuit is located between the first integrated circuit and the third integrated circuit.

Description

Technical Field

[0001] The present disclosure relates to electronic circuit systems and methods, and more particularly to circuit systems and methods for coupling integrated circuit dies. Background Art

[0002] Many modern electronic circuit systems include integrated circuit (IC) packages. An IC package may contain multiple integrated circuit dies. The integrated circuit dies in an IC package may be mounted on an interposer or a package substrate, for example. Summary of the invention

[0003] According to one aspect of the present disclosure, a circuit system is provided, comprising: a supporting device including a first interconnect conductor; and a first integrated circuit, a second integrated circuit, and a third integrated circuit coupled to the supporting device, wherein the first interconnect conductor couples the first integrated circuit to the third integrated circuit, and wherein the second integrated circuit is between the first integrated circuit and the third integrated circuit.

[0004] According to one aspect of the present disclosure, a method is provided, comprising: transmitting a first signal from a first integrated circuit to a second integrated circuit through a first interconnect conductor in a supporting device; and transmitting a second signal from the second integrated circuit to the first integrated circuit through the first interconnect conductor, wherein the first integrated circuit, the second integrated circuit, and a third integrated circuit are mounted on the supporting device, and wherein the third integrated circuit is located between the first integrated circuit and the second integrated circuit in a circuit system.

[0005] According to one aspect of the present disclosure, an integrated circuit package is provided, comprising: an interconnect device, which includes a first conductor; and a first integrated circuit die, a second integrated circuit die, and a third integrated circuit die, which are coupled to the interconnect device, wherein the first integrated circuit die is coupled to the third integrated circuit die through the first conductor, and wherein the first conductor is arranged between the first integrated circuit die and the third integrated circuit die below the second integrated circuit die. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram illustrating a top view of an example of a circuit system including a support device and 16 integrated circuit dies.

[0007] Figure 2 is an example of having additional vertical conductors in the support device Figure 1 FIG. 1 is a diagram of a top view of a circuit system.

[0008] Figure 3is an example of a device having additional conductors arranged vertically and horizontally in the support device. Figure 1 FIG. 1 is a diagram of a top view of a circuit system.

[0009] Figure 4 is an example of an additional conductor having a diagonal arrangement in the support device. Figure 1 FIG. 1 is a diagram of a top view of a circuit system.

[0010] Figure 5 is a diagram illustrating a side view of an example of a circuit system or a portion thereof including five integrated circuits and supporting devices.

[0011] Figure 6 is a diagram illustrating a side view of an example of a circuit system or a portion thereof including six integrated circuits and supporting devices.

[0012] Figure 7 Yes, it can be Figures 1 to 6 Diagrams of illustrative examples of any one or more of the programmable integrated circuits (ICs) shown. DETAILED DESCRIPTION

[0013] Some electronic circuit systems include multiple integrated circuits (ICs) in the same package. As an example, two, three, four or more ICs can be housed in the same package. The integrated circuits in the package can be coupled together, for example, by a package substrate or an insert in the package. As another example, two integrated circuits can be stacked vertically and coupled together in a 3-dimensional (3D) arrangement. For example, a single integrated circuit (IC) package can be designed to accommodate a processing IC and a transceiver IC, and the transceiver IC implements a data transmission protocol for communication between the processing IC and one or more devices outside the IC package. Some IC packages include interconnect bridges. However, the interconnect bridge only couples the ICs adjacent to each other in the IC package together.

[0014] According to some examples disclosed herein, two or more non-adjacent integrated circuits in a circuit system are coupled together by interconnecting conductors in a supporting device. The circuit system includes a supporting device and a first, second, and third integrated circuit. The circuit system may be, for example, an integrated circuit package. The supporting device may be, for example, a package substrate or an insert. The interconnecting conductors in the supporting device couple the first integrated circuit to the third integrated circuit. The second integrated circuit is located between the first and third integrated circuits. The interconnecting conductors may be arranged around the second integrated circuit (e.g., below, above, or beside the second integrated circuit), depending on the orientation of the supporting device relative to the integrated circuit. Thus, the interconnecting conductors provide an electrical path for signals to be routed between the first and third integrated circuits that are not adjacent to each other in the circuit system. As an example, the interconnecting conductors may be arranged horizontally, vertically, diagonally, or in a stepped configuration through the supporting device relative to the orientation of the supporting device in the circuit system.

[0015] One or more specific examples are described below. In order to provide a concise description of these examples, not all features of actual implementations are described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which may vary from implementation to implementation. Moreover, it should be understood that such development efforts may be complex and time-consuming, but are still routine tasks of design, fabrication, and manufacturing for those of ordinary skill who have the benefit of this disclosure.

[0016] Throughout the specification and claims, the term "connected" means a direct electrical connection between connected circuits without any intermediate devices. The term "coupled" means a direct electrical connection between circuits or an indirect electrical connection through one or more passive or active intermediate devices that allows information transfer between circuits. The term "circuit" may mean one or more passive and / or active electrical components that are arranged to cooperate with each other to provide a desired functionality.

[0017] Figure 1 1 is a diagram illustrating a top view of an example of a circuit system including a support device 100 and 16 integrated circuits 101-116. Each of the integrated circuits (ICs) 101-116 is a separate integrated circuit (IC) die mounted on and coupled to the support device 100. Figure 1 In the example of FIG. 1 , ICs 101 - 116 are arranged in a 4×4 array with ICs 101 , 104 , 113 , and 116 in the 4 corners of the array. Figure 1 16 dies are shown arranged in a 4×4 array, but it should be understood that the techniques disclosed herein can be used in a circuit system having any suitable number of ICs arranged in any suitable configuration. Each of ICs 101-116 can be any type of IC, such as a programmable logic IC, a microprocessor IC, a graphics processing unit IC, a memory IC, a special purpose IC, a transceiver IC, a memory IC, etc. Figure 1 The circuit system may be, for example, an integrated circuit (IC) package. As an example, the support device 100 may be a package substrate or an interposer.

[0018] The support device 100 includes eight interconnecting conductors 121-128, which are arranged relative to each other. Figure 1The orientation shown is arranged horizontally. Support device 100 may also be referred to as an interconnect device. Interconnect conductor 121 couples integrated circuit (IC) 101 and IC 103. Interconnect conductor 121 can route signals between IC 101 and 103. Interconnect conductor 121 is arranged below IC 102. IC 102 is between IC 101 and 103. Interconnect conductor 122 couples IC 102 and IC 104. Interconnect conductor 122 can route signals between IC 102 and 104. Interconnect conductor 122 is arranged below IC 103. IC 103 is between IC 102 and 104.

[0019] Interconnect conductor 123 couples integrated circuit (IC) 105 and IC 107. Interconnect conductor 123 may route signals between ICs 105 and 107. Interconnect conductor 123 is disposed under IC 106. IC 106 is between ICs 105 and 107. Interconnect conductor 124 couples IC 106 and IC 108. Interconnect conductor 124 may route signals between ICs 106 and 108. Interconnect conductor 124 is disposed under IC 107. IC 107 is between ICs 106 and 108.

[0020] Interconnect conductors 125, 126, 127, and 128 couple (and may route signals between) ICs 109 and 111, ICs 110 and 112, ICs 113 and 115, and ICs 114 and 116, respectively. Interconnect conductors 125, 126, 127, and 128 are routed under ICs 110, 111, 114, and 115, respectively. ICs 110, 111, 114, and 115 are located between ICs 109 and 111, ICs 110 and 112, ICs 113 and 115, and ICs 114 and 116, respectively.

[0021] Figure 2 The example of the support device 100 having an additional vertical conductor is shown in FIG. Figure 1 A top view of the circuit system. Figure 2 In the example of FIG. 1 , the support device 100 includes 8 additional interconnect conductors 201 - 208 , which are relative to Figure 2 109. Interconnect conductor 201 couples integrated circuit (IC) 101 and IC 109. Interconnect conductor 201 may route signals between ICs 101 and 109. Interconnect conductor 201 is routed below IC 105. IC 105 is between ICs 101 and 109. Interconnect conductor 202 couples integrated circuits (ICs) 105 and 113. Interconnect conductor 202 may route signals directly between ICs 105 and 113. Interconnect conductor 202 is routed below IC 109. IC 109 is between ICs 105 and 113.

[0022] Interconnect conductors 203, 204, 205, 206, 207, and 208 couple (and may route signals between) ICs 102 and 110, ICs 106 and 114, ICs 103 and 111, ICs 107 and 115, ICs 104 and 112, and ICs 108 and 116, respectively. Interconnect conductors 203, 204, 205, 206, 207, and 208 are routed under ICs 106, 110, 107, 111, 108, and 112, respectively. ICs 106, 110, 107, 111, 108, and 112 are between ICs 102 and 110, ICs 106 and 114, ICs 103 and 111, ICs 107 and 115, ICs 104 and 112, and ICs 108 and 116, respectively.

[0023] Figure 3 is an example of having additional conductors arranged vertically and horizontally in the support device 100 Figure 1 A top view of the circuit system. Figure 3 In the example of FIG. 1 , the support device 100 includes five additional interconnecting conductors 301 - 305 , each of which is relative to Figure 3 The orientations shown are vertical and horizontal. Figure 3 In the top view of FIG. 1 , each of the interconnecting conductors 301 - 305 includes a right angle (90 degree) turn. Figure 3 The top view includes two right-angle turns.

[0024] Interconnect conductor 301 couples ICs 101 and 116 together. Interconnect conductor 301 may route signals between ICs 101 and 116. Interconnect conductor 301 is routed under ICs 105 and 109-112. ICs 105 and 109-112 are between ICs 101 and 116 in the circuit system.

[0025] Interconnect conductors 302 couple ICs 101 and 108 together and route signals between ICs 101 and 108. Interconnect conductors 302 are routed underneath ICs 105-107. ICs 105-107 are between ICs 101 and 108 in the circuit system.

[0026] Interconnect conductors 303, 304, and 305 couple together and route signals between ICs 104 and 106, ICs 110 and 113, and 104 and 113, respectively. Interconnect conductors 303, 304, and 305 are arranged under ICs 107-108, IC 114, and ICs 108, 112, and 114-116, respectively. ICs 107-108 are between ICs 104 and 106. IC 114 is between ICs 110 and 113. ICs 108, 112, and 114-116 are between ICs 104 and 113 in the circuit system.

[0027] Figure 4 is an example of an additional conductor having a diagonal arrangement in the support device 100. Figure 1 A top view of the circuit system. Figure 4 In the example of FIG. 1 , the support device 100 includes four additional interconnecting conductors 401-404, each of which is relative to Figure 4 The orientation shown is diagonally arranged. Each of the interconnect conductors 401 - 404 is arranged diagonally with respect to each of the four sides of the device 100 .

[0028] Interconnect conductor 401 couples ICs 101 and 108 and routes signals between ICs 101 and 108. Interconnect conductor 401 is routed under ICs 102 and 107. ICs 102 and 107 are between ICs 101 and 108 in the circuit system. Interconnect conductor 402 couples ICs 101 and 107 and routes signals between ICs 101 and 107. Interconnect conductor 402 is routed under ICs 102 and 106. ICs 102 and 106 are between ICs 101 and 107 in the circuit system. Interconnect conductor 403 couples ICs 101 and 116 and routes signals between ICs 101 and 116. Interconnect conductor 403 is routed under ICs 106 and 111. ICs 106 and 111 are between ICs 101 and 116 in the circuit system. Interconnect conductor 404 couples ICs 104 and 113 and routes signals between ICs 104 and 113. Interconnect conductor 404 is routed below ICs 107 and 110. ICs 107 and 110 are between ICs 104 and 113 in the circuit system.

[0029] Figure 5 is a diagram illustrating a side view of an example of a circuit system or a portion thereof including five integrated circuits (ICs) 501 - 503 and 507 - 508 and a support device 510 . Figure 5 For example it could be Figures 1 to 41-16, and wherein support device 510 is a portion of support device 100. Each of ICs 501, 502, and 503 is coupled to support device 510 and mounted on support device 510 via a subset of conductive bumps 504. IC 507 is vertically stacked on top of IC 501 in a three-dimensional (3D) configuration, and IC 507 is coupled to IC 501 via conductive bumps 505. IC 508 is vertically stacked on top of IC 503 in a 3D configuration, and IC 508 is coupled to IC 503 via conductive bumps 509. In an alternative embodiment, conductive posts may be used instead of IC 501. Figure 5 Some or all of the conductive bumps.

[0030] exist Figure 5 In the example of FIG. 5 , interconnect conductors 506 in support device 510 couple integrated circuits (ICs) 501 and IC 503 through two of the conductive bumps 504. One of these conductive bumps 504 connects IC 501 to conductor 506, and a second of these conductive bumps 504 connects IC 503 to conductor 506. Signals can be transmitted between ICs 501 and 503 through these two conductive bumps and conductors 506. Figure 5 In the side view of FIG. 5 , conductor 506 includes two vertical portions and one horizontal portion. Interconnect conductor 506 is arranged below IC 502. IC 502 is between ICs 501 and 503. Conductor 506 may be, for example, any one of conductors 121-128 or 201-208.

[0031] IC die 507 is coupled to conductor 506 through one of conductive bumps 505, conductive material in through silicon via 511 in IC 501, and one of conductive bumps 504 under IC 501. IC die 508 is coupled to conductor 506 through one of conductive bumps 509, conductive material in through silicon via (TSV) 512 in IC 503, and one of conductive bumps 504 under IC 503. Signals can be transmitted between ICs 507 and 508 through these conductive bumps, TSVs 511-512, and conductor 506 in supporting device 510.

[0032] Figure 6 is a diagram illustrating a side view of an example of a circuit system or a portion thereof including six integrated circuits 601 - 604 and 607 - 608 and a support device 610 . Figure 6 For example it could be Figures 1 to 41-604, and wherein support device 610 is a cross-section of support device 100. Each of ICs 601, 602, 603, and 604 is coupled to and mounted on support device 610 via a subset of conductive bumps 605. IC 607 is vertically stacked on top of IC 601 in a three-dimensional (3D) configuration, and IC 607 is coupled to IC 601 via conductive bumps 611. IC 608 is vertically stacked on top of IC 604 in a 3D configuration, and IC 608 is coupled to IC 604 via conductive bumps 612. In alternative embodiments, conductive posts may be used instead of IC 601. Figure 6 Some or all of the conductive bumps.

[0033] exist Figure 6 In the example of FIG. 6 , an interconnect conductor 606 in a support device 610 couples an integrated circuit (IC) 607 and an IC 608 via two wire bonding connections 613-614. Wire bonding connection 613 connects IC 607 to conductor 606 in support device 610, and wire bonding connection 614 connects IC 608 to conductor 606 in support device 610. Signals can be transmitted between IC 607 and 608 via these two wire bonding connections 613 and 614 and conductor 606. Figure 6 In the side view of FIG. 6 , conductor 606 includes two vertical portions and a horizontal portion connecting the two vertical portions. Interconnect conductor 606 is arranged below IC 602-603. IC 602-603 is between IC 601 and IC 604. If Figure 4 If the circuit system includes vertically stacked ICs, conductor 606 can be, for example, any one of conductors 401, 403, or 404.

[0034] Figure 7 Yes, it can be Figures 1 to 6 FIG. 7 is a diagram of an illustrative example of any one or more of the programmable integrated circuits (ICs) shown in FIG. Figure 7 As shown, programmable integrated circuit 700 may include a two-dimensional array of functional blocks, for example including logic array blocks (LABs) 710 and other functional blocks, such as random access memory (RAM) blocks 730 and digital signal processing (DSP) blocks 720. Functional blocks such as LABs 710 may include smaller programmable areas (e.g., logic elements, configurable logic blocks, or adaptive logic modules) that receive input signals and perform customized functions on the input signals to generate output signals. One or more of LABs 710 and / or DSPs 720 may implement the above-mentioned processing elements.

[0035] In addition, the programmable integrated circuit 700 may have an input / output element (IOE) 702, which is used to drive the signal to leave the programmable integrated circuit 700 and receive signals from other devices. The input / output element 702 may include a parallel input / output circuit, a serial data transceiver circuit, a differential receiver and transmitter circuit, or other circuits for connecting an integrated circuit to another integrated circuit. As shown, the input / output element 702 may be located around the periphery of the IC. If desired, the programmable integrated circuit 700 may have input / output elements 702 arranged in different ways. For example, the input / output element 702 may form one or more columns of input / output elements, which may be located anywhere on the programmable integrated circuit 700 (e.g., uniformly distributed across the width of the programmable integrated circuit). If desired, the input / output element 702 may form one or more rows of input / output elements (e.g., distributed across the height of the programmable integrated circuit). Alternatively, the input / output element 702 may form an island of input / output elements, which may be distributed above the surface of the programmable integrated circuit 700 or gathered in a selected area.

[0036] The programmable integrated circuit 700 may also include programmable interconnect circuits in the form of vertical routing channels 740 (i.e., interconnects formed along the vertical axis of the programmable integrated circuit 700) and horizontal routing channels 750 (i.e., interconnects formed along the horizontal axis of the programmable integrated circuit 700), each routing channel including at least one track for routing at least one conductive line.

[0037] It should be noted that in addition to Figure 7 In addition to the topology of the interconnect circuit depicted, other layout topologies may be used. For example, in the case of a three-dimensional integrated circuit, the layout topology may include wires that run diagonally or horizontally and vertically along different portions of its extent and wires that are perpendicular to the device plane, and the drivers of the wires may be located at points different from one end of the wire. The layout topology may include global wires that span substantially all of the programmable integrated circuit 700, partial global wires such as wires that span a portion of the programmable integrated circuit 700, staggered wires of a specific length, smaller local wires, or any other suitable interconnect resource arrangement.

[0038] In addition, it should be understood that the examples disclosed herein can be implemented in any type of integrated circuit. If desired, the functional blocks of such an integrated circuit can be arranged in more levels or layers, wherein multiple functional blocks are interconnected to form larger blocks. Other device arrangements can use functional blocks that are not arranged in rows and columns.

[0039] Programmable integrated circuit 700 may include programmable memory elements. The memory elements may be loaded with configuration data (also referred to as programming data) using input / output elements (IOEs) 702. Once loaded, the memory elements each provide a corresponding static control signal that controls the operation of an associated functional block (e.g., LAB 710, DSP 720, RAM 730, or input / output element 702).

[0040] In a typical case, the output of the loaded memory element is applied to the gate of the field effect transistor in the functional block to turn on or off certain transistors, thereby configuring the logic in the functional block including the routing path. Programmable logic circuit elements that can be controlled in this way include multiplexers (e.g., multiplexers used to form routing paths in interconnect circuits), lookup tables, logic arrays, AND, OR, NAND and NOR logic gates, pass gates, etc.

[0041] The memory elements may use any suitable volatile and / or nonvolatile memory structures, such as random access memory (RAM) cells, fuses, antifuses, programmable read-only memory cells, mask programming and laser programming structures, combinations of these structures, etc. Because the memory elements are loaded with configuration data during programming, the memory elements are sometimes referred to as configuration memories or programmable memory elements.

[0042] Programmable memory elements can be organized in a configuration memory array consisting of rows and columns. Data registers spanning all columns and address registers spanning all rows can receive configuration data. Configuration data can be shifted onto the data registers. When the appropriate address register is asserted, the data registers write the configuration data to the configuration memory element of the row specified by the address register.

[0043] Programmable integrated circuit 700 may include configuration memory organized in sectors, whereby a sector may include configuration RAM bits that specify the functions and / or interconnections of subcomponents and conductors in or across the sector. Individual sectors may include separate data and address registers.

[0044] Figure 7The programmable IC is only one example of an IC that can be used with the embodiments disclosed herein. The embodiments disclosed herein can be used with any suitable integrated circuit or system. For example, the embodiments disclosed herein can be used with many types of devices, such as processor integrated circuits, central processing units, memory integrated circuits, graphics processing unit integrated circuits, application specific standard products (ASSPs), application specific integrated circuits (ASICs), and programmable logic integrated circuits. Examples of programmable logic integrated circuits include programmable array logic (PAL), programmable logic arrays (PLA), field programmable logic arrays (FPLA), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), just to name a few examples.

[0045] The integrated circuit disclosed in one or more embodiments of the present invention may be part of a data processing system that includes one or more of the following components: a processor; a memory; an input / output circuit; and peripheral devices. The data processing system may be used for a variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other suitable application. The integrated circuit may be used to perform a variety of different logic functions.

[0046] Typically, software and data for performing any function disclosed herein can be stored in a non-transient computer-readable storage medium. A non-transient computer-readable storage medium is a tangible computer-readable storage medium that stores data and software for access at a later time, which is different from a medium (e.g., a wire) that only transmits a propagation electrical signal. Software code may sometimes be referred to as software, data, program instructions, instructions, or code. A non-transient computer-readable storage medium may, for example, include a computer memory chip, a non-volatile memory such as a non-volatile random access memory (NVRAM), one or more hard disk drives (e.g., a magnetic drive or a solid-state drive), one or more removable flash drives or other removable media, a compact disk (CD), a digital versatile disk (DVD), a blue disc (BD), other optical media, and a floppy disk, a magnetic tape, or any other suitable (one or more) memory or storage device.

[0047] Additional examples are now disclosed. Example 1 is a circuit system comprising: a support device including a first interconnect conductor; and first, second, and third integrated circuits coupled to the support device, wherein the first interconnect conductor couples the first integrated circuit to the third integrated circuit, and wherein the second integrated circuit is between the first integrated circuit and the third integrated circuit.

[0048] In Example 2, the circuit system of Example 1 further includes: fourth and fifth integrated circuits coupled to the support device, wherein the support device further includes a second interconnect conductor coupling the first integrated circuit to the fifth integrated circuit, and wherein the fourth integrated circuit is between the first integrated circuit and the fifth integrated circuit.

[0049] In Example 3, the circuit system of any one of Examples 1 to 2 may optionally include, wherein the support device includes an interposer.

[0050] In Example 4, the circuit system of any one of Examples 1 to 3 may optionally include, wherein the circuit system is an integrated circuit package, and wherein the support device includes a package substrate.

[0051] In Example 5, the circuit system of any one of Examples 1 to 4 may optionally include, wherein the first interconnect conductor includes a first portion, and the first portion is arranged at a right angle relative to the second portion of the first interconnect conductor from a top-down perspective of the circuit system.

[0052] In Example 6, the circuit system of any one of Examples 1 to 5 may optionally include, wherein the first interconnect conductor is arranged diagonally relative to an edge of the support device.

[0053] In Example 7, the circuit system of any one of Examples 1 to 6 may optionally include, wherein the first integrated circuit and the third integrated circuit are in two corners of a die array in the circuit system, and wherein the first interconnect conductor is at least a portion of a corner-to-corner connection between the first integrated circuit and the third integrated circuit.

[0054] In Example 8, the circuit system of any one of Examples 1 to 7 also includes: a fourth integrated circuit mounted on a support device, wherein the first integrated circuit is vertically mounted above the fourth integrated circuit; and a fifth integrated circuit mounted on the support device, wherein the third integrated circuit is vertically mounted above the fifth integrated circuit.

[0055] Example 9 is a method comprising: transmitting a first signal from a first integrated circuit to a second integrated circuit through a first interconnect conductor in a supporting device; and transmitting a second signal from the second integrated circuit to the first integrated circuit through the first interconnect conductor, wherein the first integrated circuit, the second integrated circuit, and a third integrated circuit are mounted on the supporting device, and wherein the third integrated circuit is located between the first integrated circuit and the second integrated circuit in a circuit system.

[0056] In Example 10, the method of Example 9 also includes: transmitting a third signal from a fourth integrated circuit to a fifth integrated circuit through a second interconnect conductor in a supporting device; and transmitting a fourth signal from the fifth integrated circuit to the fourth integrated circuit through a second interconnect conductor, wherein the fourth integrated circuit, the fifth integrated circuit, and the sixth integrated circuit are mounted on the supporting device, and wherein the sixth integrated circuit is located between the fourth integrated circuit and the fifth integrated circuit in the circuit system.

[0057] In Example 11, the method of any one of Examples 9 to 10 can optionally include, wherein the support device includes an insert.

[0058] In Example 12, the method of any one of Examples 9 to 11 may optionally include, wherein the support device includes a packaging substrate.

[0059] In Example 13, the method of any one of Examples 9 to 12 may optionally include, wherein a fourth integrated circuit is mounted on the support device, and wherein the fourth integrated circuit is between the first integrated circuit and the second integrated circuit.

[0060] In Example 14, the method of any one of Examples 9 to 13 can optionally include, wherein the first interconnect conductor includes a right angle turn in a top-down perspective of the circuitry.

[0061] In Example 15, the method of any one of Examples 9 to 14 may optionally include, wherein the first interconnect conductor is arranged diagonally relative to an edge of the support device.

[0062] Example 16 is an integrated circuit package comprising: an interconnect device comprising a first conductor; and first, second, and third integrated circuit dies coupled to the interconnect device, wherein the first integrated circuit die is coupled to the third integrated circuit die via the first conductor, and wherein the first conductor is arranged between the first integrated circuit die and the third integrated circuit die below the second integrated circuit die.

[0063] In Example 17, the integrated circuit package of Example 16 also includes: fourth, fifth and sixth integrated circuit dies, which are coupled to the interconnect device, wherein the fourth integrated circuit die is coupled to the fifth integrated circuit die via a second conductor in the interconnect device, and wherein the second conductor is arranged between the fourth integrated circuit die and the fifth integrated circuit die below the sixth integrated circuit die.

[0064] In Example 18, the integrated circuit package of any one of Examples 16 to 17 can optionally include, wherein the interconnect device is an interposer.

[0065] In Example 19, the integrated circuit package of any one of Examples 16 to 17 may optionally include wherein the interconnect device is a package substrate.

[0066] In Example 20, the integrated circuit package of any one of Examples 16 to 19 can optionally include, wherein the first conductor includes at least one right angle turn in a top view of the integrated circuit package.

[0067] For the purpose of illustration, the above description of examples has been presented. The above description is not intended to be exhaustive or limited to the examples disclosed herein. In some cases, the features of the examples may be adopted without corresponding use of other features described. According to the above teachings, many modifications, substitutions and variations are possible.

Claims

1. A circuit system, comprising: a support device comprising a first interconnect conductor; as well as A first integrated circuit, a second integrated circuit, and a third integrated circuit coupled to the support device, wherein the first interconnect conductor couples the first integrated circuit to the third integrated circuit, and wherein the second integrated circuit is between the first integrated circuit and the third integrated circuit.

2. The circuit system according to claim 1, further comprising: A fourth integrated circuit and a fifth integrated circuit coupled to the support device, wherein the support device further comprises a second interconnect conductor coupling the first integrated circuit to the fifth integrated circuit, and wherein the fourth integrated circuit is between the first integrated circuit and the fifth integrated circuit.

3. The circuit system according to any one of claims 1 to 2, wherein: The supporting means comprises an insert.

4. The circuit system according to any one of claims 1 to 2, wherein: The circuit system is an integrated circuit package, and wherein the support device includes a package substrate.

5. The circuit system according to any one of claims 1 to 2, wherein: The first interconnect conductor includes a first portion that is arranged at a right angle to a second portion of the first interconnect conductor from a top-down perspective of the circuit system.

6. The circuit system according to any one of claims 1 to 2, wherein: The first interconnect conductor is arranged diagonally with respect to an edge of the support device.

7. The circuit system according to any one of claims 1 to 2, wherein: The first integrated circuit and the third integrated circuit are in two corners of a die array in the circuit system, and wherein the first interconnect conductor is at least a portion of a corner-to-corner connection between the first integrated circuit and the third integrated circuit.

8. The circuit system according to any one of claims 1 to 2, further comprising: a fourth integrated circuit mounted on the support device, wherein the first integrated circuit is vertically mounted above the fourth integrated circuit; and A fifth integrated circuit is mounted on the support device, wherein the third integrated circuit is vertically mounted above the fifth integrated circuit.

9. A method comprising: transmitting a first signal from the first integrated circuit to the second integrated circuit via a first interconnect conductor in the support device; as well as transmitting a second signal from the second integrated circuit to the first integrated circuit through the first interconnect conductor, The first integrated circuit, the second integrated circuit and the third integrated circuit are mounted on the supporting device, and the third integrated circuit is located between the first integrated circuit and the second integrated circuit in the circuit system.

10. The method according to claim 9, further comprising: transmitting a third signal from the fourth integrated circuit to the fifth integrated circuit via a second interconnect conductor in the support device; as well as transmitting a fourth signal from the fifth integrated circuit to the fourth integrated circuit through the second interconnect conductor, The fourth integrated circuit, the fifth integrated circuit and the sixth integrated circuit are mounted on the supporting device, and the sixth integrated circuit is located between the fourth integrated circuit and the fifth integrated circuit in the circuit system.

11. The method according to any one of claims 9 to 10, wherein: The supporting means comprises an insert.

12. The method according to any one of claims 9 to 10, wherein: The supporting device includes a packaging substrate.

13. The method according to any one of claims 9 to 10, wherein: A fourth integrated circuit is mounted on the support device, and wherein the fourth integrated circuit is between the first integrated circuit and the second integrated circuit.

14. The method according to any one of claims 9 to 10, wherein: The first interconnect conductor includes a right angle turn in a top-down view of the circuitry.

15. The method according to any one of claims 9 to 10, wherein: The first interconnect conductor is arranged diagonally with respect to an edge of the support device.

16. An integrated circuit package, comprising: An interconnect device comprising a first conductor; as well as A first integrated circuit die, a second integrated circuit die, and a third integrated circuit die coupled to the interconnect device, wherein the first integrated circuit die is coupled to the third integrated circuit die through the first conductor, and wherein the first conductor is arranged between the first integrated circuit die and the third integrated circuit die below the second integrated circuit die.

17. The integrated circuit package of claim 16, further comprising: A fourth integrated circuit die, a fifth integrated circuit die, and a sixth integrated circuit die coupled to the interconnect device, wherein the fourth integrated circuit die is coupled to the fifth integrated circuit die through a second conductor in the interconnect device, and wherein the second conductor is arranged between the fourth integrated circuit die and the fifth integrated circuit die below the sixth integrated circuit die.

18. The integrated circuit package according to any one of claims 16 to 17, wherein: The interconnect device is an interposer.

19. The integrated circuit package according to any one of claims 16 to 17, wherein: The interconnect device is a package substrate.

20. The integrated circuit package according to any one of claims 16 to 17, wherein: The first conductor includes at least one right-angle turn in a top view of the integrated circuit package.

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