Hybrid semiconductor-on-insulator substrate, integrated circuit device, and method of manufacturing same

Abstract

A method of manufacturing a hybrid SOI substrate includes epitaxially growing a sacrificial layer on a semiconductor body and then epitaxially growing an upper semiconductor layer. The sacrificial layer may be a heavily doped semiconductor. The heavy doping allows the sacrificial layer to be selectively etched while leaving the upper semiconductor layer substantially intact. An SOI region of a semiconductor body is masked while an upper semiconductor layer and a sacrificial layer are etched from a peripheral region of the semiconductor body. A bulk semiconductor is then grown to replace the etch layer on the peripheral region. An opening is formed through the upper semiconductor layer in the SOI region, and the sacrificial layer is etched from below the upper semiconductor. The opening may then be filled with a dielectric, leaving a cavity under the upper semiconductor layer in the SOI region. The embodiment of the invention also discloses a hybrid semiconductor-on-insulator substrate, an integrated circuit device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a hybrid semiconductor-on-insulator substrate, an integrated circuit device, and a method for manufacturing the same. Background Art

[0002] Semiconductor devices are typically fabricated on bulk semiconductor substrates. Another type of substrate is a semiconductor-on-insulator (SOI) substrate. An SOI substrate includes an upper layer of a silicon layer or some other semiconductor separated from the underlying semiconductor body by an insulating layer. SOI substrates include partially depleted SOI substrates and fully depleted SOI substrates. The difference lies in the thickness of the upper semiconductor layer. If a transistor disposed on the upper semiconductor layer has a depletion region that is shallower than the upper semiconductor layer, the substrate is a partially depleted SOI substrate. If the substrate is thinner, so that the depletion region extends through the entire thickness of the upper semiconductor layer, the substrate is a fully depleted SOI substrate.

[0003] For certain applications, SOI substrates have advantages over bulk semiconductor substrates. For example, SOI substrates have lower parasitic capacitance than bulk semiconductor substrates. This advantage is more pronounced in circuits operating at high frequencies. As frequency increases, parasitic capacitance has a more significant effect. Examples of circuits that operate at high frequencies and benefit from SOI substrates include circuits with radio frequency devices, etc. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a hybrid SOI substrate is provided, comprising: a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region; an upper semiconductor layer located in the first region, wherein the upper semiconductor layer is separated from the semiconductor substrate by a cavity; and a bulk semiconductor layer located above the semiconductor substrate in the second region, wherein the bulk semiconductor layer extends from a height below the cavity to a height above the upper surface of the upper semiconductor layer.

[0005] According to another aspect of an embodiment of the present application, there is provided an integrated circuit device, comprising: a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region; an upper semiconductor layer located above the first region; an insulating layer located between the upper semiconductor layer and the semiconductor substrate in the first region; a bulk semiconductor layer located above the semiconductor substrate in the second region, wherein the bulk semiconductor layer is at the same height as the insulating layer and the upper semiconductor layer; and a polycrystalline semiconductor structure located between the upper semiconductor layer and the bulk semiconductor layer on one side of the first region.

[0006] According to another aspect of an embodiment of the present application, a method for manufacturing an integrated circuit device is provided, the method comprising: forming a sacrificial layer over a semiconductor body comprising a first region and a second region; epitaxially growing an upper semiconductor layer over the sacrificial layer; forming a mask over the first region; etching through the upper semiconductor layer and the sacrificial layer in the second region while masking the first region; epitaxially growing a bulk semiconductor layer in the second region; etching an opening, wherein the sacrificial layer is exposed through the opening; etching the sacrificial layer through the opening to form a cavity below the upper semiconductor layer in the first region; and sealing the opening with a dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A-Figure 1C Cross-sectional views and plan views of integrated circuit (IC) devices according to some embodiments of the present disclosure are shown. Figure 1A and Figure 1B are respectively corresponding to Figure 1C Cross-sectional view along lines AA' and BB' in the plan view.

[0009] Figure 2A-2C A cross-sectional view and a plan view of an IC device according to another embodiment of the present disclosure are shown.

[0010] Figure 3A-3C A cross-sectional view and a plan view of an IC device according to another embodiment of the present disclosure are shown.

[0011] Figure 4A-4C A cross-sectional view and a plan view of an IC device according to another embodiment of the present disclosure are shown.

[0012] Figure 5A-5C A cross-sectional view and a plan view of an IC device according to another embodiment of the present disclosure are shown.

[0013] Figure 6A-6C A cross-sectional view and a plan view of an IC device according to another embodiment of the present disclosure are shown.

[0014] Figure 7-Figure 16 A series of cross-sectional views illustrating methods according to some embodiments of the present disclosure are shown.

[0015] Figure 17-Figure 19 Shows Figure 7-Figure 16 A series of cross-sectional views of another embodiment of a variation of the method.

[0016] Fig. 20Flowcharts of methods according to some aspects of the present disclosure are provided.

[0017] Fig.21 Provided Fig. 20 A flowchart of another embodiment of the present disclosure of a variation of the method. DETAILED DESCRIPTION

[0018] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component is not in direct contact with the second component.

[0019] As shown, for ease of description, spacing relationship terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship between one element or component shown and another element or component. In addition to the orientation shown, the spatial relationship terms are intended to include different orientations of the device in use or in the operating process. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used in this article may be interpreted accordingly. The terms "first," "second," "third," "fourth," etc. are merely general identifiers and therefore may be interchanged in various embodiments. For example, although an element (e.g., an opening) may be referred to as a "first" element in some embodiments, in other embodiments, the element may be referred to as a "second" element.

[0020] While SOI substrates are advantageous for RF devices, for example, bulk semiconductor substrates have advantages for other types of devices as well. Bulk semiconductor substrates provide better thermal management, can be grounded for noise management, and are more suitable for forming a wider variety of devices than SOI substrates. Given that SOI substrates and bulk substrates each provide advantages for different types of devices, and it is desirable to combine devices of various device types on a single chip, there has long been a need for hybrid SOI substrates, which are substrates that include an SOI region and a bulk substrate region. RF and similar devices can be formed in the SOI region, while logic devices and similar devices can be formed in the bulk substrate region.

[0021] Some aspects of the present disclosure relate to a method for manufacturing a hybrid SOI substrate. The method includes forming a sacrificial layer above a semiconductor substrate. Epitaxially growing an upper semiconductor layer above the sacrificial layer. Masking a first area of ​​the SOI region while etching the upper semiconductor layer and the sacrificial layer from a second area that will be a bulk substrate (logic) region. The bulk epitaxial layer is then grown in the logic region to replace the etched layer. A mask is formed and used to etch openings. A liquid etchant is introduced through the openings and used to selectively etch the sacrificial layer from below the upper semiconductor layer, thereby leaving a cavity in the SOI region below the upper semiconductor layer. The openings can then be sealed with a dielectric. The dielectric that seals the openings forms a dielectric via.

[0022] In some embodiments, the openings are formed in the peripheral portion and the central portion of the SOI region. Including the openings in the peripheral portion and the central portion facilitates the removal of the sacrificial layer. In some embodiments, the openings are limited to the periphery of the SOI region. Limiting the openings to the periphery of the SOI region increases the active device area in the SOI region.

[0023] In some embodiments, after the opening is sealed, the cavity remains below the upper semiconductor layer in the SOI region. The cavity is filled with air or the like and provides a high degree of insulation between the upper semiconductor layer and the bulk semiconductor substrate. In some embodiments, the cavity is lined with a dielectric for filling the opening. In some other embodiments, the cavity is filled with a dielectric. The dielectric filling the cavity may be the same as the dielectric sealing the opening.

[0024] In some embodiments, the opening filling process is combined with a process for forming a shallow trench isolation (STI) structure in the logic area. The trench for the STI structure is etched simultaneously with the opening. In some embodiments, the trench and the opening are etched to equal depths. In some embodiments, the opening is etched deeper. The trench and the opening can be filled simultaneously and filled with the same dielectric. Forming these structures simultaneously reduces the overall processing time and the overall number of manufacturing steps.

[0025] The sacrificial layer is a type that seeds the growth of the upper semiconductor layer. In some embodiments, the sacrificial layer itself is an epitaxially grown semiconductor layer, but is grown with a higher dopant concentration than the upper semiconductor layer. In some embodiments, the sacrificial layer is heavily doped. The heavy doping provides at least about 1x10 18 atoms / cm 3 In some embodiments, the dopant is a P-type dopant.

[0026] When the bulk epitaxial layer is grown in the logic region, the upper semiconductor layer in the SOI region is masked, and therefore, the semiconductor of the bulk epitaxial layer does not grow above the top of the SOI region. However, the bulk epitaxial layer can grow from the edge of the sacrificial layer and the edge of the upper semiconductor layer on the side of the SOI region. The growth can be particularly fast and polycrystalline, especially at and above the interface between the sacrificial layer and the upper semiconductor layer. The lateral growth may cause protrusions of the polycrystalline semiconductor. In some embodiments, these protrusions can be reduced by a planarization process. In some embodiments, the planarization process completely removes the polycrystalline semiconductor grown from the side of the SOI region.

[0027] Figure 1A and Figure 1B A cross-sectional view of an integrated circuit (IC) device 100 is provided. Figure 1C A plan view is provided, which is an example of the present disclosure. Figure 1A is along Figure 1C The cross-sectional view taken along the line A-A' is Figure 1B is along Figure 1C 1. The IC device 100 includes a semiconductor substrate 125, which includes a semiconductor body 141 and an undoped semiconductor layer 145 epitaxially grown on the semiconductor body 141. The semiconductor body 141 can be a high-resistivity bulk semiconductor. The semiconductor substrate 125 includes an SOI region 135 and a bulk substrate or logic region 131. The undoped semiconductor layer 145 is thicker and higher in the SOI region 135.

[0028] A bulk semiconductor layer 149 is disposed over the undoped semiconductor layer 145 in the logic region 131. An upper semiconductor layer 109 is disposed over the undoped semiconductor layer 145 in the SOI region 135. The bulk semiconductor layer 149 and the upper semiconductor layer 109 have different sources and have different compositions than the undoped semiconductor layer 145. In some embodiments, the bulk semiconductor layer 149 and the upper semiconductor layer 109 are lightly P-doped. In some embodiments, the bulk semiconductor layer 149 and the upper semiconductor layer 109 have different dopant concentrations from each other.

[0029] The upper semiconductor layer 109 is separated from the undoped semiconductor layer 145 by an insulating layer 113. The insulating layer 113 includes a dielectric liner 107 and a cavity 103. The dielectric liner 107 surrounds the cavity 103 and is engaged with a dielectric through hole 111. The dielectric through hole 111 extends from the surface 101 to the insulating layer 113. Some dielectric through holes 111 are located on the edge of the SOI region 135. Other dielectric through holes in the dielectric through holes 111 are located in the SOI region 135 and pass through the upper semiconductor layer 109. The dielectric through hole 111 is shown as a rectangular structure to form a trench, but can be square or elongated. Alternatively, the dielectric through hole 111 can have other cross-sectional shapes, such as circular, elliptical, etc., or any other shape or combination of shapes.

[0030] like Figure 1B and Figure 1C As shown, polycrystalline structure 110 abuts upper semiconductor layer 109 at the outer edge of SOI region 135. Polycrystalline structure 110 may have a tapered shape that widens as it approaches upper surface 101. Polycrystalline structure 110 is an artifact of forming bulk semiconductor layer 149 using an epitaxial growth process after forming upper semiconductor layer 109.

[0031] Semiconductor devices are disposed in the logic region 131. These semiconductor devices may include transistors, diodes, capacitors, memory cells, transistors, resistors, etc., or any combination thereof. Examples are n-channel metal oxide semiconductor (NMOS) transistors 115 and p-channel metal oxide semiconductor (PMOS) transistors 119. Isolation structures such as shallow trench isolation (STI) structures 121 may also be disposed in the logic region 131.

[0032] A radio frequency device is formed in the SOI region 135. Examples of radio frequency devices include, but are not limited to, a radio frequency transmitter, a radio frequency receiver, a radio frequency switch, a low noise amplifier, a power amplifier, a mixer, a voltage controlled oscillator, a phase shifter, a resonator, a filter, an antenna, a modulator, a demodulator, etc. As the term is used herein, a radio frequency device includes a microwave device. As an example, a transistor 105 is shown as a component of the radio frequency device.

[0033] The SOI region 135 may have a first width W1 and a second width W2. In some embodiments, the first width W1 and the second width W2 are each in a range of about 100 μm to about 1000 μm. In some embodiments, the area of ​​the SOI region 135 is about 0.01 mm 2 To about 1mm 2 In some embodiments, the IC device 100 includes a plurality of SOI regions 135 .

[0034] Figure 2A and Figure 2B Provides cross-sectional views, Figure 2C A plan view of an IC device 200 is provided, which is another example of the present disclosure. The IC device 200 is similar to Figure 1A-Figure 1C The IC device 100 is similar to the IC device 200 except that the IC device 200 has an STI structure 221 having the same depth and composition as the dielectric via 111. The STI structure 221 can be produced by the same process as producing the dielectric via 111. The dielectric via 111 can provide an STI structure in the SOI region 135. On the other hand, the SOI region 135 and the logic region 131 can include other STI structures that are shallower than the dielectric via 111 and can include other types of isolation structures. The shallow STI structure may be narrower than the dielectric via 111 and therefore may occupy less area.

[0035] Figure 3A and Figure 3B Provides cross-sectional views, Figure 3C A plan view of an IC device 300 is provided, which is another example of the present disclosure. The IC device 300 is similar to Figure 2A-2C The IC device 200 is different in that the IC device 300 has a structure deeper than the STI structure 221 and also deeper than the STI structure 221. Figure 1A-Figure 1C The dielectric via 111 of the IC device 100 is deeper than the dielectric via 311. In some embodiments, the depth of the dielectric via 311 is equal to or greater than the thickness of the bulk semiconductor layer 149. Making the dielectric via 311 deeper and / or wider facilitates the removal of sacrificial material to leave the cavity 103.

[0036] Etching openings for dielectric vias 311 may overlap etching trenches for STI structures 221. Filling openings to form dielectric vias 311 may be performed simultaneously with filling trenches for STI structures 221. Thus, dielectric vias 311 and STI structures 221 may have the same composition.

[0037] Figure 4A and Figure 4B A cross-sectional view of an IC device 400 is provided. Figure 4C A plan view is provided, which is another example of the present disclosure. IC device 400 is similar to Figure 1A-Figure 1C The IC device 100 is different in that the IC device 400 has an insulating layer 413 completely filled with a dielectric. Figure 1A-1B The insulating layer 113 including the cavity 103 provides the highest degree of insulation and the lowest parasitic capacitance, but when the variability introduced by the manufacturing process is taken into account, the insulating layer 413 filled with a dielectric can provide more stable performance for the device.

[0038] Figure 5A and Figure 5B A cross-sectional view of an IC device 500 is provided. Figure 5C A plan view is provided, which is another example of the present disclosure. IC device 500 is similar to Figure 1A-Figure 1C The IC device 100 of FIG. 5 is different from the IC device 500 in that the dielectric vias 111 are limited to the periphery of the SOI region 135. The dielectric vias 111 fill the openings used to etch the sacrificial layer to form the insulating layer 113. Having some of these openings in the center of the SOI region 135 can help remove the sacrificial layer, however, if these openings can be limited to the periphery of the SOI region 135, so that the dielectric vias 111 are also limited to the periphery of the SOI region 135, more area is reserved for devices within the SOI region 135.

[0039] Fig. 6A and Figure 6B A cross-sectional view of an IC device 600 is provided. Figure 6C A plan view is provided, which is another example of the present disclosure. IC device 600 is similar to Figure 1A-Figure 1C The IC device 100 is different in that the polycrystalline structure 110 does not exist in the IC device 600 (see Figure 1B-Figure 1C ). The polycrystalline structure 110 generally does not affect device performance, but if there is some concern about the polycrystalline structure, the polycrystalline structure can be eliminated through appropriate processing.

[0040] Figure 7-Figure 16 A series of cross-sectional views 700-1600 are provided showing an IC device at various stages of fabrication according to the process of the present disclosure. Figure 7-Figure 16 The description is about a series of actions, but it should be understood that in some cases, the order of the actions may be changed and that the series of actions are applicable to structures other than the structure shown. In some embodiments, some of these actions can be omitted in whole or in part. In addition, Figure 7-Figure 16 It is about a series of actions, and it should be understood that Figure 7-Figure 16 The structure shown in is not limited to the manufacturing method but can be independently used as a structure separate from the method.

[0041] like Figure 7 As shown in the cross-sectional view 700 of FIG. 1 , the method may start by forming a series of layers above the semiconductor body 141. These layers may include an undoped semiconductor layer 145, a sacrificial layer 701, an upper semiconductor layer 109, and a stop layer 703. Each of the undoped semiconductor layer 145, the sacrificial layer 701, and the upper semiconductor layer 109 is formed by an epitaxial growth process, etc. The stop layer 703 may include one or more layers formed by oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc., or any other suitable process.

[0042] The semiconductor body 141 is a bulk semiconductor substrate. The semiconductor body 141 can be silicon (Si), a III-V semiconductor (e.g., GaAs), or some other binary semiconductor, ternary semiconductor (e.g., AlGaAs), a higher-order semiconductor, etc., or any other suitable semiconductor. In some embodiments, the semiconductor body 141 is silicon (Si), etc. In some embodiments, the semiconductor body 141 is a high-resistivity substrate. A high-resistivity substrate has fewer free charge carriers than a conventional substrate and reduces parasitic capacitance that may affect radio frequency devices. In some embodiments, the semiconductor body 141 is a conventional substrate (not high-resistivity). Conventional substrates are cheaper than high-resistivity substrates. An insulating layer 113 (see Figure 1A-1B ) can reduce parasitic capacitance to a level that eliminates the need for a high resistivity substrate. In some embodiments, the semiconductor body 141 is lightly P-doped. Light P-doping can facilitate grounding of the semiconductor body 141.

[0043] The undoped semiconductor layer 145 is optional. It can be a semiconductor of the same type as the semiconductor body 141, but substantially free of or completely free of dopants. Because it is undoped, the undoped semiconductor layer 145 has a lower concentration of crystalline source particles than the semiconductor body 141. Crystalline source particles with such a lower concentration reduce leakage current. In some embodiments, the thickness of the undoped semiconductor layer 145 is in a range from about 0.5 μm to about 10 μm. In some embodiments, the thickness of the undoped semiconductor layer 145 is in a range from about 0.1 μm to about 3 μm, for example about 2 μm. If the thickness is too low, the layer may be etched through in the logic region 131 during subsequent processes. If the layer is too thick, the processing time may be excessively increased.

[0044] The sacrificial layer 701 may be any epitaxially grown material that supports epitaxial growth of the upper semiconductor layer 109 as a single crystalline layer and has a higher etching sensitivity than the upper semiconductor layer 108 with respect to a suitable etchant. In some embodiments, the upper semiconductor layer 109 is a heavily doped semiconductor layer. In some embodiments, the dopant concentration is at least about 1×10 18 Atom / cm 3 In some embodiments, the dopant concentration is at least about 1×10 19 atoms / cm 3 In some embodiments, the dopant is a P-type dopant. Examples of P-type dopants include boron (B), gallium (Ga), aluminum (Al), indium (In), etc. In some embodiments, the P-type dopant is boron (B). The thickness of the sacrificial layer 701 is relative to the insulating layer 113 (see Figure 1A to Figure 1B). In some embodiments, the thickness of the sacrificial layer 701 is in the range of about 1 μm to about 5 μm. In some embodiments, the thickness of the sacrificial layer 701 is in the range of about 1.5 μm to about 3 μm.

[0045] The upper semiconductor layer 109 can be silicon (Si), a III-V semiconductor (e.g., GaAs), or some other binary semiconductor, ternary semiconductor (e.g., AlGaAs), more elemental semiconductor, etc., or any other suitable semiconductor. In some embodiments, the upper semiconductor layer 109 is silicon (Si), etc. In some embodiments, the upper semiconductor layer 109 is the same type of semiconductor as the semiconductor body 141. In some embodiments, the upper semiconductor layer 109 is lightly P-doped. In some embodiments, the upper semiconductor layer 109 is formed to a thickness in the range of about 0.5 μm to about 5 μm. In some embodiments, the upper semiconductor layer 109 is formed to a thickness in the range of about 1 μm to about 2 μm. The upper semiconductor layer 109 can be thinned during processing, so the deposited thickness can be greater than the final thickness for the layer.

[0046] Stop layer 703 provides an etch stop layer that can be removed during subsequent processing. Since this layer will be removed during subsequent processing, its composition may vary greatly. In some embodiments, stop layer 703 is a dielectric. Examples of suitable dielectrics include silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), combinations thereof, and the like. In some embodiments, stop layer 703 is silicon dioxide (SiO2) and the like. In some embodiments, stop layer 703 is formed from a tetraethyl orthosilicate (TEOS) precursor by plasma enhanced chemical vapor deposition (PECVD). Silicon dioxide (SiO2) deposited by TEOS by PECVD has well-defined physical properties. In some embodiments, the thickness of stop layer 703 is in the range of about 50 nm to about 1 μm.

[0047] like Figure 8As shown in the cross-sectional view 800 of , a mask 801 may be formed to cover the SOI region 135 while removing the stop layer 703, the upper semiconductor layer 109, and the sacrificial layer 701 from the logic region 131 using an etching process. The mask 801 may be a photoresist patterned by photolithography or the like, or any other type of mask patterned by any suitable process. The etching process may include dry etching, wet etching, or a combination thereof. In some embodiments, the etching process includes plasma etching or the like. The etching process may extend a depth D1 below the sacrificial layer 701. In some embodiments, the depth D1 is approximately halfway through the undoped semiconductor layer 145. In some embodiments, the depth D1 is about 100 nm to about 2 μm. In some embodiments, the depth D1 is about 500 nm to about 1500 nm. The contrast between the sacrificial layer 701 and the undoped semiconductor layer 145 may not be apparent during the etching process. Allowing the etching to proceed to a certain distance into the undoped semiconductor layer 145 ensures that the etching has extended through the sacrificial layer 701 so that it is completely removed from the logic region 131. After the etching process, the mask 801 may be stripped.

[0048] like Fig. 9 As shown in the cross-sectional view 900, Figure 8 A bulk semiconductor layer 149 is epitaxially grown on the structure shown in the cross-sectional view 800 of . The bulk semiconductor layer 149 is grown on the undoped semiconductor layer 145 of the logic region 131 and on the sides of the SOI region 135, but is typically not grown on the stop layer 703. The bulk semiconductor layer 149 is typically a single crystal structure, however, the polycrystalline structure 110 may be grown from the sides of the SOI region 135. The bulk semiconductor layer 149 is grown to a thickness at least approximately equal to the combined thickness of the upper semiconductor layer 109, the sacrificial layer 701, and the depth D1, so that the upper surface 905 of the bulk semiconductor layer 149 is at or above the upper surface 903 of the upper semiconductor layer 109. The polycrystalline structure 110 may form a protrusion 901, which extends higher, and specifically may extend above the stop layer 703.

[0049] The bulk semiconductor layer 149 can be silicon (Si), a III-V semiconductor (e.g., GaAs), or some other binary semiconductor, ternary semiconductor (e.g., AlGaAs), more semiconductors, etc., or any other suitable semiconductor. In some embodiments, the bulk semiconductor layer 149 is silicon (Si), etc. In some embodiments, the bulk semiconductor layer 149 is the same type of semiconductor as the upper semiconductor layer 109. In some embodiments, the bulk semiconductor layer 149 is silicon (Si), etc. In some embodiments, the bulk semiconductor layer 149 is lightly P-doped.

[0050] like Fig.10 As shown in the cross-sectional view 1000, it can be Fig. 9A planarization film 1001 is formed on the structure shown in the cross-sectional view 900 of FIG. 1 to facilitate planarization of the structure. The planarization film 1001 can be formed by any suitable process. In some embodiments, the planarization film 1001 is formed from a liquid precursor using a spin coating process. In some embodiments, the planarization film 1001 is a photoresist material or a bottom anti-reflective coating (BARC) material. In some embodiments, the planarization film 1001 is an organic polymer or the like.

[0051] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , the surface 1101 is recessed by etching, and the etching stops on the stop layer 703. The etching can remove the planarization film 1001. The etching process can include wet etching, dry etching, or a combination of wet etching and dry etching. In some embodiments, the etching process is plasma etching, etc.

[0052] like Fig.12 As shown in the cross-sectional view 1200, the stop layer 703 is removed (see Fig.11 ), and planarizes the surface 1101. In some embodiments, the stop layer 703 is removed by wet etching before chemical mechanical polishing (CMP). Removing the stop layer 703 before CMP can result in a relatively flatter surface and less thinning of the upper semiconductor layer 109 than when the stop layer 703 is removed only by CMP. This can help control the final thickness of the upper semiconductor layer 109. In some embodiments, although the protrusion 901 (see Fig. 9 ) is removed, but a portion of the polycrystalline structure 110 remains after planarization. In some embodiments, the planarization is further continued so that the polycrystalline structure 110 is completely removed.

[0053] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a photoresist mask 1307 may be formed and used to etch the trench 1305 in the logic region 131 and the opening 1301 in and at the edge of the SOI region 135. The etching process may be a dry etching such as plasma etching. After the etching is completed, the photoresist mask 1307 may be stripped.

[0054] Optionally, a hard mask 1303 is also formed and patterned. The hard mask 1303 may include one or more layers of dielectric materials, such as silicon dioxide (SiO2), silicon nitride (SiN), etc. In some embodiments, the hard mask 1303 includes a silicon dioxide (SiO2) layer and a silicon nitride (SiN) layer, which helps to form an isolation structure in the logic area 131. In some embodiments, the total thickness of the hard mask 1303 is in the range of about 20nm to about 200nm. In some embodiments, the total thickness of the hard mask 1303 is in the range of about 50nm to about 100nm. In some embodiments, the hard mask 1303 includes a silicon dioxide (SiO2) layer having a thickness of about 20nm or less and a silicon nitride (SiN) layer having a thickness of about 80nm or more.

[0055] The trenches 1305 may have a desired pattern for the STI structure in the logic region 131. The openings 1301 may have any pattern suitable for providing access to the sacrificial layer 701. Figure 1C , Figure 5C The openings 1301 may have the pattern of dielectric vias 111 as shown, or any other suitable pattern. In some embodiments, the openings 1301 include openings within the SOI region 135. In some embodiments, the openings 1301 are confined to the periphery of the SOI region 135.

[0056] like Fig.14 As shown in the cross-sectional view 1400, the sacrificial layer 701 can be etched through the opening 1301 (see Fig.13 ), thereby leaving the cavity 103. The opening 1301 does not completely surround the SOI region 135, so that the structure in the interior of the SOI region 135 is not separated. The etching process can be a wet etching. In some embodiments, the wet etching uses a mixture of HNA (HNA is hydrofluoric acid (HF)), nitric acid (HNO3) and acetic acid (CH3COOH). The ratio of these acids can be selected to provide an etching selectivity of about 100:1, thereby removing the sacrificial layer 701 without significantly corroding the upper semiconductor layer 109.

[0057] like Fig.15As shown in the cross-sectional view 1500 of , a dielectric 1501 can be deposited to seal or fill the opening 1301 and fill the trench 1305. The dielectric 1501 can be any suitable dielectric. In some embodiments, the dielectric 1501 is silicon dioxide (SiO2) or the like. The dielectric 1501 can be deposited by CVD, PVD, ALD, or the like, or any other suitable process. In some embodiments, the dielectric 1501 is silicon dioxide (SiO2) deposited using high-density plasma CVD (HDP-CVD) that combines plasma-enhanced CVD (PECVD) and sputtering. HDP-CVD can provide good gap fill for this application. In some embodiments, the deposition process is performed in such a way that the dielectric 1501 forms a dielectric liner 107 and leaves a cavity 103. In some other embodiments, the process is performed in such a way that the dielectric 1501 fills the cavity 103 (see Figure 4A-4B ). The deposition process conditions can be adjusted to select between these results.

[0058] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , a planarization process such as CVD may be performed to remove excess dielectric 1501 and reduce the upper semiconductor layer 109 to a desired thickness. The dielectric 1501 remaining in the opening 1301 forms a dielectric through hole 111, and the dielectric 150 remaining in the trench 1305 forms an STI structure 221. The planarization process may leave some polycrystalline structure 110 (not present in the STI structure 221). Fig.16 in the plane, but see e.g. Fig.12 ), or the polycrystalline structure 110 may be removed. In some embodiments, the final thickness of the upper semiconductor layer 109 is in the range of about 100 nm to about 200 nm. In some embodiments, the final thickness of the upper semiconductor layer 109 is in the range of about 50 nm to about 100 nm, for example, about 75 nm. Additional processing may form logic devices in the logic region 131, form radio frequency devices in the SOI region 135, and form metal interconnect structures (not shown) over the SOI region 135 and the logic region 131.

[0059] Figure 17-Figure 19 A series of cross-sectional views 1700-1900 are provided illustrating the above process variations. Fig.16 This variation allows the STI structures 221 to be shallower than the dielectric vias 111 while still having extensive overlap between the processes used to form these structures.

[0060] The change began Fig.13 The changes shown in the cross-sectional view 1300. Fig.17As shown in the cross-sectional view 1700 of FIG. 1 , the photoresist mask 1307 may initially have only openings 1701 corresponding to the desired locations of the openings 1301, and only a partial etching of the openings 1301 may be performed. Fig.18 As shown in the cross-sectional view 1800 of FIG. 1 , additional openings 1801 may then be added to the photoresist mask 1307. Fig.19 As shown in the cross-sectional view 1900 of FIG. 1900 , further etching is then performed. Further etching completes the formation of the opening 1301 and simultaneously forms the trench 1305. The trench 1305 is then filled to provide the STI structure 121 (see FIG. 1901 ). Figure 1A to Figure 1B ), while sealing the opening 1301. Some of the trenches 1305 may be in the SOI region 135, so that some of the STI structures 121 are formed in the SOI region 135. Figure 14-16 As shown in cross-sectional views 1400-1600, additional processing has been performed.

[0061] Fig. 20 A flow chart of a method 2000 according to some embodiments of forming an IC device is provided. Although method 2000 is shown and described as a series of actions or events, it should be understood that the order of such actions or events shown should not be interpreted in a limiting sense. For example, some actions may occur in different orders and / or simultaneously with other actions or events other than those shown and / or described herein. In addition, not all illustrated actions may be required to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0062] The method 2000 starts with an optional step (action 2001) of epitaxially growing an undoped semiconductor layer on a semiconductor body. The method 2000 continues with action 2003 of sequentially forming a sacrificial layer, an upper semiconductor layer, and a stop layer. Figure 7 An example of these processes is provided in cross-sectional view 700 .

[0063] Action 2005 is to mask the SOI region and etch in the logic region to remove the layer formed by action 2003 . Figure 8 The cross-sectional view 800 provides an example.

[0064] Action 2007 forms a bulk epitaxial layer in the logic region. The stop layer may prevent such growth in the SOI region. The bulk epitaxial layer fills the space etched by action 2005. In some embodiments, polycrystalline semiconductor growth occurs at the edge of the SOI region during this process. Fig. 9 An example is provided by cross-sectional view 900 .

[0065] Action 2009 is a planarization process. The process may include actions such as applying a planarization film, dry etching, wet etching, chemical mechanical polishing, or a combination thereof. The stop layer may facilitate control of the process. The stop layer may also be removed during the planarization process. Figure 10-12 An example is provided by cross-sectional views 1000-1200.

[0066] Action 2011 is to form a mask and use the mask to etch openings through the upper semiconductor layer to provide access to the sacrificial layer located therebelow. Fig.13 An example is provided in the cross-sectional view 1300 of FIG. In some embodiments, the opening extends through the sacrificial layer. In some embodiments, the opening extends about halfway or further into the undoped semiconductor layer. Making the opening deeper and wider facilitates subsequent etching processes. In some embodiments, the opening includes an opening that passes through the interior of the SOI region. Figure 1C An example is provided by the IC device 100, in which the location of the dielectric vias 111 corresponds to the location of the openings. In some embodiments, the openings are confined to the periphery of the SOI region. Figure 5C The IC device 500 provides an example.

[0067] Action 2013 etches away the sacrificial layer below the upper semiconductor layer. In some embodiments, this is a wet etch using HNO. Fig.14 An example is provided by cross-sectional view 1400 .

[0068] Act 2015 is sealing the opening with a dielectric. In some embodiments, sealing the opening fills the opening with a dielectric, thereby creating a dielectric via extending through the upper semiconductor layer. In some embodiments, sealing the opening leaves a cavity below the upper semiconductor layer. Figure 15-16 Examples are provided in cross-sectional views 1500-1600 of FIG. 1. In some embodiments, sealing the opening is to fill the cavity with a dielectric. Figure 4A-4C The IC device 400 provides an example.

[0069] Fig.21 A flow chart of a method 2100 is provided, which is a variation of the above-described method 2000. The method 2100 allows STI structures that are shallower than dielectric vias to be formed simultaneously with the dielectric vias. Figures 1A to 1C The IC device 100 and FIG. 3A to FIG. 3C IC device 300 provides an example of a device that can be fabricated using this variation.

[0070] The changes begin at act 2101 where a mask is formed having openings corresponding to the holes for accessing the sacrificial layer and the holes are partially etched using the mask. Fig.17An example is provided by cross-sectional view 1700 of . Changes continue to act 2103, which adds additional openings to the mask corresponding to the desired locations of the STI structures. Fig.18 An example is provided in cross-sectional view 1800 of FIG. 2105 . Action 2105 is to perform the opening etch while etching the trench. Fig.19 An example is provided by cross-sectional view 1900 of . Next is action 2013, which etches the sacrificial layer through the opening, just as in method 2000. Action 2107 of method 2100 corresponds to action 2015 of method 2000, except that in action 2107, the trench is filled to form an STI structure while sealing the opening.

[0071] Some aspects of the present disclosure relate to a hybrid SOI substrate, comprising: a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region; an upper semiconductor layer located in the first region, wherein the upper semiconductor layer is separated from the semiconductor substrate by a cavity; and a bulk semiconductor layer located above the semiconductor substrate in the second region, wherein the bulk semiconductor layer extends from a height below the cavity to a height above an upper surface of the upper semiconductor layer. In some embodiments, a dielectric via extends through a thickness of the upper semiconductor layer. The dielectric via is continuous with and has the same composition as a dielectric lining the cavity.

[0072] Some aspects of the present disclosure relate to an integrated circuit device including a semiconductor substrate. The semiconductor substrate has a first region and a second region. An upper semiconductor layer is located above the first region. An insulating layer is located between the upper semiconductor layer and the semiconductor substrate in the first region. There is a bulk semiconductor layer located above the semiconductor substrate in the second region. The bulk semiconductor layer is at a height equal to that of the insulating layer and the upper semiconductor layer. A polycrystalline semiconductor structure is located between the upper semiconductor layer and the bulk semiconductor layer on one side of the first region. In some embodiments, the semiconductor substrate includes a semiconductor body and an undoped semiconductor layer disposed above the semiconductor body. The undoped semiconductor layer has a lower concentration of crystal source particles than the semiconductor body.

[0073] Some aspects of the present disclosure relate to a method of manufacturing an integrated circuit device. The method includes forming a sacrificial layer above a semiconductor body including a first region and a second region, and epitaxially growing an upper semiconductor layer above the sacrificial layer. A mask is formed above the first region, and while masking the first region, etching through the upper semiconductor layer and the sacrificial layer in the second region. A bulk semiconductor layer is then epitaxially grown in the second region. An opening is then etched, wherein the sacrificial layer is exposed through the opening. The sacrificial layer is etched through the opening to form a cavity below the upper semiconductor layer in the first region. The opening is sealed with a dielectric.

[0074] In some embodiments, the method further comprises planarizing so that the bulk semiconductor layer in the second region is coplanar with the upper semiconductor layer in the first region. Planarizing may be performed prior to etching to form the cavity. In some embodiments, the semiconductor body is a high resistivity substrate. In some embodiments, the method further comprises epitaxially growing an undoped semiconductor layer above the semiconductor body prior to forming the sacrificial layer. Etching through the upper semiconductor layer and the sacrificial layer in the second region comprises etching into the undoped semiconductor layer.

[0075] In some embodiments, when the bulk semiconductor layer is epitaxially grown in the second region, a polycrystalline semiconductor is grown from an edge of the first region. In some embodiments, the polycrystalline semiconductor forms a protrusion that is higher than the mask, and the method further includes a planarization process, the planarization process including forming a sacrificial coating from a liquid precursor, etching to recess the sacrificial coating, and chemical mechanical polishing. In some embodiments, planarization completely removes the polycrystalline semiconductor.

[0076] In some embodiments, forming the sacrificial layer comprises epitaxially growing the sacrificial layer, and the sacrificial layer is heavily doped. In some embodiments, etching the sacrificial layer comprises etching with a mixture of hydrofluoric acid, acetic acid, and nitric acid. In some embodiments, the opening is located at the periphery of the first zone. In some embodiments, etching the opening comprises: forming a second mask; forming a first opening in the second mask in the first zone; forming a second opening in the second mask in the second zone; and etching through the first opening to form the opening, and etching through the second opening to form a trench. In some embodiments, the trench is filled to provide a shallow trench isolation structure in the second zone. In some embodiments, the process of sealing the opening fills the trench. In some embodiments, the method further comprises etching through the first opening before forming the second opening, whereby the opening is deeper than the trench. In some embodiments, the process of sealing the opening with a dielectric fills the cavity with a dielectric.

[0077] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A hybrid semiconductor-on-insulator substrate, comprising: A semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region; an upper semiconductor layer located in the first region, wherein the upper semiconductor layer is separated from the semiconductor substrate by a cavity; and A bulk semiconductor layer is located above the semiconductor substrate in the second region, wherein the bulk semiconductor layer extends from a height below the cavity to a height of an upper surface of the upper semiconductor layer.

2. The hybrid semiconductor-on-insulator substrate of claim 1 , further comprising a dielectric via extending through a thickness of the upper semiconductor layer, wherein The dielectric via is continuous with and has the same composition as the dielectric lining the cavity.

3. An integrated circuit device comprising: A semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region; an upper semiconductor layer located above the first region; an insulating layer located between the upper semiconductor layer and the semiconductor substrate in the first region; a bulk semiconductor layer located above the semiconductor substrate in the second region, wherein the bulk semiconductor layer is at a height equal to that of the insulating layer and the upper semiconductor layer; and A polycrystalline semiconductor structure is located between the upper semiconductor layer and the bulk semiconductor layer on one side of the first region.

4. The integrated circuit device according to claim 3, wherein: The semiconductor substrate includes a semiconductor body and an undoped semiconductor layer disposed above the semiconductor body; and The undoped semiconductor layer has a lower concentration of crystal source particles than the semiconductor body.

5. A method for manufacturing an integrated circuit device, the method comprising: forming a sacrificial layer over the semiconductor body including the first region and the second region; epitaxially growing an upper semiconductor layer above the sacrificial layer; forming a mask over the first region; etching through the upper semiconductor layer and the sacrificial layer in the second region while masking the first region; epitaxially growing a bulk semiconductor layer in the second region; etching an opening, wherein the sacrificial layer is exposed through the opening; etching the sacrificial layer through the opening to form a cavity below the upper semiconductor layer in the first region; and The opening is sealed with a dielectric. 6 . The method of claim 5 , further comprising planarizing such that the bulk semiconductor layer in the second region is coplanar with the upper semiconductor layer in the first region. 7 . The method of claim 5 , further comprising epitaxially growing an undoped semiconductor layer over the semiconductor body before forming the sacrificial layer. 8 . The method of claim 7 , etching through the upper semiconductor layer and the sacrificial layer in the second region comprises etching into the undoped semiconductor layer.

9. The method according to claim 5, wherein: When the bulk semiconductor layer is epitaxially grown in the second region, a polycrystalline semiconductor is grown from an edge of the first region.

10. The method according to claim 5, wherein: Forming the sacrificial layer includes epitaxially growing the sacrificial layer, and the sacrificial layer is heavily doped.

Images