Semiconductor device structure and forming method thereof

Abstract

Semiconductor device structures and methods of forming the same are described. The structure includes a first semiconductor layer disposed over a substrate, the first semiconductor layer having an edge portion and a central portion, and a height of the central portion is substantially greater than a height of the edge portion. The structure further includes a dielectric spacer disposed below and in contact with an edge portion of the first semiconductor layer; a gate dielectric layer surrounding a central portion of the first semiconductor layer; and a gate electrode layer disposed on the gate dielectric layer surrounding a central portion of the first semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced successive generations of ICs, each of which is smaller and more complex than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per unit of chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This process of downscaling generally provides benefits by increasing production efficiency and reducing associated costs. This downscaling presents new challenges.

[0003] In pursuit of higher device density, higher performance and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field effect transistors (FETs), including nanosheet FETs. In nanosheet FETs, all side surfaces of the channel are surrounded by gate electrodes, which allows for more complete depletion in the channel and produces less short channel effects and better gate control. As transistor dimensions continue to shrink, further improvements in nanosheet FETs are needed. Summary of the invention

[0004] In one aspect, an embodiment of the present application provides a semiconductor device structure, comprising: a first semiconductor layer, disposed on a substrate, wherein the first semiconductor layer has an edge portion and a center portion, and the height of the center portion is greater than the height of the edge portion; a dielectric spacer, disposed below the edge portion of the first semiconductor layer and in contact with the edge portion of the first semiconductor layer; a gate dielectric layer, surrounding the center portion of the first semiconductor layer; and a gate electrode layer, disposed on the gate dielectric layer surrounding the center portion of the first semiconductor layer.

[0005] On the other hand, an embodiment of the present application provides a semiconductor device structure, comprising: a first plurality of semiconductor layers, arranged in a first region of a substrate, wherein the bottom semiconductor layer of the first plurality of semiconductor layers has a first height; a second plurality of semiconductor layers, arranged in a second region of the substrate, wherein the height of each semiconductor layer in the second plurality of semiconductor layers is less than the first height; a first gate electrode layer, surrounding a portion of the first plurality of semiconductor layers; and a second gate electrode layer, surrounding a portion of the second plurality of semiconductor layers.

[0006] In another aspect, an embodiment of the present application provides a method, comprising: forming a first fin structure and a second fin structure, wherein the first fin structure includes a first plurality of semiconductor layers and the second fin structure includes a second plurality of semiconductor layers; forming a mask layer around the second plurality of semiconductor layers, wherein the first plurality of semiconductor layers are exposed; increasing the size of each semiconductor layer in the first plurality of semiconductor layers; removing the mask layer; depositing a gate dielectric layer around the first plurality of semiconductor layers and the second plurality of semiconductor layers; forming a first gate electrode layer around the first plurality of semiconductor layers; and forming a second gate electrode layer around the second plurality of semiconductor layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood through the following detailed description. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1-6 is a perspective view of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0009] Fig. 7A , Figure 7B and Figure 7C Along the Figure 6 A cross-sectional side view of the semiconductor device structure taken along lines AA, BB, and CC.

[0010] Figure 8A-13A According to some embodiments, Figure 6 Cross-sectional side views of various stages in the manufacture of a semiconductor device structure taken along line AA.

[0011] Figure 8B-13B According to some embodiments, Figure 6 Cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line BB.

[0012] Figure 8C-13C According to some embodiments, Figure 6 Cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line CC.

[0013] Figure 14-24 According to some embodiments, Figure 6 Cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line BB.

[0014] Figures 25A-25D According to some embodiments, Figure 6 A perspective view of one of the various stages in the manufacture of a semiconductor device structure taken along lines AA, BB, CC and DD.

[0015] Figure 26-34 According to an alternative embodiment along Figure 6 Cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line BB.

[0016] Figure 35-40 According to an alternative embodiment along Figure 6 Cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line BB. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly in contact with each other, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "on," "top," "upper," etc. may be used herein to describe the relationship of one element or feature to another (one or more) elements or (one or more) features as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0019] Although embodiments of the present disclosure are discussed with respect to nanostructured channel FETs (e.g., gate-around (GAA) FETs, such as horizontal gate-around (HGAA) FETs or vertical gate-around (VGAA) FETs), embodiments of some aspects of the present disclosure may be used for other processes and / or other devices, such as planar FETs, Fin-FETs, and other suitable devices. It will be readily understood by those of ordinary skill in the art that other modifications that may be made are contemplated within the scope of the present disclosure. In the case of a gate-around (GAA) transistor structure, the GAA transistor structure may be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multiple patterning processes) may be used to pattern the structure. In general, double patterning or multiple patterning processes combine photolithography processes with self-alignment processes, thereby allowing patterns to be created with, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

[0020] Figure 1-25D An exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure is shown. It is to be understood that additional embodiments of the method may be Figure 1-25D Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated. The order of operations / processes is not limited and may be interchanged.

[0021] Figure 1-6 1 is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a single crystal semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide antimony (GaAsSb) and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer.

[0022] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having P-type or N-type conductivity). Depending on the circuit design, the dopant may be, for example, boron for a P-type field effect transistor (PFET) and phosphorus for an N-type field effect transistor (NFET).

[0023] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanosheet channels in multi-gate devices, such as nanosheet channel FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, any of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0024] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of each layer of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0025] The first semiconductor layer 106 or a portion thereof may form a nanosheet or (one or more) nanostructured channels of the semiconductor device structure 100 in a subsequent manufacturing stage. The term "nanosheet" is used herein to refer to any material portion having nanometer-scale, even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Therefore, the term refers to an elongated material portion of a circular and substantially circular cross section, and a beam-shaped or strip-shaped material portion including, for example, a cylindrical or substantially rectangular cross section. The (one or more) nanosheet channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanosheet transistor. The nanosheet transistor may be referred to as a nanowire transistor, a gate-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0026] Each first semiconductor layer 106 may have a thickness in a range between about 5 nm and about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in a range between about 2 nm and about 50 nm. Figure 1 The alternating arrangement shown is for illustrative purposes and is not intended to limit the scope beyond the specific description in the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0027] exist Figure 2 In the embodiment of the present invention, the fin structure 112 is formed by the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed by the substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using multiple patterning operations including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, patterning the photoresist layer to form a masking element may be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 in unprotected areas through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 may be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0028] exist Figure 3In the embodiment, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trench 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed so that the top of the fin structure 112 is exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-K dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0029] exist Figure 4 In the embodiment of the present invention, the insulating material 118 is recessed to form the isolation region 120. The recess of the insulating material 118 exposes a portion of the fin structure 112, such as the semiconductor layer stack 104. The recess of the insulating material 118 reveals the trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with or below the surface of the second semiconductor layer 108 that contacts the well portion 116 formed by the substrate 101.

[0030] exist Figure 5 In the embodiment of the present invention, one or more sacrificial gate structures 130 are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Gate spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 may be formed by conformally depositing one or more layers for the gate spacers 138 and anisotropically etching the one or more layers. In some embodiments, the gate spacers 138 are also formed on the sidewalls of the exposed portions of the fin structure 112. Although one sacrificial gate structure 130 is shown, two or more sacrificial gate structures 130 may be arranged along the X-direction in some embodiments.

[0031] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0032] The portion of fin structure 112 covered by sacrificial gate electrode layer 134 of sacrificial gate structure 130 serves as a channel region of semiconductor device structure 100. Fin structure 112 partially exposed on opposite sides of sacrificial gate structure 130 defines source / drain (S / D) regions of semiconductor device structure 100.

[0033] exist Figure 6 In the embodiment, portions of the fin structure 112 in the S / D region (e.g., regions on the opposite side of the sacrificial gate structure 130) are recessed downward below the top surface of the isolation region 120 (or the insulating material 118) by removing portions of the fin structure 112 that are not covered by the sacrificial gate structure 130. The recessing of these portions of the fin structure 112 may be accomplished by an etching process (either an isotropic or anisotropic etching process), or may further be accomplished by having selectivity with respect to one or more crystal planes of the substrate 101. The etching process may be a dry etch, such as RIE, NBE, etc., or a wet etch, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant. Due to the recessing of these portions of the fin structure 112, trenches 119 are formed in the S / D region.

[0034] Fig. 7A , Figure 7B and Figure 7C Along the Figure 6 1 is a cross-sectional side view of the semiconductor device structure 100 taken along lines AA, BB, and CC. Figure 8A-13A According to some embodiments, Figure 6 1 is a cross-sectional side view of various stages of fabricating the semiconductor device structure 100 taken along line AA. Figure 8B-13B According to some embodiments, Figure 6 1 is a cross-sectional side view of various stages of fabricating the semiconductor device structure 100 taken along line BB. Figure 8C-13C According to some embodiments, Figure 61 and 1 . The cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 are taken along the line CC of FIG. 1 . The line AA is located in the plane of the fin structure 112 along the X direction. The line BB is located in a plane perpendicular to the line AA and is located in the sacrificial gate structure 130. The line CC is located in a plane perpendicular to the line AA along the Y direction and is located in the source / drain region (e.g., Fig. 9A The epitaxial S / D features 146 shown in FIG.

[0035] exist Figures 8A-8C In the embodiment of the present invention, an edge portion of each second semiconductor layer 108 of the semiconductor layer stack 104 is horizontally removed along the X direction. The edge portion of the second semiconductor layer 108 is removed to form a cavity. In some embodiments, a portion of the second semiconductor layer 108 is removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0036] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 can be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacer 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process such as ALD, and then performing anisotropic etching to remove the portion of the conformal dielectric layer except the dielectric spacer 144. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is wrapped between the dielectric spacers 144 along the X direction.

[0037] exist Figures 9A-9C In the present disclosure, epitaxial source / drain (S / D) features 146 are formed in the S / D region. In the present disclosure, source features and drain features are used interchangeably, and their structures are substantially the same. In addition, (one or more) source / drain features may refer to the source or drain individually or collectively, depending on the context. For n-channel FETs, the epitaxial S / D features 146 may be made of one or more layers of Si, SiP, SiC, and SiCP, or for p-channel FETs, the epitaxial S / D features 146 may be made of Si, SiGe, Ge. For p-channel FETs, p-type dopants such as boron (B) may also be included in the epitaxial S / D features 146. The epitaxial S / D features 146 may be formed by an epitaxial growth method using CVD, ALD, or MBE.

[0038] Epitaxial S / D features 146 may grow vertically and horizontally to form facets, which may correspond to crystal planes of the material used for substrate 101. In some cases, epitaxial S / D features 146 of a fin structure may grow and merge with epitaxial S / D features 146 of an adjacent fin structure, such as Fig. 9C An example is shown.

[0039] exist Figures 10A-10C In the embodiment of the present invention, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the epitaxial S / D features 146. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material of the ILD layer 164 may include a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may also be used for the ILD layer 164. The ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 164 , the semiconductor device structure 100 may be thermally treated to anneal the ILD layer 164 .

[0040] exist Figures 11A-11C In the embodiment, after forming the ILD layer 164 , a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed.

[0041] exist Figures 12A-12C, the sacrificial gate structure 130 is removed. During the removal of the sacrificial gate structure 130, the ILD layer 164 protects the epitaxial S / D features 146. The sacrificial gate structure 130 may be removed using plasma dry etching and / or wet etching. For example, in the case where the sacrificial gate electrode layer 134 is polysilicon and the ILD layer 164 is silicon oxide, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer 134 without removing the dielectric material of the ILD layer 164, the CESL 162, and the gate spacers 138. The sacrificial gate dielectric layer 132 is then removed using plasma dry etching and / or wet etching. The removal of the sacrificial gate structure 130 (i.e., the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132) forms trenches 166 in the areas where the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 are removed. The trench 166 exposes the top and side surfaces of the semiconductor layer stack 104 (eg, the first semiconductor layer 106 and the second semiconductor layer 108 ).

[0042] exist Figures 13A-13C , the exposed second semiconductor layer 108 is removed. The removal of the second semiconductor layer 108 exposes the dielectric spacer 144 and the first semiconductor layer 106. In some embodiments, during the removal of the second semiconductor layer 108, a small amount (e.g., about 1 nm to about 2.5 nm in terms of thickness) of the first semiconductor layer 106 may be removed. The removal process may be any suitable etching process, such as dry etching, wet etching, or a combination thereof. The etching process may be a selective etching process that removes the second semiconductor layer 108 but does not remove the gate spacer 138, the CESL 162, the ILD layer 164, and the first semiconductor layer 106. As a result, an opening 151 is formed around the first semiconductor layer 106, and a portion of the first semiconductor layer 106 not covered by the dielectric spacer 144 is exposed to the opening 151.

[0043] Figure 14-24 According to some embodiments, Figure 6 Cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line BB. Figure 14-24 Also shown are the various stages of manufacturing Fig. 13B The portion 147 of the semiconductor device structure 100 is shown. The substrate 101 has a first region 153 and a second region 155. In some embodiments, the first region 153 is an n-type region and is used to form an n-type device, such as an NMOS transistor, such as an n-type field effect transistor (FET) (NFET), and the second region 155 is a p-type region and is used to form a p-type device, such as a PMOS transistor, such as a p-type FET (PFET). Although one first region 153 and one second region 155 are shown, the substrate 101 may include any desired number of such regions. Fig.14 As shown, the first semiconductor layer 106 in the first region 153 has a height H1 and a width W1, and the first semiconductor layer 106 in the second region 155 has a height H2 and a width W2. In some embodiments, the height H1 is substantially the same as the height H2, and the width W1 is substantially the same as the width W2.

[0044] like Fig.14 As shown, the mask layer 150 is formed to surround the exposed surface of the first semiconductor layer 106 (ie, the nanosheet channel) and is formed on the well portion 116 of the substrate 101. The mask layer 150 may also be formed on the ILD layer 164 ( Figures 13A-13C ). The mask layer 150 may include any suitable material having a different etching selectivity than the first semiconductor layer 106. In some embodiments, the mask layer 150 includes a dielectric material, such as SiO x 、AlO x or SiON x The mask layer 150 is formed by a conformal process such as an ALD process. Fig.14 As shown, in some embodiments, the mask layer 150 fills the opening 151 surrounding the first semiconductor layer 106 to prevent the subsequently formed photoresist 154 ( Fig.15 ) is formed in the opening 151, which may be difficult to remove. .

[0045] like Fig.15 As shown, a photoresist 154 is formed to cover a portion of the mask layer 150 formed around the first semiconductor layer 106 in the second region 155. Next, the exposed portion of the mask layer 150 is removed, as shown in FIG. Fig.16 As shown. The exposed portion of the mask layer 150 may be removed by any suitable process. In some embodiments, a selective etching process is performed to remove the exposed portion of the mask layer 150. The selective etching process may be a dry etching process or a wet etching process, and does not substantially affect the photoresist 154 and the first semiconductor layer 106. In some embodiments, in order to completely remove the exposed portion of the mask layer 150, the selective etching process may be performed for an extended period of time, and the size of the first semiconductor layer 106 in the first region 153 may be reduced by the selective etching process. After removing the exposed portion of the mask layer 150, the photoresist 154 is removed, as shown. Fig.17 The photoresist 154 may be removed by any suitable process. In some embodiments, the photoresist 154 may be removed by an ashing process that does not substantially affect the first semiconductor layer 106 and the mask layer 150 .

[0046] Next, if Fig.18As shown, the size of the first semiconductor layer 106 in the first region 153 is enlarged. In some embodiments, the size is enlarged by an epitaxial process or a thermal treatment. For example, a semiconductor material is epitaxially grown from the first semiconductor layer 106 in the first region 153. In some embodiments, the semiconductor material is the same as the material of the first semiconductor layer 106 located in the first region 153. For example, the first semiconductor layer 106 in the first region 153 includes silicon, and silicon is epitaxially grown from the first semiconductor layer 106 in the n-type region. The precursor in the epitaxial process may include a silicon-containing precursor, such as silane, disilane or other suitable precursors. In other words, the semiconductor material layer is formed to surround the exposed portion of each first semiconductor layer 106 located in the first region 153. Therefore, in some embodiments, each first semiconductor layer 106 in the first region 153 has a height H3 and a width W3. A height H3 of the first semiconductor layer 106 in the first region 153 is substantially greater than a height H2 of the first semiconductor layer 106 in the second region 155, and a width W3 of the first semiconductor layer 106 in the first region 153 is substantially greater than a height W2 of the first semiconductor layer 106 in the second region 155. Semiconductor material may also be grown on the well portion 116 in the first region 153. Therefore, in some embodiments, a distance D1 between a top surface of the well portion 116 in the first region 153 and a top surface of the insulating material 118 is substantially greater than a distance D2 between a top surface of the well portion 116 in the second region 155 and a top surface of the insulating material 118. Enlarging the size of the first semiconductor layer 106 and the well portion 116 located in the first region 153 is a selective process, and thus semiconductor material is not formed on the mask layer 150.

[0047] like Fig.18 As shown, in some embodiments, the size of each first semiconductor layer 106 in the first region 153 increases by substantially the same amount. As a result, each first semiconductor layer 106 in the first region 153 has a width W3 and a height H3. In some embodiments, the size of each first semiconductor layer 106 in the first region 153 increases by different amounts, such as Fig.19As shown. For example, a deposition process such as an epitaxial deposition process is performed to form a semiconductor material layer on the exposed surface of the first semiconductor layer 106 in the first region 153. During the deposition process, the top first semiconductor layer 106 in the first region 153 is exposed to a precursor before the bottom first semiconductor layer 106 in the first region 153. As a result of the deposition process, the topmost first semiconductor layer 106 in the first region 153 has a height H3 and a width W3, the middle first semiconductor layer 106 has a height H4 and a width W4, and the bottom first semiconductor layer 106 has a height H5 and a width W5. In some embodiments, the height H3 is substantially greater than the height H4, the height H4 is substantially greater than the height H5, and the width W3 is substantially greater than the width W4, and the width W4 is substantially greater than the width W5. In other words, the height and width of the first semiconductor layer 106 in the first region 153 decrease in a direction toward the well portion 116. In some embodiments, the width W5 and the height H5 are substantially greater than the width W2 and the height H2. In some embodiments, a small amount of semiconductor material or no semiconductor material is formed on the well portion 116 in the first region 153, and the distance D1 may be substantially the same as the distance D2. Fig.19 shown.

[0048] like Fig.18 and Fig.19 As shown, the size of the first semiconductor layer 106 in the first region 153 is substantially larger than the size of the first semiconductor layer 106 in the second region 155. Therefore, the size of the channel in the first region 153 is substantially larger than the size of the channel in the second region 155. In some embodiments, the first region 153 is an n-type region, and the second region 155 is a p-type region. As a result, the on-current of the NFET in the first region 153 can be substantially greater than the on-current of the PFET in the second region 155. In some embodiments, the first region 153 is a p-type region, and the second region 155 is an n-type region. As a result, the on-current of the PFET in the first region 153 can be substantially greater than the on-current of the NFET in the second region 155. By making the channel sizes of the NFET and the PFET different, the performance of the device having the NFET and the PFET is improved.

[0049] Next, if Fig. 20 As shown, the mask layer 150 in the second region 155 is removed. The mask layer 150 can be removed by any suitable process. In some embodiments, the mask layer 150 is removed by the same process as the portion of the mask layer 150 in the first region 153, such as Fig.16In some embodiments, the removal of the mask layer 150 may remove portions of the first semiconductor layer 106 in both the first region 153 and the second region 155, and a second deposition process is performed to compensate for damage to the first semiconductor layer 106 in the first region 153 and the second region 155 caused by the process of removing the mask layer 150. For example, after removing the mask layer 150, the height and width of the first semiconductor layer 106 in the first region 153 are less than the height H3 and the width W3 (or less than the height H3, H4, H5 and the width W3, W4, W5), and the second deposition process forms a semiconductor material layer around the first semiconductor layer 106, so that the first semiconductor layer 106 in the first region 153 has a height H3 and a width W3 (or a height H3, H4, H5 and a width W3, W4, W5). Similarly, after removing the mask layer 150, the height and width of the first semiconductor layer 106 in the second region 155 are less than the height H2 and the width W2, and the second deposition process forms a semiconductor material layer around the first semiconductor layer 106, so the first semiconductor layer 106 in the second region 155 has a height H2 and a width W2. The semiconductor material layer formed by the second deposition process may include the same material as the first semiconductor layer 106. In some embodiments, the semiconductor material layer includes undoped silicon.

[0050] like Fig.21 As shown, gate dielectric layer 160 is formed on the exposed surface of semiconductor device structure 100. In some embodiments, gate dielectric layer 160 is formed in regions 153, 155 to surround first semiconductor layer 106 and over well portion 116. Gate dielectric layer 160 is also formed on insulating material 118. The gate dielectric layer 160 may include or be made of a high-K dielectric material, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (La2O), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), or other suitable high-K dielectric materials. The gate dielectric layer 160 may be a conformal layer formed by a conformal process such as an ALD process or a CVD process. The gate dielectric layer 160 may have a thickness ranging from about 0.5 nm to about 3 nm.

[0051] In some embodiments, an interfacial layer (IL) (not shown) may be formed on the first semiconductor layer 106 and the well portion 116, and a gate dielectric layer 160 is formed on the interfacial layer. The interfacial layer may include or be made of an oxygen-containing material, such as silicon oxide, silicon oxynitride, oxynitride, etc. In one embodiment, the IL is silicon oxide.

[0052] like Fig. 22 As shown, a first gate electrode layer 165 is formed on the gate dielectric layer 160. The first gate electrode layer 165 fills the opening 151 ( Fig.21 ) and surround a portion of each first semiconductor layer 106 in regions 153, 155. In some embodiments, the first gate electrode layer 165 can be formed using multiple layers, each layer being sequentially deposited adjacent to each other using a highly conformal deposition process such as ALD. Other deposition techniques, such as PVD, CVD, or electroplating, may also be used. Although not shown, the first gate electrode layer 165 may include one or more work function layers and filling materials. The work function layer may be formed of a metal-containing material, such as W, Cu, AlCu, TiAlC, TiAlN, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. Once the work function layer is formed, a filling material is deposited to fill the remainder of the opening 151. The filling material may be a conductive material, such as W, Al, Cu, AlCu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, and the like.

[0053] like Fig.23 As shown, the portion of the first gate electrode layer 165 in the first region 153 is removed. A patterned resist layer 167 may be first formed to cover the portion of the first gate electrode layer 165 located in the second region 155, while exposing the portion of the first gate electrode layer 165 located in the first region 153. The patterned resist layer 167 may be formed by first forming a blanket layer on the semiconductor device structure 100, followed by a patterning and etching process to remove the portion of the blanket layer at the selected region to form the patterned resist layer 167. Once the patterned resist layer 167 is formed, the portion of the first gate electrode layer 165 above the first semiconductor layer 106 in the first region 153 is removed. The first gate electrode layer 165 may be removed using any suitable process, such as dry etching, wet etching, or a combination thereof. The removal process may be a selective etching process that removes the first gate electrode layer 165 but does not remove the gate dielectric layer 160.

[0054] Next, if Fig.24As shown, a second gate electrode layer 163 is formed on the gate dielectric layer 160 in the first region 153. The second gate electrode layer 163 may be deposited to surround the first semiconductor layer 106 in the first region 153. The second gate electrode layer 163 may be formed by the same process as the first gate electrode layer 165. The second gate electrode layer 163 may also include one or more work function layers and filler materials, such as those listed for the first gate electrode layer 165. In some embodiments, the second gate electrode layer 163 is chemically different from the first gate electrode layer 165 and includes a different material from the first gate electrode layer 165. Each of the first gate electrode layer 165 and the second gate electrode layer 163 may be selected according to the threshold voltage and application of the NMOS or PMOS device in the regions 153, 155.

[0055] The second gate electrode layer 163 may also be formed on the patterned resist layer 167 and the ILD layer 164. A planarization process such as a CMP process may be performed to remove a portion of the second gate electrode layer 163 formed on the patterned resist layer 167 and the ILD layer 164. In some embodiments, the patterned resist layer 167 is also removed by the planarization process.

[0056] Figures 25A-25D According to some embodiments, Figure 6 AA, BB, CC and DD are taken along the lines AA, BB, CC and DD of FIG. 1 . Line DD is perpendicular to line CC and is located in the plane of fin structure 112 along the X direction. Specifically, Figures 25A-25D A stage is shown after the second gate electrode layer 163 is formed in the first region 153 and the patterned resist layer 167 is removed.

[0057] like Fig.25A , which shows a second region 155 in which each first semiconductor layer 106 has a substantially constant height H2. In some embodiments, the height of the central portion (adjacent to the gate dielectric layer 160) of each first semiconductor layer 106 in the second region 155 may be substantially less than the height of the edge portion (adjacent to the dielectric spacer 144) due to the process of removing the second semiconductor layer 108. In contrast, Fig.25D As shown, it shows a first region 153 in which each first semiconductor layer 106 has an edge portion of a height H2 and a central portion of a height H3 (or height H4, H5) substantially greater than the height H2. Fig.18 and Fig.19As a result of the process described in the foregoing, the height of the central portion of the first semiconductor layer 106 in the first region 153 is substantially greater than the height of the edge portion of the first semiconductor layer 106 in the first region 153. The edge portion of the first semiconductor layer 106 in the first region 153 is covered by the dielectric spacer 144, and no semiconductor material layer is formed on the edge portion of the first semiconductor layer 106 in the first region 153.

[0058] It is to be understood that the semiconductor device structure 100 may undergo further complementary metal oxide semiconductor (CMOS) and / or back-end of line (BEOL) processes to form various features, such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0059] Figure 26-34 According to an alternative embodiment along Figure 6 Cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line BB. Figure 26-34 Also shown are the various stages of manufacturing Fig. 13B The portion 147 of the semiconductor device structure 100. Fig.26 As shown, in Figures 13A-13C After the process described in, the IL 156 is formed to surround the exposed portion of the first semiconductor layer 106 in the first region 153 and the second region 155. The IL 156 may also be formed on the well portion 116. The IL 156 may be selectively formed on the semiconductor material of the first semiconductor layer 106 and the well portion 116. At this stage, the size of the first semiconductor layer 106 in the first region 153 and the size of the first semiconductor layer 106 in the second region 155 may be substantially the same.

[0060] Next, if Fig. 27 As shown, a gate dielectric layer 160 is formed on the IL 156 and the insulating material 118. Then, a first gate electrode layer 165 is formed on the gate dielectric layer 160 in the first region 153 and the second region 155. Fig.28 Then, a patterned resist layer 167 is formed on the portion of the first gate electrode layer 165 in the second region 155, and the exposed portion of the first gate electrode layer 165 in the first region 153 is removed, as shown. Fig.29 The process of removing part of the first gate electrode layer 165 can be similar to Fig.23 Next, the exposed portion of the gate dielectric layer 160 in the first region 153 and the portion of the IL 156 in the first region 153 are removed, as shown in FIG. Fig.30As shown. Portions of the gate dielectric layer 160 and the IL 156 may be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, portions of the gate dielectric layer 160 and the IL 156 are removed by a selective etching process that does not substantially affect the patterned resist layer 167, the first gate electrode layer 165, and the first semiconductor layer 106. After the removal process, the first semiconductor layer 106 located in the first region 153 that is not covered by the dielectric spacer 144 is exposed.

[0061] Next, if Fig.31 As shown in FIG. 1 , the size of the exposed first semiconductor layer 106 in the first region 153 is increased. The process of increasing the size of the first semiconductor layer 106 in the first region 153 may be the same as that of Fig.18 Therefore, each of the first semiconductor layers 106 in the first region 153 has a height H3 and a width W3, and each of the first semiconductor layers 106 in the second region 155 has a height H2 substantially smaller than the height H3 and a width W2 substantially smaller than the width W3. In addition, a distance D1 between a top surface of the well portion 116 in the first region 153 and a top surface of the insulating material 118 is substantially greater than a distance D2 between a top surface of the well portion 116 in the second region 155 and a top surface of the insulating material 118.

[0062] Alternatively, if Fig.32 As shown, the topmost first semiconductor layer 106 in the first region 153 has a height H3 and a width W3, the middle first semiconductor layer 106 has a height H4 and a width W4, and the bottom first semiconductor layer 106 has a height H5 and a width W5. In some embodiments, the height H3 is substantially greater than the height H4, the height H4 is substantially greater than the height H5, and the width W3 is substantially greater than the width W4, and the width W4 is substantially greater than the width W5. In other words, the height and width of the first semiconductor layer 106 in the first region 153 decrease in a direction toward the well portion 116. In some embodiments, the width W5 and the height H5 are substantially greater than the width W2 and the height H2. In some embodiments, the distance D1 may be substantially the same as the distance D2, such as Fig.32 shown.

[0063] Next, if Fig.33As shown, IL 180 is formed to include an exposed portion of the first semiconductor layer 106 in the first region 153, and a gate dielectric layer 182 is formed on the exposed portions of IL 180 and the insulating material 118. IL 180 may include the same material as IL 156 and may be formed by the same process as IL 156. Gate dielectric layer 182 may include the same material as gate dielectric layer 160 and may be formed by the same process as gate dielectric layer 160. In some embodiments, gate dielectric layer 182 and gate dielectric layer 160 include different materials. In some embodiments, gate dielectric layer 182 is formed by a conformal process such as ALD. Gate dielectric layer 182 may also be formed on sidewalls of first gate electrode layer 165 and patterned resist layer 167, as shown in FIG. Fig.33 shown.

[0064] Next, if Fig.34 As shown, a second gate electrode layer 163 is formed on the gate dielectric layer 182 to surround the first semiconductor layer 106 in the first region 153. A planarization process is then performed to remove a portion of the second gate electrode layer 163, a portion of the gate dielectric layer 182, and the patterned resist layer 167. The resulting structure can be Fig.24 The structures shown are substantially the same, except that a portion of the gate dielectric layer 182 is disposed between the first gate electrode layer 163 and the second gate electrode layer 165. Thus, in some embodiments, each of the first gate electrode layer 165 and the second gate electrode layer 163 has its own conductive contact for providing power thereto.

[0065] Figure 35-40 According to an alternative embodiment along Figure 6 A cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line BB. Fig.35 As shown, a semiconductor layer stack 104 is formed on a substrate 101 . Fig.35 The semiconductor device structure 100 shown can be Figure 1 The semiconductor device structure 100 shown is the same.

[0066] Next, if Fig.36 As shown, a patterned mask layer 202 is formed on the portion of the semiconductor layer stack 104 in the second region 155, and the exposed portion of the semiconductor layer stack 104 in the first region 153 is removed to expose a portion of the substrate 101. The removal of the portion of the semiconductor layer stack 104 can be performed by any suitable process. In some embodiments, the process of performing the process as shown in FIG. Figure 2The process for forming the fin structure 112 described in the above is used to remove a portion of the semiconductor layer stack 104. In some embodiments, the exposed portion of the substrate 101 in the first region 153 has a top surface that is substantially coplanar with a top surface of a portion of the substrate 101 in the second region 155, such as Fig.36 In some embodiments, the top surface of the substrate 101 in the first region 153 is located at a level lower than the top surface of the substrate 101 in the second region 155 due to over-etching.

[0067] like Fig.37 As shown, a semiconductor layer stack 204 is formed on the exposed portion of the substrate 101. In some embodiments, the semiconductor layer stack 204 includes alternating first semiconductor layers 206 (206a, 206b, 206c) and second semiconductor layers 208. The first semiconductor layer 206 may include the same material as the first semiconductor layer 106, and the second semiconductor layer 208 may include the same material as the second semiconductor layer 108. In some embodiments, the height of the second semiconductor layer 208 is substantially less than the height of the second semiconductor layer 108, and the height of the first semiconductor layer 206 is substantially greater than the height of the first semiconductor layer 106. In some embodiments, the semiconductor layer stack 104 has a height H7, the semiconductor layer stack 204 has a height H8, and the height H8 is substantially greater than the height H7.

[0068] like Fig.38 As shown, the patterned mask layer 202 is removed, and the top surface 104t of the semiconductor layer stack 104 in the second region 155 and the top surface 204t of the semiconductor layer stack 204 in the first region 153 can be substantially coplanar. In some embodiments, a planarization process such as a CMP process is performed to planarize the semiconductor device structure 100. The planarization process removes a portion of the topmost first semiconductor layer 206c. As a result, in some embodiments, the height of the topmost first semiconductor layer 206c is less than the heights of the other first semiconductor layers 206a, 206b in the semiconductor layer stack 204. The height of the topmost first semiconductor layer 206c can be greater than, equal to, or less than the height of the first semiconductor layer 106 of the semiconductor layer stack 104 in the second region 155.

[0069] like Fig.39 As shown, the fin structures 212 and 112 are formed in the first region 153 and the second region 155, respectively. The fin structures 212 and 112 can be formed as shown in FIG. Figure 2 In some embodiments, the width of the fin structure 212 and the fin structure 112 in the Y direction are substantially the same. In some embodiments, the width of the fin structure 212 is substantially greater than the width of the fin structure 112. Subsequent processes are performed, such as Figures 3 to 13C as well as Figure 26 to Figure 28 In performing the process described in Fig.28 After the process in, the portion of the first gate electrode layer 165 in the first region 153 is removed, and the second gate electrode layer 163 is formed in the first region 153, as shown in FIG. Fig.40 shown.

[0070] like Fig.40 As shown, each first semiconductor layer 106 in the second region 155 has a height H11 and a width W7. Each first semiconductor layer 206a, 206b, 206c has a width W6. In some embodiments, widths W6 and W7 may be substantially the same. In some embodiments, width W6 is substantially greater than width W7. Widths W6 and W7 are defined by the widths of the fin structures 212 and 112, respectively. The topmost first semiconductor layer 206c in the first region 153 has a height H10, and the other first semiconductor layers 206b, 206a in the first region 153 have a height H9. In some embodiments, due to Fig.38 In the planarization process described in , height H10 is substantially less than height H9. Height H10 may be less than, greater than, or equal to height H11. For clarity, Fig.40 IL 156 is omitted.

[0071] Embodiments of the present disclosure provide a semiconductor device structure 100 and a method for forming the same. In some embodiments, the semiconductor device structure 100 includes a first plurality of semiconductor layers 106 located in a first region 153 of a substrate 101 and a second plurality of semiconductor layers 106 located in a second region 155 of the substrate 101. The size of the first plurality of semiconductor layers 106 located in the first region 153 may be substantially larger than the size of the second plurality of semiconductor layers 106 located in the second region 155. Some embodiments may achieve advantages. For example, by making the channel sizes of the NFET and the PFET different, the performance of a device having the NFET and the PFET may be improved.

[0072] One embodiment is a semiconductor device structure. The structure includes a first semiconductor layer disposed on a substrate, the first semiconductor layer having an edge portion and a central portion, and the height of the central portion is significantly greater than the height of the edge portion. The structure also includes: a dielectric spacer, the dielectric spacer is disposed below the edge portion of the first semiconductor layer and in contact with the edge portion of the first semiconductor layer; a gate dielectric layer surrounding the central portion of the first semiconductor layer; and a gate electrode layer disposed on the gate dielectric layer surrounding the central portion of the first semiconductor layer.

[0073] Another embodiment is a semiconductor device structure. The structure includes a first plurality of semiconductor layers disposed in a first region of a substrate, a bottom semiconductor layer of the first plurality of semiconductor layers having a first height. The structure also includes a second plurality of semiconductor layers disposed in a second region of the substrate, a height of a semiconductor layer in the second plurality of semiconductor layers being significantly less than the first height. The structure also includes: a first gate electrode layer surrounding a portion of the first plurality of semiconductor layers; and a second gate electrode layer surrounding a portion of the second plurality of semiconductor layers.

[0074] Yet another embodiment is a method for forming a semiconductor device structure. The method includes forming a first fin structure and a second fin structure, the first fin structure including a first plurality of semiconductor layers, and the second fin structure including a second plurality of semiconductor layers. The method also includes forming a mask layer around the second plurality of semiconductor layers, and the first plurality of semiconductor layers are exposed. The method also includes: increasing the size of each semiconductor layer in the first plurality of semiconductor layers; removing the mask layer; depositing a gate dielectric layer around the first plurality of semiconductor layers and the second plurality of semiconductor layers; forming a first gate electrode layer around the second plurality of semiconductor layers; and forming a second gate electrode layer around the first plurality of semiconductor layers.

[0075] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, comprising: A first semiconductor layer is disposed on the substrate, wherein the first semiconductor layer has an edge portion and a central portion, and a height of the central portion is greater than a height of the edge portion; a dielectric spacer disposed below and in contact with an edge portion of the first semiconductor layer; a gate dielectric layer surrounding a central portion of the first semiconductor layer; and A gate electrode layer is disposed on the gate dielectric layer surrounding a central portion of the first semiconductor layer. 2 . The semiconductor device structure according to claim 1 , further comprising a second semiconductor layer disposed below the first semiconductor layer and a third semiconductor layer disposed below the second semiconductor layer.

3. The semiconductor device structure according to claim 2, wherein: A central portion of the second semiconductor layer has a height greater than a height of an edge portion of the second semiconductor layer, and a central portion of the third semiconductor layer has a height greater than a height of an edge portion of the third semiconductor layer.

4. The semiconductor device structure according to claim 3, wherein: The gate dielectric layer and the gate electrode layer surround a central portion of the second semiconductor layer and a central portion of the third semiconductor layer.

5. The semiconductor device structure according to claim 1, wherein: The gate dielectric layer contacts the dielectric spacer.

6. A semiconductor device structure, comprising: a first plurality of semiconductor layers disposed in a first region of the substrate, wherein a bottom semiconductor layer of the first plurality of semiconductor layers has a first height; A second plurality of semiconductor layers are disposed in a second region of the substrate, wherein a height of each semiconductor layer in the second plurality of semiconductor layers is less than the first height; a first gate electrode layer surrounding a portion of the first plurality of semiconductor layers; and The second gate electrode layer surrounds a portion of the second plurality of semiconductor layers.

7. The semiconductor device structure according to claim 6, wherein: A top semiconductor layer of the first plurality of semiconductor layers has a second height that is less than the first height.

8. The semiconductor device structure according to claim 7, wherein: A height of each semiconductor layer in the second plurality of semiconductor layers is less than the second height.

9. The semiconductor device structure according to claim 7, wherein: A height of each semiconductor layer in the second plurality of semiconductor layers is greater than the second height.

10. A method comprising: forming a first fin structure and a second fin structure, wherein the first fin structure includes a first plurality of semiconductor layers and the second fin structure includes a second plurality of semiconductor layers; forming a mask layer around the second plurality of semiconductor layers, wherein the first plurality of semiconductor layers are exposed; increasing a size of each semiconductor layer in the first plurality of semiconductor layers; removing the mask layer; depositing a gate dielectric layer around the first plurality of semiconductor layers and the second plurality of semiconductor layers; forming a first gate electrode layer around the first plurality of semiconductor layers; and A second gate electrode layer is formed around the second plurality of semiconductor layers.

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