Charger circuitry

By using the input voltage detection circuit and fast charging protocol chip in the charger, dynamically adjusting the output power and performing voltage protection, the low efficiency and safety of the charger under different mains conditions are solved, and the efficient utilization and safety of the charger is achieved. promote.

CN119109165APending Publication Date: 2024-12-10ON BRIGHT INTEGRATIONS CO INC
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Patent Information

Application Number
CN202411206289.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-08-29
Publication Date
2024-12-10

AI Technical Summary

Technical Problem

The system efficiency of the charger is low, the temperature is high, and large-size power devices are required under different mains conditions. The fluctuation of the mains voltage makes it difficult to achieve undervoltage or overvoltage protection, resulting in huge size of the charger and redundant output power, and Unsupported mains range may damage or cause safety issues.

Method used

A charger circuit system is designed, including an input voltage detection circuit and a fast charging protocol chip. By dividing the drain voltage of the synchronous rectifier tube, an input voltage characterization voltage is generated to characterize the AC input voltage, and used for a fast charging protocol chip. Determines the voltage value of the AC input voltage, thereby dynamically adjusting the output power and protecting it in undervoltage or overvoltage.

Benefits of technology

It realizes efficient utilization of the charger output power, avoids damage or safety problems under the unsupported mains range, and optimizes the hardware resource utilization and security of the charger.

✦ Generated by Eureka AI based on patent content.

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Abstract

The charger circuit system comprises an input voltage detection circuit, a fast charge protocol chip and a synchronous rectifier tube, the input voltage detection circuit is configured to generate an input voltage characterization voltage characterizing an alternating current input voltage of the charger circuit system by dividing a drain voltage of the synchronous rectifier tube, and the input voltage characterization voltage characterizes the alternating current input voltage of the charger circuit system. Therefore, the fast charge protocol chip can determine the voltage value of the AC input voltage based on the input voltage characterization voltage.
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Description

Technical Field

[0001] The present invention relates to the field of circuits, and more particularly to a charger circuit system. Background Art

[0002] As consumers' demand for fast charging increases, the output power of chargers is getting higher and higher. The global standard USB-PD3.1 fast charging protocol supports an output power of up to 240W. In order to be compatible with global mains application scenarios, it is usually necessary to expand the applicable mains range of the charger to an AC voltage of 90V to 264V. Some regions (for example, India) even require the charger to support an AC input voltage of 330V, which requires the charger to be designed to output maximum power under different mains conditions. However, since the system efficiency, safety temperature, etc. of the charger under different mains conditions vary greatly, based on the barrel effect, larger power devices (for example, transformers / input and output capacitors / switches, etc.) are required for parts with low system efficiency and high temperature rise, which makes the charger large in size and has redundant output power under other mains conditions. On the other hand, since the mains usually has a certain voltage fluctuation, the charger needs to support undervoltage and overvoltage protection for the input mains to prevent the charger from being damaged or causing safety problems when working in an unsupported mains range. Summary of the invention

[0003] According to an embodiment of the present invention, the charger circuit system includes an input voltage detection circuit, a fast charging protocol chip, and a synchronous rectifier. The input voltage detection circuit is configured to generate an input voltage characterization voltage characterizing the AC input voltage of the charger circuit system by dividing the drain voltage of the synchronous rectifier, so that the fast charging protocol chip can determine the voltage value of the AC input voltage based on the input voltage characterization voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present invention can be better understood from the following description of specific embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0005] Figure 1 An exemplary logic structure diagram of a charger circuit system and an input voltage detection circuit thereof according to an embodiment of the present invention is shown.

[0006] Figure 2 An exemplary logic structure diagram of another charger circuit system and an input voltage detection circuit thereof according to an embodiment of the present invention is shown.

[0007] Figure 3 A schematic diagram showing an example logic structure of another charger circuit system and an input voltage detection circuit thereof according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0008] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement and improvement of elements, parts and algorithms without departing from the spirit of the present invention. In the accompanying drawings and the following description, known structures and technologies are not shown to avoid unnecessary ambiguity in the present invention. In addition, it should be noted that the term "A is connected to B" used here can mean "A is directly connected to B" and can also mean "A is indirectly connected to B via one or more other elements".

[0009] In view of the above situation, a charger circuit system and an input voltage detection circuit thereof according to an embodiment of the present invention are proposed, which can enable the maximum power output of the charger to be dynamically adjusted following the input voltage, thereby more efficiently utilizing the hardware resources of the charger and / or avoiding damage to the charger or causing safety problems when the charger operates in an unsupported AC power range.

[0010] Figure 1 FIG. 1 shows an exemplary logic structure diagram of a charger circuit system and an input voltage detection circuit thereof according to an embodiment of the present invention. Figure 1 In the charger circuit system 100 shown, the AC input voltage Vac is rectified and filtered by the rectifier bridge D1 and the input capacitor Cin to generate a DC input voltage Vbulk; when the switch tube Q1 is in the on state under the control of the pulse width modulation (PWM) controller U1 and the synchronous rectifier tube Q2 is in the off state under the control of the synchronous rectification (SR) controller U2, the primary winding Np of the transformer T1 stores energy; when the switch tube Q1 is in the off state under the control of the PWM controller U1 and the synchronous rectifier tube Q2 is in the on state under the control of the SR controller U2, the primary winding Np of the transformer T1 releases energy to the secondary winding Ns. Energy; the voltage on the secondary winding Ns of the transformer T1 is filtered by the output capacitor Cout to generate a DC voltage as the system output voltage Vin; when the switch tube Q3 is in the on state under the control of the fast charging protocol chip U3, the system output voltage Vin charges the terminal device (for example, a mobile phone, a laptop computer, etc.) via the universal serial bus (USB) interface; the fast charging protocol chip U3 interacts with the terminal device via the CC1 / CC2 / DP / DN signal lines of the USB interface based on the fast charging protocol, and adjusts the system output voltage Vin and / or the system output current according to the needs of the terminal device to achieve fast charging of the terminal device.

[0011] exist Figure 1 During the operation of the charger circuit system 100 shown, there is a certain proportional relationship between the voltage on the primary winding Np of the transformer T1 and the voltage on the secondary winding Ns, and the AC input voltage Vac can be detected by detecting the voltage on the secondary winding Ns of the transformer T1. However, since the voltage on the secondary winding Ns of the transformer T1 is a high-frequency AC rectangular wave signal and is usually high, it is difficult for the fast charging protocol chip U3 to directly detect the AC input voltage Vac based on the voltage on the secondary winding Ns of the transformer T1. Therefore, the fast charging protocol chip U3 detects the AC input voltage Vac via an input voltage detection circuit 102 connected between its general purpose input and output (GPIO) port and the drain of the synchronous rectifier Q2.

[0012] exist Figure 1 In the charger circuit 100 shown, the input voltage detection circuit 102 is configured to generate an input voltage characterizing voltage Vd_div characterizing the AC input voltage Vac by dividing the drain voltage Vd of the synchronous rectifier Q2. For example, the input voltage detection circuit 102 includes voltage-dividing resistors R1 and R2 and a diode D2 connected in series between the drain of the synchronous rectifier Q2 and the circuit reference ground, wherein the GPIO port of the fast charging protocol chip U3 is connected to the voltage-dividing node between the voltage-dividing resistors R1 and R2. When the voltage drop of the diode D2 is ignored, the relationship between the input voltage characterizing voltage Vd_div at the voltage-dividing node between the voltage-dividing resistors R1 and R2 and the AC output voltage Vac can be derived as follows:

[0013] The maximum voltage of the DC input voltage Vbulk is

[0014]

[0015] The drain voltage of the synchronous rectifier Q3 when it is in the off state is

[0016] V d =V bulk / N+V in (Equation 2)

[0017] Where N = N p / N s .

[0018] The voltage-dividing resistors R1 and R2 divide the drain voltage Vd of the synchronous rectifier Q3 to generate the rectifier drain voltage, which is the input voltage representation voltage, that is,

[0019] V d_div =K div *V d (Equation 3)

[0020] Among them, K div=R2 / (R1+R2)

[0021] Combining equations 1 to 3, the relationship between the input voltage characterizing voltage Vd_div and the AC input voltage Vac is obtained as follows:

[0022]

[0023] exist Figure 1 In the charger circuit system 100 shown, the fast charging protocol chip U3 is configured to detect the input voltage characterization voltage Vd_div via its GPIO port, determine the voltage value of the AC input voltage Vac based on the input voltage characterization voltage Vd_div, search the output power corresponding to the voltage value of the AC input voltage Vac in a predetermined truth table, adjust the output power of the charger circuit system 100 based on the comparison relationship between the output power corresponding to the voltage value of the AC input voltage Vac and the charging power required by the terminal device, and control the conduction and shutdown of the switch tube Q3 based on the comparison relationship between the voltage value of the AC input voltage Vac and the undervoltage protection threshold and the overvoltage protection threshold.

[0024] like Figure 1 As shown, in some embodiments, the fast charging protocol chip U3 includes an analog-to-digital converter (ADC) sampling module, a logic control module, a fast charging interface module, and a protection module, wherein: the ADC sampling module is configured to determine the voltage value of the AC input voltage Vac based on the input voltage characterization voltage Vd_div, the system output voltage Vin, the turns ratio N between the primary winding Np and the secondary winding Ns of the transformer T1, and the voltage dividing ratio Kdiv of the voltage dividing resistor R2 in the voltage dividing network composed of the voltage dividing resistors R1 and R2; the logic control module is configured to determine the output power corresponding to the voltage value of the AC input voltage Vac by looking up the table based on the voltage value of the AC input voltage Vac, and to determine the output power by interacting with the terminal device through the fast charging interface module. The charging power required by the terminal device is determined, and when the output power corresponding to the voltage value of the AC input voltage Vac is equal to or greater than the charging power required by the terminal device, the charger circuit system 100 is controlled to charge the terminal device with the charging power required by the terminal device; when the output power corresponding to the voltage value of the AC input voltage Vac is less than the charging power required by the terminal device, the charger circuit system 100 is controlled to charge the terminal device with the output power corresponding to the voltage value of the AC input voltage Vac, and when the voltage value of the AC input voltage Vac is lower than the undervoltage protection threshold or higher than the overvoltage protection threshold, a protection function trigger signal is sent to the protection module; the protection module is configured to control the switch tube Q3 to change from an on state to an off state based on the protection function trigger signal.

[0025] Since the output power of the charger circuit system 100 can be dynamically adjusted following the AC input voltage Vac, the hardware resources of the charger circuit system 100 can be used more efficiently. In addition, since the switch tube Q3 can be controlled to change from an on state to an off state when the voltage value of the AC input voltage Vac is lower than the undervoltage protection threshold or higher than the overvoltage protection threshold, the charger circuit system 100 can be prevented from being damaged or causing safety problems when operating in an unsupported AC power range.

[0026] Figure 2 FIG. 2 shows an exemplary logic structure diagram of another charger circuit system and its input voltage detection circuit according to an embodiment of the present invention. Figure 1 and Figure 2 It can be seen that the difference between the charger circuit system 200 and the charger circuit system 100 is that the synchronous rectifier Q2 is located at the high side of the charger circuit system 200, and the voltage on the secondary winding Ns of the transformer T1 is negative. Therefore, the input voltage detection circuit 202 includes a constant current source Iup in addition to the voltage-dividing resistors R1 and R2 and the diode D2, wherein the constant current source Iup can be set inside the fast charging protocol chip U3 and connected to the voltage-dividing node between the voltage-dividing resistors R1 and R2 via the GPIO port of the fast charging protocol chip U3.

[0027] exist Figure 2 In the charger circuit system 200 shown, the constant current source Iup provides a pull-up current Iup for raising the input voltage representative voltage Vd_div to a positive voltage. When the voltage drop of the diode D2 is ignored, the relationship between the input voltage representative voltage Vd_div and the AC output voltage Vac can be derived as follows:

[0028] The maximum voltage of the DC input voltage Vbulk is

[0029]

[0030] The drain voltage of synchronous rectifier Q2 when it is in the off state is

[0031] V d =V bulk / N(Equation 5)

[0032] Where N = N p / N s .

[0033] The input voltage representation voltage Vd_div is generated by the voltage-dividing resistors R1 and R2 dividing the drain voltage Vd of the synchronous rectifier Q3, and the voltage generated by the pull-up current Iup on the combined resistance (R1 / / R2) generated by the voltage-dividing resistors R1 and R2 in parallel.

[0034] V d_div =Vd*K div +I up *(R1 / / R2)(Equation 6)

[0035] Among them, K div =R2 / (R1+R2).

[0036] Combining equations 4 to 6, the relationship between the input voltage characterizing voltage Vd_div and the AC input voltage Vac is obtained as follows:

[0037]

[0038] exist Figure 2 In the charger circuit system 200 shown, the ADC sampling module inside the fast charge protocol chip U3 is configured to determine the voltage value of the AC input voltage Vac based on the input current characterization voltage Vd_div, the pull-up current Iup, the turns ratio N between the primary winding Np and the secondary winding Ns of the transformer T1, and the voltage divider ratio Kdiv of the voltage divider resistor R2 in the voltage divider network composed of the voltage divider resistors R1 and R2. It should be noted that Figure 2 The charger circuit system 200 shown in FIG. 1 is similar in other respects to the Figure 1 The charger circuit system 100 shown is similar and therefore will not be described in detail.

[0039] Figure 3 FIG. 2 shows an exemplary logic structure diagram of another charger circuit system and its input voltage detection circuit according to an embodiment of the present invention. Figure 1 and Figure 3 It can be seen that the difference between the charger circuit system 300 and the charger circuit system 100 is that the synchronous rectifier Q2 is located on the high side of the charger circuit system 300, and the voltage on the secondary winding Ns of the transformer T1 is negative. Therefore, the input voltage detection circuit 302 includes a constant voltage source Vup and a pull-up resistor R3 in addition to the voltage-dividing resistors R1 and R2 and the diode D2, wherein the constant voltage source Vup can be set inside the fast charging protocol chip U3 and connected to one end of the pull-up resistor R3 via the GPIO port of the fast charging protocol chip U3, and the other end of the pull-up resistor R3 is connected to the voltage-dividing node between the voltage-dividing resistors R1 and R2.

[0040] exist Figure 3 In the charger circuit system 300 shown, the constant voltage source Vup and the pull-up resistor R3 provide a pull-up current Iup for raising the input voltage representative voltage Vd_div to a positive voltage, wherein, ignoring the voltage drop of the diode D2, the relationship between the input voltage representative voltage Vd_div and the AC output voltage Vac can be derived as follows:

[0041] The maximum voltage of the DC input voltage Vbulk is

[0042]

[0043] The drain voltage of synchronous rectifier Q2 when it is in the off state is

[0044] V d =V bulk / N(Equation 9)

[0045] Where N = N p / N s .

[0046] The input voltage representation voltage Vd_div is generated by the voltage-dividing resistors R1 and R2 dividing the drain voltage Vd of the synchronous rectifier Q3, and the voltage generated by the pull-up current Iup on the combined resistance (R1 / / R2) generated by the voltage-dividing resistors R1 and R2 in parallel.

[0047] V d_div =Vd*K div +I up *(R1 / / R2)(Equation 10)

[0048] Among them, K div =R2 / (R1+R2), I up =(V up -V d_div ) / R3.

[0049] Combining equations 8 to 10, the relationship between the input voltage characterizing voltage Vd_div and the AC input voltage Vac is obtained as follows:

[0050]

[0051] exist Figure 3 In the charger circuit system 300 shown, the ADC sampling module inside the fast charging protocol chip U3 is configured to determine the voltage value of the AC input voltage Vac based on the input current characterization voltage Vd_div, the pull-up voltage Vup, the pull-up resistor R3, the turns ratio N between the primary winding Np and the secondary winding Ns of the transformer T1, and the voltage divider ratio Kdiv of the voltage divider resistor R2 in the voltage divider network composed of the voltage divider resistors R1 and R2. It should be noted that Figure 3 The charger circuit system 300 shown in FIG. 1 is similar in other respects to the Figure 1 The charger circuit system 100 shown is similar and therefore will not be described in detail.

[0052] It should be understood that the above description only takes the charger circuit system of the flyback architecture as an example. The charger circuit system according to the embodiment of the present invention can adopt various circuit topologies such as buck, boost, buck-boost, flyback, forward, asymmetric half-bridge, etc. In addition, the specific process of the fast charging protocol chip interacting with the terminal device and the specific process of the fast charging protocol chip adjusting the output power of the charger circuit system can adopt various technical solutions known in the art, which will not be repeated here.

[0053] The present invention can be implemented in other specific forms without departing from its spirit and essential features. For example, the algorithms described in the specific embodiments can be modified, and the system architecture does not depart from the basic spirit of the present invention. Therefore, the current embodiments are regarded as exemplary and non-restrictive in all aspects, and the scope of the present invention is defined by the appended claims rather than the above description, and all changes falling within the meaning and equivalent scope of the claims are thus included in the scope of the present invention.

Claims

1. A charger circuit system, comprising an input voltage detection circuit, a fast charging protocol chip, and a synchronous rectifier, wherein the input voltage detection circuit is configured to generate an input voltage characterization voltage characterizing the AC input voltage of the charger circuit system by dividing the drain voltage of the synchronous rectifier, so that the fast charging protocol chip can determine the voltage value of the AC input voltage based on the input voltage characterization voltage.

2. The charger circuit system according to claim 1, in, The input voltage detection circuit is connected between the drain of the synchronous rectifier and a circuit reference ground.

3. The charger circuit system according to claim 2, in, The input voltage detection circuit includes a first voltage-dividing resistor and a second voltage-dividing resistor, and the universal input and output port of the fast charging protocol chip is connected to a voltage-dividing node between the first voltage-dividing resistor and the second voltage-dividing resistor.

4. The charger circuit system according to claim 3, in, The input voltage detection circuit further includes a constant current source connected to a voltage dividing node between the first voltage dividing resistor and the second voltage dividing resistor.

5. The charger circuit system according to claim 4, in, The constant current source is arranged inside the fast charging protocol chip and is connected to a voltage dividing node between the first voltage dividing resistor and the second voltage dividing resistor via a general input and output port of the fast charging protocol chip.

6. The charger circuit system according to claim 3, in, The input voltage detection circuit also includes a constant voltage source and a pull-up resistor, wherein the constant voltage source is connected to a first end of the pull-up resistor, and a second end of the pull-up resistor is connected to a voltage dividing node between the first voltage dividing resistor and the second voltage dividing resistor.

7. The charger circuit system according to claim 6, in, The constant voltage source is arranged inside the fast charging protocol chip and is connected to a voltage dividing node between the first voltage dividing resistor and the second voltage dividing resistor via a general input and output port of the fast charging protocol chip.