Switching circuit and control method thereof, converter and power transformation equipment

Abstract

The invention discloses a switching circuit and a control method thereof, a converter and power transformation equipment, the switching circuit comprises at least one bridge arm, the bridge arm comprises an upper bridge switch unit and a lower bridge switch unit, the upper bridge switch unit is configured to prevent reverse current generated by the lower bridge switch unit in dead time, and the lower bridge switch unit is configured to prevent reverse current generated by the lower bridge switch unit in dead time. And the lower bridge switch unit is configured to prevent the upper bridge switch unit from generating reverse current in the dead zone time so as to enable the upper bridge switch unit to realize zero-voltage turn-on, and the lower bridge switch unit is configured to prevent the upper bridge switch unit from generating reverse current in the dead zone time so as to enable the upper bridge switch unit to realize zero-voltage turn-on. According to the switching circuit, the upper bridge switching unit prevents the lower bridge switching unit from generating reverse current in the dead time, and the lower bridge switching unit prevents the upper bridge switching unit from generating reverse current in the dead time, so that the problem that a switching device is damaged due to reverse recovery current generated by inaccurate setting of the dead time is solved; and the failure probability of the switching device is reduced.

Description

Technical Field

[0001] The present application relates to the field of frequency conversion technology, and in particular to a switch circuit and a control method thereof, a converter and a power conversion device. Background Art

[0002] Power conversion technology is one of the key technologies in the energy storage industry. With the continuous improvement of voltage levels, the efficiency of traditional hard switching conversion technology is low, and the heat generation of power devices is also increasing. It is difficult to meet the requirements of product heat dissipation and users' requirements for energy throughput. Therefore, soft switching technology has become the mainstream technical route in the energy storage industry. Common soft switching technologies are mainly divided into two categories. The first is the non-isolated power converter topology, which mainly makes the circuit work in discontinuous mode, relying on a small negative current to extract the voltage of the parasitic capacitance of the switching device and then drive it to open, thereby achieving ZVS (Zero Voltage Switch); the second is the isolated power converter topology, which adopts full-bridge or half-bridge resonant conversion technology, and uses the phase difference between voltage and current to extract the voltage of the parasitic capacitance of the semiconductor device to be turned on in the dead time and then drive it to open, so as to achieve ZVS, such as half-bridge or full-bridge LLC topology.

[0003] However, the setting of dead time is crucial. If the dead time is too small, it will easily lead to hard switching and fail to achieve the purpose of improving efficiency. If the dead time is too large, it will cause the resonant current to reverse and turn on the parasitic diode of the device that was turned off at the previous moment. At this time, if the other switch tube in the same bridge arm is turned on, it will cause a large reverse recovery current, resulting in serious consequences such as device failure. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art to at least a certain extent. To this end, one object of the present invention is to provide a switching circuit, which blocks the reverse current generated by the lower bridge switch unit during the dead time through the upper bridge switch unit, and blocks the reverse current generated by the upper bridge switch unit during the dead time through the lower bridge switch unit, thereby solving the problem of damage to the switch device caused by the reverse recovery current generated by inaccurate dead time setting, thereby reducing the probability of failure of the switch device.

[0005] A second object of the present invention is to provide a converter.

[0006] The third object of the present invention is to provide a power transformation device.

[0007] A fourth objective of the present invention is to provide a control method for a switch circuit.

[0008] To achieve the above-mentioned purpose, according to an embodiment of the first aspect of the present invention, a switching circuit is proposed, comprising at least one bridge arm, the bridge arm comprising an upper bridge switch unit and a lower bridge switch unit, the upper bridge switch unit being configured to prevent the reverse current generated by the lower bridge switch unit during the dead time, so that the lower bridge switch unit can be turned on with zero voltage, and the lower bridge switch unit being configured to prevent the reverse current generated by the upper bridge switch unit during the dead time, so that the upper bridge switch unit can be turned on with zero voltage.

[0009] According to an embodiment of the present invention, the switching circuit includes at least one bridge arm, and the bridge arm includes an upper bridge switch unit and a lower bridge switch unit. The upper bridge switch unit is configured to prevent the reverse current generated by the lower bridge switch unit during the dead time, so that the lower bridge switch unit can achieve zero voltage switching. In the process of the lower bridge switch unit achieving zero voltage switching, the upper bridge switch unit will prevent the reverse current generated by the dead time being too long, so that the parasitic diode in the upper bridge switch unit will not be turned on, and when the lower bridge switch unit is turned on, a large reverse recovery current will not be generated; the lower bridge switch unit is configured to prevent the reverse current generated by the upper bridge switch unit during the dead time, so that the upper bridge switch unit can achieve zero voltage switching. In the process of the upper bridge switch unit achieving zero voltage switching, the lower bridge switch unit will prevent the reverse current generated by the dead time being too long, so that the parasitic diode in the lower bridge switch unit will not be turned on, and when the upper bridge switch unit is turned on, a large reverse recovery current will not be generated, thereby solving the problem of damage to the switching device due to the reverse recovery current generated by inaccurate dead time setting, thereby reducing the probability of failure of the switching device.

[0010] According to one embodiment of the present invention, the upper bridge switch unit includes a first switch tube and a second switch tube connected in series, and the first switch tube and the second switch tube are arranged back to back.

[0011] According to one embodiment of the present invention, the lower bridge switch unit includes a third switch tube and a fourth switch tube connected in series, and the third switch tube and the fourth switch tube are arranged back to back.

[0012] According to one embodiment of the present invention, the drain of the first switch tube is suitable for connecting to the positive pole of the power supply, the source of the first switch tube is connected to the source of the second switch tube, the drain of the second switch tube is connected to the drain of the third switch tube, the source of the third switch tube is connected to the source of the fourth switch tube, and the drain of the fourth switch tube is suitable for connecting to the negative pole of the power supply.

[0013] According to an embodiment of the present invention, a first node is provided between the drain of the second switch tube and the drain of the third switch tube, and the first node is suitable for connecting an inductive device.

[0014] According to an embodiment of the present invention, the first switch tube is turned off synchronously with the second switch tube, the third switch tube is turned off synchronously with the fourth switch tube, and the second switch tube is turned on and off complementarily with the fourth switch tube.

[0015] According to one embodiment of the present invention, the second switch tube is turned off after a first preset time delay than the first switch tube, the fourth switch tube is turned off after a first preset time delay than the third switch tube, the fourth switch tube is turned on when the first switch tube is turned off, and the second switch tube is turned on when the third switch tube is turned off.

[0016] According to one embodiment of the present invention, the first preset time is obtained according to the following formula: Among them, T d is the dead time, C gs , C gd , C ds is the junction capacitance of the switch tube, T s is the switching cycle, L m is the excitation inductance, and Δt is the first preset time.

[0017] To achieve the above object, a converter is provided according to a second aspect of the present invention, comprising a switching circuit according to any one of the above embodiments.

[0018] According to the converter of the embodiment of the present invention, by adopting the above-mentioned switching circuit, the upper bridge switching unit blocks the reverse current generated by the lower bridge switching unit during the dead time, and the lower bridge switching unit blocks the reverse current generated by the upper bridge switching unit during the dead time, thereby solving the problem of damage to the switching device due to the reverse recovery current generated by inaccurate dead time setting, thereby reducing the probability of failure of the switching device.

[0019] To achieve the above object, a power transformation device is provided according to a third aspect of the present invention, comprising the above-mentioned converter.

[0020] According to the substation equipment of the embodiment of the present invention, by adopting the above-mentioned converter, the upper bridge switch unit blocks the reverse current generated by the lower bridge switch unit during the dead time, and the lower bridge switch unit blocks the reverse current generated by the upper bridge switch unit during the dead time, thereby solving the problem of damage to the switching device due to the reverse recovery current generated by inaccurate dead time setting, thereby reducing the probability of failure of the switching device.

[0021] To achieve the above-mentioned purpose, a control method for a switching circuit is proposed according to an embodiment of the fourth aspect of the present invention, wherein the switching circuit includes at least one bridge arm, the bridge arm includes an upper bridge switch unit and a lower bridge switch unit, the upper bridge switch unit includes a first switch tube and a second switch tube connected in series, the first switch tube and the second switch tube are arranged back to back, and the lower bridge switch unit includes a third switch tube and a fourth switch tube connected in series, the third switch tube and the fourth switch tube are arranged back to back, and the method includes: controlling the fourth switch tube to turn on when the first switch tube is turned off, and controlling the second switch tube to turn on when the third switch tube is turned off, and respectively controlling the first switch tube and the second switch tube and the third switch tube and the fourth switch tube to turn off in a preset order.

[0022] According to the control method of the switch circuit of the embodiment of the present invention, the fourth switch tube is controlled to be turned on when the first switch tube is turned off, and the second switch tube is controlled to be turned on when the third switch tube is turned off, and the first switch tube and the second switch tube and the third switch tube and the fourth switch tube are respectively controlled to be turned off in a preset order, wherein the first switch tube and the second switch tube are arranged back to back, and the third switch tube and the fourth switch tube are arranged back to back, thereby, the directions of the parasitic diodes of the first switch tube and the second switch tube are opposite, the directions of the parasitic diodes of the third switch tube and the fourth switch tube are opposite, and the second switch tube and the fourth switch tube have a blocking effect on the reverse current, thereby preventing the reverse current generated by the upper / lower bridge switch unit during the dead time.

[0023] According to one embodiment of the present invention, respectively controlling the first switch tube and the second switch tube and the third switch tube and the fourth switch tube to shut down in a preset order includes: controlling the first switch tube and the second switch tube to shut down synchronously, and controlling the third switch tube and the fourth switch tube to shut down synchronously; or controlling the second switch tube to shut down after a first preset time delay than the first switch tube, and controlling the fourth switch tube to shut down after a first preset time delay than the third switch tube.

[0024] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a circuit topology diagram of a switch circuit in the related art;

[0026] Figure 2 It is a control timing diagram of a switch tube in a switch circuit in the related art;

[0027] Figure 3-Figure 6 It is a schematic diagram of current flow when a switch circuit in the related art is working;

[0028] Figure 7 is a circuit topology diagram of a switch circuit according to a first embodiment of the present invention;

[0029] Figure 8 is a circuit topology diagram of a switch circuit according to a second embodiment of the present invention;

[0030] Fig. 9 is a control timing diagram of a switch tube in a switch circuit according to a first embodiment of the present invention;

[0031] Fig.10 is a simulation diagram of a switch circuit in the related art;

[0032] Fig.11 is a simulation diagram of a switch circuit according to an embodiment of the present invention;

[0033] Fig.12 is a control timing diagram of a switch tube in a switch circuit according to a second embodiment of the present invention;

[0034] Figure 13-Figure 18 is a schematic diagram of current flow when a switch circuit according to an embodiment of the present invention is working;

[0035] Fig.19 is a system schematic diagram of a converter according to an embodiment of the present invention;

[0036] Fig. 20 is a system schematic diagram of a power transformation device according to an embodiment of the present invention;

[0037] Fig.21 4 is a flow chart of a method for controlling a switch circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0039] It should be noted that this application is made based on the inventor's understanding and research of the following issues:

[0040] Figure 1 shows a half-bridge conversion topology in the related art, Figure 2 yes Figure 1 The control timing diagram of the two switch tubes in FIG. 1 is shown in FIG. 1 , where Ts is the switching period, Td is the dead time between the two switch tube drive signals, and the carrier wave is the triangle wave inside the control unit (not shown) in the switch circuit. The control unit controls the two switch tubes Q9 and Q10 by comparing the carrier wave with the voltage reference signals Vref1-Vref6.

[0041] At the moment t1-t2, the upper bridge switch Q9 is controlled to turn on, and the current direction is as follows Figure 3 As shown. At t2, the upper bridge switch Q9 is turned off. At t2-t3, due to the effect of the magnetizing inductance in the circuit, the current direction remains unchanged, as shown in Figure 4 As shown, the current charges the parasitic capacitance of the upper bridge switch tube Q9 and discharges the parasitic capacitance of the lower bridge switch tube Q10, so that the voltage across the lower bridge switch tube Q10 is reduced. When the parasitic capacitance of the lower bridge switch tube Q10 is discharged, the voltage across the lower bridge switch tube Q10 is 0, and the parasitic diode of the lower bridge switch tube Q10 is turned on. This is the moment t3. At moment t3, the lower bridge switch tube Q10 is controlled to be turned on to achieve ZVS. At moment t3-t4, the lower bridge switch tube Q10 is controlled to be turned on, and the current direction is as follows Figure 5 As shown. At t4, the lower bridge switch Q10 is turned off. At t4-t5, due to the effect of the magnetizing inductance in the circuit, the current direction remains unchanged, as shown in Figure 6 As shown, the current discharges the parasitic capacitance of the upper bridge switch tube Q9 and charges the parasitic capacitance of the lower bridge switch tube Q10, so that the voltage across the upper bridge switch tube Q9 is reduced. When the parasitic capacitance of the upper bridge switch tube Q9 is discharged, the voltage across the upper bridge switch tube Q9 is 0, and the parasitic diode of the upper bridge switch tube Q9 is turned on. This is the time t5. At the time t5, the upper bridge switch tube Q9 is controlled to be turned on, and ZVS can be achieved.

[0042] If the dead time is set too long, that is, the time from t2 to t3 is too long, after the parasitic diode of the lower bridge switch Q10 is turned on, if the lower bridge switch Q10 is not turned on for a long time, the circuit will produce the following Figure 6 The reverse current shown in the figure will charge the parasitic capacitance of the lower bridge switch tube Q10, causing the voltage at both ends of the lower bridge switch tube Q10 to rise, and discharge the parasitic capacitance of the upper bridge switch tube Q9, thereby turning on the parasitic diode of the upper bridge switch tube Q9. At this time, if the lower bridge switch tube Q10 is controlled to be turned on, the lower bridge switch tube Q10 cannot achieve ZVS, and the upper bridge switch tube Q9 is subjected to reverse voltage at the moment of turning on the lower bridge switch tube Q10, and a large reverse recovery current will appear, causing the device to fail. In addition, the setting of the dead time is closely related to the parasitic parameters, inductance, transformer and other parameters of the semiconductor devices in the circuit topology. In the actual development process, it usually takes a lot of time and energy, and the introduction of auxiliary materials may also cause secondary development problems, thereby further increasing costs.

[0043] Based on this, an embodiment of the present invention provides a switching circuit, a converter and a substation equipment, which prevents the reverse current generated by the lower bridge switch unit during the dead time through the upper bridge switch unit, and prevents the reverse current generated by the upper bridge switch unit during the dead time through the lower bridge switch unit, thereby solving the problem of damage to the switching device due to the reverse recovery current generated by inaccurate dead time setting, thereby reducing the probability of failure of the switching device.

[0044] The switching circuit, converter and power conversion equipment according to the embodiments of the present invention will be described below with reference to the accompanying drawings.

[0045] Figure 7 is a circuit topology diagram of a switch circuit according to a first embodiment of the present invention. Figure 7 As shown, the switch circuit includes at least one bridge arm 10 , and the bridge arm 10 includes an upper bridge switch unit 11 and a lower bridge switch unit 12 .

[0046] Among them, the upper bridge switch unit 11 is configured to prevent the reverse current generated by the lower bridge switch unit 12 during the dead time, so that the lower bridge switch unit 12 can be turned on with zero voltage, and the lower bridge switch unit 12 is configured to prevent the reverse current generated by the upper bridge switch unit 11 during the dead time, so that the upper bridge switch unit 11 can be turned on with zero voltage.

[0047] Specifically, during the process of the lower bridge switch unit 12 realizing zero voltage switching, the upper bridge switch unit 11 will prevent the reverse current generated by the long dead time, so that the parasitic diode in the upper bridge switch unit 11 will not be turned on, and when the lower bridge switch unit 12 is turned on, no large reverse recovery current will be generated; during the process of the upper bridge switch unit 11 realizing zero voltage switching, the lower bridge switch unit 12 will prevent the reverse current generated by the long dead time, so that the parasitic diode in the lower bridge switch unit 12 will not be turned on, and when the upper bridge switch unit 11 is turned on, no large reverse recovery current will be generated.

[0048] In the above embodiment, the reverse current is blocked by the upper bridge switch unit during the process of the lower bridge switch unit realizing zero voltage switching, and the reverse current is blocked by the lower bridge switch unit during the process of the upper bridge switch unit realizing zero voltage switching, thereby solving the problem of damage to the switching device due to the reverse recovery current generated by inaccurate dead time setting, thereby reducing the probability of failure of the switching device.

[0049] In some embodiments, Figure 7 As shown, the upper bridge switch unit 11 includes a first switch tube Q1 and a second switch tube Q2 connected in series, and the first switch tube Q1 and the second switch tube Q2 are arranged back to back.

[0050] Specifically, the first switch tube Q1 and the second switch tube Q2 are arranged back to back, so the directions of the parasitic diodes of the first switch tube Q1 and the second switch tube Q2 are opposite. In the process of realizing zero voltage switching of the lower bridge switch unit 12, since the direction of the parasitic diode of the second switch tube Q2 is opposite to that of the first switch tube Q1, the parasitic diode of the second switch tube Q2 will not be switched on by the reverse current, so the second switch tube Q2 blocks the reverse current, and the reverse current will not flow into the first switch tube Q1, so that the parasitic diode of the first switch tube Q1 will not be switched on by the reverse current.

[0051] In the above embodiment, the first switch tube and the second switch tube are arranged back to back so that the parasitic diode of the first switch tube and the parasitic diode of the second switch tube are reversed, and the second switch tube blocks the reverse current, thereby preventing the reverse current generated by the lower bridge switch unit during the dead time.

[0052] In some embodiments, Figure 7 As shown, the lower bridge switch unit 12 includes a third switch tube Q3 and a fourth switch tube Q4 connected in series, and the third switch tube Q3 and the fourth switch tube Q4 are arranged back to back.

[0053] It can be understood that since the third switch tube Q3 and the fourth switch tube Q4 are arranged back to back, the directions of the parasitic diodes of the third switch tube Q3 and the fourth switch tube Q4 are opposite, and the parasitic diode of the fourth switch tube Q4 will not be turned on by the reverse current. Therefore, the fourth switch tube Q4 blocks the reverse current, and the reverse current will not flow into the third switch tube Q3. In this way, the parasitic diode of the third switch tube Q3 will not be turned on due to the reverse current, thereby preventing the reverse current generated by the upper bridge switch unit 11 during the dead time.

[0054] It should be noted that, in actual applications, the switch tubes in the upper bridge switch unit 11 and the lower bridge switch unit 12 are not limited to two, but can be more than two. However, the parasitic diode of the first switch tube Q1 needs to be in the opposite direction to the parasitic diode of at least one of the remaining switch tubes of the upper bridge switch unit 11, and the parasitic diode of the third switch tube Q3 needs to be in the opposite direction to the parasitic diode of at least one of the remaining switch tubes of the lower bridge switch unit 12.

[0055] Furthermore, in some embodiments, Figure 7 and Figure 8 As shown, the drain of the first switch tube Q1 is suitable for connecting to the positive electrode of the power supply Uin, the source of the first switch tube Q1 is connected to the source of the second switch tube Q2, the drain of the second switch tube Q2 is connected to the drain of the third switch tube Q3, the source of the third switch tube Q3 is connected to the source of the fourth switch tube Q4, and the drain of the fourth switch tube Q4 is suitable for connecting to the negative electrode of the power supply Uin.

[0056] Specifically, the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4 are all NMOS (N-Metal-Oxide-Semiconductor) tubes, and the source of the first switch tube Q1 is connected to the source of the second switch tube Q2, so the directions of the parasitic diode of the first switch tube Q1 and the parasitic diode of the second switch tube Q2 are opposite. The source of the third switch tube Q3 is connected to the source of the fourth switch tube Q4, so the directions of the parasitic diode of the third switch tube Q3 and the parasitic diode of the fourth switch tube Q4 are opposite.

[0057] In some embodiments, Figure 8 As shown, there is a first node J1 between the drain of the second switch tube Q2 and the drain of the third switch tube Q3 , and the first node J1 is suitable for connecting the inductive device 20 .

[0058] In an optional embodiment, the inductive device 20 includes a resonant inductor Lr, a primary winding of a transformer T and a resonant capacitor Cr, wherein one end of the resonant inductor Lr is connected to the first node J1, the other end of the resonant inductor Lr is connected to one end of the primary winding of the transformer T, the other end of the primary winding of the transformer T is connected to one end of the resonant capacitor Cr, and the other end of the resonant capacitor Cr is connected to the drain of the fourth switch tube Q4.

[0059] Further, the switching circuit also includes a first capacitor C1 and an output unit 30, wherein the first capacitor C1 is arranged between the two ends of the power supply Uin, the output unit 30 includes a secondary winding of a transformer T, a fifth switch tube Q5, a sixth switch tube Q6, a seventh switch tube Q7, an eighth switch tube Q8 and a second capacitor C2, one end of the secondary winding of the transformer T is connected to the source of the fifth switch tube Q5, the zero end of the secondary winding of the transformer T is connected to the source of the sixth switch tube Q6, the drain of the fifth switch tube Q5 is connected to the drain of the sixth switch tube Q6, the drain of the seventh switch tube Q7 is connected to the source of the fifth switch tube Q5, the source of the seventh switch tube Q7 is connected to the source of the eighth switch tube Q8, the drain of the eighth switch tube Q8 is connected to the source of the sixth switch tube Q6, one end of the second capacitor C2 is connected to the drain of the sixth switch tube Q6, and the other end of the second capacitor C2 is connected to the source of the eighth switch tube Q8.

[0060] In some embodiments, Fig. 9 As shown, the first switch tube Q1 and the second switch tube Q2 are turned off synchronously, the third switch tube Q3 and the fourth switch tube Q4 are turned off synchronously, and the second switch tube Q2 and the fourth switch tube Q4 are turned on and off complementarily.

[0061] Specifically, at the moment t1-t2, the first switch tube Q1 and the second switch tube Q2 are turned on at the same time. At the moment t2, the first switch tube Q1 and the second switch tube Q2 are turned off synchronously, and the fourth switch tube Q4 is turned on. At the moment t2-t3, due to the effect of the excitation inductance in the circuit, the current direction remains unchanged, and the current charges the parasitic capacitance of the first switch tube Q1 and the second switch tube Q2. Since the fourth switch tube Q4 is in the on state, the current discharges the parasitic capacitance of the third switch tube Q3, so that the voltage across the third switch tube Q3 is reduced. When the parasitic capacitance of the third switch tube Q3 is discharged, the voltage across the third switch tube Q3 is 0, and the parasitic diode of the third switch tube Q3 is turned on. At this time, the third switch tube Q3 should be controlled to be turned on. However, if the dead time is long, the inductive device 20 will generate a reverse current, and the second switch tube Q2 will prevent the reverse current to avoid the parasitic diode of the first switch tube Q1 from being turned on. If the parasitic diode of the third switch tube Q3 is turned on at the moment t3, the third switch tube Q3 is controlled to be turned on at this time, and the third switch tube Q3 is turned on at zero voltage; if the dead time is long and the moment t3 is delayed, the voltage across the third switch tube Q3 will increase slightly. At this time, the third switch tube Q3 is controlled to be turned on, and the third switch tube Q3 can be turned on at approximately zero voltage. However, due to the blocking effect of the second switch tube Q2, the first switch tube Q1 will not be subjected to reverse voltage at the moment of turning on the third switch tube Q3, thereby protecting the first switch tube Q1. At the moment t3-t4, the third switch tube Q3 and the fourth switch tube Q4 are turned on. At the moment t4, the third switch tube Q3 and the fourth switch tube Q4 are turned off synchronously, and the second switch tube Q2 is turned on. At the moment t4-t5, the voltage across the first switch tube Q1 is reduced, and the fourth switch tube Q4 blocks the reverse current. At the moment t5, the first switch tube Q1 is turned on, and the first switch tube Q1 is turned on at zero voltage.

[0062] Furthermore, Fig.10 The control timing diagram of the switch tube in the related art, the waveform diagram of the resonant current and the current waveform diagram of the upper bridge switch tube are shown. Fig.11 The circuit topology and the Fig. 9 The control timing diagram of the first switch tube and the third switch tube, the control timing diagram of the second switch tube and the fourth switch tube, the waveform diagram of the resonant current and the current waveform diagram of the first switch tube are shown. Fig.11 It can be seen from the figure that the circuit topology of this embodiment and Fig. 9 In the switch tube control sequence shown, the reverse recovery current of the first switch tube disappears, thereby preventing the switch device from being damaged by the reverse recovery current.

[0063] In some embodiments, Fig.12As shown, the second switch tube Q2 is turned off after a first preset time delay than the first switch tube Q1, the fourth switch tube Q4 is turned off after a first preset time delay than the third switch tube Q3, the fourth switch tube Q4 is turned on when the first switch tube Q1 is turned off, and the second switch tube Q2 is turned on when the third switch tube Q3 is turned off.

[0064] Specifically, at the time t1-t2, the first switch tube Q1 and the second switch tube Q2 are turned on at the same time, and the current direction is as follows: Fig.13 As shown. At time t2, the first switch tube Q1 is turned off, the second switch tube Q2 is still in the on state, and the fourth switch tube Q4 is turned on. At time t2-t3, after the first switch tube Q1 is turned off, the resonant current generated by the resonant inductor Lr and the resonant capacitor Cr is not zero, and the current flows as shown in Fig.14 As shown, at the moment t2-t3, the resonant current gradually decreases, and the second switch tube Q2 is turned off at this time, and the second switch tube Q2 can achieve approximate ZCS (Zero Current Switch). At the moment t3, the second switch tube Q2 is turned off, and the fourth switch tube Q4 is still in the on state. At the moment t3-t4, the current flows as follows Fig.15 As shown, the current charges the parasitic capacitance of the first switch tube Q1 and the second switch tube Q2. Since the fourth switch tube Q4 is in the on state, the current discharges the parasitic capacitance of the third switch tube Q3, so that the voltage across the third switch tube Q3 is reduced. When the discharge of the parasitic capacitance of the third switch tube Q3 is completed, the voltage across the third switch tube Q3 is 0, and the parasitic diode of the third switch tube Q3 is turned on. At this time, the third switch tube Q3 is controlled to be turned on. Even if the dead time is long, a reverse current will be generated in the circuit. However, due to the blocking effect of the second switch tube Q2, the first switch tube Q1 will not withstand the reverse voltage at the moment of the third switch tube Q3 being turned on, thereby protecting the first switch tube Q1. At time t4, the third switch tube Q3 is turned on. At time t4-t5, the third switch tube Q3 and the fourth switch tube Q4 are turned on, and the current direction is as shown in FIG. Fig.16 At time t5, the third switch tube Q3 is turned off, the fourth switch tube Q4 is still in the on state, and the second switch tube Q2 is turned on. At time t5-t6, as shown Fig.17 As shown, the resonant current decreases, and the fourth switch tube Q4 can achieve approximate ZCS. At time t6, the fourth switch tube Q4 is turned off, and the second switch tube Q2 is still in the on state. At time t6-t7, the current flows as follows Fig.18 As shown, the parasitic capacitance of the first switch tube Q1 is discharged, and the parasitic capacitance of the third switch tube Q3 is charged, so that the first switch tube Q1 can be turned on at zero voltage.

[0065] In the above embodiment, by delaying the shutdown of the second switch tube after the first switch tube is turned off, and by delaying the shutdown of the fourth switch tube after the third switch tube is turned off, the resonant current can be reduced, so that the second switch tube and the fourth switch tube can achieve approximately zero current shutdown when they are turned off.

[0066] Furthermore, in some embodiments, the first preset time is obtained according to the following formula (1):

[0067]

[0068] Among them, T d is the dead time, C gs , C gd , C ds is the junction capacitance of the switch tube, T s is the switching cycle, L m is the excitation inductance, and Δt is the first preset time.

[0069] Specifically, the dead time T d According to the junction capacitance C of the switch tube gs , C gd and C ds , switching cycle T s And the excitation inductance L m The first preset time Δt can be calculated based on the dead time T d Therefore, the dead time T d The debugging time and development cycle of the first preset time Δt are shorter; and, due to the dead time T d Only the parasitic parameters C of the switch tube gs , C gd and C ds , Excitation inductance L m and the switching period T s Therefore, the dead time T d The first preset time Δt can be adapted to switch circuits containing different auxiliary materials, thereby avoiding the secondary development problem of introducing alternative materials after the switch circuit product is released.

[0070] In an optional implementation, the voltage reference signals Vref1-Vref6 may be calculated according to formula (2):

[0071]

[0072] According to formula (2), the voltage reference signals Vref1-Vref6 are calculated based on the dead time T d , switching cycle T sand the first preset time Δt, therefore, the voltage reference signals Vref1-Vref6 can also adapt to the switch circuits containing different auxiliary materials, thereby avoiding the secondary development problem of introducing alternative materials after the switch circuit product is released.

[0073] It should be noted that the switch tube in the embodiment of the present invention is not limited to the NMOS tube described in the text, but can also be a switch combination module including IGBT (Insulated Gate Bipolar Transistor) and SiC (Silicon Carbide) with an integrated diode and other switch combination units composed of other switches and unidirectional conducting devices.

[0074] In summary, according to the switching circuit of the embodiment of the present invention, in the process of the lower bridge switch unit realizing zero voltage switching, the upper bridge switch unit will prevent the reverse current generated by the long dead time, so that the parasitic diode in the upper bridge switch unit will not be turned on, and when the lower bridge switch unit is turned on, a large reverse recovery current will not be generated; in the process of the upper bridge switch unit realizing zero voltage switching, the lower bridge switch unit will prevent the reverse current generated by the long dead time, so that the parasitic diode in the lower bridge switch unit will not be turned on, and when the upper bridge switch unit is turned on, a large reverse recovery current will not be generated, thereby solving the problem of damage to the switching device due to the reverse recovery current generated by inaccurate dead time setting, thereby reducing the probability of failure of the switching device; and, by delaying the shutdown of the second switch tube after the first switch tube is turned off, and by delaying the shutdown of the fourth switch tube after the third switch tube is turned off, the resonant current can be reduced, so that the second switch tube and the fourth switch tube can achieve approximate zero current shutdown when they are turned off. Furthermore, since the dead time and the first preset time are only related to the parasitic parameters, switching cycle and excitation inductance of the switching tube, the debugging time of the dead time and the first preset time is short, and can be adapted to switching circuits containing different auxiliary materials, thereby avoiding the secondary development problem of introducing alternative materials after the switching circuit product is released.

[0075] Corresponding to the above embodiment, the embodiment of the present invention further proposes a converter. Fig.19 As shown, the converter 200 includes the switch circuit 100 of any one of the aforementioned embodiments.

[0076] According to the converter of the embodiment of the present invention, the upper bridge switch unit blocks the reverse current generated by the lower bridge switch unit during the dead time, and the lower bridge switch unit blocks the reverse current generated by the upper bridge switch unit during the dead time, thereby solving the problem of damage to the switching device due to the reverse recovery current generated by inaccurate dead time setting, thereby reducing the probability of failure of the switching device.

[0077] Corresponding to the above embodiment, the embodiment of the present invention further proposes a power conversion device. Fig. 20 As shown, the power transformation device 300 includes the aforementioned converter 200 .

[0078] According to the substation equipment of the embodiment of the present invention, the upper bridge switch unit blocks the reverse current generated by the lower bridge switch unit within the dead time, and the lower bridge switch unit blocks the reverse current generated by the upper bridge switch unit within the dead time, thereby solving the problem of damage to the switching device due to the reverse recovery current generated by inaccurate dead time setting, thereby reducing the probability of failure of the switching device.

[0079] Corresponding to the above embodiment, the embodiment of the present invention further proposes a control method for a switch circuit. Figure 7 As shown, the switch circuit includes at least one bridge arm 10, the bridge arm 10 includes an upper bridge switch unit 11 and a lower bridge switch unit 12, the upper bridge switch unit 11 includes a first switch tube Q1 and a second switch tube Q2 connected in series, the first switch tube Q1 and the second switch tube Q2 are arranged back to back, and the lower bridge switch unit 12 includes a third switch tube Q3 and a fourth switch tube Q4 connected in series, the third switch tube Q3 and the fourth switch tube Q4 are arranged back to back. Fig.21 As shown, the control method of the switch circuit includes the following steps:

[0080] S101, controlling the fourth switch tube to turn on when the first switch tube is turned off, controlling the second switch tube to turn on when the third switch tube is turned off, and controlling the first switch tube and the second switch tube and the third switch tube and the fourth switch tube to turn off in a preset order respectively.

[0081] Specifically, the first switch tube Q1 and the second switch tube Q2 are arranged back to back, so the directions of the parasitic diodes of the first switch tube Q1 and the second switch tube Q2 are opposite. In the process of realizing zero voltage switching of the lower bridge switch unit 12, since the parasitic diode of the second switch tube Q2 is opposite to the direction of the first switch tube Q1, the parasitic diode of the second switch tube Q2 will not be switched on by the reverse current, so the second switch tube Q2 blocks the reverse current, and the reverse current will not flow into the first switch tube Q1, so the parasitic diode of the first switch tube Q1 will not be switched on by the reverse current. Similarly, the third switch tube Q3 and the fourth switch tube Q4 are arranged back to back, so the fourth switch tube Q4 blocks the reverse current, and the reverse current will not flow into the third switch tube Q3, so the parasitic diode of the third switch tube Q3 will not be switched on by the reverse current.

[0082] In the above embodiment, by arranging the first switch tube and the second switch tube back to back, and arranging the third switch tube and the fourth switch tube back to back, the parasitic diode of the first switch tube and the parasitic diode of the second switch tube are reversed, and the parasitic diode of the third switch tube and the parasitic diode of the fourth switch tube are reversed, and the second switch tube and the fourth switch tube have a blocking effect on the reverse current, thereby preventing the reverse current generated by the upper / lower bridge switch unit during the dead time.

[0083] In some embodiments, respectively controlling the first switch tube and the second switch tube and the third switch tube and the fourth switch tube to be turned off in a preset order includes: Fig. 9 As shown, the first switch tube and the second switch tube are controlled to be turned off synchronously, and the third switch tube and the fourth switch tube are controlled to be turned off synchronously; or, as shown Fig.12 As shown, the second switch tube is controlled to be turned off after a first preset time delay than the first switch tube, and the fourth switch tube is controlled to be turned off after a first preset time delay than the third switch tube.

[0084] Specifically, when using Fig. 9In the control sequence shown, at the moment t1-t2, the first switch tube Q1 and the second switch tube Q2 are turned on at the same time. At the moment t2, the first switch tube Q1 and the second switch tube Q2 are turned off synchronously, and the fourth switch tube Q4 is turned on. At the moment t2-t3, due to the effect of the excitation inductance in the circuit, the current direction remains unchanged, and the current charges the parasitic capacitance of the first switch tube Q1 and the second switch tube Q2. Since the fourth switch tube Q4 is in the on state, the current discharges the parasitic capacitance of the third switch tube Q3, so that the voltage across the third switch tube Q3 is reduced. When the parasitic capacitance of the third switch tube Q3 is discharged, the voltage across the third switch tube Q3 is 0, and the parasitic diode of the third switch tube Q3 is turned on. At this time, the third switch tube Q3 should be controlled to be turned on. However, if the dead time is long, the inductive device 20 will generate a reverse current, and the second switch tube Q2 will prevent the reverse current to avoid the parasitic diode of the first switch tube Q1 from turning on. If the parasitic diode of the third switch tube Q3 is turned on at the moment t3, the third switch tube Q3 is controlled to be turned on at this time, and the third switch tube Q3 is turned on at zero voltage; if the dead time is long and the moment t3 is delayed, the voltage across the third switch tube Q3 will increase slightly. At this time, the third switch tube Q3 is controlled to be turned on, and the third switch tube Q3 can be turned on at approximately zero voltage. However, due to the blocking effect of the second switch tube Q2, the first switch tube Q1 will not be subjected to reverse voltage at the moment of turning on the third switch tube Q3, thereby protecting the first switch tube Q1. At the moment t3-t4, the third switch tube Q3 and the fourth switch tube Q4 are turned on. At the moment t4, the third switch tube Q3 and the fourth switch tube Q4 are turned off synchronously, and the second switch tube Q2 is turned on. At the moment t4-t5, the voltage across the first switch tube Q1 is reduced, and the fourth switch tube Q4 blocks the reverse current. At the moment t5, the first switch tube Q1 is turned on, and the first switch tube Q1 is turned on at zero voltage.

[0085] Furthermore, Fig.10 The control timing diagram of the switch tube in the related art, the waveform diagram of the resonant current and the current waveform diagram of the upper bridge switch tube are shown. Fig.11 The circuit topology and the Fig. 9 The control timing diagram of the first switch tube and the third switch tube, the control timing diagram of the second switch tube and the fourth switch tube, the waveform diagram of the resonant current and the current waveform diagram of the first switch tube are shown. Fig.11 It can be seen from the figure that the circuit topology of this embodiment and Fig. 9 In the switch tube control sequence shown, the reverse recovery current of the first switch tube disappears, thereby preventing the switch device from being damaged by the reverse recovery current.

[0086] In adopting Fig.12 In the control sequence shown in FIG. 1 , at the moment t1-t2, the first switch tube Q1 and the second switch tube Q2 are turned on at the same time, and the current direction is as follows: Fig.13 As shown. At time t2, the first switch tube Q1 is turned off, the second switch tube Q2 is still in the on state, and the fourth switch tube Q4 is turned on. At time t2-t3, after the first switch tube Q1 is turned off, the resonant current generated by the resonant inductor Lr and the resonant capacitor Cr is not zero, and the current flows as shown in Fig.14 As shown, at the moment t2-t3, the resonant current gradually decreases, and the second switch tube Q2 is turned off at this time, and the second switch tube Q2 can achieve approximate ZCS (Zero Current Switch). At the moment t3, the second switch tube Q2 is turned off, and the fourth switch tube Q4 is still in the on state. At the moment t3-t4, the current flows as follows Fig.15 As shown, the current charges the parasitic capacitance of the first switch tube Q1 and the second switch tube Q2. Since the fourth switch tube Q4 is in the on state, the current discharges the parasitic capacitance of the third switch tube Q3, so that the voltage across the third switch tube Q3 is reduced. When the discharge of the parasitic capacitance of the third switch tube Q3 is completed, the voltage across the third switch tube Q3 is 0, and the parasitic diode of the third switch tube Q3 is turned on. At this time, the third switch tube Q3 is controlled to be turned on. Even if the dead time is long, a reverse current will be generated in the circuit. However, due to the blocking effect of the second switch tube Q2, the first switch tube Q1 will not withstand the reverse voltage at the moment of the third switch tube Q3 being turned on, thereby protecting the first switch tube Q1. At time t4, the third switch tube Q3 is turned on. At time t4-t5, the third switch tube Q3 and the fourth switch tube Q4 are turned on, and the current direction is as shown in FIG. Fig.16 At time t5, the third switch tube Q3 is turned off, the fourth switch tube Q4 is still in the on state, and the second switch tube Q2 is turned on. At time t5-t6, as shown Fig.17 As shown, the resonant current decreases, and the fourth switch tube Q4 can achieve approximate ZCS. At time t6, the fourth switch tube Q4 is turned off, and the second switch tube Q2 is still in the on state. At time t6-t7, the current flows as follows Fig.18 As shown, the parasitic capacitance of the first switch tube Q1 is discharged, and the parasitic capacitance of the third switch tube Q3 is charged, so that the first switch tube Q1 can be turned on at zero voltage.

[0087] According to the control method of the switch circuit of the embodiment of the present invention, the fourth switch tube is controlled to be turned on when the first switch tube is turned off, and the second switch tube is controlled to be turned on when the third switch tube is turned off, and the first switch tube and the second switch tube and the third switch tube and the fourth switch tube are respectively controlled to be turned off in a preset order, wherein the first switch tube and the second switch tube are arranged back to back, and the third switch tube and the fourth switch tube are arranged back to back, thereby, the directions of the parasitic diodes of the first switch tube and the second switch tube are opposite, the directions of the parasitic diodes of the third switch tube and the fourth switch tube are opposite, and the second switch tube and the fourth switch tube have a blocking effect on the reverse current, thereby preventing the reverse current generated by the upper / lower bridge switch unit during the dead time.

[0088] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0089] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0090] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0091] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of the features. In the description of the present invention, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0092] In the present invention, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific implementation situation.

[0093] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A switching circuit, characterized in that: The invention comprises at least one bridge arm, wherein the bridge arm comprises an upper bridge switch unit and a lower bridge switch unit, wherein the upper bridge switch unit is configured to prevent the reverse current generated by the lower bridge switch unit during a dead time so that the lower bridge switch unit can be turned on with zero voltage, and the lower bridge switch unit is configured to prevent the reverse current generated by the upper bridge switch unit during the dead time so that the upper bridge switch unit can be turned on with zero voltage.

2. The switch circuit according to claim 1, characterized in that: The upper bridge switch unit includes a first switch tube and a second switch tube connected in series, and the first switch tube and the second switch tube are arranged back to back.

3. The switch circuit according to claim 2, characterized in that: The lower bridge switch unit includes a third switch tube and a fourth switch tube connected in series, and the third switch tube and the fourth switch tube are arranged back to back.

4. The switch circuit according to claim 3, characterized in that: The drain of the first switch tube is suitable for connecting to the positive pole of the power supply, the source of the first switch tube is connected to the source of the second switch tube, the drain of the second switch tube is connected to the drain of the third switch tube, the source of the third switch tube is connected to the source of the fourth switch tube, and the drain of the fourth switch tube is suitable for connecting to the negative pole of the power supply.

5. The switch circuit according to claim 4, characterized in that: A first node is provided between the drain of the second switch tube and the drain of the third switch tube, and the first node is suitable for connecting an inductive device.

6. The switch circuit according to any one of claims 3 to 5, characterized in that: The first switch tube and the second switch tube are turned off synchronously, the third switch tube and the fourth switch tube are turned off synchronously, and the second switch tube and the fourth switch tube are turned on and off complementarily.

7. The switch circuit according to any one of claims 3 to 5, characterized in that: The second switch tube is turned off after a first preset time delay than the first switch tube, the fourth switch tube is turned off after a first preset time delay than the third switch tube, the fourth switch tube is turned on when the first switch tube is turned off, and the second switch tube is turned on when the third switch tube is turned off.

8. The switch circuit according to claim 7, characterized in that: The first preset time is obtained according to the following formula: Among them, T d is the dead time, C gs , C gd , C ds is the junction capacitance of the switch tube, T s is the switching cycle, L m is the excitation inductance, and Δt is the first preset time.

9. A converter, characterized in that: The method comprises a switching circuit according to any one of claims 1 to 8.

10. A power transformation device, characterized in that: Comprising the converter as claimed in claim 9.

11. A method for controlling a switch circuit, characterized in that: The switch circuit includes at least one bridge arm, the bridge arm includes an upper bridge switch unit and a lower bridge switch unit, the upper bridge switch unit includes a first switch tube and a second switch tube connected in series, the first switch tube and the second switch tube are arranged back to back, the lower bridge switch unit includes a third switch tube and a fourth switch tube connected in series, the third switch tube and the fourth switch tube are arranged back to back, and the method includes: The fourth switch tube is controlled to be turned on when the first switch tube is turned off, and the second switch tube is controlled to be turned on when the third switch tube is turned off, and the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube are controlled to be turned off in a preset order.

12. The method according to claim 11, characterized in that Controlling the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube to be turned off in a preset order respectively includes: Control the first switch tube and the second switch tube to be turned off synchronously, and control the third switch tube and the fourth switch tube to be turned off synchronously; or, The second switch tube is controlled to be turned off after a delay of a first preset time compared with the first switch tube, and the fourth switch tube is controlled to be turned off after a delay of a first preset time compared with the third switch tube.

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