Time synchronization circuit and method and electronic equipment

Abstract

The invention provides a time synchronization circuit and method and electronic equipment, and relates to the technical field of cooperative work. The circuit comprises a reference timer used for receiving a time synchronization signal input by an external clock source and determining a reference time value based on the time synchronization signal; the control assembly is used for adjusting the output timing frequency of the output timer based on the reference time value and the output time value of the output timer to obtain a first target frequency; the output timer is used for outputting a target time signal synchronized with an external clock source based on the first target frequency. The method comprises the following steps: receiving a time synchronization signal input by an external clock source through a reference timer, and determining a reference time value based on the time synchronization signal; adjusting the output timing frequency of the output timer through the control component based on the reference time value and the output time value of the output timer to obtain a first target frequency; a target time signal synchronized with the external clock source is output by the output timer based on the first target frequency.

Description

Technical Field

[0001] The present application relates to the field of collaborative work technology, and in particular to a time synchronization circuit, method and electronic device. Background Art

[0002] On servers, computers, embedded devices, IoT nodes, and edge computing terminals, time-synchronized data communications may be required. In addition to the obvious need to synchronize calendar clocks (time synchronization), synchronization of working reference clocks between multiple electronic devices is also a necessary condition for multi-device systems to work together on the timeline.

[0003] Clock synchronization in computers is usually implemented by NTP (Network Time Protocol), which is the most typical time synchronization mechanism. Current computer systems or embedded systems usually contain two different clocks: system clock (system_clock) and steady clock (steady_clock), both of which can be abstracted as counters, and the count value is the time value. The system clock can obtain time and update its own value through the NTP protocol. Ideally, when there is a small difference between the local time and the NTP server time, the difference can be gradually compensated by slightly changing the counting frequency to ensure that the change of local time is continuous and gentle. When the local time and the NTP server time are very different, the local time can only be changed directly. However, directly changing the local time will cause a huge time step, and a negative step will also cause the time to be non-monotonic. The steady clock records the time that has passed since the system was powered on, and usually does not change with any external conditions. The system clocks between multiple devices are basically synchronized when there is network communication and NTP service; the steady clocks between multiple devices are not related, the initial values ​​are not related, and the counting frequency is slightly different due to different frequency sources, so it cannot be used for multi-machine synchronization.

[0004] In current computers or embedded systems, the counting frequency of the hardware clock is determined by the crystal oscillator and cannot be changed by software. Therefore, the system clock is actually implemented by a software counter driven by the interrupt generated by the hardware clock. When the counting frequency needs to be reduced, the software counter pauses counting for a period of time per second (or other unit time), or ignores an interrupt every few interrupts; when the counter frequency needs to be increased, the software counter increases several count values ​​per second (or other unit time), or counts one or more times in an interrupt every few interrupts. This implementation method is not essentially to adjust the counting frequency, but to compensate the counting value at an appropriate time.

[0005] At present, the frequency of software interrupts is usually in the kilohertz range. Therefore, when synchronizing the system clock, millisecond or sub-millisecond time steps or stagnation may occur. If the local clock is slower than the physical time (or the reference time in a multi-machine system), the system clock will make positive compensation when appropriate, resulting in time steps; if the local time is faster than the physical time, the system clock will make negative compensation when appropriate, resulting in time stagnation. When time steps or time stagnation are directly used for millisecond or sub-millisecond time synchronization, they will cause unfavorable situations such as event missed triggering, repeated triggering, and period jitter.

[0006] In order to solve the above problems, in the prior art, time synchronization is usually performed by transmitting synchronization pulses through an external synchronization cable, or by using Beidou or GPS to provide time and generate accurate second pulse synchronization signals. However, this method of time synchronization assisted by external hardware devices is costly, less usable, and has low synchronization accuracy, resulting in poor time synchronization effect and unable to meet the current time synchronization requirements for collaborative work. Summary of the invention

[0007] In view of this, an object of the embodiments of the present application is to provide a time synchronization circuit, method and electronic device to improve the problem of poor time synchronization effect existing in the prior art.

[0008] In order to solve the above problems, in a first aspect, an embodiment of the present application provides a time synchronization circuit, the circuit comprising: a reference timer, a control component and an output timer;

[0009] The control component connects the reference timer and the output timer;

[0010] The reference timer is used to receive a time synchronization signal input from an external clock source, and determine a reference time value based on the time synchronization signal;

[0011] The control component is used to adjust the output timing frequency of the output timer based on the reference time value and the output time value of the output timer to obtain a first target frequency;

[0012] The output timer is used to output a target time signal synchronized with the external clock source based on the first target frequency.

[0013] In the above implementation process, a reference timer can be set to determine the corresponding reference time value according to the time synchronization signal of the external clock source, and then the reference time value and the output time value of the output timer are respectively obtained according to the set control component, so as to adjust the output timing frequency of the output timer according to the difference between the two time values, and obtain the corresponding first target frequency, so that the output timer can be timed based on the first target frequency, thereby outputting the target time signal synchronized with the external clock source time. The timing frequency of the output timer can be fine-tuned in a closed loop according to the difference between the two timers through the control component to achieve the synchronization processing of the two timers and the externally set reference time, without the need for an externally set hardware structure to assist the time synchronization processing, and the timing frequency is adjusted during the adjustment, reducing the time step or time stagnation in the output target time signal and other unfavorable conditions, effectively reducing the unfavorable conditions such as event leakage triggering, repeated triggering, and periodic jitter, and the time synchronization cost is low, the ease of use is good, and the synchronization accuracy is high, which effectively optimizes the effect of time synchronization, is suitable for a variety of systems and devices, and meets a variety of different collaborative time synchronization requirements.

[0014] Optionally, the control component includes: a controller and a first signal conversion component;

[0015] The first signal conversion component is connected to the controller and the output timer;

[0016] The controller is used to determine a time difference between the output time value and the reference time value, and determine a target frequency signal based on the time difference;

[0017] The first signal conversion component is used to perform signal conversion on the received target frequency signal to obtain a first pulse signal for adjusting the output timing frequency of the output timer.

[0018] In the above implementation process, the control component may include a controller for controlling the frequency and a first signal conversion component for converting the frequency signal. The time difference between the two time values ​​can be determined by the controller to determine the speed of the output timer compared to the external clock source according to the specific situation of the time difference, so as to determine the target frequency signal for adjusting the output timing frequency of the output timer. In addition, considering the difference between the frequency signal and the pulse signal for controlling the output timer, the target frequency signal can be converted according to the first signal conversion component to obtain a first pulse signal for adjusting the output timing frequency of the output timer. The output timing frequency of the local output timer can be adjusted accordingly according to the time difference between the external clock source and the local clock source, which can improve the time synchronization accuracy while reducing the unfavorable conditions such as event leakage triggering, repeated triggering, and periodic jitter caused by time steps or time stagnation.

[0019] Optionally, the first signal conversion component includes: a first accumulator and a first comparator;

[0020] The first accumulator is connected to the controller and the first comparator;

[0021] The first accumulator is used to perform periodic accumulation processing on the target frequency signal to obtain a first increment signal;

[0022] The first comparator is used to perform comparison and conversion processing on the first increment signal to obtain the first pulse signal.

[0023] In the above implementation process, the first signal conversion component may include a first accumulator and a first comparator that can generate a controllable frequency pulse signal according to the frequency signal. The first accumulator performs periodic accumulation processing on the received target frequency signal to obtain a corresponding first incremental signal, and the first comparator performs comparison conversion processing on the first incremental signal to obtain a first pulse signal for controlling the output timing frequency of the output timer. Through the signal conversion processing, real-time frequency control of the output timer can be achieved, which effectively improves the efficiency and effectiveness of the control.

[0024] Optionally, if the time difference is a positive value, the target frequency signal is a signal for reducing the output timing frequency;

[0025] If the time difference is a negative value, the target frequency signal is a signal for increasing the output timing frequency.

[0026] In the above implementation process, if the time difference between the output time value and the reference time value is a positive value, it indicates that the timing speed of the output timer is faster than that of the reference timer, that is, the output timing frequency of the output timer is faster, therefore, the target frequency signal output by the controller is a signal to reduce the output timing frequency, so that the output timer can slow down the timing speed and synchronize with the external clock source; if the time difference between the output time value and the reference time value is a negative value, it indicates that the timing speed of the output timer is slower than that of the reference timer, that is, the output timing frequency of the output timer is slower, therefore, the target frequency signal output by the controller is a signal to increase the output timing frequency, so that the output timer can speed up the timing speed and synchronize with the external clock source. The corresponding target frequency signal can be generated according to the specific situation of the time difference to adjust the output timing frequency accordingly, which effectively improves the effectiveness of frequency control.

[0027] Optionally, the circuit further comprises: a prediction component;

[0028] The prediction component is connected to the reference timer;

[0029] The prediction component is used to adjust the reference timing frequency in the step cycle of the reference timer according to two adjacent time synchronization signals and the initial reference time value of the reference timer to obtain a second target frequency;

[0030] The reference timer is used for outputting the reference time value whose step is smaller than a preset value based on the second target frequency.

[0031] In the above implementation process, since the reference timer is timed based on the clock synchronization signal of the external clock source, there may be corresponding time steps or stagnation in the reference timer. In order to effectively improve the synchronization between the reference time value and the external clock source, a corresponding prediction component can also be set in the circuit to adjust the reference timing frequency in the step cycle of the reference timer according to the two adjacent time synchronization signals and the initial reference time value of the reference timer to obtain the corresponding second target frequency, so that the reference timer can be timed at the second target frequency and output a reference time value with a step less than the preset value. The time step degree of the reference timer can be reduced by adjusting the reference timing frequency, thereby improving the effectiveness of the reference time value, and then improving the synchronization between the target time signal and the external clock source.

[0032] Optionally, the prediction component includes: a calculator and a second signal conversion component;

[0033] The second signal conversion component is connected to the calculator and the reference timer;

[0034] The calculator is used to determine a periodic difference value according to two adjacent time synchronization signals and the initial reference time value, and determine a predicted frequency signal based on the periodic difference value;

[0035] The second signal conversion component is used to perform signal conversion on the received predicted frequency signal to obtain a second pulse signal for adjusting the reference timing frequency of the reference timer.

[0036] In the above implementation process, the prediction component may include a calculator for calculating the frequency and a second signal conversion component for converting the frequency signal. The calculator can calculate the periodic difference value according to the two adjacent time synchronization signals and the initial reference time value, so as to judge the step degree of the reference timer according to the specific situation of the periodic difference value, thereby determining the predicted frequency signal for adjusting the reference timing frequency of the reference timer. In addition, considering the difference between the frequency signal and the pulse signal for controlling the reference timer, the predicted frequency signal can be converted according to the second signal conversion component to obtain a second pulse signal for adjusting the reference timing frequency of the reference timer. The reference timing frequency of the local reference timer can be adjusted accordingly according to the periodic difference between the external clock source and the local clock source, thereby further improving the accuracy of time synchronization.

[0037] Optionally, the second signal conversion component includes: a second accumulator and a second comparator;

[0038] The second accumulator is connected to the calculator and the second comparator;

[0039] The second accumulator is used to perform periodic accumulation processing on the predicted frequency signal to obtain a second increment signal;

[0040] The second comparator is used for performing comparison and conversion processing on the second increment signal to obtain the second pulse signal.

[0041] In the above implementation process, the second signal conversion component may include a second accumulator and a second comparator that can generate a controllable frequency pulse signal according to the frequency signal. The second accumulator performs periodic accumulation processing on the received predicted frequency signal to obtain a corresponding second incremental signal, and the second comparator performs comparison conversion processing on the second incremental signal to obtain a second pulse signal that controls the reference timing frequency of the reference timer. Through the signal conversion processing, real-time frequency control of the reference timer can be achieved, which effectively improves the efficiency and effectiveness of the control.

[0042] Optionally, the circuit further comprises: a trigger component;

[0043] The trigger component is connected to the output timer;

[0044] The trigger component is used to trigger a target event according to the target time signal output by the output timer and a preset event rule.

[0045] In the above implementation process, considering the event triggering requirements of the device where the circuit is located, a corresponding trigger component connected to the output timer can also be set in the circuit. The trigger component is preset with event rules specified according to the actual situation of the device, so that the target time signal and time rules can trigger the corresponding target event, thereby realizing data transmission, signal switching and other functions.

[0046] In a second aspect, an embodiment of the present application further provides a time synchronization method, which is applied to the time synchronization circuit described in any one of the above items, and the method includes:

[0047] receiving a time synchronization signal input from an external clock source through a reference timer, and determining a reference time value based on the time synchronization signal;

[0048] The control component adjusts the output timing frequency of the output timer based on the reference time value and the output time value of the output timer to obtain a first target frequency;

[0049] A target time signal synchronized with the external clock source is outputted based on the first target frequency by the output timer.

[0050] In the above implementation process, the corresponding reference time value is determined according to the time synchronization signal of the external clock source through the reference timer, and the reference time value and the output time value of the output timer are respectively obtained through the control component, so that the output timing frequency of the output timer is adjusted according to the difference between the two time values ​​to obtain the corresponding first target frequency, and the output timer is used to perform timing based on the first target frequency to output the target time signal synchronized with the external clock source time.

[0051] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the time synchronization circuit described in any one of the above items.

[0052] In summary, the embodiments of the present application provide a time synchronization circuit, method and electronic device, which can perform closed-loop fine-tuning on the timing frequency of the output timer according to the difference between the two timers through the control component to realize the synchronization processing of the two timers and the externally set reference time, without the need for an external hardware structure to assist the time synchronization processing, and the adjustment is made to the timing frequency, thereby reducing adverse situations such as time steps or time stagnation in the output target time signal, effectively reducing adverse situations such as event missed triggering, repeated triggering, and periodic jitter, and having low time synchronization cost, good ease of use and high synchronization accuracy, effectively optimizing the time synchronization effect, and being suitable for a variety of systems and devices to meet a variety of different time synchronization requirements for collaborative work. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 A schematic diagram of the structure of a time synchronization circuit provided in an embodiment of the present application;

[0055] Figure 2 A schematic diagram of the structure of another time synchronization circuit provided in an embodiment of the present application;

[0056] Figure 3 A frequency adjustment schematic diagram provided in an embodiment of the present application;

[0057] Figure 4 A flowchart of a time synchronization method provided in an embodiment of the present application.

[0058] Icons: 100 - reference timer; 200 - control component; 300 - output timer; 210 - controller; 221 - first accumulator; 222 - first comparator; 400 - prediction component; 410 - calculator; 421 - second accumulator; 422 - second comparator; 500 - trigger component. DETAILED DESCRIPTION

[0059] The technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments of the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the embodiments of the present application.

[0060] The applicant has found that in the prior art, the method of using external hardware devices to assist in time synchronization is costly, less usable, and has low synchronization accuracy, resulting in poor time synchronization effects and being unable to meet the current time synchronization requirements for collaborative work.

[0061] In order to solve the above problems, the present application provides a time synchronization circuit that can adjust the timing frequency of the timer. The time synchronization has low cost, good ease of use and high synchronization accuracy, which effectively optimizes the effect of time synchronization.

[0062] See also Figure 1 , Figure 1A structural schematic diagram of a time synchronization circuit provided in an embodiment of the present application, the time synchronization circuit may include: a reference timer 100, a control component 200 and an output timer 300.

[0063] The control component 200 is connected to the reference timer 100 and the output timer 300. The reference timer 100 is used to receive a time synchronization signal input from an external clock source and determine a reference time value based on the time synchronization signal. The control component 200 is used to adjust the output timing frequency of the output timer 300 based on the reference time value and the output time value of the output timer 300 to obtain a first target frequency. The output timer 300 is used to output a target time signal synchronized with the external clock source based on the first target frequency.

[0064] Optionally, the reference timer 100 and the output timer 300 can be set as corresponding counters with timing functions such as crystal oscillators, and their count values ​​are corresponding time values, so as to abstract the timing into a corresponding counting process.

[0065] The timing frequencies of the two timers can be set according to the time accuracy requirements of the device where the circuit is located. For example, the output timer 300 with a timing accuracy of 1 μs can use a 1 MHz base frequency and increase by one each time under the 1 MHz clock drive. The timing frequency can also be other values ​​such as 10 MHz, 100 kHz, etc., corresponding to different timing accuracies.

[0066] It should be noted that the reference timer 100 can be connected to communicate with other external devices. The reference timer 100 is a counter that directly accepts an externally set time value. The count value can be directly set externally. The set value comes from a reference time outside the system (i.e., an external clock source), such as an NTP time server, an atomic clock, or other device used as a multi-machine time reference. The corresponding reference time value can be determined based on the time synchronization signal of the external clock source.

[0067] Among them, the reference time value and the output time value of the output timer 300 can be obtained respectively according to the set control component 200, so that the output timing frequency of the output timer 300 can be adjusted according to the difference between the two time values, and the corresponding first target frequency can be obtained, so that the output timer 300 can be timed based on the first target frequency, thereby outputting a target time signal synchronized with the external clock source time.

[0068] Optionally, the output time value is the time value obtained by the initial timer based on the unadjusted initial output timing frequency. The control component 200 may include various types of control chips or computing chips, which are provided with corresponding algorithms, which can perform calculations based on the reference time value and the output time value to obtain the corresponding first target frequency.

[0069] For example, the calculation parameters in the control component 200 can be adjusted through simulation. Within the available parameter range, appropriate adjustment of the parameter values ​​can improve the balance between synchronization speed, synchronization stability, and stability of the event trigger period to obtain a stable and high-precision time synchronization function.

[0070] Optionally, the output of the control component 200 may be limited, and the frequency adjustment range of the output timer 300 may be limited, so that the time synchronization process is more relaxed and the time difference of the target time signal is further reduced.

[0071] exist Figure 1 In the illustrated embodiment, the timing frequency of the output timer 300 can be fine-tuned in a closed loop according to the difference between the two timers through the control component 200, so as to realize the synchronization processing of the two timers and the externally set reference time, without the need for an external hardware structure to assist the time synchronization processing, and the adjustment is made to the timing frequency, thereby reducing the unfavorable situations such as time steps or time stagnation in the output target time signal, and effectively reducing the unfavorable situations such as event missed triggering, repeated triggering, and periodic jitter, etc., the time synchronization cost is low, the ease of use is good, and the synchronization accuracy is high, which effectively optimizes the time synchronization effect, is suitable for a variety of systems and equipment, and meets a variety of different collaborative time synchronization requirements.

[0072] See also Figure 2 , Figure 2 A schematic diagram of another time synchronization circuit provided by an embodiment of the present application, wherein the control component 200 may include: a controller 210 and a first signal conversion component, wherein the first signal conversion component connects the controller 210 and the output timer 300.

[0073] Optionally, the output end of the output timer 300 can be connected to the control component 200 to achieve corresponding closed-loop control. The controller 210 is used to determine the time difference between the output time value and the reference time value, and determine the target frequency signal based on the time difference. The first signal conversion component is used to perform signal conversion on the received target frequency signal to obtain a first pulse signal for adjusting the output timing frequency of the output timer 300. The control component 200 may include a controller 210 for controlling the frequency and a first signal conversion component for converting the frequency signal. The time difference between the two time values ​​can be determined by the controller 210 to determine the speed of the output timer 300 compared to the external clock source according to the specific situation of the time difference, thereby determining the target frequency signal for adjusting the output timing frequency of the output timer 300. In addition, considering the difference between the frequency signal and the pulse signal controlling the output timer 300, the target frequency signal can be converted according to the first signal conversion component to obtain a first pulse signal for adjusting the output timing frequency of the output timer 300. The output timing frequency of the local output timer 300 can be adjusted accordingly according to the time difference between the external clock source and the local clock source. While improving the time synchronization accuracy, it can also reduce adverse situations such as event missed triggering, repeated triggering, and periodic jitter caused by time steps or time stagnation.

[0074] It should be noted that the target frequency signal output by the controller 210 may be a corresponding frequency control word, which is a set of binary numbers and can control and manage the frequency of the radio wave.

[0075] By way of example, the controller 210 may include various types of control elements, such as a PID (Proportion Integration Differentiation) controller 210, a single P controller 210, or a PI controller 210, etc., which can output a control quantity to fine-tune the timing frequency. The controller 210 can be selected based on actual time synchronization accuracy requirements, device cost requirements, etc.

[0076] Optionally, the first signal conversion component may include: a first accumulator 221 and a first comparator 222 , and the first accumulator 221 is connected to the controller 210 and the first comparator 222 .

[0077] The first accumulator 221 is used to perform periodic accumulation processing on the target frequency signal to obtain a first increment signal, and the first comparator 222 is used to perform comparative conversion processing on the first increment signal to obtain a first pulse signal. The first accumulator 221 performs periodic accumulation processing on the received target frequency signal to obtain a corresponding first increment signal, and the first comparator 222 performs comparative conversion processing on the first increment signal to obtain a first pulse signal for controlling the output timing frequency of the output timer 300. Through the signal conversion processing, real-time frequency control of the output timer 300 can be achieved, which effectively improves the efficiency and effectiveness of the control.

[0078] For example, the first comparator 222 may be a zero-crossing comparator, and the first accumulator 221 and the first comparator 222 are used to generate pulses with controllable frequency. s , the bit width of the first accumulator 221 is W, that is, the modulus is 2 W , the frequency control word of the input target frequency signal is k, then the accumulator increment is k / 2 in each working clock cycle W Week, increments per second are f s k / 2 W The pulse frequency f output by the first comparator 222 is the number of cycles of the accumulator increment per second: f=kf s / 2 W . s =100MHz, W = 48, the minimum step of f is: 100MHz / 2 48 ≈0.36μHz, capable of outputting the first pulse signal for high-precision time synchronization.

[0079] Optionally, the output timer 300 is driven by the first pulse signal output by the first comparator 222, and its count value is the synchronized time value, i.e., the target time signal. In practical applications, the target time signal can be the number of microseconds after the circuit is powered on, the number of microseconds after a certain reset, or the number of microseconds since the Unix Epoch after external initialization. If the latter is used, the time can be directly converted into calendar time, which can replace the system clock.

[0080] It should be noted that if the time difference between the output time value and the reference time value is a positive value, it indicates that the timing speed of the output timer 300 is faster than that of the reference timer 100, that is, the output timing frequency of the output timer 300 is faster, therefore, the target frequency signal output by the controller 210 is a signal to reduce the output timing frequency, so that the output timer 300 can slow down the timing speed and synchronize with the external clock source; if the time difference between the output time value and the reference time value is a negative value, it indicates that the timing speed of the output timer 300 is slower than that of the reference timer 100, that is, the output timing frequency of the output timer 300 is slower, therefore, the target frequency signal output by the controller 210 is a signal to increase the output timing frequency, so that the output timer 300 can speed up the timing speed and synchronize with the external clock source. A corresponding target frequency signal can be generated according to the specific situation of the time difference to adjust the output timing frequency accordingly, which effectively improves the effectiveness of frequency control.

[0081] Optionally, since the reference timer 100 is timed based on the clock synchronization signal of the external clock source, there may be corresponding time steps or stagnation in the reference timer 100. The steps of the reference timer 100 are related to the period of setting the reference count value and the frequency difference between the two places. The device used as the basic frequency source in most electronic systems is a low-cost crystal oscillator with an accuracy of 10ppm. Accordingly, if the period of the reference timer 100 is set to 1s, its steps will be in the order of 10μs, the fluctuation of the time counter can be controlled within 10μs, and the inherent deviation of the time count from the external clock source will also be in the order of 10μs. If more accurate synchronization is required, the period of setting the reference timer 100 can be reduced, and it is easy to achieve microsecond or even sub-microsecond synchronization accuracy, that is, to improve the effectiveness of the reference count value by frequent synchronization.

[0082] In another way, in order to effectively improve the synchronization between the reference time value and the external clock source, further reduce the requirements for the setting period of the reference timer 100, or achieve more accurate synchronization while increasing the setting period of the reference timer 100, the circuit may also include: a prediction component 400, and the prediction component 400 is connected to the reference timer 100.

[0083] Among them, the prediction component 400 is used to adjust the reference timing frequency in the step cycle of the reference timer 100 according to two adjacent time synchronization signals and the initial reference time value of the reference timer 100 to obtain a second target frequency, and the reference timer 100 is used to output a reference time value with a step smaller than a preset value based on the second target frequency. A corresponding prediction component 400 can be set in the circuit to adjust the reference timing frequency in the step cycle of the reference timer 100 according to two adjacent time synchronization signals and the initial reference time value of the reference timer 100 to obtain the corresponding second target frequency, so that the reference timer 100 can be timed at the second target frequency and output a reference time value with a step smaller than the preset value. The time step degree of the reference timer 100 can be reduced by adjusting the reference timing frequency, thereby improving the validity of the reference time value, and further improving the synchronization of the target time signal with the external clock source.

[0084] For example, the preset value may be a time value set according to the timing accuracy and synchronization requirements of the reference timer 100 to reduce the step degree of the reference timer 100 and obtain a reference time value closer to the external clock source.

[0085] Optionally, the prediction component 400 may include: a calculator 410 and a second signal conversion component, wherein the second signal conversion component connects the calculator 410 and the reference timer 100 .

[0086] The calculator 410 is used to determine the periodic difference value according to two adjacent time synchronization signals and the initial reference time value, and determine the predicted frequency signal based on the periodic difference value, and the second signal conversion component is used to perform signal conversion on the received predicted frequency signal to obtain a second pulse signal for adjusting the reference timing frequency of the reference timer 100. The periodic difference value can be calculated by the calculator 410 according to the two adjacent time synchronization signals and the initial reference time value, so as to judge the step degree of the reference timer 100 according to the specific situation of the periodic difference value, thereby determining the predicted frequency signal for adjusting the reference timing frequency of the reference timer 100. In addition, considering the difference between the frequency signal and the pulse signal for controlling the reference timer 100, the predicted frequency signal can be converted by the second signal conversion component to obtain the second pulse signal for adjusting the reference timing frequency of the reference timer 100. The reference timing frequency of the local reference timer 100 can be adjusted accordingly according to the periodic difference between the external clock source and the local clock source, further improving the accuracy of time synchronization.

[0087] Optionally, the second signal conversion component may include: a second accumulator 421 and a second comparator 422 , and the second accumulator 421 is connected to the calculator 410 and the second comparator 422 .

[0088] The second accumulator 421 is used to perform periodic accumulation processing on the predicted frequency signal to obtain a second increment signal, and the second comparator 422 is used to perform comparative conversion processing on the second increment signal to obtain a second pulse signal. The second accumulator 421 performs periodic accumulation processing on the received predicted frequency signal to obtain a corresponding second increment signal, and the second comparator 422 performs comparative conversion processing on the second increment signal to obtain a corresponding second pulse signal for controlling the reference timing frequency of the reference timer 100. Through the signal conversion processing, real-time frequency control of the reference timer 100 can be achieved, which effectively improves the efficiency and effectiveness of the control.

[0089] For example, the calculator 410 may also be configured as a device capable of calculating frequency, such as a corresponding PID controller 210, a single P controller 210, or a PI controller 210. The calculation method of the second accumulator 421 and the second comparator 422 is similar to that of the first accumulator 221 and the first comparator 222, and will not be described in detail.

[0090] Optionally, when the calculator 410 performs calculations, the reference timing frequency of the reference timer 100 may be adjusted by the ideal value of the reference timer 100 corresponding to each external time synchronization signal, the actual value of the reference timer 100 itself, and the ideal value and actual value corresponding to the last time synchronization signal. The output predicted frequency signal is also set to the corresponding frequency control word, denoted as f k When the reference timer 100 is set once, the actual value corresponding to the two adjacent time synchronization signals is t′ k and t′ k-1 , the ideal value is t k and t k-1 , the calculation formula for the predicted frequency signal is:

[0091]

[0092] When setting for the first time, f0=basic frequency control word, that is, the initial reference timing frequency of the reference timer 100 that has not been adjusted, is taken, and t0′0=t0=the initial setting value of the reference timer 100 is taken.

[0093] After adding the prediction component 400 to the reference timer 100 for processing, unless the counting frequency of the physical time (external clock source) drifts, the reference timer 100 can maintain a very small error with the external reference time for a long time, without the need for frequent synchronization processing. The step when setting the reference timer 100 will also be significantly reduced, further improving the effectiveness of the reference time value. It is suitable for application scenarios that have more stringent requirements on synchronization accuracy and where the setting cycle of the reference timer 100 may be longer due to external conditions.

[0094] Optionally, considering the event triggering requirements of the device in which the circuit is located, the circuit may further include: a trigger component 500, which is connected to the output timer 300. The trigger component 500 is used to trigger the target event according to the target time signal output by the output timer 300 and the preset event rule. The trigger component 500 is preset with event rules specified according to the actual situation of the device, so that the target time signal and the time rule can trigger the corresponding target event, realizing multiple functions such as data transmission and signal switching.

[0095] For example, the trigger component 500 can match the preset time value in the event rule with the target time signal, and when the target time signal is the same as the preset time value, output a pulse to trigger a related event or generate an interrupt request to the processor system.

[0096] Optionally, the circuit may also include corresponding interfaces, such as register circuit interfaces, etc., to adapt to the internal bus of a system such as a digital circuit system, so that the entire circuit can be connected to other external devices or components, thereby realizing data transmission and master control access functions.

[0097] Optionally, the first signal conversion component and the second signal conversion component can also be implemented using structures such as a phase-locked loop frequency synthesizer, DDS (Direct Digital Synthesizer), VCO (Voltage-Controlled Oscillator), and the bias voltage of an analog voltage-controlled crystal oscillator circuit to achieve corresponding signal conversion functions.

[0098] Optionally, the controller 210 and the calculator 410 may also use analog control circuits, such as an analog PI controller 210 composed of an operational amplifier to implement frequency calculation.

[0099] Optionally, see Figure 3 , Figure 3 A frequency adjustment diagram is provided for an embodiment of the present application. In the embodiment provided by the present application, the output timer 300 is driven by a variable frequency pulse, and the value of each self-increment is a constant (usually 1). After the value of the reference timer 100 is set by external synchronization information, from a macroscopic point of view, the time counter changes the counting frequency, and from a microscopic point of view, the counting time interval (period) is changed. The time value does not have a step or stagnation, and is monotonous and continuous. Figure 3 As shown in the figure, the details of the time counting cycle adjustment of the present solution are shown. The horizontal axis is the physical time in the time dimension, and the vertical axis is the number of clock counts. When the local time is slower, the input pulse cycle of the output timer 300 becomes smaller. For example, from T P0 Change to T P1When the local time is faster, the input pulse period of the output timer 300 becomes larger, for example, from T P1 Change to T P2 Under the effect of closed-loop frequency fine-tuning, the output timer 300 will have a shape similar to that after smooth filtering, and its overall curve is consistent with the external clock source, thus achieving time synchronization with the external clock source.

[0100] Therefore, the present application can achieve monotonic, continuous and gentle time synchronization adjustment through closed-loop feedback control of the counting frequency, without the need for upper-level software algorithms, and can achieve microsecond-level leak-free triggering, repeated triggering, and periodically stable time synchronization. The synchronization accuracy can reach the microsecond level and the precision can reach the sub-microsecond level, thereby achieving high-precision time synchronization. The overall solution is implemented by a pure digital circuit, which is easy to implement in digital ICs or systems such as SoC (System on a Chip), ASIC (Application-Specific Integrated Circuit), and FPGA (Field Programmable Gate Array).

[0101] Optionally, see Figure 4 , Figure 4 A flowchart of a time synchronization method provided in an embodiment of the present application, the method may include steps S610-S630.

[0102] Step S610: receiving a time synchronization signal input from an external clock source through a reference timer, and determining a reference time value based on the time synchronization signal.

[0103] Step S620: adjusting the output timing frequency of the output timer based on the reference time value and the output time value of the output timer by the control component to obtain a first target frequency.

[0104] Step S630: outputting a target time signal synchronized with an external clock source based on a first target frequency through an output timer.

[0105] exist Figure 4 In the illustrated embodiment, a corresponding reference time value is determined according to a time synchronization signal of an external clock source by a reference timer, and the reference time value and the output time value of the output timer are respectively acquired by a control component, thereby adjusting the output timing frequency of the output timer according to the difference between the two time values ​​to obtain a corresponding first target frequency, and the output timer performs timing based on the first target frequency to output a target time signal synchronized with the external clock source time.

[0106] An embodiment of the present application also provides an electronic device, which includes the time synchronization circuit provided in the present application. The electronic device can be a server, a personal computer (PC), a tablet computer, a smart phone, a personal digital assistant (PDA), and other types of electronic devices.

[0107] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0108] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0109] The above description is only an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0110] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

[0111] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

Claims

1. A time synchronization circuit, characterized in that: The circuit includes: a reference timer, a control component and an output timer; The control component connects the reference timer and the output timer; The reference timer is used to receive a time synchronization signal input from an external clock source, and determine a reference time value based on the time synchronization signal; The control component is used to adjust the output timing frequency of the output timer based on the reference time value and the output time value of the output timer to obtain a first target frequency; The output timer is used to output a target time signal synchronized with the external clock source based on the first target frequency.

2. The circuit according to claim 1, characterized in that in, The control component includes: a controller and a first signal conversion component; The first signal conversion component is connected to the controller and the output timer; The controller is used to determine a time difference between the output time value and the reference time value, and determine a target frequency signal based on the time difference; The first signal conversion component is used to perform signal conversion on the received target frequency signal to obtain a first pulse signal for adjusting the output timing frequency of the output timer.

3. The circuit according to claim 2, characterized in that in, The first signal conversion component includes: a first accumulator and a first comparator; The first accumulator is connected to the controller and the first comparator; The first accumulator is used to perform periodic accumulation processing on the target frequency signal to obtain a first increment signal; The first comparator is used to perform comparison and conversion processing on the first increment signal to obtain the first pulse signal.

4. The circuit according to claim 2, characterized in that in, If the time difference is a positive value, the target frequency signal is a signal that reduces the output timing frequency; If the time difference is a negative value, the target frequency signal is a signal for increasing the output timing frequency.

5. The circuit according to any one of claims 1 to 4, characterized in that: The circuit also includes: a prediction component; The prediction component is connected to the reference timer; The prediction component is used to adjust the reference timing frequency in the step cycle of the reference timer according to two adjacent time synchronization signals and the initial reference time value of the reference timer to obtain a second target frequency; The reference timer is used for outputting the reference time value whose step is smaller than a preset value based on the second target frequency.

6. The circuit according to claim 5, characterized in that in, The prediction component includes: a calculator and a second signal conversion component; The second signal conversion component is connected to the calculator and the reference timer; The calculator is used to determine a periodic difference value according to two adjacent time synchronization signals and the initial reference time value, and determine a predicted frequency signal based on the periodic difference value; The second signal conversion component is used to perform signal conversion on the received predicted frequency signal to obtain a second pulse signal for adjusting the reference timing frequency of the reference timer.

7. The circuit according to claim 6, characterized in that in, The second signal conversion component includes: a second accumulator and a second comparator; The second accumulator is connected to the calculator and the second comparator; The second accumulator is used to perform periodic accumulation processing on the predicted frequency signal to obtain a second increment signal; The second comparator is used for performing comparison and conversion processing on the second increment signal to obtain the second pulse signal.

8. The circuit according to claim 1, characterized in that The circuit further comprises: a trigger component; The trigger component is connected to the output timer; The trigger component is used to trigger a target event according to the target time signal output by the output timer and a preset event rule.

9. A time synchronization method, characterized in that: The method is applied to the time synchronization circuit according to any one of claims 1 to 8, and the method comprises: receiving a time synchronization signal input from an external clock source through a reference timer, and determining a reference time value based on the time synchronization signal; The control component adjusts the output timing frequency of the output timer based on the reference time value and the output time value of the output timer to obtain a first target frequency; A target time signal synchronized with the external clock source is outputted based on the first target frequency by the output timer.

10. An electronic device, characterized in that: The electronic device comprises the time synchronization circuit according to any one of claims 1-8.

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