Semiconductor structure and method of fabricating the same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate and a storage structure. The substrate is provided with a first contact pad, which comprises a first type of contact pad and a second type of contact pad. The storage structure is arranged on the substrate and comprises first capacitors and second capacitors arranged in layers. Connection plugs are arranged between adjacent first capacitors. The first capacitors are connected to the first type of contact pad, and the second capacitors are connected to the second type of contact pad through the connection plugs. The cross-sectional area of the connection plug is smaller than that of the first capacitor. The semiconductor structure of the present disclosure can increase the critical dimension of the first capacitor and the second capacitor and reduce the aspect ratio of the first capacitor and the second capacitor while avoiding short circuit between adjacent capacitors and open circuit of the capacitors, thereby improving the capacitance, and further improving the performance of the semiconductor structure while ensuring the yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] Capacitors are important components in chips, and their size affects chip performance. As chip size continues to shrink and storage density increases, capacitors are distributed more and more densely in chips. Usually, increasing the aspect ratio of the capacitor is used to meet the capacitor size requirements.

[0003] However, the aforementioned capacitors are prone to short circuits and open circuits, which can affect chip yield. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a semiconductor structure and a method for fabricating the same.

[0006] A first aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0007] A substrate, wherein a first contact pad is disposed on the substrate, the first contact pad including a first type of contact pad and a second type of contact pad;

[0008] A storage structure is disposed on the substrate. The storage structure includes a first capacitor and a second capacitor stacked together. A connecting plug is disposed between adjacent first capacitors. The first capacitor is connected to a first type of contact pad. The second capacitor is connected to a second type of contact pad through the connecting plug.

[0009] The cross-sectional area of ​​the connecting plug is smaller than the cross-sectional area of ​​the first capacitor.

[0010] In some embodiments of this disclosure, the projections of the first capacitor and the second capacitor on the substrate are staggered or alternately arranged.

[0011] In some embodiments of this disclosure, the first contact pads are arranged in an array.

[0012] In a row of first contact pads, at least one second type of contact pad is provided between adjacent first type of contact pads;

[0013] In a row of first contact pads, at least one second type of contact pad is disposed between adjacent first type contact pads.

[0014] In some embodiments of this disclosure, the storage structure further includes a first conductive layer covering the first capacitor and the connection plug, and a second conductive layer covering the second capacitor, wherein the first conductive layer and the second conductive layer are in contact at the outermost periphery of the first capacitor and the second capacitor.

[0015] In some embodiments of this disclosure, an isolation layer is provided between the first capacitor and the second capacitor, and a second contact pad is provided in the isolation layer, wherein at least a portion of the second contact pad connects the connection plug to the second capacitor.

[0016] In some embodiments of this disclosure, the top surface of the second contact pad is flush with the top surface of the insulating layer; or,

[0017] The top surface of the second contact pad is lower than the top surface of the isolation layer, and an opening is provided on the isolation layer at a position corresponding to the second contact pad, through which at least a portion of the top surface of the second contact pad is exposed.

[0018] In some embodiments of this disclosure, the aspect ratio of the first capacitor and the second capacitor is 16-32; and / or,

[0019] The first capacitor and the second capacitor have the same height; and / or,

[0020] The heights of both the first capacitor and the second capacitor are 800-1080 nm;

[0021] The diameters of both the first capacitor and the second capacitor are 40-75 nm.

[0022] A second aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0023] A substrate is provided, wherein a first contact pad is disposed on the substrate, the first contact pad including a first type of contact pad and a second type of contact pad;

[0024] A first capacitor and a second capacitor are formed on the substrate in sequence, wherein a connecting plug is provided between adjacent first capacitors, the first capacitor is connected to a first type of contact pad, and the second capacitor is connected to a second type of contact pad through the connecting plug;

[0025] The cross-sectional area of ​​the connecting plug is smaller than the cross-sectional area of ​​the first capacitor.

[0026] In some embodiments of this disclosure, the first contact pads are arranged in an array, and at least one second type of contact pad is disposed between adjacent first type contact pads. The step of forming a first capacitor and a second capacitor stacked sequentially on the substrate includes:

[0027] A first capacitor is formed on the substrate to contact the first type of contact pad;

[0028] A first conductive layer is formed to cover the first capacitor;

[0029] A through-hole is formed in the first conductive layer, the through-hole exposing the top surface of the second type of contact pad;

[0030] The connecting plug is formed within the through hole, and the bottom end of the connecting plug contacts the second type of contact pad;

[0031] A second capacitor is formed on the first capacitor, and the second capacitor is connected to the connection plug;

[0032] A second conductive layer is formed to cover the second capacitor, and the second conductive layer and the first conductive layer are in contact at the outermost periphery of the first capacitor and the second capacitor.

[0033] In some embodiments of this disclosure, before the connecting plug is formed in the through hole, the manufacturing method further includes:

[0034] A first insulating material layer is formed on the first conductive layer, and the first insulating material layer covers the sidewall of the through hole and the top surface of the first conductive layer;

[0035] The connecting plug is formed within the through hole, comprising:

[0036] A conductive material layer is formed on the first insulating material layer, the conductive material layer covers the top surface of the first insulating material layer and fills the space enclosed by the first insulating material layer in the through hole, the first insulating material layer and the conductive material layer located in the through hole constitute the connecting plug;

[0037] Before forming the second capacitor on the first capacitor, the manufacturing method further includes:

[0038] The conductive material layer covering the top surface of the first insulating material layer is patterned to form a second contact pad;

[0039] A second insulating material layer is formed, which covers the first insulating material layer and exposes at least a portion of the top surface of the second contact pad. The first and second insulating material layers constitute an insulating layer, wherein the second contact pad is located in the insulating layer, and at least a portion of the second contact pad is used to connect the connection plug to the second capacitor.

[0040] The semiconductor structure and its fabrication method provided in this disclosure have the following beneficial effects:

[0041] By layering the capacitors in the memory structure, the first capacitor, closer to the substrate, is directly connected to the first contact pad on the substrate, while the second capacitor, farther from the substrate, is connected to the first contact pad through a connecting plug between the first capacitors. This reduces the number of capacitors in a single capacitor layer, and the cross-sectional area of ​​the connecting plug is smaller than that of the first capacitor. Therefore, while avoiding short circuits between adjacent capacitors and open circuits within the capacitors themselves, the critical dimensions of the first and second capacitors can be increased and their aspect ratios reduced, thereby increasing the capacitance. This, in turn, improves the performance of the semiconductor structure while ensuring its yield.

[0042] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0044] Figure 1 It is a structural diagram of a semiconductor structure in related technologies;

[0045] Figure 2 This is a top view of a substrate illustrating a semiconductor structure according to an exemplary embodiment;

[0046] Figure 3 This is a top view of a substrate of a semiconductor structure illustrated according to another exemplary embodiment;

[0047] Figure 4 This is a structural diagram illustrating a semiconductor structure forming an initial support layer and an initial sacrificial layer according to an exemplary embodiment;

[0048] Figure 5 This is a structural diagram illustrating a semiconductor structure forming a support layer and a sacrificial layer according to an exemplary embodiment;

[0049] Figure 6 This is a structural diagram illustrating a semiconductor structure forming a first lower electrode according to an exemplary embodiment;

[0050] Figure 7 This is a structural diagram illustrating a semiconductor structure forming a first dielectric layer and a first upper electrode, according to an exemplary embodiment.

[0051] Figure 8 This is a structural diagram of a semiconductor structure forming a first conductive layer according to an exemplary embodiment;

[0052] Figure 9 This is a structural diagram illustrating a semiconductor structure forming a through-hole according to an exemplary embodiment;

[0053] Figure 10 This is a structural diagram illustrating a semiconductor structure forming a first insulating material layer according to an exemplary embodiment;

[0054] Figure 11 This is a structural diagram illustrating a semiconductor structure forming a conductive material layer according to an exemplary embodiment;

[0055] Figure 12 This is a structural diagram illustrating a semiconductor structure forming a second contact pad according to an exemplary embodiment;

[0056] Figure 13 This is a structural diagram illustrating a semiconductor structure forming a second isolation material layer according to an exemplary embodiment;

[0057] Figure 14 yes Figure 13 Enlarged view of point A in the middle;

[0058] Figure 15 This is a structural diagram illustrating a semiconductor structure forming a second capacitor according to an exemplary embodiment;

[0059] Figure 16 This is a structural diagram of a semiconductor structure forming a support structure according to another exemplary embodiment;

[0060] Figure 17 This is a structural diagram illustrating a semiconductor structure forming a first lower electrode, a first dielectric layer, and a first upper electrode according to another exemplary embodiment;

[0061] Figure 18 This is a structural diagram of a semiconductor structure forming a first conductive layer according to another exemplary embodiment;

[0062] Figure 19 This is a structural diagram of a semiconductor structure forming a through-hole according to another exemplary embodiment;

[0063] Figure 20 This is a structural diagram of a semiconductor structure forming a first insulating material layer, according to another exemplary embodiment;

[0064] Figure 21 This is a structural diagram of a semiconductor structure forming a conductive material layer according to another exemplary embodiment;

[0065] Figure 22 This is a structural diagram illustrating a semiconductor structure forming a second contact pad and a second insulating material layer according to another exemplary embodiment;

[0066] Figure 23 This is a structural diagram of a semiconductor structure forming a second capacitor according to another exemplary embodiment;

[0067] Figure 24 This is a structural diagram of a semiconductor structure shown according to yet another exemplary embodiment;

[0068] Figure 25 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0069] Figure 26 This is a flowchart illustrating a method for fabricating a semiconductor structure, according to an exemplary embodiment, of forming a first capacitor and a second capacitor.

[0070] Figure label:

[0071] 1. Substrate; 2. Storage structure; 201. First capacitor; 2011. First upper electrode; 2012. First dielectric layer; 2013. First lower electrode; 202. Second capacitor; 2021. Second upper electrode; 2022. Second dielectric layer; 2023. Second lower electrode; 203. Third capacitor; 3. First contact pad; 301. First type contact pad; 302. Second type contact pad; 4. Connecting plug; 5. First conductive layer; 6. Second conductive layer; 7. Isolation layer; 701. First isolation material layer; 702. Second isolation material layer; 8. Second contact pad; 801. Third type contact pad; 802. Fourth type contact pad; 9. Support structure; 10. Initial support layer; 11. Initial sacrificial layer; 12. Support layer; 13. Sacrificial layer; 14. Through-hole; 15. Capacitor via; 16. Conductive plug; 21. Conductive material layer; 22. Third contact pad.

[0072] 1' Substrate; 2' Storage structure; 9' Support structure; 18 Contact pad; 19 Capacitor; 1901 Lower electrode; 1902 Dielectric layer; 1903 Upper electrode; 20 Conductive layer. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0074] As semiconductor structure dimensions continue to shrink and storage density continues to increase, such as in Dynamic Random Access Memory (DRAM), methods like increasing the aspect ratio of capacitors are typically used to meet capacitance requirements. However, these capacitors are prone to short circuits and open circuits, thus affecting chip yield. (Reference) Figure 1 The semiconductor structure in the related technology includes a substrate 1' and a memory structure 2' disposed on the substrate 1'. The substrate 1' includes a plurality of contact pads 18 arranged in an array, and the memory structure 2' includes a capacitor 19 corresponding to each contact pad 18. The capacitor 19 includes a lower electrode 1901, a dielectric layer 1902 and an upper electrode 1903 stacked together. The sidewall of the lower electrode 1901 is provided with a support structure 9' for supporting the capacitor 19. The bottom of the lower electrode 1901 is electrically connected to the contact pads 18. The semiconductor structure also includes a conductive layer 20 covering each capacitor 19.

[0075] To meet storage density requirements, capacitors in semiconductor structures are arranged densely. To meet capacitor size requirements, capacitors have a large depth-to-width ratio. For example, if the critical dimension (CD) of capacitor 19 is set to 30-60 nm, then if the critical dimension (CD) of capacitor 19 is set to be large, the spacing between capacitors 19 will be small, which can easily lead to short circuits between adjacent capacitors 19. On the other hand, if the critical dimension of capacitor 19 is set to be small, it will increase the manufacturing difficulty of capacitor 19, and capacitor 19 is prone to open circuit problems during the manufacturing process, affecting the yield of semiconductor structures.

[0076] Based on this, an exemplary embodiment of the present disclosure provides a semiconductor structure and a method for fabricating the same, wherein the capacitors of the semiconductor structure are arranged in layers. The first capacitor 201, which is close to the substrate, is directly connected to the first contact pad 3 on the substrate 1, and the second capacitor 202, which is far from the substrate 1, is connected to the first contact pad 3 through a connecting plug 4 between the first capacitors 201. In this way, the number of capacitors in a single capacitor layer can be reduced, and the cross-sectional area of ​​the connecting plug 4 is smaller than that of the first capacitor 201. Therefore, while avoiding short circuits between adjacent capacitors and open circuits within the capacitors themselves, the critical dimensions of the first capacitor 201 and the second capacitor 202 can be increased and the aspect ratio of the first capacitor 201 and the second capacitor 202 can be reduced, thereby increasing the capacitor size and improving the performance of the semiconductor structure while ensuring the yield of the semiconductor structure.

[0077] This disclosure provides an exemplary embodiment of a semiconductor structure, with reference to... Figure 15 The semiconductor structure includes a substrate 1 and a memory structure 2. A first contact pad 3 is disposed on the substrate 1. The first contact pad 3 includes a first type of contact pad 301 and a second type of contact pad 302.

[0078] Substrate 1 can be, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a SiGe substrate, silicon-on-insulator (SOI) or germanium-on-insulator (GOI), etc., for supporting the storage structure 2 thereon. Substrate 1 can also be a semiconductor substrate with a device structure; for example, a transistor can be formed on substrate 1. The first type of contact pad 301 and the second type of contact pad 302 can be electrically connected to the source / drain of the transistor. The first type of contact pad 301 and the second type of contact pad 302 can be made of the same material, such as conductive materials like copper or tungsten.

[0079] Storage structure 2 is disposed on substrate 1, as referenced. Figure 15 The storage structure 2 includes a first capacitor 201 and a second capacitor 202 stacked together.

[0080] Among them, reference Figure 13 as well as Figure 22 A connecting plug 4 is provided between adjacent first capacitors 201. The first capacitor 201 is connected to a first type of contact pad 301, and the second capacitor 202 is connected to a second type of contact pad 302 through the connecting plug 4. The cross-sectional area of ​​the connecting plug 4 is smaller than that of the first capacitor 201. Here, the cross-sectional area refers to the area of ​​the surface intercepted by a plane parallel to the substrate. For example, the cross-sectional area of ​​the connecting plug 4 can be a through-hole 14 for accommodating the connecting plug 4 (see...). Figure 9 The cross-sectional area of ​​the first capacitor 201 can be, for example, the cross-sectional area of ​​the capacitor hole 15 used to accommodate the first capacitor 201.

[0081] Understandably, the capacitors in a storage structure can be, for example... Figure 15 The two layers shown can also be configured as follows: Figure 24 The three or more layers shown can be specifically configured according to actual needs. When the capacitors in the storage structure are three or more layers, for example, when the capacitors are divided into N layers and N is greater than or equal to 3, each capacitor layer has multiple capacitors that are connected to different first contact pads 3. For example, the capacitors in the first capacitor layer are directly connected to the first type of contact pad 301, and the capacitors in the nth capacitor layer are connected to the second type of contact pad 302 through the connecting plugs 4 from the (n-1)th layer to the first layer. Among the capacitor layers from the first to the (N-1)th layer, the cross-sectional area of ​​the connecting plugs 4 located in the same capacitor layer is smaller than the cross-sectional area of ​​the capacitor.

[0082] In this embodiment, the capacitors in the storage structure are arranged in layers. The first capacitor, which is closer to the substrate, is directly connected to the first contact pad on the substrate, while the second capacitor, which is farther from the substrate, is connected to the first contact pad through a connecting plug between the first capacitors. This reduces the number of capacitors in a single capacitor layer. Since the cross-sectional area of ​​the connecting plug is smaller than that of the first capacitor, there is more space to accommodate the capacitors. Therefore, while avoiding short circuits between adjacent capacitors and open circuits within the capacitors themselves, the critical dimensions of the first and second capacitors can be increased and the aspect ratio of the first and second capacitors can be reduced, thereby increasing the capacitance. This improves the performance of the semiconductor structure while ensuring its yield.

[0083] In some embodiments, reference Figure 2 and Figure 3 The projections of the first capacitor 201 and the second capacitor 202 on the substrate 1 are staggered or alternately arranged.

[0084] Among them, reference Figure 2 When the projections of the first capacitor 201 and the second capacitor 202 on the substrate 1 are staggered, the projection of the first capacitor 201 on the substrate 1 can be located on the line connecting the centers of the projections of the two diagonally opposite second capacitors 202 on the substrate 1, or the projection of the second capacitor 202 on the substrate 1 can be located on the line connecting the centers of the projections of the two diagonally opposite first capacitors 201 on the substrate 1.

[0085] refer to Figure 3 When the projections of the first capacitor 201 and the second capacitor 202 on the substrate 1 are alternately arranged, the projection of the first capacitor 201 on the substrate 1 can be located on the center line connecting the projections of the two second capacitors 202 arranged in the same row or line on the substrate 1, or the projection of the second capacitor 202 on the substrate 1 can be located on the center line connecting the projections of the two first capacitors 201 arranged in the same row or line on the substrate 1.

[0086] In this embodiment, the alternating arrangement of the first capacitor 201 and the second capacitor 202 can make good use of the overall space of the semiconductor structure, avoid the first capacitor 201 from affecting the connection of the connecting plug 4 and the second capacitor 202, and enable the second capacitor 202 to be electrically connected to the second type of contact pad 302 with the shortest connection path, thereby reducing the loss and signal transmission delay generated during signal transmission.

[0087] In some embodiments, the first contact pads 3 are arranged in an array. In a row of first contact pads 3, at least one second contact pad 302 is provided between adjacent first contact pads 301. In a column of first contact pads 3, at least one second contact pad 302 is provided between adjacent first contact pads 301.

[0088] For example, refer to Figure 15 When the storage structure consists of two layers of capacitors, a second type of contact pad 302 can be provided between adjacent first-type contact pads 301, in which case the number of first capacitors 201 and second capacitors 202 can be equal. (Reference) Figure 24 The storage structure is a three-layer capacitor. The storage structure also includes a third capacitor 203 disposed above the second capacitor 202. For example, two second-type contact pads 302 can be disposed between adjacent first-type contact pads 301. One of the second-type contact pads 302 can be electrically connected to the second capacitor 202, and the other second-type contact pad 302 can be electrically connected to the third capacitor 203.

[0089] In this embodiment, the first type of contact pad 301 and the second type of contact pad 302 are interspersed, so that the capacitance of each layer can be evenly distributed. On the one hand, this facilitates layout design and improves development efficiency; on the other hand, it can ensure the structural stability and reliability of each layer and avoid problems such as local collapse caused by uneven distribution of capacitors due to the connection plug 4.

[0090] In some embodiments of this disclosure, reference is made to Figure 15 The storage structure 2 also includes a first conductive layer 5 covering the first capacitor 201 and the connecting plug 4, and a second conductive layer 6 covering the second capacitor 202. The first conductive layer 5 and the second conductive layer 6 are in contact with the outermost periphery of the first capacitor 201 and the second capacitor 202.

[0091] In this embodiment, the first conductive layer 5 and the second conductive layer 6 disposed on the outside of the storage structure 2 can control the uniform distribution of the electric field and provide electromagnetic shielding. Simultaneously, the first conductive layer 5 and the second conductive layer 6 serve as protective layers for the first capacitor 201 and the second capacitor 202, encasing the capacitors in conductive material, effectively protecting the storage structure 2 from damage by the external environment, such as preventing damage to the first capacitor 201 and the second capacitor 202 due to external impacts or vibrations. Furthermore, the first conductive layer 5 and the second conductive layer 6 provide channels for connecting the first capacitor 201 and the second capacitor 202. This arrangement simplifies the circuit layout of the storage structure 2 and ensures the stability of the electrical connection between the first capacitor 201 and the second capacitor 202. The fact that the outermost peripheries of the first conductive layer 5 and the second conductive layer 6 are in contact ensures that the internal capacitor layout of the storage structure 2 is not disrupted, further guaranteeing the stability of the storage structure 2.

[0092] In some embodiments, continue to refer to Figure 15 An isolation layer 7 is provided between the first capacitor 201 and the second capacitor 202. A second contact pad 8 is provided in the isolation layer 7. At least part of the second contact pad 8 connects the connecting plug 4 to the second capacitor 202.

[0093] In this embodiment, the isolation layer 7 can isolate the first capacitor 201 and the second capacitor 202, avoid the capacitive coupling effect between the first capacitor 201 and the second capacitor 202, avoid mutual interference or short circuit between the first capacitor 201 and the second capacitor 202, ensure that the first capacitor 201 and the second capacitor 202 can work independently, and improve the reliability and performance of the storage structure 2.

[0094] It is understandable that the second contact pad 8 can correspond one-to-one with the connecting plug 4, for example, in Figure 15 In the embodiment shown, all of the second contact pads 8 are used to connect the second capacitor 202 and the connecting plug 4.

[0095] In other embodiments, reference is made to Figure 24 The storage structure 2 may include three or more layers of capacitors. For example, the storage structure 2 includes a first capacitor 201, a second capacitor 202, and a third capacitor 203. An isolation layer 7 may also be present between the second capacitor 202 and the third capacitor 203. A third contact pad 22 is disposed in this isolation layer 7. Connecting plugs 4 may also be present between adjacent second capacitors 202. (Continue referring to...) Figure 24 The second contact pad 8 may include a third type of contact 801 and a fourth type of contact pad 802. The third type of contact pad 801 is electrically connected to the second capacitor 202, and the fourth type of contact pad 802 is electrically connected to the third capacitor 203 through a connecting plug 4. The storage structure 2 may also include a fourth capacitor (not shown in the figure), a fifth capacitor (not shown in the figure), etc. The connection and arrangement of the third capacitor 203 and the fourth capacitor can be the same as the connection and arrangement of the third capacitor 203 and the second capacitor 202, and so on. This embodiment will not be described in detail here.

[0096] In some embodiments, reference is made to 13, and in conjunction with Figure 11 and Figure 13 The isolation layer 7 includes a first isolation material layer 701 and a second isolation material layer 702, as shown in the reference. Figure 9 and Figure 10 A through-hole 14 is provided between the first capacitors 201. A first insulating material layer 701 covers the sidewall of the through-hole 14 and the top surface of the first conductive layer 5. A conductive material layer 21 covers the top surface of the first insulating material layer 701 and fills the space enclosed by the first insulating material layer 701 within the through-hole 14. The portions of the conductive material layer 21 and the first insulating material layer 701 within the through-hole 14 constitute a connecting plug 4. The conductive material layer 21 covering the top surface of the first insulating material layer 701 is patterned to form a second contact pad 8. A second insulating material layer 702 covers the first insulating material layer 701 and exposes at least a portion of the top surface of the second contact pad 8.

[0097] For example, the conductive material layer 21 can be a single-layer structure or a multi-layer structure. A single-layer conductive material layer 21 may include, for example, a metal material layer filling the space enclosed by the first insulating material layer 701. A multi-layer conductive material layer 21 may include, for example, a metal material layer and an anti-diffusion layer (not shown), wherein the anti-diffusion layer may cover the sidewalls of the first insulating material layer 701, and the metal material layer may fill the space formed by the anti-diffusion layer. The metal material layer is used for electrically connecting the second type of contact pad 302 and the second contact pad 8, and the anti-diffusion layer is used to block elemental diffusion between the metal material layer and the first insulating material layer 701.

[0098] In this embodiment, the first insulating material layer 701 can be used to achieve electrical isolation between the first capacitor 201 and the adjacent connecting plug 4, avoiding the problem of short circuit between the first capacitor 201 and the connecting plug 4. The second insulating material layer 702 can be used to isolate the adjacent second contact pad 8, and can also achieve isolation between the first capacitor 201 and the second capacitor 202.

[0099] In some embodiments, reference Figure 15 The top surface of the second contact pad 8 is flush with the top surface of the insulating layer 7. Specifically, the top surface of the second contact pad 8 is flush with the top surface of the second insulating material layer 702.

[0100] In this embodiment, as Figure 11 As shown, the second isolation material layer 702 covers the top surface of the first isolation material layer 701 and the conductive material layer 21. Subsequently, a planarization process, such as chemical mechanical polishing (CMP), can be used to remove part of the second isolation material layer 702 to expose the top surface of the second contact pad 8. At this point, the top surface of the second contact pad 8 is flush with the top surface of the isolation layer 7, and the entire top surface of the second contact pad 8 is exposed. In this embodiment, directly exposing the top surface of the second contact pad 8 through a planarization process for contact with the second capacitor 202 effectively improves the processing efficiency of the semiconductor structure, and the process is simple and easy to operate.

[0101] In other embodiments, the top surface of the second contact pad 8 is lower than the top surface of the isolation layer 7, and an opening is provided on the isolation layer 7 at a position corresponding to the second contact pad 8, with at least a portion of the top surface of the second contact pad 8 exposed through the corresponding opening.

[0102] In this embodiment, a patterned etching process can be used to remove the second isolation material layer 702 in the area where the second contact pad 8 is located, exposing part of the top surface of the second contact pad 8. In this embodiment, since the top surface of the second contact pad 8 is located within the aforementioned opening and is lower than the top surface of the isolation layer 7, the isolation layer 7 in the area above the top surface of the second contact pad 8 can effectively isolate adjacent second contact pads 8, preventing short circuits and other problems between the second contact pads 8.

[0103] In some embodiments, reference Figures 7-15 ,as well as Figures 18-23 The first capacitor 201 includes a first upper electrode 2011, a first dielectric layer 2012, and a first lower electrode 2013. The first lower electrode 2013 contacts the top surface of the first contact pad 3. The first dielectric layer 2012 covers the first lower electrode 2013 and is laid between adjacent first capacitors 201. The first upper electrode 2011 covers the first dielectric layer 2012. The connecting plug 4 passes through the first dielectric layer 2012 and the first upper electrode 2011 between adjacent first capacitors 201 to connect with the second type of contact pad 302.

[0104] refer to Figure 12 as well as Figure 15 The second capacitor 202 includes a second upper electrode plate 2021, a second dielectric layer 2022, and a second lower electrode plate 2023. The second upper electrode plate 2021 is in contact with the top surface of the second contact pad 8. The second dielectric layer 2022 covers the second lower electrode plate 2023 and is laid between adjacent second capacitors 202. The second upper electrode plate 2021 covers the second dielectric layer 2022.

[0105] For example, the first lower electrode plate 2013 and the second lower electrode plate 2023 can be columnar or other shapes, and this embodiment does not limit them.

[0106] In some embodiments, reference Figures 16-23 The first capacitor 201 further includes at least one support structure 9, which is located on the sidewall of the lower electrode plate 2013. The first dielectric layer 2012 covers the first lower electrode plate 2013 and the support structure 9. In this embodiment, the support structure 9 is used to support the first capacitor 201 and enhance the overall structural stability of the first capacitor 201.

[0107] In other embodiments, at least one support structure 9 is located between the first lower electrode plates 2013 of two adjacent first capacitors 201, and a first dielectric layer 2012 covers the first lower electrode plates 2013 and the support structure 9. The connecting plug 4 passes through the support structure 9 between adjacent first capacitors 201 to achieve electrical connection with the second type of contact pad 302.

[0108] The capacitances of the first capacitor 201 and the second capacitor 202 can be calculated using the following formula:

[0109] C=ε2πRH / A

[0110] Where ε is the dielectric constant; R is the critical dimension of the first capacitor 201 or the second capacitor 202, and in this formula, the critical dimension is the radius of the first capacitor 201 or the second capacitor 202; H is the height of the first capacitor 201 or the second capacitor 202; and A is the distance between adjacent first upper plates 2011 or adjacent second upper plates 2021.

[0111] As can be seen from the above formula, the capacitance is directly proportional to the critical dimensions and the height of the capacitor, and inversely proportional to the distance between the adjacent first upper plate 2011 or the adjacent second upper plate 2021.

[0112] For example, the heights of the first capacitor 201 and the second capacitor 202 can be equal, which can reduce the difference in capacitance and electric field concentration between the first capacitor 201 and the second capacitor 202, thereby improving the overall stability of the storage structure 2. In addition, since the second capacitor 202 is formed above the first capacitor 201 during the manufacturing process of the storage structure 2, that is, the second capacitor 202 is formed after the first capacitor 201, when the height of the second capacitor 202 is equal to that of the first capacitor 201, the various process parameters in the manufacturing process of the second capacitor 202 can be consistent with those of the first capacitor 201. This can simplify the production design process of the second capacitor 202 and improve development efficiency.

[0113] For example, the height of the first capacitor 201 or the second capacitor 202 is 800-1080 nm, and the overall height of the first capacitor 201 and the second capacitor 202 is 800-2160 nm. The height of the capacitor 201 and the second capacitor 202 provided in this disclosure is significantly reduced compared to the capacitors of the prior art. The height of the capacitor 201 and the second capacitor 202 of this disclosure is 265-540 nm higher than half the height of the capacitors of the prior art.

[0114] For example, the diameters of the first capacitor 201 and the second capacitor 202 can be equal. For example, the diameters of the first capacitor 201 and the second capacitor 202 can both be 40-75 nm. The diameters of the first capacitor 201 and the second capacitor 202 in this disclosure are increased by 10-15 nm compared with the prior art. That is, in this disclosure, the key dimensions of the first capacitor 201 and the second capacitor 202 are also significantly improved, so as to effectively increase the capacitance of the first capacitor 201 and the second capacitor 202.

[0115] For example, the aspect ratio of the first capacitor 201 or the second capacitor 202 is 16-32. The aspect ratio of the first capacitor 201 is the ratio of the height of the first capacitor 201 to its diameter, and the aspect ratio of the second capacitor 202 is the ratio of the height of the second capacitor 202 to its diameter.

[0116] Furthermore, the aspect ratio of the first capacitor 201 and the second capacitor 202 can be 16-28.

[0117] This disclosure also provides an exemplary embodiment of a method for fabricating a semiconductor structure, with reference to... Figure 25 The manufacturing method includes:

[0118] Step S100: Provide a substrate, on which a first contact pad is disposed, the first contact pad including a first type of contact pad and a second type of contact pad.

[0119] Substrate 1 can be, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a SiGe substrate, silicon-on-insulator (SOI) or germanium-on-insulator (GOI), etc., for supporting the storage structure 2 thereon. Substrate 1 can also be a semiconductor substrate with a device structure; for example, a transistor can be formed on substrate 1. The first type of contact pad 301 and the second type of contact pad 302 can be electrically connected to the source / drain of the transistor. The first type of contact pad 301 and the second type of contact pad 302 can be made of the same material, such as conductive materials like copper or tungsten.

[0120] A first contact pad 3 is formed in the substrate 1 so as to be electrically connected to the first capacitor 201 formed above it and the connecting plug 4. The material of the first contact pad 3 can be a conductive material such as tungsten metal. The first contact pad 3 can be electrically connected to the source / drain of the transistor in the substrate 1 through the conductive plug 16.

[0121] Step S200: A first capacitor and a second capacitor are formed on the substrate in sequence, wherein a connecting plug is provided between adjacent first capacitors, the first capacitor is connected to a first type of contact pad, and the second capacitor is connected to a second type of contact pad through the connecting plug.

[0122] refer to Figure 2 and Figure 3 The first type of contact pad 301 and the second type of contact pad 302 can be arranged in an array, and at least one second type of contact pad 302 is provided between adjacent first type of contact pads 301. The cross-sectional area of ​​the connecting plug 4 is smaller than the cross-sectional area of ​​the first capacitor 201.

[0123] In this embodiment, the semiconductor structure formed by this fabrication method has a capacitor layer arrangement. The first capacitor 201, which is closer to the substrate 1, is directly connected to the first contact pad 3 on the substrate 1. The second capacitor 202, which is farther from the substrate 1, is connected to the first contact pad 3 through the connecting plug 4 between the first capacitors 201. In this way, the number of capacitors in a single capacitor layer can be reduced. Moreover, the cross-sectional area of ​​the connecting plug 4 is smaller than the cross-sectional area of ​​the first capacitor 201. Therefore, while avoiding short circuits between adjacent capacitors and open circuits within the capacitors themselves, the critical dimensions of the first capacitor 201 and the second capacitor 202 can be increased and the aspect ratio of the first capacitor 201 and the second capacitor 202 can be reduced, thereby increasing the capacitor size. This improves the performance of the semiconductor structure while ensuring the yield of the semiconductor structure.

[0124] In one exemplary embodiment of this disclosure, such as Figure 26 As shown, step S200 includes the following steps:

[0125] Step S210: Form a first capacitor on the substrate that contacts the first type of contact pad.

[0126] Before forming the first capacitor 201, refer to Figure 4 An initial support layer 10 and an initial sacrificial layer 11 can be stacked and formed on the surface of substrate 1. Then, refer to... Figure 5 As shown, a portion of the initial sacrificial layer 11 and a portion of the initial support layer 10 can be removed by dry etching or wet etching to obtain multiple capacitor holes 15 corresponding one-to-one with the first type of contact pad 301. Combined with... Figure 6 and Figure 7 A first capacitor 201 can be formed inside the capacitor hole 15. After the first capacitor 201 is formed, the sacrificial layers 13 mentioned above are removed.

[0127] Step S220: Form a first conductive layer covering the first capacitor.

[0128] refer to Figure 8 For example, the first conductive layer 5 can be formed using processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), and the first conductive layer 5 covers each first capacitor 201.

[0129] For example, the material of the first conductive layer 5 may include, for example, doped polycrystalline silicon, polyethylene terephthalate (PET), polyethylene terephthalate glycol-modified (PETG), etc.

[0130] Step S230: Form a via in the first conductive layer, the via exposing the top surface of the second type of contact pad.

[0131] refer to Figure 9 Without affecting the stability of the first capacitor 201, part of the first conductive layer 5 can be removed by dry etching or wet etching. The through hole 14 is used to form the connection plug 4 described below.

[0132] Step S240: A connecting plug is formed in the through hole, and the bottom end of the connecting plug contacts the second type of contact pad.

[0133] Among them, reference Figure 13 The connecting plug 4 is filled in the through hole 14 to connect the second type of contact pad 302 to the subsequently formed second capacitor 202. The connecting plug 4 serves as an electrical connection. The cross-sectional area of ​​the connecting plug 4 can be set to be small, so the storage structure 2 can have more space to arrange the first capacitor 201. The cross-sectional area of ​​the first capacitor 201 can be set to be large, and the aspect ratio of the first capacitor 201 can be reduced, thereby increasing the capacitance of the first capacitor 201 and improving the performance of the semiconductor structure.

[0134] Step S250: A second capacitor is formed on the first capacitor, and the second capacitor is connected to the connecting plug.

[0135] Reference Figure 15 As shown, the second capacitor 202 is connected to the second type of contact pad 302 via the connecting plug 4.

[0136] Of course, it is understood that the key dimensions, height and other parameters of the first capacitor 201 and the second capacitor 202 may be the same or different, and this embodiment does not impose any restrictions on this.

[0137] Step S260: A second conductive layer is formed to cover the second capacitor, and the second conductive layer and the first conductive layer are in contact with the outermost periphery of the first capacitor and the second capacitor.

[0138] Reference Figure 15 For example, atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes can be used to form the second conductive layer 6 covering each second capacitor 202.

[0139] For example, the material of the second conductive layer 6 may be the same as or different from that of the first conductive layer 5, and may include, for example, polyethylene terephthalate (PET) and polyethylene terephthalate glycol-modified (PETG).

[0140] In this embodiment, the first capacitor 201 and the second capacitor 202 are formed by stacking them sequentially. At the same time, a connecting plug 4 is formed between the first capacitors 201 to realize the connection between the second capacitor 202 and the first contact pad 3. This effectively reduces the number of capacitors in a single capacitor layer. Moreover, the cross-sectional area of ​​the connecting plug 4 is smaller than that of the first capacitor 201. Therefore, while avoiding short circuits between adjacent capacitors and open circuits within the capacitors themselves, the critical dimensions of the first capacitor 201 and the second capacitor 202 can be increased and the aspect ratio of the first capacitor 201 and the second capacitor 202 can be reduced, thereby increasing the capacitance. This improves the performance of the semiconductor structure while ensuring the yield of the semiconductor structure.

[0141] Understandably, the formed semiconductor structure can be a two-layer capacitor, namely the first capacitor 201 and the second capacitor 202, or it can be as follows: Figure 24 As shown, after the second capacitor 202 is formed, the third capacitor 203 is stacked on top of the second capacitor 202. The formation process of the second capacitor 202 and the third capacitor 203 can refer to the formation process of the first capacitor 201. Before stacking the third capacitor 203, a connecting plug 4 needs to be set between the second capacitors 202. The specific manufacturing process can refer to the manufacturing process of the connecting plug 4 between the first capacitors 201, and will not be repeated here.

[0142] In an exemplary embodiment of this disclosure, step S210 specifically includes the following steps:

[0143] Step S211A: Form the initial support layer and initial sacrificial layer of the stack.

[0144] like Figure 4 As shown, both the initial sacrificial layer 11 and the initial support layer 10 can be multi-layered and alternately disposed. For example, an initial sacrificial layer 11 can be formed on the surface of the substrate 1 using a deposition process, and then an initial support layer 10 can be formed on the surface of the initial sacrificial layer 11, and so on, to form multiple initial sacrificial layers 11 and multiple initial support layers 10.

[0145] Step S212A: Remove part of the initial support layer and part of the initial sacrificial layer to form a capacitor hole.

[0146] In this step, refer to Figure 5Capacitor holes 15 can be formed by etching away part of the initial support layer 10 and part of the initial sacrificial layer 11, exposing the top surface of the first type of contact pad 301.

[0147] Step S213A: Form a first lower electrode plate, which covers the sidewall of the capacitor hole and the top surface of the first type of contact pad.

[0148] refer to Figure 6 The first lower electrode plate 2013 can be formed by processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). The first lower electrode plate 2013 covers the sidewall of the capacitor hole 15 and the top surface of the first type of contact pad 301 exposed by the capacitor hole 15.

[0149] Step S214A: Remove the sacrificial layer.

[0150] In this step, the sacrificial layer 13 can be completely removed by dissolving it with acid, while the support layer 12 is retained, which constitutes the support structure 9.

[0151] Step S215A: Form a first dielectric layer, which covers the first lower electrode and is laid between adjacent first lower electrodes.

[0152] refer to Figure 7 The first dielectric layer 2012 can be deposited using atomic layer deposition (ALD). The material of the first dielectric layer 2012 is a high-k dielectric material, and the dielectric constant of the high-k dielectric material is greater than that of silicon dioxide.

[0153] Step S216A: Form a first upper electrode plate, which covers a first dielectric layer.

[0154] refer to Figure 7 The first upper electrode 2011 can be formed by atomic layer deposition (ALD). The material of the first upper electrode 2011 includes compounds formed from one or two of metal nitrides and metal silicides. For example, the material of the first upper electrode 2011 may include one or two of titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy).

[0155] In another embodiment, step S210 includes the following steps:

[0156] Step S211B: Form the initial support layer and initial sacrificial layer of the stack.

[0157] Step S212 B: Remove part of the initial support layer and part of the initial sacrificial layer to form a capacitor hole.

[0158] Step S213 B: Form a first lower electrode plate, which covers the sidewall of the capacitor hole and the top surface of the first type of contact pad.

[0159] Step S214 B: Remove the sacrificial layer.

[0160] Step 215B: Remove part of the support layer to form a support structure.

[0161] refer to Figure 16 The support layer 12 can be partially removed by dry or wet etching, and a support structure 9 can be formed on the side wall of the first lower electrode plate 2013. The support structure 9 is spaced apart from the adjacent first lower electrode plate 2013.

[0162] Step S216 B: Form a first dielectric layer, which covers the first lower electrode and the support structure, and is laid between adjacent first lower electrodes.

[0163] refer to Figure 17 The first dielectric layer 2012 can be formed by atomic layer deposition (ALD) process.

[0164] Step S217 B: Form a first upper electrode plate, which covers the first dielectric layer.

[0165] Steps S211B, S212B, S213B, S214B, and S217B are similar to steps S211A, S212A, S213A, S214A, and S216A, respectively, and will not be described in detail in this embodiment.

[0166] In this embodiment, the final support structure 9 can also provide good support for the first capacitor 201. In addition, the support structure 9 occupies relatively little space, which helps to improve the overall integration of the storage structure 2 and ensures that the first capacitor 201 can achieve a more compact layout.

[0167] In an exemplary embodiment of this disclosure, step S240 includes the following steps:

[0168] Step S241: A first insulating material layer is formed on the first conductive layer, the first insulating material layer covering the sidewall of the via and the top surface of the first conductive layer.

[0169] For example, refer to Figure 10 as well as Figure 20 The first isolation material layer 701 can be formed by atomic layer deposition or chemical vapor deposition. The first isolation material layer 701 may include silicon nitride (SiN), silicon oxide (SiO2), etc., to achieve good insulation between the connecting plug 4 and the first conductive layer 5 and the first capacitor 201, so as to effectively prevent current leakage and short circuit problems in the connecting plug 4, the first capacitor 201, etc.

[0170] Step S242: Form a conductive material layer 21 on the first insulating material layer.

[0171] The conductive material layer 21 covers the top surface of the first insulating material layer 701 and fills the space enclosed by the first insulating material layer 701 in the through hole 14. The first insulating material layer 701 and the conductive material layer 21 located in the through hole 14 constitute the connecting plug 4.

[0172] For example, refer to Figure 11 as well as Figure 21 A conductive material layer 21 can be formed by atomic layer deposition (ALD) process. The material of the conductive material layer 21 can be conductive materials such as copper or tungsten.

[0173] Step S243: Pattern the conductive material layer 21 covering the top surface of the first insulating material layer to form the second contact pad.

[0174] Among them, reference Figure 12 , Figure 13 as well as Figure 22 The conductive material layer 21 can be patterned by dry or wet etching to form a plurality of second contact pads 8, which correspond one-to-one with the connecting plugs 4.

[0175] Step S244: Form a second isolation material layer that covers the first isolation material layer and exposes at least a portion of the top surface of the second contact pad.

[0176] The first insulating material layer 701 and the second insulating material layer 702 constitute the insulating layer 7, wherein the second contact pad 8 is located in the insulating layer 7, and at least a portion of the second contact pad 8 is used to connect the connecting plug 4 to the second capacitor 202.

[0177] After the second contact pad 8 is formed, for example, an atomic layer deposition (ALD) process can be used to deposit a second isolation material layer 702 covering the first isolation material layer 701 and the second contact pad 8. Then, a planarization process such as chemical mechanical planarization (CMP) is used to remove part of the second isolation material layer 702 to expose the top surface of the second contact pad 8. At this time, the top surface of the formed second contact pad 8 is flush with the top surface of the isolation layer 7, and the top surface of the second contact pad 8 is fully exposed.

[0178] For example, after forming the second isolation material layer 702, a patterned etching process can be used to remove the second isolation material layer 702 in the area where the second contact pad 8 is located, exposing part of the top surface of the second contact pad 8. In this embodiment, the top surface of the formed second contact pad 8 is lower than the top surface of the isolation layer 7. Therefore, the isolation layer 7 in the area above the top surface of the second contact pad 8 can play a good role in isolating adjacent second contact pads 8, avoiding problems such as short circuits between the second contact pads 8.

[0179] In this embodiment, the first isolation material layer 701 can provide good electrical isolation for the adjacent first capacitor 201, and the second isolation material layer 702 can provide good electrical isolation for the adjacent second contact pad 8. In addition, the conductive material layer 21 is used to form both the contact plug 4 and the second contact pad 8, thereby simplifying the semiconductor structure manufacturing process and improving production efficiency.

[0180] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0181] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0182] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0183] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0184] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0185] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0186] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: A substrate, wherein a first contact pad is disposed on the substrate, the first contact pad including a first type of contact pad and a second type of contact pad; A storage structure is disposed on the substrate. The storage structure includes a first capacitor and a second capacitor stacked together. A connecting plug is disposed between adjacent first capacitors. The first capacitor is connected to a first type of contact pad. The second capacitor is connected to a second type of contact pad through the connecting plug. An isolation layer is provided between the first capacitor and the second capacitor, and a second contact pad is provided in the isolation layer. At least part of the second contact pad connects the connecting plug to the second capacitor, and the top surface of the second contact pad is flush with the top surface of the isolation layer. The storage structure further includes a first conductive layer covering the first capacitor and the connecting plug, and a second conductive layer covering the second capacitor, wherein the first conductive layer and the second conductive layer are in contact at the outermost periphery of the first capacitor and the second capacitor; The isolation layer includes a first isolation material layer and a second isolation material layer. The first isolation material layer covers the top surface of the first conductive layer and part of the sidewall of the connecting plug. The second isolation material layer only covers the first isolation material layer and exposes the entire top surface of the second contact pad. The cross-sectional area of ​​the connecting plug is smaller than the cross-sectional area of ​​the first capacitor.

2. The semiconductor structure according to claim 1, characterized in that, The projections of the first capacitor and the second capacitor on the substrate are staggered or alternately arranged.

3. The semiconductor structure according to claim 1, characterized in that, The first contact pads are arranged in an array. In a row of first contact pads, at least one second type of contact pad is provided between adjacent first type of contact pads; In a row of first contact pads, at least one second type of contact pad is disposed between adjacent first type contact pads.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The aspect ratio of the first capacitor and the second capacitor is 16-32; and / or, The first capacitor and the second capacitor have the same height; and / or, The heights of both the first capacitor and the second capacitor are 800-1080 nm; The diameters of both the first capacitor and the second capacitor are 40-75 nm.

5. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: A substrate is provided, wherein a first contact pad is disposed on the substrate, the first contact pad including a first type of contact pad and a second type of contact pad; A first capacitor and a second capacitor are formed on the substrate in sequence, wherein a connecting plug is provided between adjacent first capacitors, the first capacitor is connected to a first type of contact pad, and the second capacitor is connected to a second type of contact pad through the connecting plug; The first contact pads are arranged in an array, and at least one second type of contact pad is disposed between adjacent first type contact pads. The formation of a first capacitor and a second capacitor stacked sequentially on the substrate includes: A first capacitor is formed on the substrate to contact the first type of contact pad; A first conductive layer is formed to cover the first capacitor; A through-hole is formed in the first conductive layer, the through-hole exposing the top surface of the second type of contact pad; The connecting plug is formed within the through hole, and the bottom end of the connecting plug contacts the second type of contact pad; A second capacitor is formed on the first capacitor, and the second capacitor is connected to the connection plug; Forming a second conductive layer covering the second capacitor, wherein the second conductive layer and the first conductive layer are in contact at the outermost periphery of the first capacitor and the second capacitor; prior to forming the connection plug within the through hole, the manufacturing method further includes: A first insulating material layer is formed on the first conductive layer, and the first insulating material layer covers the sidewall of the through hole and the top surface of the first conductive layer; The connecting plug is formed within the through hole, comprising: A conductive material layer is formed on the first insulating material layer, the conductive material layer covers the top surface of the first insulating material layer and fills the space enclosed by the first insulating material layer in the through hole, the first insulating material layer and the conductive material layer located in the through hole constitute the connecting plug; Before forming the second capacitor on the first capacitor, the manufacturing method further includes: The conductive material layer covering the top surface of the first insulating material layer is patterned to form a second contact pad; A second insulating material layer is formed, which covers the first insulating material layer and exposes the entire top surface of the second contact pad. The first and second insulating material layers constitute an insulating layer. The second contact pad is located in the isolation layer, and the second contact pad is used to connect the connection plug to the second capacitor, and the top surface of the second contact pad is flush with the top surface of the isolation layer; The cross-sectional area of ​​the connecting plug is smaller than the cross-sectional area of ​​the first capacitor.

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