Back-end thread memory device

Abstract

The invention relates to a back-end thread memory device. Structures having a substrate, a first interconnect region, a second interconnect region, and a memory device region are described. The first interconnect region is over the substrate and includes a first interconnect structure. The second interconnect region is over the first interconnect region and includes a second interconnect structure electrically connected to the first interconnect structure. Further, the memory device region is between the first interconnect region and the second interconnect region and includes ferroelectric memory cells (e.g., ferroelectric random access memory (FeRAM) cells).

Description

Technical Field

[0001] The present disclosure relates to a back-end thread memory device. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to increase. To meet these demands, the semiconductor industry continues to shrink the size of circuit elements (such as memory devices). As storage capacity increases and the number of circuit elements increases, semiconductor manufacturing processes become increasingly complex. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a first interconnection region, located above a substrate and comprising a first plurality of interconnection structures; a second interconnection region, located above the first interconnection region and comprising a second plurality of interconnection structures electrically connected to the first plurality of interconnection structures; and a memory device region, located between the first interconnection region and the second interconnection region, wherein the memory device region comprises a plurality of ferroelectric memory cells.

[0004] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate comprising one or more electrical components formed thereon; a first interconnection region located above the substrate and comprising a first plurality of interconnection structures electrically connected to the one or more electrical components; a second interconnection region located above the first interconnection region and comprising a second plurality of interconnection structures electrically connected to the first plurality of interconnection structures; and a memory device region located between the first interconnection region and the second interconnection region, wherein the memory device region comprises a plurality of ferroelectric memory cells electrically connected to the one or more electrical components via the first plurality of interconnection structures, and wherein each of the plurality of ferroelectric memory cells comprises a ferroelectric material disposed on a fin structure.

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming one or more electrical components on a substrate; forming a first interconnection region above the substrate, the first interconnection region having a first plurality of interconnection structures electrically connected to the one or more electrical components; forming a second interconnection region above the first interconnection region, the second interconnection region having a second plurality of interconnection structures electrically connected to the first plurality of interconnection structures; and forming a memory device region between the first interconnection region and the second interconnection region, wherein the memory device region comprises a plurality of ferroelectric memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1When read together, various aspects of the present disclosure can be best understood through the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a diagram of a block level representation of a memory system according to some embodiments.

[0008] Figure 2 is an illustration of a cross-sectional view of a semiconductor device incorporating one or more elements of a memory system according to some embodiments.

[0009] Figure 3 is an illustration of a cross-sectional view of a portion of a semiconductor device according to some embodiments.

[0010] Figure 4 is an illustration of another cross-sectional view of a semiconductor device according to some embodiments.

[0011] Figure 5 is a diagram of a circuit representation of a portion of a memory array in accordance with some embodiments.

[0012] Fig. 6A is an illustration of a top view layout representation of a portion of a memory array in accordance with some embodiments.

[0013] Figure 6B is an illustration of an enlarged top view layout representation of a portion of a memory array in accordance with some embodiments.

[0014] Figure 7 is an illustration of a cross-sectional view of a portion of a memory array in accordance with some embodiments.

[0015] Figure 8 is an illustration of another cross-sectional view of a portion of a memory array in accordance with some embodiments.

[0016] Fig. 9 is a diagram of another circuit representation of a portion of a memory array in accordance with some embodiments.

[0017] Fig. 10A is an illustration of another top view layout representation of a portion of a memory array in accordance with some embodiments.

[0018] Fig. 10B is an illustration of another enlarged top view layout representation of a portion of a memory array in accordance with some embodiments.

[0019] Fig.11 is an illustration of yet another cross-sectional view of a portion of a memory array in accordance with some embodiments.

[0020] Fig.12 is an illustration of a method of forming memory cells in a back-end-of-thread device memory region of a semiconductor device, according to some embodiments.

[0021] Figure 13-Figure 18 is an illustration of a partial cross-sectional view of a memory cell in a memory region of a back-end-of-thread device of a semiconductor device at various stages of its fabrication process, according to some embodiments. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are examples only and are not intended to be limiting. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and unless otherwise indicated, it does not itself specify the relationship between the various embodiments and / or configurations discussed. For ease of description, spatially related terms such as "below", "below", "lower", "above", "upper" may be used herein to describe the relationship between an element or feature as shown in the figure relative to another (one or more) element or (one or more) feature. These spatially related terms are intended to cover different orientations of the device in use or operation except for the orientation depicted in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may also be interpreted accordingly.

[0023] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it would be within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0024] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that those skilled in the relevant art will interpret the phraseology or terminology of this specification based on the teachings herein.

[0025] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given amount varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to percentages of values ​​interpreted by one of ordinary skill in the relevant art based on the teachings herein.

[0026] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to increase. To meet these demands, the semiconductor industry continues to reduce the size of circuit elements (such as memory devices). Accordingly, as the storage capacity increases and the number of circuit elements increases, the chip area of ​​​​the memory device becomes more challenging.

[0027] The present disclosure describes a semiconductor device including a memory device (e.g., a ferroelectric random access memory (FeRAM) cell) in a back-end thread region (e.g., an interconnect structure disposed above a substrate of the semiconductor device). The semiconductor device may include a substrate, a first interconnect region disposed above the substrate, a second interconnect region disposed above the first interconnect region, and a third interconnect region disposed above the second interconnect region. The substrate may include electronic components formed thereon, such as active devices, passive devices, or a combination of active and passive devices. The first interconnect region may include an interconnect structure (e.g., a metal line structure and a metal via structure) to electrically connect electrical components to each other and / or to an upper interconnect structure (e.g., an interconnect structure in the second interconnect region and in the third interconnect region). The second interconnect region may include a memory device region and an interconnect structure (e.g., a metal line structure and a metal via structure). The memory device region may include a memory cell (e.g., a FeRAM cell) electrically connected to the electrical component via an interconnect structure in the first interconnect region. Each ferroelectric memory cell may include a ferroelectric material (e.g., hafnium zirconium oxide) disposed on a top surface and a side surface of a fin structure (e.g., composed of indium gallium zinc oxide). Furthermore, the third interconnection region may include an interconnection structure (eg, a metal line structure and a metal via structure).

[0028] One of the benefits of implementing memory cells in the memory device region is that the back-end thread region of the semiconductor device can be utilized to manufacture the memory cells, thereby increasing the storage capacity in the semiconductor device. Another benefit of implementing memory cells in the back-end thread region is that additional substrate area can be used to implement additional electrical components to enhance the functionality and performance of the semiconductor device.

[0029] Figure 1 is a diagram of a block level representation of a memory system 100 according to some embodiments. In some embodiments, the memory system 100 may include a row decoder 110, input / output (I / O) circuits 120, sense amplifiers 130, column decoders 140, and a memory array 150.

[0030] The memory array 150 includes memory cells arranged in rows and columns that are accessed using memory addresses (e.g., for memory read and write operations). In some embodiments, the memory cells in the memory array 150 may be FeRAM cells. Although the following description is made in the context of a memory system having FeRAM cells, other types of systems and memory cells may also implement the embodiments described herein.

[0031] Based on the memory address, row decoder 110 selects a row of memory cells to be accessed (eg, via word lines 1120-112 m ), and column decoder 140 selects the column of memory cells to be accessed (eg, via bit lines 1420-142 n ). The intersection of the selected memory cell row and the selected memory cell column corresponds to a selected memory cell accessible in the memory array 150. The sense amplifier 130 detects whether the selected memory cell is in a conductive state or a non-conductive state during a read cycle - corresponding to the on / off state of the selected memory cell. The on / off state of the selected memory cell can correspond to a digital "0" or a digital "1", wherein the I / O circuit 120 provides this digital representation of the state of the selected memory cell to the external circuit ( Figure 1 1 ). Other memory operations may be performed using row decoder 110, I / O circuits 120, sense amplifiers 130, column decoder 140, and memory array 150. These other memory operations are within the spirit and scope of the present disclosure.

[0032] One of the challenges in the design of memory system 100 is implementing memory array 150 with increased storage capacity and, thus, an increased number of memory cells (e.g., FeRAM cells). For example, as system designs become more complex with increased functionality and performance, additional chip area is consumed to implement these complex designs - leaving limited chip area for additional memory cells to increase storage capacity. The present disclosure addresses these challenges, among others, by implementing memory array 150 (e.g., the entire memory array or a portion thereof) in a back-end threading region of a chip design (e.g., a metal layer disposed above a substrate of a semiconductor device).

[0033] Figure 2 is an illustration of a cross-sectional view of a semiconductor device 200 incorporating one or more circuit elements of a memory system 100 in accordance with some embodiments. Semiconductor device 200 may include a substrate 210 , a device region 220 , and a back-end threading region 230 , in accordance with some embodiments.

[0034] The substrate 210 may include a semiconductor material, such as crystalline silicon (Si). In some embodiments, the substrate 210 may include (i) a basic semiconductor, such as germanium (Ge); (ii) a compound semiconductor, such as silicon carbide (SiC), silicon arsenide (SiAs), gallium arsenide (GaAs), gallium phosphide (GaP), and / or a III-V semiconductor material; (iii) an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium tin (GeSn), and / or aluminum gallium arsenide (AlGaAs); (iv) a silicon-on-insulator (SOI) structure; (v) a silicon-germanium (SiGe) on-insulator structure (SiGeOI); (vi) a germanium-on-insulator (GeOI) structure; or (vii) a combination thereof. Alternatively, the substrate 210 may be made of a non-conductive material, such as glass and a sapphire wafer. In addition, the substrate 210 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, substrate 210 may be doped with a p-type dopant (eg, boron, indium, aluminum, or gallium) or an n-type dopant (eg, phosphorus or arsenic).

[0035] The device region 220 may be disposed on the substrate 210. In some embodiments, the device region 220 may include electrical components, such as active devices, passive devices, or combinations thereof. Examples of active devices may include planar metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (finFETs), gate all-around field effect transistors (GAAFETs), and nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nanoribbon transistors). The device region 220 may include one or more of these different types of active devices, which may be separated from each other using shallow trench isolation technology, deep trench isolation, local silicon oxide technology, other suitable isolation technologies, and combinations thereof. Examples of passive devices may include resistors, capacitors, and inductors. The device region 220 may also include one or more of these different types of passive devices.

[0036] In some embodiments, the device region 220 may include Figure 1 For example, device region 220 may include one or more of row decoder 110, I / O circuit 120, sense amplifier 130, and column decoder 140. In addition to the electrical components of memory system 100, device region 220 may also include other types of electrical components.

[0037] refer to Figure 2According to some embodiments, the back-end thread region 230 is disposed above the device region 220 (e.g., in the y direction) and may include a first interconnect region 231, a second interconnect region 232, and a third interconnect region 236. The first interconnect region 231 may include a dielectric structure disposed in an interlayer ( Figure 2 One or more interconnect structures (not shown) in the embodiment of the present invention, such as metal line structures and metal via structures. The metal line structures and metal via structures may include copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W) or other suitable conductive materials. The interlayer dielectric structure may include dielectric materials such as silicon oxide (SiOx), silicon hydroxide (SiOH), silicon oxynitride (SiON), silicon nitride (SiNx), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), and combinations thereof. The interlayer dielectric structure may include a stack of dielectric layers to achieve a multilayer interconnect structure.

[0038] One or more interconnect structures in the first interconnect region 231 may be electrically connected to electrical components in the device region 220. For example, one or more interconnect structures in the first interconnect region 231 may be electrically connected to Figure 1 Active devices and / or passive devices in electrical components of the memory system 100 (e.g., row decoder 110, I / O circuit 120, sense amplifier 130, and column decoder 140) are electrically connected to each other and / or to upper interconnect structures (e.g., interconnect structures in second interconnect region 232 and third interconnect region 236).

[0039] refer to Figure 2 According to some embodiments, the second interconnect region 232 is located above the first interconnect region 231 (e.g., in the y direction) and may include a memory device region 233 and a metal via structure 234, both of which are disposed in the interlayer dielectric structure 235. The metal via structure 234 may electrically connect the interconnect structure in the interconnect device region 231 to the interconnect structure in the interconnect device region 236. Figure 2 23. Although not shown in the figure, the second interconnection region 232 may also include metal line structures and other metal via structures. The metal line structure and the metal via structure (including the metal via structure 234) may include Cu, Al, TiN, TaN, W or other suitable conductive materials. The interlayer dielectric structure 235 may include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN and combinations thereof. The interlayer dielectric structure 235 may include a stack of dielectric layers to achieve a multilayer interconnection structure.

[0040] In some embodiments, the memory device region 233 may include Figure 1One or more electrical components of the memory system 100 of the semiconductor device 200, such as the memory array 150, may be implemented in the memory device area 233. One benefit of implementing the memory array 150 in the memory device area 233 is that the back-end thread area 230 may be used to fabricate memory cells (e.g., FeRAM cells), thereby increasing the storage capacity in the semiconductor device 200. Another benefit of implementing the memory array 150 in the back-end thread area 230 is that additional areas in the device area 220 may be used to implement additional electrical components to enhance the functionality and performance of the semiconductor device 200.

[0041] refer to Figure 2 The third interconnect region 236 is located above the second interconnect region 232 (eg, in the y direction) and may include one or more interconnect structures disposed in the interlayer dielectric structure 238. The interconnect structure may include a metal line structure 237 and a metal via structure ( Figure 2 The metal line structure and the metal via structure may include Cu, Al, TiN, TaN, W or other suitable conductive materials. The interconnection structure in the third interconnection region 236 may be formed by the metal via structure 234 (and Figure 2 The first interconnect region 231 is electrically connected to the electrical components in the device region 220 (other metal via structures not shown in the figure). The interlayer dielectric structure 238 may include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN, and combinations thereof. The interlayer dielectric structure 238 may include a stack of dielectric layers to achieve a multi-layer interconnect structure. Although a three-layer metal line structure 237 is shown in the third interconnect region 236, the third interconnect region 236 may have more or less than three metal line structures, depending on the design of the semiconductor device 200.

[0042] Figure 3 2 is an illustration of a cross-sectional view of a portion 300 of a semiconductor device 200 according to some embodiments. The portion 300 includes a substrate 210, a device region 220, and a first interconnect region 231. Figure 3 23. Although not shown in FIG. 23, the second interconnection region 232 and the third interconnection region 236 are arranged above the first interconnection region 231. Figure 2 shown.

[0043] Device region 220 may include active devices 310 implemented in and / or on substrate 210. According to some embodiments, active devices 310 may include one or more of planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nanoribbon transistors). Active devices 310 may be separated from each other using shallow trench isolation technology, deep trench isolation, local silicon oxide technology, other suitable isolation technologies, and combinations thereof. In some embodiments, active devices 310 may represent Figure 1 Active device 310 may represent one or more electrical components of memory system 100 (e.g., row decoder 110, I / O circuit 120, sense amplifier 130, and column decoder 140). In some embodiments, active device 310 may represent one or more electrical components of memory system 100, another system, or a combination of both systems. Figure 3 Not shown, device region 220 may also include passive devices (eg, resistors, capacitors, and inductors) implemented within and / or on substrate 210 .

[0044] In some embodiments, the first interconnection region 231 may include an interconnection structure disposed in the interlayer dielectric structure 321, for example, a metal line structure 320 and a metal via structure 234. The metal line structure 320 and the metal via structure 234 may be electrically connected to active devices and / or passive devices (e.g., active devices 310) in the device region 220, so that these electrical components may be electrically connected to each other and / or electrically connected to upper interconnection structures (e.g., interconnection structures in the second interconnection region 232 and in the third interconnection region 236, Figure 3 ). Although Figure 3 2, but the first interconnection region 231 may also include other metal via structures. The metal line structure and the metal via structure (including the metal via structure 234) may include Cu, Al, TiN, TaN, W or other suitable conductive materials. The interlayer dielectric structure 321 may include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN and combinations thereof. The interlayer dielectric structure 321 may include a stack of dielectric layers to achieve a multilayer interconnection structure.

[0045] Figure 4 is an illustration of another cross-sectional view of a portion 400 of a semiconductor device 200 according to some embodiments. Figure 4 23. Although not shown in FIG. 23, the second interconnection region 232 and the third interconnection region 236 are arranged above the first interconnection region 231. Figure 2 shown.

[0046] Portion 400 includes substrate 210, device region 220, and first interconnect region 231. According to some embodiments, device region 220 may include backside interconnect region 410 and device region 420. In some embodiments, backside interconnect region 410 is located below device region 220 (e.g., in the y direction). Backside interconnect region 410 may include an interconnect structure (e.g., as part of a redistribution layer network of an interconnect structure) disposed in an interlayer dielectric structure 417 and arranged to provide a power supply voltage to electrical components in device region 420. Interlayer dielectric structure 417 may include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN, and combinations thereof. Interlayer dielectric structure 417 may include a stack of dielectric layers to implement a multilayer interconnect structure. In addition, the interconnect structure may include metal line structures 413, 415, and 416 and metal via structures 412 and 414 that are electrically connected to each other and to a power supply to provide a power supply voltage to device region 420. The metal line structures 413 , 415 , and 416 and the metal via structures 412 and 414 may include Cu, Al, TiN, TaN, W, or other suitable conductive materials.

[0047] According to some embodiments, device region 420 may include active devices 422 disposed above substrate 210 (eg, in the y-direction). Figure 4 As shown, the active device 422 may be a GAAFET electrically connected to the backside interconnection region 410 and the first interconnection region 231 through the metal contact structure 421, the metal contact structure 423, and the metal line structure 411. In some embodiments, the active device 422 may receive a power supply voltage from the interconnection structure in the backside interconnection region 410 through the metal contact structure 421 and the metal line structure 411. In addition, in some embodiments, the active device 422 may receive a voltage from the interconnection structure in the first interconnection region 231 through the metal contact structure 423. The metal contact structures 421 and 423 and the metal line structure 411 may include Cu, Al, TiN, TaN, W, or other suitable conductive materials.

[0048] In some embodiments, the power supply voltage provided to the device region 220 through the backside interconnect region 410 is different from the power supply voltage provided to the device region 220. Figure 2 For example, referring to Figure 2 and Figure 4, the power supply voltage provided to the active devices 422 in the device region 220 may require a higher power supply voltage than the power supply voltage required by the memory cells (e.g., FeRAM cells) in the memory device region 233. In some embodiments, the power supply voltage to the device region 220 may be provided by the backside interconnect region 410, and the power supply voltage to the memory device region 233 may be provided by a power supply electrically connected to the second interconnect region 232, which includes an interconnect structure electrically connected to the memory device region 233.

[0049] refer to Figure 4 According to some embodiments, active device 422 may be other types of devices, such as planar MOSFET, finFET, nanostructure transistor (e.g., nanosheet transistor, nanowire transistor, multi-bridge channel transistor, and nanoribbon transistor), and combinations thereof. Active devices 422 may be separated from each other using shallow trench isolation technology, deep trench isolation, local silicon oxide technology, other suitable isolation technologies, and combinations thereof. In some embodiments, active device 422 may represent Figure 1 Active device 422 may represent one or more electrical components of memory system 100 (e.g., row decoder 110, I / O circuit 120, sense amplifier 130, and column decoder 140). In some embodiments, active device 422 may represent one or more electrical components of memory system 100, another system, or a combination of both systems. Figure 4 Not shown, the device region 220 may also include passive devices (eg, resistors, capacitors, and inductors).

[0050] In some embodiments, the first interconnection region 231 may include an interconnection structure disposed in the interlayer dielectric structure 434, for example, metal line structures 431 and 432 and metal via structures 234 and 433. The metal line structures 431 and 432 and the metal via structures 234 and 433 may be electrically connected to active devices and / or passive devices (e.g., active device 422) in the device region 220, so that these electrical components may be electrically connected to each other and / or electrically connected to upper interconnection structures (e.g., interconnection structures in the second interconnection region 232 and the third interconnection region 236, Figure 4 4. The metal line structure and the metal via structure may include Cu, Al, TiN, TaN, W or other suitable conductive materials. The interlayer dielectric structure 434 may include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN and combinations thereof. The interlayer dielectric structure 434 may include a stack of dielectric layers to implement a multilayer interconnect structure.

[0051] Figure 5is a diagram of a circuit representation of a portion 500 of a memory array 150 according to some embodiments. In some embodiments, portion 500 may be arranged at Figure 2 The memory device area 233 is in the reference Figure 5 , portion 500 includes the following elements: a first NOR string arrangement including FeRAM cells 510, 511, 512, and 513 electrically connected to each other along a first bit line (e.g., BL[K], where "K" is an integer equal to or greater than zero); a second NOR string arrangement including FeRAM cells 520, 521, 522, and 523 electrically connected to each other along a second bit line (e.g., BL[K+1]); a third NOR string arrangement including FeRAM cells 530, 531, 532, and 533 electrically connected to each other along a third bit line (e.g., BL[K+2]); and a fourth NOR string arrangement including FeRAM cells 540, 541, 542, and 543 electrically connected to each other along a fourth bit line (e.g., BL[K+3]). Reference Figure 1 and Figure 2 , the bit lines BL[K], BL[K+1], BL[K+2], and BL[K+3] of the portion 500 in the memory array 150 may be electrically connected to the column decoder 140. In some embodiments, the column decoder 140 may be disposed in the device region 220 and electrically connected to the FeRAM cells 510-513 in the first NOR string arrangement, the FeRAM cells 520-523 in the second NOR string arrangement, the FeRAM cells 530-533 in the third NOR string arrangement, and the FeRAM cells 540-543 in the fourth NOR string arrangement of the memory array 150 in the memory device region 233 through the interconnect structure in the first interconnect region 231.

[0052] refer to Figure 5 , portion 500 includes source lines SL[M] and SL[M+1] (where “M” is an integer equal to or greater than zero) electrically connected to a common source terminal of the FeRAM cells. Source line SL[M] is electrically connected to a common source terminal of FeRAM cells 510, 511, 520, 521, 530, 531, 540, and 541. Source line SL[M+1] is electrically connected to a common source terminal of FeRAM cells 512, 513, 522, 523, 532, 533, 542, and 543. In some embodiments, source lines SL[M] and SL[M+1] are electrically connected to a reference voltage source, such as ground (e.g., 0V).

[0053] refer to Figure 5, portion 500 also includes word lines WL[N], WL[N+1], WL[N+2], and WL[N+3], where "N" is an integer equal to or greater than zero. Word line WL[N] is electrically connected to the gate terminals of FeRAM cells 510, 520, 530, and 540. Word line WL[N+1] is electrically connected to the gate terminals of FeRAM cells 511, 521, 531, and 541. Word line WL[N+2] is electrically connected to the gate terminals of FeRAM cells 512, 522, 532, and 542. And word line WL[N+3] is electrically connected to the gate terminals of FeRAM cells 513, 523, 533, and 543. Reference Figure 1 and Figure 2 , word lines WL[N], WL[N+1], WL[N+2], and WL[N+3] to the memory array 150 may be electrically connected to the row decoder 110. The row decoder 110 may be disposed in the device region 220 and electrically connected to the FeRAM cells in the first NOR string arrangement, the second NOR string arrangement, the third NOR string arrangement, and the fourth NOR string arrangement of the memory array 150 in the memory device region 233 through the interconnect structure in the first interconnect region 231.

[0054] Based on the description herein, portion 500 may include more or less than four FeRAM cells for each NOR string arrangement and more or less than four NOR string arrangements for memory array 150. These alternative memory array 150 arrangements are within the scope of the present disclosure.

[0055] Fig. 6A is an illustration of a top view layout representation of a portion 500 of a memory array 150 according to some embodiments. Due to the repeating pattern of FeRAM cells in portion 500, a sub-portion 600 of the layout representation will be described. The description of sub-portion 600 is applicable to the rest of the memory array 150. For ease of illustration, Figure 6B An enlarged view of sub-portion 600 is shown.

[0056] In some embodiments, the sub-portion 600 includes a fin structure 610, a gate structure 620, a gate contact structure 630, a first metal line structure 640, a source / drain contact structure 650, a metal via structure 660, a second metal line structure 670, and a third metal line structure 680. In some embodiments, the fin structure 610 is formed along a first direction (e.g., an x ​​direction) and may include indium gallium zinc oxide or other suitable materials. The gate structure 620 is formed along a second direction (e.g., a z direction; a direction perpendicular to the first direction) and is formed on the fin structure 610. In some embodiments, the gate structure 620 may include polysilicon, Si, Ti, Ta, Al, W, nitrogen (N), zinc (Zn), indium (In), Ga, Ge, carbon (C), or other suitable materials. In some embodiments, the gate structure 620 may include TiN. The gate contact structure 630 is disposed on the gate structure 620. In addition, the first metal line structure 640 (e.g., WL[N+3]) is formed along a second direction (e.g., a z direction) and is formed on the gate contact structure 630. The gate contact structure 630 and the first metal line structure 640 may include Cu, Al, TiN, TaN, W, or other suitable conductive materials.

[0057] In addition, reference Figure 6B , the source / drain contact structure 650 is formed adjacent to the gate structure 620 (e.g., in the x-direction). The second metal line structure 670 (e.g., SL[M+1]) is disposed on one of the source / drain contact structures 650. The metal via structure 660 is disposed on the other source / drain contact structure 650. The third metal line structure 680 is disposed on the metal via structure 660. In some embodiments, the second metal line structure 670 (e.g., SL[M]+1]) and the first metal line structure 640 (e.g., WL[N+3]) can be disposed in the same metallization layer (e.g., metallization layer [X]), and the third metal line structure 680 can be disposed in the next higher metallization layer (e.g., metallization layer [X+1]). The source / drain contact structure 650, the metal via structure 660, the second metal line structure 670, and the third metal line structure 680 may include Cu, Al, TiN, TaN, W, or other suitable conductive materials.

[0058] Figure 7 6 is an illustration of a cross-sectional view of a sub-portion 600 in a memory array 150 according to some embodiments. The cross-sectional view is along the x-direction and shows an interlayer dielectric structure 235, a fin structure 610, a gate structure 620, a gate contact structure 630, a first metal line structure 640 (e.g., WL[N+3]), a source / drain contact structure 650, a metal via structure 660, a second metal line structure 670, a third metal line structure 680, and a ferroelectric material layer 710. The above describes a structure having a structure similar to the ferroelectric material layer 710. Figure 2 and Fig. 6A , Figure 6B The same annotation as the components in Figure 7 Components in .

[0059] refer to Figure 7 , the fin structure 610 is disposed on the interlayer dielectric structure 235. In some embodiments, the fin structure 610 can provide an n-type channel to the FeRAM cell. Figure 2 , the interlayer dielectric structure 235 may include a dielectric material (e.g., SiOx, SiOH, SiON, SiNx, SiOC, SiOCN, and combinations thereof) and may include a stack of dielectric layers to implement a multilayer interconnect structure. Here, instead of forming a multilayer interconnect structure on the portion of the interlayer dielectric structure 235, a FeRAM cell (e.g., Figure 5 FeRAM cells 510-513, 520-523, 530-533 and 540-543).

[0060] In some embodiments, to form a FeRAM cell, a ferroelectric material layer 710 is disposed on the fin structure 610. According to some embodiments, the ferroelectric material layer 710 may include hafnium zirconium oxide with a zirconium percentage between about 30% and about 60%. In some embodiments, the ferroelectric material layer 710 may be lead zirconate titanate (PbZrTiO), lead zirconate (PbZrO3), lead titanate (PbTiO3), barium titanate (BaTiO3), lead niobate (PbNbO), bismuth titanate (BiTiO), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), or any other suitable material. According to some embodiments, a gate structure 620 is disposed on the ferroelectric material layer 710, and a source / drain contact structure 650 is disposed adjacent to the gate structure 620 (e.g., in the x-direction), wherein the gate structure 620 forms a gate terminal of the FeRAM cell, and the source / drain contact structure 650 is electrically connected to the source / drain region of the FeRAM cell. The source / drain region(s) may be referred to individually or collectively as a source or a drain, depending on the context. In some embodiments, when the FeRAM cell conducts current based on voltages applied to the gate terminal of the FeRAM cell and the source / drain regions, electrons may flow through the fin structure 610 (e.g., an n-type channel) between the source / drain regions. Through the gate contact structure 630, the first metal line structure 640, the metal via structure 660, and the second metal line structure 670, the FeRAM cell may be provided with gate and source / drain voltages to perform memory read operations, memory write operations, and other memory operations.

[0061] Figure 81 is another cross-sectional view of a sub-portion 600 in a memory array 150 according to some embodiments. The cross-sectional view is along the y-direction and shows an interlayer dielectric structure 235, a fin structure 610, a gate structure 620, a gate contact structure 630, a first metal line structure 640 (e.g., WL[N+3]), and a ferroelectric material layer 710. Figure 2 , Fig. 6A , Figure 6B and Figure 7 The same annotation as the components in Figure 8 Components in .

[0062] refer to Figure 8 According to some embodiments, the fin structure 610 may have a height H (eg, in the y direction) between about 50 nm and about 1000 nm. In some embodiments, if the height H is less than about 50 nm, the saturation current (I sat ) may not be suitable for device applications. In some embodiments, if the height H is greater than about 1000 nm, the fin structure 610 may collapse. In some embodiments, the ferroelectric material layer 710 (e.g., hafnium zirconium oxide) has a thickness T greater than about 3 nm along the top and side surfaces of the fin structure 610 and has an orthorhombic phase. In some embodiments, if the thickness T is less than about 3 nm, the hafnium zirconium oxide may not have an orthorhombic phase and ferroelectric properties, which is desirable for the ferroelectric material layer 710.

[0063] In some embodiments, in order to solve reliability issues caused by applying a higher voltage (e.g., about 5V or more) to the ferroelectric material layer 710 during various memory operations (e.g., program memory operations), the ferroelectric material layer 710 may have three layers: a first protective layer in contact with the top and side surfaces of the fin structure 610; an intermediate ferroelectric material layer (e.g., hafnium zirconium oxide) in contact with the top and side surfaces of the first protective layer; and a second protective layer in contact with the top and side surfaces of the intermediate ferroelectric material layer. In some embodiments, each of the first protective layer and the second protective layer may have a thickness between about 1 nm and about 2 nm. According to some embodiments, in order to reduce leakage in the FeRAM cell, each of the first protective layer and the second protective layer may have a zirconium doping between about 1% and about 2%. In addition, according to some embodiments, the first protective layer and the second protective layer may each include hafnium oxide (HfO2), hafnium aluminum oxide (HfAlO x ), Hafnium Silicate (HfSiO x ) or other suitable materials, wherein the first protective layer may include the same material as the second protective layer or a material different from the second protective layer.

[0064] Fig. 9is a diagram of a circuit representation of a portion 900 of a memory array 150 according to some embodiments. In some embodiments, portion 900 may be arranged at Figure 2 The memory device area 233 is in the reference Fig. 9 , portion 900 includes the following elements: a first NAND string arrangement, including a bit line select transistor 910, FeRAM cells 911, 912 and 913, and a ground select transistor 914; and a second NAND string arrangement, including a bit line select transistor 920, FeRAM cells 921, 922 and 923, and a ground select transistor 924. In the first NAND string arrangement, the source / drain terminal of the bit line select transistor 910 is electrically connected to a first bit line (e.g., BL[K], where "K" is an integer equal to or greater than zero). In the second NAND string arrangement, the source / drain terminal of the bit line select transistor 920 is electrically connected to a second bit line (e.g., BL[K+1]). Reference Figure 1 and Figure 2 , bit lines BL[K] and BL[K+1] of portion 900 in memory array 150 may be electrically connected to column decoder 140. In some embodiments, column decoder 140 may be disposed in device region 220 and electrically connected to FeRAM cells 911-913 in a first NAND string arrangement and FeRAM cells 921-923 in a second NAND string arrangement of memory array 150 in memory device region 233 through an interconnect structure in first interconnect region 231.

[0065] refer to Fig. 9 , portion 900 includes a bit line select line BLS and a ground select line GS. In some embodiments, the bit line select line BLS activates bit line select transistors 910 and 920 to enable the first NAND string arrangement and the second NAND string arrangement. In some embodiments, the ground select line GS activates ground select transistors 914 and 924 to electrically connect the first NAND string arrangement and the second NAND string arrangement to a reference voltage source 930, such as ground (e.g., 0V).

[0066] refer to Fig. 9 , portion 900 further includes word lines WL[N], WL[N+1], and WL[N+2], where "N" is an integer equal to or greater than zero. Word line WL[N] is electrically connected to the gate terminals of FeRAM cells 911 and 921. Word line WL[N+1] is electrically connected to the gate terminals of FeRAM cells 912 and 922. And word line WL[N+2] is electrically connected to the gate terminals of FeRAM cells 913 and 923. Reference Figure 1 and Figure 2, word lines WL[N], WL[N+1], and WL[N+2] in the memory array 150 may be electrically connected to the row decoder 110. In some embodiments, the row decoder 110 may be disposed in the device region 220 and electrically connected to the FeRAM cells in the first NAND string arrangement and the second NAND string arrangement of the memory array 150 in the memory device region 233 through the interconnect structure in the first interconnect region 231.

[0067] Based on the description herein, portion 900 may include more than three or less than three FeRAM cells for each NAND string arrangement and more than two or less than two NAND string arrangements for memory array 150. These alternative memory array 150 arrangements are within the scope of the present disclosure.

[0068] Fig. 10A 1 is an illustration of a top view layout representation of portion 900 of memory array 150 according to some embodiments. Due to the repeating pattern of FeRAM cells in portion 900, sub-portion 1000 of the layout representation will be described. The description of sub-portion 1000 is applicable to the rest of memory array 150. For ease of description, Fig. 10B An enlarged view of subsection 1000 is shown.

[0069] In some embodiments, the sub-portion 1000 includes a fin structure 1010, a gate structure 1020, a gate contact structure 1030, and a metal line structure 1040. In some embodiments, the fin structure 1010 is formed along a first direction (e.g., the x direction) and may include indium gallium zinc oxide or other suitable materials. The gate structure 1020 is formed along a second direction (e.g., the z direction; a direction perpendicular to the first direction) and is formed on the fin structure 1010. In some embodiments, the gate structure 1020 may include polysilicon, Si, Ti, Ta, Al, W, N, Zn, In, Ga, Ge, C, or other suitable materials. In some embodiments, the gate structure 1020 may include TiN. The gate contact structure 1030 is disposed on the gate structure 1020. In addition, the metal line structure 1040 (e.g., WL[N+2]) is formed along the second direction (e.g., the z direction) and is formed on the gate contact structure 1030. The gate contact structure 1030 and the metal line structure 1040 may include Cu, Al, TiN, TaN, W, or other suitable conductive materials.

[0070] Fig.111 is an illustration of a cross-sectional view of a sub-portion 1000 in a memory array 150 according to some embodiments. The cross-sectional view is along the y-direction and shows an interlayer dielectric structure 235, a fin structure 1010, a gate structure 1020, a gate contact structure 1030, a metal line structure 1040 (e.g., WL[N+2]), and a ferroelectric material layer 710. Figure 2 , Figure 7 , Figure 8 , Fig. 10A and Fig. 10B The components in the same annotation Fig.11 Components in .

[0071] refer to Fig.11 According to some embodiments, the fin structure 1010 may have a height H (eg, in the y direction) between about 50 nm and about 1000 nm. In some embodiments, if the height H is less than about 50 nm, the saturation current (I sat ) may not be suitable for device applications. In some embodiments, if the height H is greater than about 1000 nm, the fin structure 1010 may collapse. In some embodiments, the fin structure 1010 may provide an n-type channel to a FeRAM cell. In some embodiments, the ferroelectric material layer 710 (e.g., hafnium zirconium oxide) has a thickness T greater than about 3 nm along the top and side surfaces of the fin structure 610 and has an orthorhombic phase. In some embodiments, if the thickness T is less than about 3 nm, the hafnium zirconium oxide may not have an orthorhombic phase and ferroelectric properties, which is desirable for the ferroelectric material layer 710.

[0072] In some embodiments, in order to solve the reliability problem caused by applying a higher voltage (e.g., about 5V or higher) to the ferroelectric material layer 710 during various memory operations (e.g., program memory operations), the ferroelectric material layer 710 may have three layers: a first protective layer in contact with the top surface and side surfaces of the fin structure 1010; an intermediate ferroelectric material layer (e.g., hafnium zirconium oxide) in contact with the top surface and side surfaces of the first protective layer; and a second protective layer in contact with the top surface and side surfaces of the intermediate ferroelectric material layer. In some embodiments, each of the first protective layer and the second protective layer may have a thickness between about 1nm and about 2nm. According to some embodiments, in order to reduce leakage in the FeRAM cell, each of the first protective layer and the second protective layer may have a zirconium doping between about 1% and about 2%. In addition, according to some embodiments, the first protective layer and the second protective layer may each include HfO2, HfAlO x 、HfSiO x or other suitable materials, wherein the first protective layer may include the same material as the second protective layer or a different material from the second protective layer.

[0073] Fig.12 is an illustration of a method 1200 of forming a memory cell in a back-end thread device memory region of a semiconductor device according to some embodiments. Additional operations may be performed between the various operations of method 1200 and may be omitted merely for clarity and ease of description. Additional operations may be provided before, during, and / or after method 1200; one or more of these additional operations are briefly described herein. Furthermore, not all operations are required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in parallel with the Fig.12 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described.

[0074] For illustrative purposes, reference will be made to Figure 2-5 , Fig. 6A , Figure 6B , Figure 7-9 , Fig. 10A , Fig. 10B and Fig.11 An example manufacturing process for forming a memory cell in the memory device region 233 of the second interconnect region 232 is described below. Fig.12 The operations shown in . Figure 13-18 1 shows a partial cross-sectional view of a memory cell at various stages of its manufacturing process according to some embodiments. Figure 1-5 , Fig. 6A , Figure 6B , Figure 7-9 , Fig. 10A , Fig. 10B and Fig.11 The same annotation as the components in Figure 13-18 Components in .

[0075] refer to Fig.12 At operation 1210, one or more electrical components are formed on a substrate. Figure 3 and Figure 4 , the device region 220 may be formed on the substrate 210. Figure 3 , the device region 220 may include active devices 310 (eg, planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors) implemented within and / or on the substrate 210. Figure 4, the device region 220 may include a backside interconnect region 410 and a device region 420. The backside interconnect region 410 may include an interconnect structure (e.g., as part of a redistribution layer network of interconnect structures) disposed in an interlayer dielectric structure 417 and arranged to provide a power supply voltage to electrical components in the device region 420. The device region 420 may include active devices 422 (e.g., planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors) disposed above the substrate 210 (e.g., in the y-direction). Although Figure 3 and Figure 4 Not shown, but device region 220 may also include passive devices (eg, resistors, capacitors, and inductors).

[0076] refer to Fig.12 At operation 1220, a first interconnect region is formed on the substrate. The first interconnect region includes a first interconnect structure electrically connected to one or more electrical components. For example, referring to Figure 3 and Figure 4 , a first interconnection region 231 is formed on the substrate 210. Figure 3 , the first interconnection region 231 may include an interconnection structure disposed in the interlayer dielectric structure 321, such as a metal line structure 320 and a metal via structure 234. The metal line structure 320 and the metal via structure 234 may be electrically connected to active devices and / or passive devices (e.g., active device 310) in the device region 220, so that these electrical components may be electrically connected to each other and / or electrically connected to the upper interconnection structure (e.g., the interconnection structure in the second interconnection region 232 and the third interconnection region 236, Figure 3 ). Figure 4 , the first interconnection region 231 may include an interconnection structure disposed in the interlayer dielectric structure 434, such as metal line structures 431 and 432 and metal via structures 234 and 433. The metal line structures 431 and 432 and the metal via structures 234 and 433 may be electrically connected to active devices and / or passive devices (e.g., active device 422) in the device region 220, so that these electrical components may be electrically connected to each other and / or electrically connected to upper interconnection structures (e.g., interconnection structures in the second interconnection region 232 and the third interconnection region 236, Figure 4 not shown).

[0077] refer to Fig.12 At operation 1230, a second interconnect region is formed over the first interconnect region. The second interconnect region includes a second interconnect structure electrically connected to the first interconnect structure. For example, referring to Figure 2The third interconnect region 236 is located above the first interconnect region 231 (eg, in the y direction) and may include one or more interconnect structures disposed in the interlayer dielectric structure 238. The interconnect structure may include a metal line structure 237 and a metal via structure ( Figure 2 not shown).

[0078] refer to Fig.12 At operation 1240, a memory device region is formed between the first interconnect region and the second interconnect region. The memory device region includes a ferroelectric memory cell. Figure 2 , the memory device region 233 is formed between the first interconnect region 231 and the third interconnect region 236. In some embodiments, the memory device region 233 may include Figure 1 One or more electrical components of the memory system 100, such as the memory array 150. In some embodiments, the memory array 150 may include ferroelectric memory cells.

[0079] The formation of memory cells (eg, ferroelectric memory cells) in the memory device region 233 is referred to as Figure 13-Figure 18 Although Figure 13-Figure 18 shows partial cross-sectional views of a single memory cell at different stages of its fabrication process, but the following description also applies to Figure 1 The formation of a plurality of memory cells in the memory array 150, such as memory cells in a NOR string arrangement (eg, Figure 5 , Fig. 6A and Figure 6B 500) and memory cells in a NAND string arrangement (e.g., Fig. 9 , Fig. 10A and Fig. 10B 900 of the memory array 150 in FIG.

[0080] refer to Fig.13 , the fin structure 610 / 1010 is formed on the interlayer dielectric structure 235. The formation may include depositing indium gallium zinc oxide or other suitable materials onto the interlayer dielectric structure 235 (e.g., using an atomic layer deposition process and a physical vapor deposition process) and a fin cutting operation to form the fin structure 610 / 1010. According to some embodiments, the height H (e.g., in the y direction) of the fin structure 610 / 1010 may be between about 50 nm and about 1000 nm.

[0081] refer to Fig.14The ferroelectric material layer 710 and the gate structure 620 / 1020 are deposited on the fin structure 610 / 1010 using, for example, an atomic layer deposition process. In some embodiments, the ferroelectric material layer 710 (eg, hafnium zirconium oxide) has a thickness T greater than about 3 nm along the top and side surfaces of the fin structure 610 / 1010 and has an orthorhombic phase.

[0082] refer to Fig.15 , performing a polishing operation (eg, a chemical mechanical polishing operation) and a cutting operation. Fig.16 ,exist Fig.15 Another interlayer dielectric structure 235 is formed on the structure shown. Fig.17 , a gate terminal opening 1710 and a source / drain terminal opening 1720 are formed by, for example, a photo pattern and an etching process. And referring to Fig.18 , the gate terminal opening 1710 and the source / drain terminal openings 1720 are filled with a conductive material (e.g., Cu, Al, TiN, TaN, W or other suitable conductive materials), and the resulting filled structure is polished to form a gate contact structure and a source / drain contact structure.

[0083] The present disclosure describes a semiconductor device (eg, Figure 2 The semiconductor device 200 includes a back-end thread region (eg, Figure 2 232) in a memory device (eg, Figure 2 The semiconductor device may include a substrate, a first interconnect region disposed on the substrate, a second interconnect region disposed on the first interconnect region, and a third interconnect region disposed on the second interconnect region. Figure 2 The substrate 210 may include electrical components formed thereon, such as active devices, passive devices, or a combination of active devices and passive devices. The first interconnect region (e.g., Figure 2 The first interconnect region 231 may include interconnect structures (eg, metal line structures and metal via structures) to electrically connect electrical components to each other and / or to upper interconnect structures (eg, Figure 2 The second interconnect region 232 and the third interconnect region 236 may include an interconnect structure in the second interconnect region 232 and the third interconnect region 236. The second interconnect region may include a memory device region (eg, Figure 2 The memory device region 233) and the interconnect structure (e.g., metal line structure and metal via structure) in the first interconnect region. The memory device region may include a memory cell (e.g., a FeRAM cell) electrically connected to the electrical component via the interconnect structure in the first interconnect region. Each ferroelectric memory cell may include a fin structure (e.g., Figure 6B , Figure 7 and Figure 8 The fin structure 610 and Fig. 10B and Fig.11 The ferroelectric material (eg, Figure 7 , Figure 8 and Fig.11 In addition, the third interconnection region may include an interconnection structure (eg, a metal line structure and a metal via structure).

[0084] One of the benefits of implementing memory cells in the memory device region is that the back-end thread region of the semiconductor device can be utilized to manufacture the memory cells, thereby increasing the storage capacity in the semiconductor device. Another benefit of implementing memory cells in the back-end thread region is that additional substrate area can be used to implement additional electrical components to enhance the functionality and performance of the semiconductor device.

[0085] Embodiments of the present disclosure include a structure having a first interconnect structure, a second interconnect structure, and a memory device region. The first interconnect region is located above a substrate and includes the first interconnect structure. The second interconnect region is located above the first interconnect region and includes a second interconnect structure electrically connected to the first interconnect structure. The memory device region is located between the first interconnect region and the second interconnect region and includes a ferroelectric memory cell.

[0086] Embodiments of the present disclosure include a semiconductor structure having a substrate, a first interconnect region, a second interconnect region, and a memory device region. The substrate includes one or more electrical components formed thereon. The first interconnect region is located above the substrate and includes a first interconnect structure electrically connected to the one or more electrical components. The second interconnect region is located above the first interconnect region and includes a second interconnect structure electrically connected to the first interconnect structure. The memory device region is located between the first interconnect region and the second interconnect region, and includes a ferroelectric memory cell electrically connected to the one or more electrical components through the first interconnect structure. Each ferroelectric memory cell includes a ferroelectric material disposed on a fin structure.

[0087] Embodiments of the present disclosure include a method for forming a memory cell in a back-end thread device memory region of a semiconductor device. The method includes forming one or more electrical components on a substrate. The method also includes: forming a first interconnect region on the substrate, the first interconnect region having a first interconnect structure electrically connected to the one or more electrical components; forming a second interconnect region on the first interconnect region, the second interconnect region having a second interconnect structure electrically connected to the first interconnect structure. The method also includes forming a memory device region between the first interconnect region and the second interconnect region, wherein the memory device region includes a ferroelectric memory cell.

[0088] It should be understood that the detailed description section (rather than the abstract section of the present disclosure) is intended to be used to interpret the claims. The abstract section of the present disclosure may set forth one or more but not all possible embodiments of the present disclosure contemplated by the inventor, and is therefore not intended to limit the appended claims in any way.

[0089] The features of several embodiments have been summarized above so that those skilled in the art can better understand the detailed description that follows. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various modifications, substitutions, and changes to this document without departing from the spirit and scope of the present disclosure.

[0090] Example 1 is a semiconductor structure comprising: a first interconnect region located above a substrate and comprising a first plurality of interconnect structures; a second interconnect region located above the first interconnect region and comprising a second plurality of interconnect structures electrically connected to the first plurality of interconnect structures; and a memory device region located between the first interconnect region and the second interconnect region, wherein the memory device region comprises a plurality of ferroelectric memory cells.

[0091] Example 2 is the structure described in Example 1, wherein the plurality of ferroelectric memory cells include a plurality of ferroelectric random access memory cells, wherein each of the plurality of ferroelectric random access memory cells includes a ferroelectric material layer having a first protective layer and a second protective layer, and wherein the first protective layer and the second protective layer have a width between approximately 1 nm and approximately 2 nm and a zirconium doping between approximately 1% and approximately 2%.

[0092] Example 3 is the structure of Example 1, wherein each of the ferroelectric memory cells includes: a fin structure including an indium gallium zinc oxide material; and a hafnium zirconium oxide layer disposed on the fin structure.

[0093] Example 4 is the structure described in Example 3, further comprising: a first protective layer disposed between the fin structure and the hafnium zirconium oxide layer; and a second protective layer disposed on the hafnium zirconium oxide layer, wherein the first protective layer and the second protective layer include one or more of hafnium oxide, hafnium aluminum oxide and hafnium silicon oxide.

[0094] Example 5 is the structure of Example 1, wherein the plurality of ferroelectric memory cells are arranged in a NOR string arrangement of ferroelectric memory cells.

[0095] Example 6 is the structure described in Example 5, wherein the multiple ferroelectric memory cells include a first ferroelectric memory cell and a second ferroelectric memory cell, and wherein the NOR string arrangement of the ferroelectric memory cells includes: a source / drain (S / D) region of the first ferroelectric memory cell and an S / D region of the second ferroelectric memory cell, electrically connected to a common source line; and another S / D region of the first ferroelectric memory cell and another S / D region of the second ferroelectric memory cell, electrically connected to a bit line.

[0096] Example 7 is the structure of Example 6, wherein the common source line is electrically connected to a ground terminal.

[0097] Example 8 is the structure of Example 1, wherein the plurality of ferroelectric memory cells are arranged in a NAND string arrangement of ferroelectric memory cells.

[0098] Example 9 is the structure described in Example 8, wherein the multiple ferroelectric memory cells include a first ferroelectric memory cell and a second ferroelectric memory cell, and wherein the NAND string arrangement of the ferroelectric memory cells includes: a source / drain (S / D) region of the first ferroelectric memory cell, electrically connected to a bit line selection transistor; an S / D region of the second ferroelectric memory cell, electrically connected to a ground selection transistor; and another S / D region of the first ferroelectric memory cell and another S / D region of the second ferroelectric memory cell, electrically connected to each other.

[0099] Example 10 is the structure of Example 3, wherein the fin structure has a height between about 50 nm and about 1000 nm.

[0100] Example 11 is a semiconductor structure comprising: a substrate including one or more electrical components formed thereon; a first interconnect region located above the substrate and including a first plurality of interconnect structures electrically connected to the one or more electrical components; a second interconnect region located above the first interconnect region and including a second plurality of interconnect structures electrically connected to the first plurality of interconnect structures; and a memory device region located between the first interconnect region and the second interconnect region, wherein the memory device region includes a plurality of ferroelectric memory cells electrically connected to the one or more electrical components via the first plurality of interconnect structures, and wherein each of the plurality of ferroelectric memory cells includes a ferroelectric material disposed on a fin structure.

[0101] Example 12 is the semiconductor structure of Example 11, further comprising: a third interconnect region disposed below the plurality of electrical components.

[0102] Example 13 is the semiconductor structure of Example 11, wherein the one or more electrical components include a plurality of active devices, a plurality of passive devices, or a combination thereof.

[0103] Example 14 is the semiconductor structure of Example 13, wherein the plurality of active devices include fin field effect transistors, gate-all-around transistors, planar field effect transistors, or a combination thereof.

[0104] Example 15 is the semiconductor structure of Example 11, wherein the substrate includes a backside interconnect region having an interconnect structure arranged to provide a power supply voltage to the one or more electrical components.

[0105] Example 16 is a method of forming a semiconductor structure, comprising: forming one or more electrical components on a substrate; forming a first interconnection region above the substrate, the first interconnection region having a first plurality of interconnection structures electrically connected to the one or more electrical components; forming a second interconnection region above the first interconnection region, the second interconnection region having a second plurality of interconnection structures electrically connected to the first plurality of interconnection structures; and forming a memory device region between the first interconnection region and the second interconnection region, wherein the memory device region includes a plurality of ferroelectric memory cells.

[0106] Example 17 is the method of Example 16, further comprising: forming a third interconnect structure below the one or more electrical components.

[0107] Example 18 is the method described in Example 16, wherein forming the memory device region includes: forming a plurality of ferroelectric random access memory cells, wherein each of the ferroelectric memory cells includes: a fin structure including an indium gallium zinc oxide material; and a hafnium zirconium oxide layer disposed on the fin structure.

[0108] Example 19 is the method described in Example 16, wherein forming the memory device area includes: forming a NOR string arrangement of ferroelectric memory cells, wherein the multiple ferroelectric memory cells include a first ferroelectric memory cell and a second ferroelectric memory cell, and wherein the NOR string arrangement of ferroelectric memory cells includes: a source / drain (S / D) region of the first ferroelectric memory cell and an S / D region of the second ferroelectric memory cell, electrically connected to a common source line; and another S / D region of the first ferroelectric memory cell and another S / D region of the second ferroelectric memory cell, electrically connected to a bit line.

[0109] Example 20 is the method described in Example 16, wherein forming the memory device area includes: forming a NAND string arrangement of ferroelectric memory cells, wherein the multiple ferroelectric memory cells include a first ferroelectric memory cell and a second ferroelectric memory cell, and wherein the NAND string arrangement of ferroelectric memory cells includes: a source / drain (S / D) region of the first ferroelectric memory cell, electrically connected to a bit line selection transistor; an S / D region of the second ferroelectric memory cell, electrically connected to a ground selection transistor; and another S / D region of the first ferroelectric memory cell and another S / D region of the second ferroelectric memory cell, electrically connected to each other.

Claims

1. A semiconductor structure comprising: a first interconnect region located above the substrate and comprising a first plurality of interconnect structures; a second interconnect region located above the first interconnect region and comprising a second plurality of interconnect structures electrically connected to the first plurality of interconnect structures; as well as A memory device region is located between the first interconnect region and the second interconnect region, wherein the memory device region includes a plurality of ferroelectric memory cells.

2. The structure according to claim 1, wherein: The plurality of ferroelectric memory cells include a plurality of ferroelectric random access memory cells, wherein each of the plurality of ferroelectric random access memory cells includes a ferroelectric material layer having a first protective layer and a second protective layer, and wherein the first protective layer and the second protective layer have a width between 1 nm and 2 nm and a zirconium doping between 1% and 2%.

3. The structure according to claim 1, wherein: Each of the ferroelectric memory cells comprises: A fin structure including an indium gallium zinc oxide material; and A hafnium zirconium oxide layer is disposed on the fin structure.

4. The structure according to claim 3, further comprising: A first protective layer, disposed between the fin structure and the hafnium zirconium oxide layer; as well as A second protective layer is disposed on the hafnium zirconium oxide layer, wherein the first protective layer and the second protective layer include one or more of hafnium oxide, hafnium aluminum oxide and hafnium silicon oxide.

5. The structure according to claim 1, wherein: The plurality of ferroelectric memory cells are arranged in a NOR string arrangement of ferroelectric memory cells.

6. The structure according to claim 5, wherein: The plurality of ferroelectric memory cells include a first ferroelectric memory cell and a second ferroelectric memory cell, and wherein the NOR string arrangement of the ferroelectric memory cells includes: The source / drain S / D region of the first ferroelectric memory cell and the S / D region of the second ferroelectric memory cell are electrically connected to a common source line; and Another S / D region of the first ferroelectric memory cell and another S / D region of the second ferroelectric memory cell are electrically connected to a bit line.

7. The structure according to claim 6, wherein: The common source line is electrically connected to a ground terminal.

8. The structure according to claim 1, wherein: The plurality of ferroelectric memory cells are arranged in a NAND string arrangement of ferroelectric memory cells.

9. A semiconductor structure comprising: a substrate including one or more electrical components formed thereon; a first interconnect region located over the substrate and comprising a first plurality of interconnect structures electrically connected to the one or more electrical components; a second interconnect region located above the first interconnect region and comprising a second plurality of interconnect structures electrically connected to the first plurality of interconnect structures; as well as A memory device region is located between the first interconnect region and the second interconnect region, wherein the memory device region includes a plurality of ferroelectric memory cells electrically connected to the one or more electrical components through the first plurality of interconnect structures, and wherein each of the plurality of ferroelectric memory cells includes a ferroelectric material disposed on a fin structure.

10. A method of forming a semiconductor structure, comprising: forming one or more electrical components on the substrate; forming a first interconnect region over the substrate, the first interconnect region having a first plurality of interconnect structures electrically connected to the one or more electrical components; forming a second interconnect region over the first interconnect region, the second interconnect region having a second plurality of interconnect structures electrically connected to the first plurality of interconnect structures; as well as A memory device region is formed between the first interconnect region and the second interconnect region, wherein the memory device region includes a plurality of ferroelectric memory cells.

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