Method for building artificial vision system based on cluster heterojunction and application
By introducing clusters into semiconductor devices to form heterojunctions, the problems of complex design and limited functions of existing artificial vision systems are solved, and the multifunctional biological vision system integration and simplified preparation process are realized, which promotes the artificial vision system. Multifunctional integration and large-scale applications.
Patent Information
- Application Number
- CN202310686786.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-09
- Publication Date
- 2024-12-10
AI Technical Summary
The existing artificial vision system design can only meet the implementation of a single function or a few visual functions, and there are problems such as complex device structure and preparation process, difficult materials to process on a large scale, and limited visual function simulation, which limits its multifunctional compatibility and large Scale application.
By introducing clusters into semiconductor devices to form cluster heterojunctions, multi-wavelength light recognition, graphics memory and strong and weak light adaptation are achieved. A simplified wafer-level preparation process is adopted to select cheap, stable and universal material systems with low-cost properties and universal properties. , build a multifunctional artificial vision system.
Achieving multifunctional biological vision system integration, simplifying device structure and preparation process, reducing costs, expanding the range of material selection, overcoming the problems of large-scale preparation and complex processes, and promoting the multifunctional integration of artificial vision systems and Large-scale application.
Smart Images
Figure CN119110654A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of field effect transistors and relates to a method for building a wafer-level multifunctional integrated artificial vision system based on cluster heterojunction and an application thereof. Background Art
[0002] Artificial vision system is a system that uses modern electronic devices (transistors, memristors, photodiodes, etc.) to simulate the functions of biological visual system. Its functions include response to external light, recognition, strong and weak light adaptation, and conversion of light signals into electrical signals for brain processing. Thanks to the amplification gain and convenient integration of transistors, a type of transistor devices that respond to external light with current or voltage are used as the hardware carrier of artificial vision system.
[0003] The current and voltage signals output by the transistor can be used for further reading, calculation, storage, encoding, decoding and other operations to simulate and emulate various signals in the visual system of organisms. The transconductance signal of the device can be modulated by gate voltage and external light, where the means of light modulation device include but are not limited to light wavelength, light intensity, coherent light phase, etc. ((a) Yang, Y.; da Costa, R.; Fuchter, M.; et al. Nature Photon 7, 634–638 (2013). (b) Seo, S.; Jo, SH.; Kim, S.; et al. Nat Commun 9, 5106 (2018)). For the visual system of organisms, the basic structure and the principle of imaging the outside world are common among different organisms. Light is incident from the lens into the eyeball, and the light signal is converted into an electrical signal through multiple layers of cells and tissues and transmitted to the brain through the visual neural network. In nerve cells, signal transmission mainly occurs at synapses, generating excitatory or inhibitory postsynaptic potentials, which are transmitted in the form of electrical signals. Therefore, photoelectric signal conversion and electrical signal utilization are the key to artificial visual neural transistor devices.
[0004] Existing artificial vision systems have made breakthrough progress in photoelectric signal conversion and electrical signal utilization. They can distinguish light of different wavelengths (Seo, S.; Jo, SH.; Kim, S.; et al. Nat Commun 9, 5106 (2018)), adapt to strong and weak light ((a) Liao, F.; Zhou, Z.; Kim, BJ; et al. Nat Electron 5, 84–91 (2022). (b) He, Z.; Shen, H.; Ye, D.; et al. Nat Electron 4, 522–529 (2021)), and learn images (Chen-Yu Wang; et al. Sci. Adv. 6, eaba6173 (2020)), etc.
[0005] However, existing artificial vision system design strategies can only meet the realization and application of a single function or a few visual functions, and do not consider the feasibility of large-scale integration and the complexity of the preparation process. These limit its multifunctional compatibility, future commercialization and large-scale application. The main problems include the complexity of the existing device structure and preparation process, the difficulty of large-scale processing of materials, and the limited degree of visual function simulation, which is far from meeting the application requirements of machine vision, artificial intelligence and artificial eyes. Artificial vision systems that meet the needs of industrial production society need to optimize device structures and select cheap, stable and universal material systems. Therefore, it is essential to design artificial vision system design strategies that are wafer-level, multifunctionally integrated and simple in processing technology. Summary of the invention
[0006] The purpose of the present invention is to provide a method and application for building an artificial visual system. By introducing clusters into semiconductor devices to form cluster heterojunctions, the functional integration of multi-wavelength light recognition, pattern memory, and strong and weak light adaptation to the visual systems of various organisms can be achieved, becoming a suitable choice for manufacturing artificial visual receptors; and this method can achieve wafer-level preparation, with a simple process and good universality, overcoming the problems currently encountered by artificial visual receptors in large-scale preparation and multifunctionality.
[0007] To achieve the above object, the present invention provides the following technical solutions:
[0008] In a first aspect, the present invention provides a method for building an artificial vision system, comprising the following steps:
[0009] S1, preparing a gate electrode on the surface of the cleaned substrate;
[0010] S2, preparing a dielectric layer on the surface of the gate electrode;
[0011] S3, preparing a cluster accumulation layer on the surface of the dielectric layer;
[0012] S4, preparing a semiconductor layer on the surface of the cluster accumulation layer and contacting the semiconductor layer with the cluster accumulation layer to form a cluster semiconductor heterojunction;
[0013] S5. Prepare source and drain electrodes on the surface of the semiconductor layer to form an artificial vision system.
[0014] In step S1, the cleaning solution used for cleaning is one or more of acid solution, alcohol cleaning agent, ketone cleaning agent and deionized water.
[0015] The acid solution is one or more of piranha solution, concentrated sulfuric acid, nitric acid and aqua regia.
[0016] The alcohol cleaning agent is one or more of methanol, ethanol and isopropanol.
[0017] The ketone cleaning solution is acetone and / or pentanone.
[0018] In step S1, the substrate is one of a silicon wafer, a gallium nitride wafer, a silicon carbide wafer, a glass, a metal sheet, an engineering plastic substrate and a resin. Preferably, the substrate is a P-doped silicon wafer, which can be used as both a substrate and a gate electrode. The size and shape of the substrate can be adjusted according to actual needs.
[0019] In step S1, the cleaning method is ultrasonic cleaning. The ultrasonic conditions are: power of 150-250W, preferably 200W, time longer than 10min, preferably 30min.
[0020] In step S1, the substrate may also be processed, including modification, physical and chemical modification of the substrate.
[0021] In step S1, the gate electrode is made of a material with a conductivity higher than 10S cm -1 materials, such as one or more of gold, silver, copper, aluminum, single crystal silicon, carbon nanotubes, silver nanowires and conductive polymer PEDOT:PSS.
[0022] In step S1, the gate electrode is prepared by one or more of magnetron sputtering, electron beam lithography, vacuum thermal evaporation, electroplating, spin coating, rod coating, spray coating and scraper coating.
[0023] Preferably, before preparing the gate electrode, an adhesion layer or a modification layer, such as a Cr metal layer or a Ti metal layer, is deposited on the surface of the substrate.
[0024] Preferably, after the gate electrode is prepared, the surface work function, surface energy and other properties of the gate electrode are physically modified or chemically modified, such as by oxygen-plasma bombardment.
[0025] In step S1, the thickness of the gate electrode is 10-50 nm, preferably 20-30 nm.
[0026] In step S2, the material of the dielectric layer is an insulating material with a capacitance range of 1 nF / cm 2 -100μF / cm 2 , preferably 10-15μF / cm 2 ; Its relative dielectric constant ranges from 1-90, preferably 3-5.
[0027] Preferably, the material of the dielectric layer is one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, polymethyl methacrylate (PMMA), CYTOP and polystyrene (PS).
[0028] In step S2, the preparation process of the dielectric layer is one or more of magnetron sputtering, laser direct writing, electrospray printing, solution spin coating annealing, spin coating, rod coating, spray coating and scraper coating.
[0029] In step S2, the thickness of the dielectric layer is 50-1000nm, preferably 300-350nm, and the thickness of the dielectric layer must ensure that the transistor does not leak and reduce pinholes and surface defects during preparation; the surface (root mean square) roughness of the dielectric layer is controlled below 2nm, preferably less than 1nm; when the artificial vision system is working, the current passing through the dielectric layer should be less than 1 / 1000 of the source-drain current of the source-drain electrode.
[0030] In step S3, the material of the cluster accumulation layer is a cluster material with a core-shell structure, that is, the central metal or non-metal atom (core) is wrapped by a ligand (shell) on the periphery of the spherical cluster to stabilize the cluster.
[0031] In step S3, the cluster material must have the following characteristics to meet the requirements of device preparation:
[0032] Peripheral ligands: Groups containing π electron systems, such as phenyl and thienyl, can form fast charge transfer channels with the semiconductor layer, which is conducive to the transfer of charges between heterojunctions; they do not contain sites that easily capture charges, such as hydroxyl and carboxyl groups, so as not to affect the electrical properties of the semiconductor layer;
[0033] Particle size distribution standard deviation: <1nm;
[0034] Heat stability: no decomposition below 100°C, no change in physical structure and chemical properties; preferably below 150°C;
[0035] Water and oxygen stability: within 30 days, it does not react chemically with water and oxygen, maintains the physical and chemical structure unchanged, and can meet the ability to be stored in a low-water and oxygen environment; the low-water and oxygen environment refers to a water content of <1ppm (20℃, 1atm) and an oxygen content of <1ppm (20℃, 1atm);
[0036] Photoelectric properties: molar absorption coefficient>1000L mol -1 cm -1 , fluorescence quantum yield>20%;
[0037] The size of a single cluster is in the range of 0.2-5 nm. The stacking of the clusters is driven by van der Waals forces to form a thermodynamically or kinetically stable stacking state. Within this range, a dense cluster stacking layer without cavities can be formed.
[0038] Preferably, the cluster material is a metal cluster material (gold nanoclusters, silver nanoclusters), an atomically precise carbon cluster or a carbon quantum dot.
[0039] According to an embodiment of the present invention, the cluster material is a silver nanocluster, which is prepared according to the following steps:
[0040] (1) N,N-dimethylacetamide and acetonitrile were mixed in a weight ratio of 3:1 to prepare a mixed solution;
[0041] (2) adding 2-phenylglycinol and silver nitrate in a molar ratio of 1:1 to the mixed solution, stirring rapidly to generate a yellow precipitate;
[0042] (3) The obtained precipitate is repeatedly washed with acetonitrile, and then heated and dried under nitrogen protection to obtain silver nanoclusters. The obtained silver nanoclusters are stored in a dark, dry and sealed environment for use.
[0043] In step S3, the cluster accumulation layer is prepared by a process selected from the group consisting of a solution process, an in-situ growth method, a chemical vapor deposition method, a physical vapor transport method, an electrochemical oxidation-reduction method, and a transfer method; preferably, the solution process is selected from the group consisting of spin coating, rod coating, and blade coating.
[0044] According to an embodiment of the present invention, the cluster stacking layer is prepared according to the following steps:
[0045] (1) dissolving the cluster material in a low boiling point solvent to prepare a cluster solution;
[0046] (2) applying the cluster solution to the surface of the dielectric layer by spin coating, rod coating or blade coating to form the cluster accumulation layer;
[0047] (3) Annealing the cluster accumulation layer.
[0048] In the step (1), the concentration of the cluster solution is 3-5 mg / mL, preferably 4 mg / mL.
[0049] In the step (1), the low boiling point solvent is one or more of tetrahydrofuran, dichloromethane, chloroform, methanol, ethanol, and acetone. The use of a low boiling point solvent can avoid cluster aggregation or nucleation crystallization, ensuring that the resulting cluster accumulation layer has a low surface roughness.
[0050] In the step (2), the process conditions of the spin coating are: rotation speed>3000rpm / s, preferably 5000rpm / s-8000rpm / s; the process conditions of the rod coating and the scraper coating are: horizontal movement speed of the rod and the scraper>2cm / s.
[0051] In the step (3), the process conditions of the annealing treatment are: the temperature is 5-15°C lower than the boiling point of the selected low-boiling point solvent. Taking tetrahydrofuran as an example, the annealing temperature is 35-45°C, preferably 40°C, and the time is 2-10 min, preferably 5 min.
[0052] In step S3, the thickness of the cluster accumulation layer is 5-30 nm, preferably 10 nm.
[0053] In step S3, the surface roughness of the cluster accumulation layer is less than 2 nm, preferably less than 0.5 nm, to ensure that the cluster heterojunction interface has a clear and smooth interface.
[0054] In step S3, the cluster accumulation layer may be further processed, including: patterning the cluster accumulation layer, physically adsorbing the clusters in the cluster accumulation layer or performing chemical surface modification.
[0055] In step S4, the semiconductor layer is made of an organic semiconductor material or an inorganic semiconductor material that can form a heterojunction structure with the cluster accumulation layer.
[0056] The organic semiconductor material is an organic small molecule and / or an organic polymer, preferably pentacene.
[0057] The inorganic semiconductor material is one or more of molybdenum disulfide, tin disulfide, graphene and black phosphorus.
[0058] In step S4, the process of preparing the semiconductor layer using the organic semiconductor material is vacuum evaporation and solution processing. The solution processing is spin coating, rod coating, spray coating, scraper coating, etc. The solution processing uses an orthogonal solvent to prevent damage to the underlying cluster accumulation layer.
[0059] The process for preparing the semiconductor layer by using the inorganic semiconductor material is one of mechanical peeling and transfer bonding, physical vapor deposition and chemical vapor deposition.
[0060] Preferably, the semiconductor layer is deposited by vacuum evaporation. The process conditions of the vacuum evaporation are:
[0061] Vacuum degree of vacuum chamber: (3-5)×10 -6 mBar, preferably 4×10 -6 mBar;
[0062] Vacuum evaporation rate: <0.2□ / s, preferably 0.1□ / s;
[0063] Rotation rate: 115-125° / s, preferably 120° / s;
[0064] By setting the above parameters, the thermal damage to the cluster accumulation layer caused by the evaporated pentacene can be reduced.
[0065] In step S4, the semiconductor layer functions as a conductive channel layer of a field effect transistor. The structure of the semiconductor layer is a single material intrinsic semiconductor layer, a doped semiconductor layer, or a mixed semiconductor layer or stacked layer of two or more semiconductors.
[0066] Preferably, the semiconductor layer is processed, including annealing, patterning, physical modification, chemical modification, etc. of the semiconductor layer.
[0067] In step S4, the thickness of the semiconductor layer is 20-40 nm, preferably 30 nm.
[0068] In step S5, the thickness of the source-drain electrode is 20-40 nm, preferably 30 nm.
[0069] In step S5, the material of the source and drain electrodes has a conductivity higher than 10S cm -1 The material is preferably one or more of gold, silver, copper, aluminum, single crystal silicon, carbon nanotubes, silver nanowires and conductive polymer PEDOT:PSS.
[0070] In step S5, the source-drain electrode is prepared by a process selected from magnetron sputtering, electron beam lithography, vacuum thermal evaporation, electroplating, spin coating, rod coating, spray coating and scraper coating, preferably vacuum thermal evaporation.
[0071] The process conditions of the vacuum evaporation method are as follows: vacuum degree of the vacuum chamber: (3-5)×10 -6 mBar, preferably 4×10 -6mBar; vacuum evaporation rate: <0.2□ / s, preferably 0.1□ / s; rotation rate: 115-125° / s, preferably 120° / s.
[0072] In step S5, the preparation of the source-drain electrode further includes patterned mask processing; the thickness of the metal mask used in the patterned mask processing is 10-15 μm, preferably 10 μm.
[0073] Preferably, before preparing the source and drain electrodes, a modification layer, such as a LiF layer, a MoO3 layer, etc., is formed on the surface of the semiconductor layer to achieve the purpose of changing the work function difference (energy barrier) of the semiconductor-metal interface, which is beneficial to the injection of electrons or holes.
[0074] In a second aspect, the present invention provides a transistor device, which is prepared by the method.
[0075] The transistor devices include: artificial vision system transistor devices, photoelectric field effect transistors and light-responsive neural synapse devices.
[0076] The artificial vision system transistor device is preferably a wafer-level artificial vision receptor.
[0077] The present invention has the following technical effects:
[0078] 1. The present invention innovatively introduces clusters into field effect transistors, and forms a cluster heterojunction structure with good light response through the cluster and the semiconductor layer. By utilizing the characteristics of efficient photogenerated exciton separation of clusters and the high conductivity of semiconductors, the functions of multi-wavelength light recognition, pattern memory, and strong and weak light adaptation of the visual system of various organisms can be realized, which is conducive to promoting the large-scale integration of multiple functions of artificial visual systems. At the same time, it can also serve as a good platform for constructing optoelectronic devices such as optoelectronic field effect transistors and light-responsive neural synaptic devices.
[0079] 2. Compared with other artificial vision system construction methods, the construction method provided by the present invention simplifies the device structure and preparation process, reduces the cost of preparation materials, and expands the selection range of material systems; at the same time, the optimization of cluster materials and the optimization of the conditions for forming stacking layers and heterojunction structures overcomes the difficulties of existing cluster synthesis processes that are too complicated and cannot be prepared on a large scale, and achieves the goal of wafer-level preparation. The resulting products have good uniformity and high yield, thereby providing the semiconductor device industry with a cluster material selection solution for rapid gram-level preparation, and realizing the large-scale application of cluster materials in semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0080] Figure 1 A process flow chart for preparing a wafer-level artificial visual receptor provided by the present invention.
[0081] Figure 2 This is a device cross-sectional structure diagram of the wafer-level artificial visual receptor provided by the present invention.
[0082] Figure 3 This is a device structure simulation effect diagram of the wafer-level artificial visual receptor provided by the present invention.
[0083] Figure 4 This is a physical photo of the wafer-level artificial visual receptor provided by the present invention.
[0084] Figure 5 The multi-wavelength light response and distinction diagram of the wafer-level artificial visual receptor provided by the present invention.
[0085] Figure 6 This is an external light memory storage diagram of the wafer-level artificial visual receptor provided by the present invention.
[0086] Figure 7 This is a diagram of the strong and weak light adaptability of the wafer-level artificial visual receptor provided by the present invention.
[0087] Figure 8 The transfer characteristic curve diagram of 200 transistors randomly selected from the wafer-level artificial visual receptor provided by the present invention.
[0088] Description of reference numerals:
[0089] 1. Substrate; 2. Gate electrode; 3. Dielectric layer; 4. Cluster accumulation layer; 5. Semiconductor layer; 6. Source and drain electrodes. DETAILED DESCRIPTION
[0090] The present invention will be further described below in conjunction with specific embodiments, but the present invention is not limited to the following embodiments.
[0091] Unless otherwise specified, the experimental methods used in the following examples are conventional methods.
[0092] The P-doped silicon wafer used in the following embodiments: the product name is silicon single-sided polished wafer, which adopts the crystal orientation 100 face, the resistivity is 0.05-0.2Ω / cm, the dopant is boron, the wafer diameter is 100±0.3mm, and the thickness is 400±15μm.
[0093] The silver nanoclusters used in the following examples were prepared according to the following steps:
[0094] (1) N,N-dimethylacetamide and acetonitrile were mixed in a weight ratio of 3:1 to prepare a mixed solution;
[0095] (2) adding 2-phenylglycinol and silver nitrate in a molar ratio of 1:1 to the mixed solution, stirring rapidly to generate a yellow precipitate;
[0096] (3) The obtained substrate was repeatedly washed with acetonitrile, and then heated and dried at 50° C. under nitrogen protection to obtain silver nanoclusters, which were stored in a dark, dry and sealed environment for use.
[0097] Example 1: Preparation of wafer-level artificial visual receptors
[0098] like Figure 1 As shown, the following steps are included:
[0099] (1) Immersing the P-doped silicon wafer in a piranha solution for ultrasonic cleaning at an ultrasonic power of 200 W for 30 min; the P-doped silicon wafer after treatment can be used as both a hard substrate and a gate electrode of a transistor;
[0100] (2) forming a silicon dioxide dielectric layer on the surface of the P-doped silicon wafer obtained in step (1) by a thermal oxidation process and a surface polishing process;
[0101] The capacitance of silicon dioxide is 11.5 μF / cm 2 , the relative dielectric constant is 3.9; the thickness of the silicon dioxide dielectric layer is 300nm, and the surface roughness is <1nm;
[0102] During specific operation, the current passing through the dielectric layer should be less than 1 / 1000 of the source-drain current of the source-drain electrode;
[0103] (3) dissolving atomically precise silver nanoclusters in a low boiling point solvent, tetrahydrofuran, to prepare a 4 mg / mL solution; using a spin coating method to spin coat the silicon dioxide dielectric layer at a speed of 8000 rpm / s to form a cluster stacking layer film; then annealing at 40° C. for 5 min to remove the solvent, at which point the obtained cluster stacking layer film has a thickness of 10 nm and a surface roughness of less than 0.5 nm;
[0104] (4) depositing a pentacene semiconductor layer on the annealed cluster stacking layer film by vacuum evaporation, and contacting the pentacene semiconductor layer with the cluster stacking layer to form a cluster heterojunction; wherein the vacuum degree of the vacuum chamber is 4×10 -6 mBar, vacuum evaporation rate of 0.1□ / s, rotation rate of 120° / s, so that the hard substrate rotates in the chamber and obtains better electrode thickness uniformity; the thickness of the obtained semiconductor layer is 30nm;
[0105] (5) A gold electrode layer is prepared on the obtained semiconductor layer by vacuum evaporation and patterned mask processing as a source and drain electrode, thereby completing the preparation of a wafer-level artificial visual receptor; wherein the vacuum degree of the vacuum chamber is 4×10 -6 mBar, the vacuum evaporation rate is 0.1□ / s, the rotation rate is 120° / s, the thickness of the metal mask is 10μm; the thickness of the obtained gold electrode layer is 30nm.
[0106] The device cross-sectional structure diagram of the wafer-level artificial visual receptor obtained in the above embodiment is shown in FIG. Figure 2 As shown in the figure, the device structure simulation effect diagram is as follows Figure 3 As shown, the actual photos of the device are as follows Figure 4 shown.
[0107] 1. Multi-vision function:
[0108] The wafer-level artificial visual receptor obtained in the above embodiment can realize multiple visual functions, including multi-wavelength light response and differentiation, external light memory storage, and strong and weak light adaptability, as follows:
[0109] (1) Multi-wavelength light response and differentiation:
[0110] A parallel light source was placed 2 cm above the wafer-level artificial visual receptor device, and the wavelength of the applied light was changed, including red light (620 nm), green light (525 nm), blue light (460 nm), and ultraviolet light (365 nm), while the light intensity of all wavelengths was unified to 2 mW / cm 2 .
[0111] The results are as follows Figure 5 As shown, the device exhibits response and discrimination to light of different wavelengths.
[0112] (2) External light memory storage
[0113] The obtained wafer-level artificial visual receptor device was simultaneously subjected to gate voltage and light pulses. The gate voltage was 20V, 40V, 60V and 80V, and the light pulse was blue light (460nm, light intensity 2mW / cm 2 ), and the pulse time is 5s.
[0114] The results are as follows Figure 6 As shown in the figure, the four curves shown in the figure correspond to the applied gate voltages of 20V, 40V, 60V and 80V from bottom to top, and the other pulse application conditions remain unchanged. The results show that the source-drain current of the device increases with the increase of the gate voltage, and the current value is maintained for a long time, which indicates that the above device can realize the memory storage behavior of external light.
[0115] (3) Adaptability to strong and weak light
[0116] A constant gate voltage of 0V or -10V was applied to the obtained wafer-level artificial visual receptor device, and light (blue light) of different light intensities was applied at the same time, and the device current value was read.
[0117] The results are as follows Figure 7As shown in the figure, when the gate voltage of the device is 0V, the stronger the light intensity, the current continues to rise, and the rising rate and amplitude increase accordingly; when the gate voltage of the device is -10V, the stronger the light intensity, the current continues to decrease, and the decreasing rate and amplitude increase accordingly. This current behavior is similar to the reaction of the human eye to strong light and weak light.
[0118] 2. Uniformity and yield
[0119] The transfer characteristic curves of 200 wafer-level artificial visual receptors were randomly tested, and the results are as follows: Figure 8 As shown, 200 wafer-level artificial visual receptors exhibit consistent transfer characteristic curves, indicating that transistors prepared on a large scale using the construction method provided by the present invention have good device uniformity and yield.
[0120] Although the present invention has been described in detail above with general descriptions and specific embodiments, it is obvious to those skilled in the art that some modifications or improvements may be made thereto based on the present invention. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of protection claimed by the present invention.
Claims
1. A method for building an artificial vision system, comprising the following steps: S1, preparing a gate electrode on the surface of the cleaned substrate; S2, preparing a dielectric layer on the surface of the gate electrode; S3, preparing a cluster accumulation layer on the surface of the dielectric layer; S4, preparing a semiconductor layer on the surface of the cluster accumulation layer and contacting the semiconductor layer with the cluster accumulation layer to form a cluster semiconductor heterojunction; S5. Prepare source and drain electrodes on the surface of the semiconductor layer to form an artificial vision system.
2. The method for building an artificial vision system according to claim 1, characterized in that: In step S1, the cleaning solution used for cleaning is one or more of an acid solution, an alcohol cleaning agent, a ketone cleaning agent and deionized water; The acid solution is one or more of piranha solution, concentrated sulfuric acid, nitric acid and aqua regia; The alcohol cleaning agent is one or more of methanol, ethanol and isopropanol; The ketone cleaning solution is acetone and / or pentanone; The cleaning method is ultrasonic cleaning; The ultrasonic conditions are as follows: power of 150-250W and time of more than 10 minutes; The substrate is one of a silicon wafer, a gallium nitride wafer, a silicon carbide wafer, glass, a metal sheet, an engineering plastic substrate and a resin; The gate electrode is made of a material with a conductivity higher than 10S cm -1 materials; The gate electrode is prepared by one or more of magnetron sputtering, electron beam lithography, vacuum thermal evaporation, electroplating, spin coating, rod coating, spray coating and scraping coating; The thickness of the gate electrode is 10-50 nm.
3. The method for building an artificial vision system according to claim 1 or 2, characterized in that: In step S2, the material of the dielectric layer is an insulating material with a capacitance range of 1 nF / cm 2 -100μF / cm 2 , relative dielectric constant range is 1.0-90; The preparation process of the dielectric layer is one or more of magnetron sputtering, laser direct writing, electrospray printing, solution spin coating annealing, spin coating, rod coating, spray coating and blade coating; The thickness of the dielectric layer is 50-1000 nm; The surface roughness of the dielectric layer is controlled to be below 2 nm; When the artificial vision system is working, the current passing through the dielectric layer should be less than 1 / 1000 of the source-drain current of the source-drain electrode.
4. The method for building an artificial vision system according to any one of claims 1 to 3, characterized in that: In step S3, the material of the cluster accumulation layer is a cluster material with a core-shell structure; The cluster material has the following characteristics: Periphery Ligand: A group containing a π electron system and does not contain sites that can easily capture charge; Particle size distribution standard deviation: <1nm; Heat stability: It does not decompose below 100°C, and its physical structure and chemical properties do not change; Water and oxygen stability: within 30 days, it does not react chemically with water and oxygen, maintains the physical and chemical structure unchanged, and can meet the storage capacity in a low water and oxygen environment; the low water and oxygen environment refers to a water content of <1ppm (20℃, 1atm) and an oxygen content of <1ppm (20℃, 1atm); Photoelectric properties: molar absorption coefficient>1000L mol -1 cm -1 , fluorescence quantum yield>20%; The diameter of a single cluster is in the range of 0.2-5 nm.
5. The method for building an artificial vision system according to any one of claims 1 to 4, characterized in that: In step S3, the material of the cluster is a silver nanocluster, which is prepared according to the following steps: (1) N,N-dimethylacetamide and acetonitrile were mixed in a weight ratio of 3:1 to prepare a mixed solution; (2) adding 2-phenylglycinol and silver nitrate in a molar ratio of 1:1 to the mixed solution, stirring rapidly to generate a yellow precipitate; (3) The obtained precipitate is repeatedly washed with acetonitrile, and then heated and dried under nitrogen protection to obtain the silver nanoclusters.
6. The method for building an artificial vision system according to any one of claims 1 to 5, characterized in that: In step S3, the preparation process of the cluster accumulation layer is one of a solution process, an in-situ growth method, a chemical vapor deposition method, a physical vapor transport method, an electrochemical oxidation-reduction method, and a transfer method; When the cluster stacking layer is prepared by a solution process, the following steps are followed: (1) dissolving the cluster material in a low boiling point solvent to prepare a cluster solution; (2) applying the cluster solution to the surface of the dielectric layer by spin coating, rod coating or blade coating to form the cluster accumulation layer; (3) annealing the cluster accumulation layer; In the step (1), the concentration of the cluster solution is 3-5 mg / mL; In the step (1), the low boiling point solvent is one or more of tetrahydrofuran, dichloromethane, chloroform, methanol, ethanol, and acetone; In the step (2), the process conditions of the spin coating are: rotation speed>3000rpm / s; the process conditions of the rod coating and the scraper coating are: horizontal movement speed of the rod and the scraper>2cm / s; In the step (3), the process conditions of the annealing treatment are: the temperature is 5-15° C. lower than the boiling point of the selected low-boiling-point solvent, and the time is 2-10 min.
7. The method for building an artificial vision system according to any one of claims 1 to 6, characterized in that: In step S3, the cluster accumulation layer has a thickness of 5-30 nm and a surface roughness of less than 2 nm.
8. The method for building an artificial vision system according to any one of claims 1 to 7, characterized in that: In step S4, the semiconductor layer is made of an organic semiconductor material and an inorganic semiconductor material that form a heterojunction structure with the cluster accumulation layer; When the semiconductor layer is deposited by vacuum evaporation, the process conditions of the vacuum evaporation are: Vacuum degree of vacuum chamber: (3-5)×10 -6 mBar; Vacuum evaporation rate: Rotation rate: 115-125° / s.
9. The method for building an artificial vision system according to any one of claims 1 to 8, characterized in that: In step S5, the material of the source and drain electrodes has a conductivity higher than 10S cm -1 materials; The source-drain electrode is prepared by one of magnetron sputtering, electron beam lithography, vacuum thermal evaporation, electroplating, spin coating, rod coating, spray coating and scraper coating; When the source-drain electrode is deposited by the vacuum evaporation method, the process conditions of the vacuum evaporation method are: Vacuum degree of vacuum chamber: (3-5)×10 -6 mBar; Vacuum evaporation rate: Rotation rate: 115-125° / s; The preparation of the source-drain electrode also includes patterned mask processing; the thickness of the metal mask used in the patterned mask processing is 10-15 μm.
10. A transistor device, characterized in that: Prepared by the method according to any one of claims 1 to 9; The transistor devices include: artificial vision system transistor devices, photoelectric field effect transistors and light-responsive neural synapse devices.