Preparation process of piezoelectric chip with stress adjusting structure
By growing multi-layer structures and etching the stress adjustment layer in the piezoelectric chip preparation process, the chip performance degradation and damage caused by stress release in the wafer are solved, and the yield rate is improved.
Patent Information
- Application Number
- CN202311219604.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-20
- Publication Date
- 2024-12-10
AI Technical Summary
During the assembly process of piezoelectric materials, the internal stress of the wafer will be gradually released when the chip is manufactured, resulting in the accumulation of residual stress, which may damage the chip structure and reduce the yield.
Using a piezoelectric chip preparation process with a stress-regulating structure, the metal layer is extended into the gap by growing a multilayer structure, including a metal layer and a piezoelectric layer, on the substrate surface, and etching and patterning in the stress-regulating layer, extending the metal layer into the gap to release the and adjust the wafer pressure.
Effectively release and adjust the stress of the wafer, improve the performance and yield of the chip device, and prevent stress from damaging the chip.
Smart Images
Figure CN119110665A_ABST
Abstract
Description
Technical Field
[0001] One or more embodiments of the present specification relate to the field of semiconductor process technology, and in particular, to a process for preparing a piezoelectric chip with a stress regulation structure. Background Art
[0002] At present, the composition of piezoelectric materials is complex, and the growth environment requires high temperature, high pressure and special atmosphere, which causes large internal stress to accumulate in the wafer. During the process of wafer manufacturing chips, the internal stress of the wafer will be gradually released. If the original internal stress of the wafer is too large, residual stress may be accumulated in the structure of the device during the stress release process, causing the device performance to deteriorate. In severe cases, the residual stress may even destroy the fragile structure in the chip, causing chip damage and reduced yield.
[0003] In summary, the present application now proposes a piezoelectric chip preparation process with a stress adjustment structure to solve the above-mentioned problems. Summary of the invention
[0004] The present invention aims to solve the problems raised in the background technology. The purpose of one or more embodiments of this specification is to propose a piezoelectric chip preparation process with a stress adjustment structure, which releases the pressure accumulated in the wafer through stress adjustment, ensures the performance of the chip device, and improves the yield rate.
[0005] Based on the above purpose, one or more embodiments of the present specification provide a process for preparing a piezoelectric chip with a stress adjustment structure, including the following steps: preparing a substrate, the substrate having a relative front and back side; growing a first metal layer on the front side of the substrate; growing a first piezoelectric layer on a surface of the first metal layer away from the substrate; growing a first stress adjustment layer on a surface of the first piezoelectric layer away from the substrate; etching the first stress adjustment layer to pattern the first stress adjustment layer; growing a second metal layer on a surface of the first stress adjustment layer away from the substrate, the second metal layer extending into a gap generated by the patterning of the first stress adjustment layer.
[0006] According to the process for preparing a piezoelectric chip with a stress adjustment structure described in an embodiment of the present invention, the substrate is a silicon substrate.
[0007] According to the process for preparing a piezoelectric chip with a stress adjustment structure described in an embodiment of the present invention, the substrate is an SOI substrate.
[0008] The process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention also includes the steps of: growing a second piezoelectric layer on a surface of the second metal layer away from the substrate; and growing a third metal layer on a surface of the second piezoelectric layer away from the substrate.
[0009] The process for preparing a piezoelectric chip with a stress adjustment structure described in an embodiment of the present invention also includes the following steps: growing a second piezoelectric layer on a surface of the second metal layer away from the substrate; growing a second stress adjustment layer on a surface of the second piezoelectric layer away from the substrate, etching the second stress adjustment layer, and patterning the second stress adjustment layer; growing a third metal layer on a surface of the second stress adjustment layer away from the substrate, the third metal layer extending into a gap in the second stress adjustment layer caused by patterning.
[0010] The process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention further includes the following steps: growing a third stress adjustment layer on the back side of the substrate.
[0011] According to the process for preparing a piezoelectric chip with a stress adjustment structure described in an embodiment of the present invention, the stress adjustment layer includes one or a combination of two of silicon oxide, silicon nitride and aluminum oxide.
[0012] The beneficial effects of the present invention are described in detail below with reference to the embodiments and drawings of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate one or more embodiments of the present specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of the present specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0014] Figure 1 A schematic diagram of step S1 in a process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention;
[0015] Figure 2 A schematic diagram of step S2 in a process for preparing a piezoelectric chip with a stress regulating structure according to an embodiment of the present invention;
[0016] Figure 3 A schematic diagram of step S3 in the process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention;
[0017] Figure 4 A schematic diagram of step S4 in the process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention;
[0018] Figure 5 A schematic diagram of step S5 in the process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention;
[0019] Figure 6A schematic diagram of step S6 in the process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention;
[0020] Figure 7 This is a schematic diagram of step S7 in the process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention.
[0021] In the figure markings: 1. substrate; 101. bottom silicon; 102. buried oxide layer; 103. top silicon; 2. first metal layer; 3. first piezoelectric layer; 4. first stress adjustment layer; 5. second metal layer; 6. second piezoelectric layer; 7. second stress adjustment layer; 8. third metal layer; 9. third stress adjustment layer. DETAILED DESCRIPTION
[0022] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments.
[0023] According to the following Figure 1-Figure 7 The specific steps of the process for preparing a piezoelectric chip with a stress adjustment structure in an embodiment of the present invention are described below.
[0024] Embodiment 1
[0025] The process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention comprises the following steps:
[0026] S1, prepare a substrate 1, the substrate 1 has a front side and a back side opposite to each other, and grow a first metal layer 2 on the front side of the substrate 1. Optionally, the substrate 1 is a silicon substrate 1. Optionally, the substrate 1 is an SOI substrate 1, which is composed of a top silicon 103 and a bottom silicon 101 fixedly connected by a buried oxide layer 102 (not shown in the figure).
[0027] S2, growing the first piezoelectric layer 3 on the plane of the first metal layer 2 away from the substrate 1, such as Figure 2 shown.
[0028] S3, growing a first stress adjustment layer 4 on a plane of the first piezoelectric layer 3 away from the substrate 1, and etching the first stress adjustment layer 4 to pattern the first stress adjustment layer 4, such as Figure 3 shown.
[0029] S4, growing a second metal layer 5 on a plane of the first stress adjustment layer 4 away from the substrate 1, and the second metal layer 5 extends into the gap of the first stress adjustment layer 4, such as Figure 4 shown.
[0030] Embodiment 2
[0031] The process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention comprises the following steps:
[0032] S1, prepare a substrate 1, the substrate 1 has a front side and a back side opposite to each other, and grow a first metal layer 2 on the front side of the substrate 1. Optionally, the substrate 1 is a silicon substrate 1. Optionally, the substrate 1 is an SOI substrate 1, which is composed of a top silicon 103 and a bottom silicon 101 fixedly connected by a buried oxide layer 102 (not shown in the figure).
[0033] S2, growing the first piezoelectric layer 3 on the plane of the first metal layer 2 away from the substrate 1, such as Figure 2 shown.
[0034] S3, growing a first stress adjustment layer 4 on a plane of the first piezoelectric layer 3 away from the substrate 1, and etching the first stress adjustment layer 4 to pattern the first stress adjustment layer 4, such as Figure 3 shown.
[0035] S4, growing a second metal layer 5 on a plane of the first stress adjustment layer 4 away from the substrate 1, and the second metal layer 5 extends into the gap of the first stress adjustment layer 4, such as Figure 4 shown.
[0036] S5, growing a second piezoelectric layer 6 on a plane of the second metal layer 5 away from the substrate, such as Figure 5 shown.
[0037] S6, growing a third metal layer 8 on a plane of the second piezoelectric layer 6 away from the substrate.
[0038] Embodiment 3
[0039] The process for preparing a piezoelectric chip with a stress adjustment structure according to an embodiment of the present invention comprises the following steps:
[0040] S1, prepare a substrate 1, the substrate 1 has a front side and a back side opposite to each other, and grow a first metal layer 2 on the front side of the substrate 1. Optionally, the substrate 1 is a silicon substrate 1. Optionally, the substrate 1 is an SOI substrate 1, which is composed of a top silicon 103 and a bottom silicon 101 fixedly connected by a buried oxide layer 102 (not shown in the figure).
[0041] S2, growing the first piezoelectric layer 3 on the plane of the first metal layer 2 away from the substrate 1, such as Figure 2 shown.
[0042] S3, growing a first stress adjustment layer 4 on a plane of the first piezoelectric layer 3 away from the substrate 1, and etching the first stress adjustment layer 4 to pattern the first stress adjustment layer 4, such as Figure 3 shown.
[0043] S4, growing a second metal layer 5 on a plane of the first stress adjustment layer 4 away from the substrate 1, and the second metal layer 5 extends into the gap of the first stress adjustment layer 4, such as Figure 4 shown.
[0044] S5, growing a second piezoelectric layer 6 on a plane of the second metal layer 5 away from the substrate, such as Figure 5 shown.
[0045] S6, growing a second stress adjustment layer 7 on a plane of the second piezoelectric layer 6 away from the substrate, etching the second stress adjustment layer 7, and patterning the second stress adjustment layer 7, such as Figure 6 shown.
[0046] S7 , growing a third metal layer 8 on a plane of the second piezoelectric layer 6 away from the substrate, and extending the third metal layer 8 into the gap of the second stress adjustment layer 7 .
[0047] Optionally, as a preferred embodiment of Embodiment 1-3, the method further includes the following steps:
[0048] A third stress adjustment layer 9 is grown on the back side of the substrate 1. Figure 7 shown.
[0049] Among them, the stress adjustment layer includes one or a combination of two of silicon oxide, silicon nitride and aluminum oxide. Due to the different growth materials, thickness, temperature and density, different compressive stress or tensile stress can be applied to the wafer to achieve the adjustment of the positive and negative stress of the wafer to an appropriate degree.
[0050] One or more embodiments of this specification are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of this disclosure.
Claims
1. A process for preparing a piezoelectric chip with a stress adjustment structure, characterized in that: The following steps are involved: Preparing a substrate (1), wherein the substrate (1) has a front side and a back side opposite to each other; Growing a first metal layer (2) on the front side of the substrate (1); Growing a first piezoelectric layer (3) on a surface of the first metal layer (2) away from the substrate; Growing a first stress adjustment layer (4) on a surface of the first piezoelectric layer (3) away from the substrate; Etching the first stress adjustment layer (4) to pattern the first stress adjustment layer (4); A second metal layer (5) is grown on a surface of the first stress adjustment layer (4) away from the substrate, and the second metal layer (5) extends into a gap generated by patterning the first stress adjustment layer (5).
2. The process for preparing a piezoelectric chip with a stress adjustment structure according to claim 1, characterized in that: The substrate (1) is a silicon substrate (1).
3. The process for preparing a piezoelectric chip with a stress adjustment structure according to claim 1, characterized in that: The substrate (1) is an SOI substrate (1).
4. The process for preparing a piezoelectric chip with a stress adjustment structure according to claim 1, characterized in that: Also includes the steps: Growing a second piezoelectric layer (6) on a surface of the second metal layer (5) away from the substrate; A third metal layer (8) is grown on a surface of the second piezoelectric layer (6) away from the substrate.
5. The process for preparing a piezoelectric chip with a stress adjustment structure according to claim 1, characterized in that: The following steps are also included: Growing a second piezoelectric layer (6) on a surface of the second metal layer (5) away from the substrate; Growing a second stress adjustment layer (7) on a surface of the second piezoelectric layer (6) away from the substrate, etching the second stress adjustment layer (7), and patterning the second stress adjustment layer (7); A third metal layer (8) is grown on a surface of the second stress adjustment layer (7) away from the substrate, and the third metal layer (8) extends into a gap formed by patterning of the second stress adjustment layer (7).
6. The process for preparing a piezoelectric chip with a stress regulating structure according to any one of claims 1 to 5, characterized in that: The following steps are also included: A third stress adjustment layer (9) is grown on the back side of the substrate (1).
7. The process for preparing a piezoelectric chip with a stress regulating structure according to any one of claim 6, characterized in that: The stress adjustment layer (4, 7, 9) comprises one or a combination of two of silicon oxide, silicon nitride and aluminum oxide.