Compound Hall integrated chip and preparation method thereof

Abstract

The invention discloses a compound Hall integrated chip and a preparation method thereof, and the preparation method comprises the steps: forming a groove in the wafer surface of a silicon-based signal conditioning chip after the completion of a device manufacturing process through yellow light and etching, depositing a dielectric film and an organic adhesive in the groove, and then assembling a compound Hall element into the groove, and filling the groove with a dielectric layer, and finally realizing signal connection between the compound Hall element and a conditioning circuit of the silicon-based signal conditioning chip by utilizing CONTACT, VIA and an interconnection line, thereby finally obtaining the compound Hall integrated chip. The compound Hall element and the silicon-based signal conditioning chip are integrated together through heterogeneous integration to form an independent compound Hall integrated chip, and compared with a single-chip silicon-based Hall, the compound Hall integrated chip has the performance advantages of sensitivity, temperature excursion characteristics and the like.

Description

Technical Field

[0001] The invention relates to the technical field of Hall chips, and in particular to a compound Hall integrated chip and a preparation method thereof. Background Art

[0002] The Hall chip can convert the external input magnetic field into an output electrical signal and detect the change of the magnetic field through the electrical signal. The Hall chip mainly consists of two parts: the signal conditioning circuit and the Hall element. Among them, the signal conditioning circuit is generally made on a silicon-based substrate using standard integrated circuit technology, and mainly includes functional module components such as amplification, filtering, oscillation, clock, and storage. Hall elements can be divided into silicon-based and compound-based (GaAs / InSb / InAs, etc.) according to the different substrates. Because the compound substrate has material performance advantages such as carrier concentration and carrier mobility, the compound-based Hall element has higher sensitivity and better temperature characteristics than the silicon-based Hall element.

[0003] At present, there are two types of Hall chips in the industry. The first type is a pure silicon-based Hall and silicon-based signal conditioning circuit integrated chip. This chip is limited by the silicon-based material itself and has problems such as low sensitivity and poor temperature drift. The second type is to integrate the compound Hall chip and the silicon-based signal conditioning circuit chip in the same package by die bonding, wire bonding, and plastic sealing. The package level integration generally refers to bonding the compound Hall chip and the silicon-based signal conditioning circuit chip separately during die bonding, and then interconnecting the compound Hall chip and the silicon-based signal conditioning circuit chip by wire bonding, and finally plastic sealing them together in the package to achieve integration. This chip benefits from the advantages of compound materials and is obviously superior to the first pure silicon-based Hall chip in terms of Hall electrical performance indicators. However, this sealing method has the disadvantages of large packaging volume, difficult alignment accuracy, long signal transmission path, and poor packaging reliability. At present, there is no method in the industry to obtain a single-chip integrated compound Hall and silicon-based signal conditioning circuit through heterogeneous integration.

[0004] The complete wafer process can be divided into three parts from front to back: device manufacturing process → CONTACT manufacturing process → interconnection line manufacturing process. The device manufacturing process mainly includes active area definition, ion implantation, oxidation isolation device function definition and other related processes; the CONTACT manufacturing process is to connect the functional device with the interconnection line through a through-hole structure; the interconnection line manufacturing process mainly includes VIA through-holes, metal interconnects, metal pads, dielectric layers, passivation layers and other signal lines and other related processes.

[0005] In view of the shortcomings of the existing technology, the present invention provides a compound Hall integrated chip and a preparation method thereof to solve the problem of heterogeneous integration of existing compound Hall and silicon-based signal conditioning circuits. Summary of the invention

[0006] The important significance of the present invention is to solve the problem that the current compound Hall and silicon-based signal conditioning circuits cannot be heterogeneously integrated, and to provide a method for preparing a compound Hall integrated chip. The preparation method of the compound Hall integrated chip first proposes to combine the compound Hall element and the silicon-based signal conditioning chip together through heterogeneous integration to form a separate compound Hall integrated chip; it overcomes the current implementation method that can only realize the dual-chip sealing of the compound Hall chip and the silicon-based signal conditioning chip at the packaging level, and the prepared compound Hall integrated chip has the characteristics of higher integration, higher precision, better performance, and higher reliability.

[0007] The above-mentioned purpose of the present invention is achieved by the following technical measures: Provided are a structure of a compound Hall integrated chip and a preparation method thereof. After the device manufacturing process is completed, a groove is formed on the wafer surface of a silicon-based signal conditioning chip by yellow light and etching, a dielectric film is deposited and an organic adhesive is coated in the groove, and then a compound Hall element is assembled inside the groove, and the groove is filled with a dielectric layer. Finally, CONTACT, VIA and interconnection lines are used to realize signal connection between the compound Hall element and a conditioning circuit of the silicon-based signal conditioning chip, and finally the compound Hall integrated chip is obtained.

[0008] The preparation method of the compound Hall integrated chip of the present invention is carried out by the following steps: S1, performing device manufacturing process on the wafer to obtain a silicon-based signal conditioning chip; S2, forming grooves on the surface of the wafer of the silicon-based signal conditioning chip obtained in S1 by yellow light and etching, and depositing a dielectric film and coating an organic adhesive in the grooves; S3, assembling the compound Hall element into the inside of the groove obtained in S2, and proceeding to S4; S4, depositing a dielectric layer on the surface of the wafer so that the dielectric layer fills the gap between the groove and the compound Hall element, thereby completing the chip surface flattening operation and entering S5; S5. Perform a CONTACT manufacturing process, and then perform an interconnect manufacturing process. The interconnect manufacturing process includes the production of a VIA structure, a METAL structure, an output signal pad PAD, and a passivation layer structure to achieve signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip, and finally obtain the compound Hall integrated chip.

[0009] Preferably, the above S2 is performed by the following steps: S2.1, performing yellow light treatment and etching on the S1 silicon-based signal conditioning chip to obtain a first groove structure; S2.2, depositing a dielectric film on the inner surface of the first groove structure obtained in S2.1 to obtain a second groove structure; S2.3. Apply an organic adhesive to the bottom of the second groove structure obtained in S2.2 to obtain the groove.

[0010] Preferably, the width of the first groove structure increases gradually from the bottom to the opening, and the cross-sectional shape of the first groove structure is an inverted trapezoid.

[0011] Preferably, the above S2.3 is specifically to spin-coat a layer of organic adhesive on the inner surface wafer of the second groove structure obtained in S2.2, and then only retain the organic adhesive at the bottom of the second groove structure through exposure and development to obtain the groove.

[0012] Preferably, the bottom width of the first groove structure is greater than the maximum length of the compound Hall element.

[0013] Preferably, the bottom width of the first groove structure is 100 μm to 250 μm.

[0014] Preferably, the opening width of the first groove structure is 150 μm to 300 μm.

[0015] Preferably, the depth of the first groove structure is 1 μm to 10 μm.

[0016] Preferably, the thickness of the dielectric film is 1 nm to 5 nm.

[0017] Preferably, the thickness of the organic adhesive is 1 nm to 5 nm.

[0018] Preferably, the silicon-based signal conditioning chip is provided with a substrate and functional module elements constituting a silicon-based signal conditioning circuit.

[0019] Another object of the present invention is to avoid the shortcomings of the prior art and provide a compound Hall integrated chip. The compound Hall integrated chip has the characteristics of higher integration, higher precision and higher reliability.

[0020] The above-mentioned purpose of the present invention is achieved by the following technical measures: Provided is a compound Hall integrated chip, which is prepared by using the preparation method of the compound Hall integrated chip.

[0021] A compound Hall integrated chip and a preparation method thereof of the present invention, wherein the preparation method is to form a groove on the wafer surface of the silicon-based signal conditioning chip by yellow light and etching after the device manufacturing process is completed, deposit a dielectric film and apply an organic adhesive in the groove, and then assemble the compound Hall element to the inside of the groove, and then use a dielectric layer to fill the groove, and finally use CONTACT, VIA, and interconnection lines to realize the signal connection between the compound Hall element and the functional module element of the silicon-based signal conditioning chip, and finally obtain the compound Hall integrated chip. The present invention combines the compound Hall element and the silicon-based signal conditioning chip together to form a separate compound Hall integrated chip through heterogeneous integration, which has performance advantages such as sensitivity and temperature drift characteristics compared to the single-chip silicon-based Hall. Moreover, compared with the dual-chip sealing method of the prior art through the compound Hall element and the silicon-based signal conditioning circuit, the present invention has the advantages of higher integration, higher precision, and higher reliability. The present invention forms a groove in the silicon-based signal conditioning chip to provide a wafer integration space for the compound Hall, so that the compound Hall and the silicon-based signal conditioning circuit can achieve the purpose of wafer integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention is further described with reference to the accompanying drawings, but the contents in the accompanying drawings do not constitute any limitation to the present invention.

[0023] Figure 1 This is a schematic diagram of the compound Hall integrated chip of the present invention.

[0024] Figure 2 for Figure 1 Schematic diagram of the cross section along the “AA” direction.

[0025] Figure 3 Schematic diagram of the structure of the silicon-based signal conditioning chip.

[0026] Figure 4 Schematic diagram of the silicon-based signal conditioning chip after S2.1 processing.

[0027] Figure 5 Schematic diagram of the silicon-based signal conditioning chip after S2.2 processing.

[0028] Figure 6 for Figure 5 Top view of the .

[0029] Figure 7 Schematic diagram of the silicon-based signal conditioning chip after S2.3 processing.

[0030] Figure 8 for Figure 7 A partial enlarged schematic diagram of the middle groove.

[0031] Fig. 9Schematic diagram of the compound Hall element after being assembled into the groove in S3.

[0032] Fig.10 Schematic diagram after the dielectric layer is deposited in S4.

[0033] exist Figures 1 to 10 Including: Silicon-based signal conditioning chip 100, The first groove structure 200, the dielectric film 210, the organic adhesive 220, Dielectric layer 300 , compound Hall element 400 , CONTACT structure 500 , VIA structure / METAL structure 600 , output signal pad PAD 700 , substrate 800 , and functional module element 900 . DETAILED DESCRIPTION

[0034] The technical solution of the present invention is further described in conjunction with the following embodiments.

[0035] Example 1 A preparation method of a compound Hall integrated chip, wherein a groove is formed on the wafer surface of a silicon-based signal conditioning chip 100 after the device manufacturing process is completed by yellow light and etching, a dielectric film 210 is deposited in the groove and an organic adhesive 220 is coated, and then a compound Hall element 400 is assembled into the inside of the groove, and then filled with a dielectric layer 300, and finally a signal connection between the compound Hall element 400 and the conditioning circuit of the silicon-based signal conditioning chip 100 is realized by using CONTACT, VIA, and interconnection lines, and finally a compound Hall integrated chip is obtained, such as Figure 1 and Figure 2 shown.

[0036] It should be noted that in the conventional silicon-based Hall chip wafer processing process, there are three major parts from front to back, namely, device manufacturing process → CONTACT manufacturing process → interconnection line manufacturing process. The present invention innovatively introduces a structure and its process method between the device manufacturing process and the CONTACT manufacturing process to achieve chip-level integration of compound Hall and silicon-based signal conditioning circuits, and solves the current problem of heterogeneous integration of compound Hall and silicon-based conditioning circuits on the same wafer. The present invention specifically forms a groove on the surface of the wafer after the device manufacturing process is completed by yellow light and etching, and an adhesive layer is applied in the groove. The compound Hall element 400 is assembled in the groove, and the dielectric layer 300 is filled and flattened. At this point, the newly added structure and process are completed, and then the CONTACT manufacturing process and the interconnection line manufacturing process are carried out according to the standard process to finally obtain a compound Hall integrated chip.

[0037] It can be seen that the preparation method of the compound Hall integrated chip of the present invention overcomes the current implementation approach that can only realize the dual-chip sealing of the compound Hall chip and the silicon-based signal conditioning chip 100 at the packaging level, and the prepared compound Hall integrated chip has the characteristics of higher integration, higher precision, better performance and higher reliability.

[0038] The silicon-based signal conditioning chip 100 of the present invention is a silicon-based signal conditioning chip 100 obtained by processing the device manufacturing process in the prior art and before the CONTACT manufacturing process. The specific structure of the silicon-based signal conditioning chip 100 is not the focus of the invention of the present invention, and the silicon-based signal conditioning chip 100 is provided with a substrate 800 and functional module elements 900 constituting a silicon-based signal conditioning circuit, and the functional module elements 900 can be elements such as amplification, filtering, oscillation, clock, storage, etc., and these functional module elements 900 constitute the conditioning circuit of the silicon-based signal conditioning chip 100. Moreover, the device manufacturing process, the CONTACT manufacturing process and the interconnection line manufacturing process are all conventional technical means of integrated chips, and those skilled in the art should know the specific operation process.

[0039] The preparation method of the compound Hall integrated chip of the present invention is carried out by the following steps: S1, performing device manufacturing process on the wafer to obtain a silicon-based signal conditioning chip 100, such as Figure 3 , and the silicon-based signal conditioning chip 100 has not been processed by the CONTACT process; S2, the wafer surface of the silicon-based signal conditioning chip 100 obtained in S1 is subjected to yellow light and etching to form a groove, and a dielectric film 210 is deposited in the groove and an organic adhesive 220 is coated, wherein S2 is specifically performed by the following steps: S2.1, perform yellow light and etching on the S1 silicon-based signal conditioning chip 100 to obtain a first groove structure 200, such as Figure 4 ; The width of the first groove structure 200 increases from the bottom to the opening direction, and the cross-sectional shape of the first groove structure 200 is an inverted trapezoid. The bottom width of the first groove structure 200 is greater than the maximum length of the compound Hall element 400, the bottom width of the first groove structure 200 is 100μm to 250μm, the opening width of the first groove structure 200 is 150μm to 300μm, and the depth of the first groove structure 200 is 1μm to 10μm; S2.2, depositing a dielectric film 210 on the inner surface of the first groove structure 200 obtained in S2.1 to obtain a second groove structure, such as Figure 5 and Figure 6 , wherein the dielectric film 210 has a thickness of 1 nm to 5 nm; S2.3, coating the bottom of the second groove structure obtained in S2.2 with an organic adhesive 220 to obtain a groove, such as Figure 7 and Figure 8 , wherein the thickness of the organic adhesive 220 is 1nm to 5nm; S3, assemble the compound Hall element 400 into the inside of the groove obtained in S2, and proceed to S4, as shown in Fig. 9 ; S4, depositing a dielectric layer 300 on the surface of the wafer so that the dielectric layer 300 fills the gap between the groove and the compound Hall element 400, thereby completing the chip surface flattening operation and entering S5, such as Fig.10 , wherein the dielectric layer 300 is SiO2; S5. Perform the CONTACT manufacturing process, and then perform the interconnect manufacturing process. The interconnect manufacturing process includes the production of the VIA structure 600, the METAL structure 600, the output signal pad PAD700 and the passivation layer structure to achieve the signal connection between the compound Hall element 400 and the conditioning circuit of the silicon-based signal conditioning chip 100, and finally obtain the compound Hall integrated chip.

[0040] It should be noted that the role of the organic adhesive 220 is to temporarily fix the compound Hall element 400. By depositing the dielectric layer 300 on the surface of the wafer by S4, the compound Hall element 400 can be completely fixed on the wafer and form an integral structure with the silicon-based signal conditioning chip 100. The width of the first groove structure 200 increases from the bottom to the opening direction, that is, the cross-sectional shape of the first groove structure 200 is an inverted trapezoidal shape, and the first groove structure is an inverted trapezoidal shape as a whole. The advantage of this structure is that it can facilitate the uniform deposition of the dielectric layer 300. The compound substrate 800 of the compound Hall element 400 can be made of GaAs, InSb, InAs, etc.

[0041] The compound Hall element 400 of the present invention is prepared by pre-preparing a Hall chip wafer (including a Hall functional area and interconnection lines) of a compound substrate 800 and completing thinning and cutting to separate each compound Hall element 400 from each other, and then picking up a single compound Hall element 400 and assembling it into a groove.

[0042] In the present invention, in S4, the dielectric layer 300 is deposited to fill the gap between the groove and the compound Hall element 400 with the dielectric layer 300, and then the deposition is continued to form a planarized structure surface on the surface of the first integrated chip.

[0043] S2.3 specifically comprises spin coating a layer of organic adhesive 220 on the inner surface wafer of the second groove structure obtained in S2.2, and then only retaining the organic adhesive 220 at the bottom of the second groove structure through exposure and development to obtain a groove.

[0044] It should be noted that the METAL structure 600 is a circuit routing structure in the X / Y direction, and the VIA structure 600 is a column connection point structure in the Z direction. The IC circuit design specifications are followed for the METAL structure 600 and the VIA structure 600. The METAL structure 600 and the VIA structure 600 are internal interconnections between the Hall element pads and the signal conditioning pads. The preparation methods of the METAL structure 600 and the VIA structure 600 are common knowledge in the art, and those skilled in the art should know them, so they will not be described in detail here. The output signal pad PAD700 is an externally exposed dielectric layer 300, and the output signal pad PAD700 is used for subsequent packaging leads, and the preparation method of the output signal pad PAD700 is common knowledge in the art, and those skilled in the art should know them, so they will not be described in detail here.

[0045] The compound Hall integrated chip obtained by the present invention can be used in subsequent packaging processes after thinning and cutting. The thickness after thinning is generally 150 μm to 300 μm. Thinning the substrate 800 is also common knowledge in the art, and those skilled in the art should know it, and will not be described in detail here.

[0046] The preparation method of the compound Hall integrated chip innovatively introduces a structure and its process method between the device manufacturing process and the CONTACT manufacturing process to achieve chip-level integration of the compound Hall and the silicon-based signal conditioning circuit, solving the current problem of heterogeneous integration of the compound Hall and the silicon-based conditioning circuit on the same wafer. The preparation method of the compound Hall integrated chip combines the compound Hall element 400 and the silicon-based signal conditioning chip 100 together through heterogeneous integration to form a separate compound Hall integrated chip, which has performance advantages such as sensitivity and temperature drift characteristics compared to the single-chip silicon-based Hall. Moreover, compared with the dual-chip sealing method of the compound Hall element 400 and the silicon-based signal conditioning circuit in the prior art, the present invention has the advantages of higher integration, higher precision and higher reliability. The present invention forms a groove in the silicon-based signal conditioning chip 100 to provide a wafer integration space for the compound Hall, so that the compound Hall and the silicon-based signal conditioning circuit can achieve the purpose of wafer integration.

[0047] Example 2 A method for preparing a compound Hall integrated chip, the other features of which are the same as those of Example 1, except that: the dielectric film 210 and the dielectric layer 300 are both SiO2. The dielectric film 210 has a thickness of 2nm, and the organic adhesive 220 has a thickness of 2nm. The bottom width of the first groove structure 200 is 150μm, the opening width of the first groove structure 200 is 250μm, and the depth of the first groove structure 200 is 6μm.

[0048] The size of the first groove structure 200 of the present embodiment can facilitate the compound Hall element 400 and reduce the gap between the groove and the compound Hall element 400.

[0049] Example 3 A compound Hall integrated chip is prepared by the preparation method of the compound Hall integrated chip in embodiment 1 or 2.

[0050] The compound Hall integrated chip combines the compound Hall element 400 and the silicon-based signal conditioning chip 100 to form a single compound Hall integrated chip, which has performance advantages such as sensitivity and temperature characteristics compared to single-chip silicon-based Hall. Moreover, compared with the dual-chip sealing method of the prior art using the compound Hall element 400 and the silicon-based signal conditioning circuit, the present invention has the advantages of higher integration, higher precision, and higher reliability. The present invention forms a groove in the silicon-based signal conditioning chip 100 to provide a wafer integration space for the compound Hall, so that the compound Hall and the silicon-based signal conditioning circuit can achieve the purpose of wafer integration.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the present invention.

Claims

1. A method for preparing a compound Hall integrated chip, characterized in that: After the device manufacturing process is completed, grooves are formed on the wafer surface of the silicon-based signal conditioning chip by yellow light and etching, a dielectric film is deposited and an organic adhesive is applied in the grooves, and then the compound Hall element is assembled into the inside of the grooves, and the grooves are filled with a dielectric layer. Finally, CONTACT, VIA, and interconnect lines are used to realize the signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip, and finally the compound Hall integrated chip is obtained.

2. The method for preparing the compound Hall integrated chip according to claim 1, characterized in that: The following steps are performed: S1, performing device manufacturing process on the wafer to obtain a silicon-based signal conditioning chip; S2, forming grooves on the surface of the wafer of the silicon-based signal conditioning chip obtained in S1 by yellow light and etching, and depositing a dielectric layer and coating an organic adhesive in the grooves; S3, assembling the compound Hall element into the inside of the groove obtained in S2, and proceeding to S4; S4, depositing a dielectric layer on the surface of the wafer so that the dielectric layer fills the gap between the groove and the compound Hall element, thereby completing the chip surface flattening operation and entering S5; S5. Perform a CONTACT manufacturing process, and then perform an interconnect manufacturing process. The interconnect manufacturing process includes the production of a VIA structure, a METAL structure, an output signal pad PAD, and a passivation layer structure to achieve signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip, and finally obtain the compound Hall integrated chip.

3. The method for preparing the compound Hall integrated chip according to claim 2, characterized in that: The S2 is performed by the following steps: S2.1, performing yellow light treatment and etching on the S1 silicon-based signal conditioning chip to obtain a first groove structure; S2.2, depositing a dielectric film on the inner surface of the first groove structure obtained in S2.1 to obtain a second groove structure; S2.

3. Apply an organic adhesive to the bottom of the second groove structure obtained in S2.2 to obtain the groove.

4. The method for preparing the compound Hall integrated chip according to claim 3, characterized in that: The width of the first groove structure increases gradually from the bottom to the opening direction, and the cross-sectional shape of the first groove structure is an inverted trapezoid.

5. The method for preparing the compound Hall integrated chip according to claim 3, characterized in that: The S2.3 is specifically to spin-coat a layer of organic adhesive on the inner surface wafer of the second groove structure obtained in S2.2, and then to retain only the organic adhesive at the bottom of the second groove structure through exposure and development to obtain the groove.

6. The method for preparing the compound Hall integrated chip according to claim 3, characterized in that: The bottom width of the first groove structure is greater than the maximum length of the compound Hall element.

7. The method for preparing the compound Hall integrated chip according to claim 3, characterized in that: The bottom width of the first groove structure is 100 μm to 250 μm; The opening width of the first groove structure is 150 μm to 300 μm; The depth of the first groove structure is 1 μm to 10 μm.

8. The method for preparing the compound Hall integrated chip according to claim 3, characterized in that: The thickness of the dielectric film is 1 nm to 5 nm.

9. The method for preparing the compound Hall integrated chip according to claim 3, characterized in that: The thickness of the organic adhesive is 1nm to 5nm; The silicon-based signal conditioning chip is provided with a substrate and functional module elements constituting a silicon-based signal conditioning circuit.

10. A compound Hall integrated chip, characterized in that: The compound Hall integrated chip is prepared by the preparation method of any one of claims 1 to 9.

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