Preparation method of coplanar waveguide circuit, chip substrate and chip

Abstract

The invention discloses a preparation method of a coplanar waveguide circuit, a chip substrate and a chip, and relates to the technical field of quantum. The method comprises the following steps: forming a first material layer on a first surface of a substrate, and forming a second material layer on a second surface of the substrate; forming at least one first through hole in the first material layer; forming at least one second through hole in the substrate; in the first material layer, etching a part corresponding to a conductor pattern of the first coplanar waveguide circuit to obtain the etched first material layer; in the second material layer, etching a part corresponding to a conductor pattern of the second coplanar waveguide circuit to obtain the etched second material layer; depositing a conductor material; and removing the etched first material layer and the etched second material layer to obtain the substrate with the coplanar waveguide circuit. According to the method, the preparation efficiency of the coplanar waveguide circuit is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of quantum technology, and in particular to a method for preparing a coplanar waveguide circuit, a chip substrate, and a chip. Background Art

[0002] Superconducting quantum chips have attracted widespread attention because they can be expanded to large numbers of quantum bits. Quantum bits, like classical bits, are the smallest unit of computer operation. The more bits there are, the stronger the computer's operating capabilities. Superconducting quantum bits require corresponding control wires and superconducting resonant cavities to work together. These control wires and superconducting resonant cavities are essentially coplanar waveguide circuits.

[0003] The coplanar waveguide circuits of the current chip structure are distributed on one side of the substrate, and the number of coplanar waveguide circuits that can be loaded on a single chip is limited. Therefore, it is considered to develop the chip structure from a single-sided circuit to a double-sided circuit or even a structure with multiple chips stacked (multi-layer stacking). Double-sided circuits and multi-layer stacked quantum chips rely on through holes to conduct the coplanar waveguide circuits on the upper and lower surfaces of the substrate.

[0004] Further research is needed on the preparation method of double-sided coplanar waveguide circuits. Summary of the invention

[0005] The embodiment of the present application provides a method for preparing a coplanar waveguide circuit, a chip substrate and a chip, which can improve the preparation efficiency of the coplanar waveguide circuit. The technical solution is as follows:

[0006] According to one aspect of an embodiment of the present application, a method for preparing a coplanar waveguide circuit is provided, the method comprising:

[0007] forming a first material layer on a first surface of a substrate, and forming a second material layer on a second surface of the substrate;

[0008] forming at least one first through hole in the first material layer;

[0009] Based on the at least one first through hole on the first material layer, the substrate is etched to form at least one second through hole on the substrate; wherein the second material layer serves as a stop layer for etching the substrate;

[0010] In the first material layer, a portion corresponding to the conductor pattern of the first coplanar waveguide circuit is etched to obtain an etched first material layer;

[0011] In the second material layer, etching away a portion corresponding to the conductor pattern of the second coplanar waveguide circuit to obtain an etched second material layer;

[0012] Depositing a conductor material on the surface of the substrate with the etched first material layer and the etched second material layer, and on the sidewall of at least one second through hole on the substrate;

[0013] The etched first material layer and the etched second material layer are removed to obtain a substrate with a coplanar waveguide circuit; wherein the first coplanar waveguide circuit is formed on the first surface of the substrate with the coplanar waveguide circuit, and the second coplanar waveguide circuit is formed on the second surface, and the first coplanar waveguide circuit and the second coplanar waveguide circuit are electrically connected through the conductor material at the position of the at least one second through hole.

[0014] According to one aspect of an embodiment of the present application, a chip substrate is provided, on which a coplanar waveguide circuit is provided. The coplanar waveguide circuit is prepared by using the above-mentioned method for preparing the coplanar waveguide circuit.

[0015] According to one aspect of an embodiment of the present application, a chip is provided, wherein a coplanar waveguide circuit is provided on a substrate of the chip, and the coplanar waveguide circuit is prepared by using the above-mentioned method for preparing the coplanar waveguide circuit.

[0016] According to one aspect of an embodiment of the present application, a computer device is provided, wherein the computer device is used to prepare the method for preparing the above-mentioned coplanar waveguide circuit.

[0017] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the above-mentioned method for preparing a coplanar waveguide circuit.

[0018] According to one aspect of the embodiments of the present application, a computer program product is provided, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the above-mentioned method for preparing a coplanar waveguide circuit.

[0019] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0020] On the one hand, the technical solution proposed in the embodiment of the present application solves the problem of preparing a double-sided coplanar waveguide circuit. On the other hand, when preparing a coplanar waveguide circuit, the embodiment of the present application first etches the area where the conductor material needs to be deposited, and then deposits the conductor material, so that the circuits on both sides of the substrate can be formed at one time, simplifying the preparation process and improving the preparation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1is a schematic diagram of a coplanar waveguide circuit provided by an embodiment of the present application;

[0022] Figure 2 is a schematic diagram of a deep hole preparation method in the related art;

[0023] Figure 3 It is a front circuit preparation method in the related art;

[0024] Figure 4 It is a back side circuit preparation method in the related art;

[0025] Figure 5 is a schematic diagram of the edge glue effect in the related art;

[0026] Figure 6 It is a flow chart of a method for preparing a coplanar waveguide circuit provided by an embodiment of the present application;

[0027] Figure 7 It is a block diagram of a method for preparing a coplanar waveguide circuit provided by an embodiment of the present application;

[0028] Figure 8 is a schematic diagram of a method for preparing a coplanar waveguide circuit provided by an embodiment of the present application;

[0029] Fig. 9 It is a structural block diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0031] Cloud technology refers to a hosting technology that unifies hardware, software, network and other resources within a wide area network or local area network to achieve data computing, storage, processing and sharing.

[0032] Cloud technology is a general term for network technology, information technology, integration technology, management platform technology, application technology, etc. based on the cloud computing business model. It can form a resource pool, which can be used on demand and is flexible and convenient. Cloud computing technology will become an important support. The backend services of the technical network system require a large amount of computing and storage resources, such as video websites, picture websites and more portal websites. With the rapid development and application of the Internet industry, in the future, each item may have its own identification mark, which needs to be transmitted to the backend system for logical processing. Data of different levels will be processed separately. All kinds of industry data need strong system backing support, which can be achieved through cloud computing.

[0033] Cloud technology involves basic technologies such as cloud computing, cloud storage, databases and big data. Cloud applications based on cloud technology include medical cloud, cloud IoT, cloud security, cloud calling, private cloud, public cloud, hybrid cloud, cloud gaming, cloud education, cloud conferencing, cloud social networking, artificial intelligence cloud services, etc. With the development of cloud technology and its application in different fields, more and more cloud applications will emerge.

[0034] Generally speaking, a system built based on cloud technology includes a server and a terminal. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. It can also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. The terminal can be a smart phone, tablet computer, laptop computer, desktop computer, smart speaker, smart watch, etc., but is not limited to this. The terminal and the server can be directly or indirectly connected by wired or wireless communication, and this application is not limited here.

[0035] A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. The main characteristics of quantum computers are fast operation speed, strong information processing capabilities, and a wide range of applications. Compared with classical computers, the more information is processed, the more advantageous it is for quantum computers to perform operations, and the more accurate the operations can be.

[0036] Quantum chips are the core components of quantum computers. Quantum chips integrate quantum circuits on a substrate to carry the function of quantum information processing. Drawing on the development history of traditional computers, after overcoming bottleneck technologies, research on quantum computers needs to take the path of integration in order to achieve commercialization and industrial upgrading. Superconducting systems, semiconductor quantum dot systems, micro-nano photonics systems, and even atomic and ion systems all want to take the path of chipization. From the perspective of development, superconducting quantum chip systems are ahead of other physical systems in terms of technology; traditional semiconductor quantum dot systems are also the goal of people's efforts to explore, because after all, the traditional semiconductor industry has been very mature. For example, once semiconductor quantum chips break through the threshold of fault-tolerant quantum computing in terms of decoherence time and control accuracy, it is expected to integrate the existing achievements of the traditional semiconductor industry and save development costs.

[0037] Given the advantages of quantum computers, quantum computers can be used in future systems built on cloud technology to perform some processing and calculations to provide better services.

[0038] The embodiment of the present application provides a method for preparing a coplanar waveguide circuit, a chip substrate, and a chip. The coplanar waveguide circuit prepared by the method provided in the embodiment of the present application can be applied to the substrate of a quantum chip, thereby producing a chip substrate and a quantum chip with better quality. The technical solution of the present application will be introduced and explained through several embodiments.

[0039] Before introducing the technical solution of the present application, some terms involved in the present application are explained. The following related explanations can be combined arbitrarily with the technical solution of the embodiment of the present application as optional solutions, and they all belong to the protection scope of the embodiment of the present application. The embodiment of the present application includes at least part of the following contents.

[0040] Coplanar waveguide circuit: It consists of a central conductor and semi-infinite ground planes on both sides.

[0041] Hard mask: Photoresist is usually used to define the shape of the pattern as a mask for etching the underlying circuit. Materials such as SiO2 can also be used as a pattern definition layer to etch the underlying circuit. In this case, the SiO2 layer is called a hard mask.

[0042] Deep silicon via (through silicon via): a small hole of a certain depth is etched on the silicon wafer through an etching process.

[0043] Lift off: The process in which the underlying medium is dissolved in the solution and the film layer on the medium is also removed from the substrate.

[0044] Step coverage: When a film is grown on the side wall of a deep hole, the ratio of the thickness of the film at the bottom of the deep hole to the thickness of the film at the hole opening.

[0045] The ratio of depth to width: the ratio of the depth and width of a deep hole.

[0046] Superconducting: Below a certain characteristic temperature, the resistance of the material suddenly drops to 0 and it becomes completely anti-magnetic.

[0047] Superconducting circuits: Circuit structures made of superconducting materials in superconducting quantum chips.

[0048] Ion milling: Bombarding the surface of a material with an ion beam in a certain direction to remove the oxide layer on the surface of the material.

[0049] In situ: Multiple processes are performed in a single vacuum chamber or multiple interconnected vacuum chambers without being exposed to the atmosphere.

[0050] Parasitic junction: A non-target Josephson junction caused by defects in the chip manufacturing process.

[0051] Before explaining the embodiments of the present application, a coplanar waveguide circuit and a method for preparing the coplanar waveguide circuit in the related art are first explained.

[0052] Please refer to Figure 1 , which shows a schematic diagram of a coplanar waveguide circuit. Figure 1 FIG. 1 shows a three-dimensional view of a coplanar waveguide circuit, in which a central conductor 20 and two side conductor planes 10 are present on one surface of a substrate 30. The central conductor 20 and the two side conductor planes 10 constitute a coplanar waveguide circuit. Figure 1 Sub-figure (b) of , which shows a top view of a possible coplanar waveguide circuit, wherein the central conductor 50 and the conductor planes 40 on both sides constitute a coplanar waveguide circuit. In some embodiments, the conductor planes on both sides can also be referred to as semi-infinite ground planes on both sides. In some embodiments, the central conductor is separated from the conductor plane, and the microwave signal propagates in the central conductor. In some embodiments, a superconducting film (such as titanium nitride TiN, etc.) is used as the central conductor and the ground plane, and the superconducting film between the central conductor and the ground is removed by photolithography and etching processes to form a superconducting circuit. As the number of quantum bits increases, the number of coplanar waveguide circuits required also increases exponentially, so the wiring of multi-bit superconducting quantum chips becomes a major difficulty. In the current chip structure, the coplanar waveguide circuits are distributed on one side of the substrate, and the number of coplanar waveguide circuits that can be loaded on a single chip is limited. Therefore, the problem of the limited number of coplanar waveguide circuits that can be loaded on a single chip is solved by developing the chip structure from a single-sided circuit to a double-sided circuit or even a structure in which multiple chips are stacked (multi-layer stacking). Optionally, the double-sided circuit relies on through holes to conduct the coplanar waveguide circuits on the upper and lower surfaces of the substrate. The coplanar waveguide circuits between multi-layer stacked quantum chips can be connected by solder joints.

[0053] In the field of superconducting quantum chip preparation, there is no technical solution for preparing TiN through holes first and then preparing coplanar waveguide circuits before the embodiments of this application. The preparation idea in the related art is to first prepare blind holes on the silicon substrate, then prepare the front circuit, expose the through holes on the back of the silicon substrate through thinning and polishing steps, and finally prepare the back circuit. The following embodiments describe the above preparation scheme in detail. For the convenience of description, the process flow is displayed using a side sectional view.

[0054] Please refer to Figure 2 , which shows a schematic diagram of a deep hole preparation method in the related art. Prepare a silicon wafer substrate 200 with a thickness of 500um, and spin-coat a thick photoresist. In some embodiments, the photoresist is AZ4620, the spin-coating parameters are 1000rpm, and the spin-coating is 40s to obtain a photoresist layer 210. Optionally, the thickness of the photoresist layer 210 is 13um AZ4620. In some embodiments, after spin-coating the photoresist, the small hole portion to be exposed is exposed using an ultraviolet exposure device. Optionally, a mask plate 220 is covered above the photoresist layer 210, and the photoresist layer 210 is exposed through the mask plate 220. The exposed photoresist layer is developed so that the exposed small hole area exposes the silicon substrate. In some embodiments, the diameter of the small hole is 10um. Through a deep silicon etching device, C4F8 gas and SF6 gas are cyclically and alternately introduced into the cavity to etch a deep hole with a depth greater than 200um. C4F8 plays a passivation role, so that the part of the deep hole close to the surface is protected from further etching by SF6 etching gas, so as to form a deep hole with steep side walls. SF6 gas can react chemically with silicon to etch a small hole of a certain depth.

[0055] In some embodiments, it is necessary to define the pattern by a photomask (also called a mask) in the photolithography process. The photomask has a shape, which controls whether light can pass through or not, so that the photoresist at the corresponding position is exposed or not, and then the pattern corresponding to the photomask can be obtained by development. Optionally, the properties of the region where the photoresist is exposed change and can be dissolved in a developer. Therefore, after photolithography development, a pinhole region can be exposed on the silicon substrate. Further, a deep silicon etching device is used to perform deep silicon etching on the pinhole region to obtain a deep hole.

[0056] Please refer to Figure 3 , which shows a schematic diagram of a front circuit preparation method in the related art.

[0057] In passing Figure 2 After the deep hole (blind hole) is prepared, the remaining photoresist is removed by a stripping solution to obtain a silicon substrate with a blind hole. Figure 3As shown. A TiN film 300 is grown on the front surface of the silicon wafer and the side wall of the deep hole by an atomic layer deposition (ALD) device. The atomic layer deposition method is selected because atomic layer deposition has a high step coverage rate and can grow a thin film at the bottom and side wall of the deep hole, which is suitable for a high aspect ratio structure. In some embodiments, the atomic layer deposition growth mode is plasma enhanced atomic layer deposition (PEALD). In this growth mode, the film growth is directional, and the TiN film 310 is mainly formed on the front side of the substrate and the side wall of the deep hole. Since plasma enhanced atomic layer deposition is directional, and when preparing the front circuit, it is deposited from the front side of the substrate to the back side of the substrate, making it difficult to deposit on the back side of the substrate. And because the back side of the substrate may be blocked (there is a chassis holding the substrate), it is difficult for TiN to grow on it. In some embodiments, the atomic layer deposition precursor source is TiCl4 and NH3. At a growth temperature of 450°C, TiCl4 gas and NH3 plasma are alternately introduced in a cycle. After each introduction of the precursor source, N2 is purged to remove the excess precursor source. The self-limiting property of the precursor source (no more attachment growth after a full layer) and the chemical reaction of TiCl4 and NH3 can be used to grow a 100nm thick TiN superconducting film. Then, a layer of photoresist is spin-coated on the front side of the substrate to obtain a photoresist layer 310. In some embodiments, the photoresist includes but is not limited to s1805 and AZ6112, and the thickness of the photoresist can be selected to be 1um. The front coplanar waveguide circuit is exposed using an ultraviolet exposure device. Optionally, a mask plate 320 is covered on the top of the photoresist layer 310, and the photoresist layer 310 is photoetched through the mask plate 320 to obtain an exposed photoresist layer. The exposed photoresist layer is then developed, and the front TiN to be etched is exposed. In some embodiments, after exposure, the mask plate is removed and then developed. The photoresist at the position corresponding to the mask opening will be removed by the developer to form a pattern with the same shape as the mask opening. Then, the exposed front TiN is etched by dry etching equipment to form a front coplanar waveguide circuit. In some embodiments, the dry etching scheme is to etch TiN using BCl3 and Cl2 as etching gases.

[0058] Please refer to Figure 4 , which shows a schematic diagram of a back side circuit preparation method in the related art.

[0059] The substrate 410 with the front circuit prepared is thinned and polished from the back to 200um thick by a thinning machine and a polishing machine, so that the through hole is exposed on the back of the substrate. Next, a layer of superconducting film needs to be deposited on the back of the silicon substrate for preparing the back coplanar waveguide circuit. Since the TiN in the deep hole has been exposed to the atmosphere when it is taken out from the atomic layer deposition equipment, an oxide layer will be formed on the surface. The non-superconducting contact will affect the transmission properties of the coplanar waveguide circuit. Therefore, before evaporating the back superconducting film, it is necessary to use ion milling to remove the oxidized TiN in the through hole. In some embodiments, in a vacuum environment of 1E-4torr, the substrate is bombarded with 7sccm of Ar ions for 5 minutes. Subsequently, a 100nm thick superconducting film 400 is grown in situ. The superconducting film can be a superconducting metal such as TiN, Al, etc., and the growth method can be selected from electron beam evaporation, magnetron sputtering, etc. Since the TiN oxide layer at the deep hole connection has been removed and the back superconducting film is grown in situ, the two can form a good superconducting contact. After the back film is plated, the substrate is taken out and a layer of photoresist is spin-coated on the back to obtain a photoresist layer 430. Similarly, the optional photoresists include s1805, AZ6112, etc., and the thickness of the photoresist can be selected to be 1um. The back coplanar waveguide circuit is exposed using a UV exposure device. After development, the back superconducting film to be etched is exposed, and then the exposed back superconducting film is etched away by dry etching or wet etching (depending on the back superconducting film material, if the back superconducting film material is TiN, BCl3 and Cl2 can be used to dry etch TiN; if the back superconducting film material is Al, Al etching solution can be used to etch the back circuit) to form a back coplanar waveguide circuit. Finally, the degumming liquid is used to remove the glue, and the front and back coplanar waveguide circuit can be obtained, and the front and back circuits of the substrate are electrically connected through deep holes.

[0060] The preparation of double-sided TiN coplanar waveguide circuits in the above-mentioned related technologies has the following difficulties:

[0061] 1. The process sequence is fixed, and deep holes need to be prepared first, and then the front and back coplanar waveguide circuits are prepared. Superconducting film needs to be evaporated on the side walls of the through-holes to achieve connectivity between the front and back circuits of the chip. Since the through-holes on the chip have a high aspect ratio (hole depth: hole diameter = 200um: 10um = 20:1), atomic layer deposition is required to achieve film growth with high step coverage. If the front and back circuits are prepared first, and then deep hole etching and filling are performed, the previously prepared front and back coplanar waveguide circuits need to be protected when the deep holes are filled (usually protected by photoresist), and the substrate temperature required for atomic layer deposition to grow TiN is generally very high (>300°C), and photoresist is difficult to withstand high temperatures. Therefore, deep holes need to be prepared and filled before the front and back circuits can be prepared. The photoresist-based stripping process is also difficult to use with the atomic layer deposition coating process.

[0062] 2. Based on difficulty 1, the front and back circuits need to be prepared after the thin film is evaporated on the side wall of the through hole. Otherwise, it is difficult for the prepared circuit structure to be protected by photoresist in the atomic layer deposition coating step. When preparing the front and back circuits, due to the existence of the hole, there will be areas at the edge of the hole that are not covered by photoresist (or the photoresist is uneven) after spin coating the photoresist (such as Figure 5 As shown in the sub-figure (a), the edge glue effect) leads to the failure of the subsequent etching steps (such as Figure 5 As shown in sub-figure (b), 500 is a TiN film, 520 is a small hole, there is a circle of brighter part around the small hole, and 510 is the exposed substrate. This part should have been the TiN film and was retained, so that two adjacent small holes can be connected through the TiN film, but due to the edge glue effect caused by the small hole, there is an area around the small hole that is not covered by the photoresist. Therefore, in the process of etching the coplanar waveguide circuit, there is a circle of etched area around the small hole, resulting in the two adjacent small holes that should have been connected being unable to connect). The edge glue effect is particularly significant in the case of through holes, because in the process of spin coating the photoresist, the vacuum adsorption of the base will cause the photoresist to be adsorbed to the other side of the substrate along the through hole, exacerbating the non-uniformity of the photoresist. In some embodiments, when spin coating the photoresist, the glue is dripped on the substrate, and the substrate is adsorbed on the suction cup by vacuum, and the suction cup is connected to the motor and can rotate at high speed. Generally, the substrate is flat and the photoresist is relatively uniform. However, due to the presence of small holes, it is difficult to obtain uniform photoresist by spin coating in engineering. The photoresist at the edge of the hole will be thicker than that in other areas due to surface tension. During photolithography, the gap between the mask and the photoresist surface is very small, and the photoresist at the edge of the hole can easily stick to the mask and be torn off. After exposure, there will be an area at the edge of the hole that is not covered by photoresist.

[0063] 3. When preparing the back side circuit, due to the presence of through holes, the efficiency of vacuum adsorption during the glue spreading process will be weakened, increasing the risk of the substrate being thrown out and broken.

[0064] 4. When preparing the back pattern, the front pattern needs to be protected ( Figure 4 The display shows the situation where the front pattern is not protected). The front pattern must not be damaged during the process of coating, developing, etching, etc., which imposes stronger restrictions on the selection of front and back superconducting thin film materials and processing technology.

[0065] 5. The solution using the above-mentioned related technology requires coating the front and back sides separately. When coating the back side, in order to ensure good superconducting contact between the back film and the through-hole side wall film, before coating the back side, the through-hole side wall film needs to be ion milled in situ to remove the oxide layer of the through-hole side wall film. This requires the coating equipment itself to have an ion milling function, and because the hole has a high aspect ratio, it is difficult to ensure that all oxide layers in the through-hole side wall are completely removed. If there is an oxide layer that has not been completely etched between the back-plated layer and the through-hole side wall film layer, there will be a parasitic junction, which will affect the performance of the quantum chip.

[0066] 6. Based on difficulty 5, ion milling before back-side coating will indiscriminately bombard the back-side substrate with ions, which may cause the atomic arrangement at the entire back-side substrate interface to be destroyed, affecting chip performance.

[0067] The technical solution provided in the embodiment of the present application achieves film coverage of the front and back surfaces and the side walls of the through-holes in one coating, naturally forms an ideal superconducting contact, does not require ion milling, does not damage the substrate, can effectively reduce the process steps, and is more friendly to the coating equipment. Therefore, the technical solution provided in the embodiment of the present application improves the preparation efficiency of through-hole coplanar waveguide circuits.

[0068] Please refer to Figure 6 , which shows a flow chart of a method for preparing a coplanar waveguide circuit provided by an embodiment of the present application. The execution subject of each step of the method may be a coplanar waveguide circuit preparation device. The method may include at least one of the following steps (610-670):

[0069] Step 610: forming a first material layer on a first surface of a substrate, and forming a second material layer on a second surface of the substrate.

[0070] The substrate in the embodiment of the present application is a substrate of a coplanar waveguide circuit, and can also be considered as a substrate of a chip. The present application does not limit the material of the specific substrate. In some embodiments, the substrate is an insulating material. Optionally, the material of the substrate is silicon, in which case the substrate is also referred to as a silicon substrate.

[0071] In some embodiments, the shape of the substrate surface is circular. Optionally, the two planes with the largest areas in the substrate are respectively used as the front and back (reverse) sides of the substrate. Optionally, the front and back sides of the substrate are two opposite sides. In some embodiments, the area of ​​the front and back sides of the substrate is the same.

[0072] In some embodiments, the first side of the substrate and the second side of the substrate are two opposite sides of the substrate. In some embodiments, the first side of the substrate is the front side of the substrate, and the second side of the substrate is the back side of the substrate. In some embodiments, the second side of the substrate is the front side of the substrate, or the first side of the substrate is the back side of the substrate. This application is not limited to this.

[0073] In some embodiments, the first material layer is a hard mask layer. Optionally, the first material layer is used to expose the first through hole and the conductor pattern of the first coplanar waveguide circuit on the substrate. In some embodiments, the first material layer is also a non-conductor material. Optionally, the first material layer is SiO2.

[0074] In some embodiments, the second material layer is a hard mask layer. Optionally, the second material layer is used to expose a conductor pattern of the second coplanar waveguide circuit on the substrate. Optionally, the second material layer is SiO2.

[0075] The embodiment of the present application does not limit the method of forming the first material layer and the second material layer on the substrate. The method of forming the material layer includes but is not limited to oxidation, electroplating, covering, etc.

[0076] Step 620: Form at least one first through hole on the first material layer.

[0077] In some embodiments, at least one first through hole is formed on the first material layer, and a portion of the substrate may be exposed based on the first through hole.

[0078] In some embodiments, the first through hole refers to a hole punched through the first material layer, and the hole penetrates the first material layer. The embodiment of the present application does not limit the method for forming the first through hole on the first material layer. Optionally, the first through hole is formed on the first material layer using a drilling device. Optionally, the first through hole is formed on the first material layer using a photolithography development method. Optionally, a through hole mold is buckled on the first material layer and removed, so that at least one first through hole is formed on the first material layer.

[0079] Step 630, etching the substrate based on the at least one first through hole on the first material layer to form at least one second through hole on the substrate; wherein the second material layer serves as a stop layer for etching the substrate.

[0080] In some embodiments, after forming at least one first through hole on the first material layer and exposing the substrate, etching the substrate at the exposed position of the substrate. Optionally, etching the substrate to open the substrate and form at least one second through hole.

[0081] In some embodiments, a through-hole etching device is used to etch a substrate based on at least one first through-hole on a first material layer to form at least one second through-hole on the substrate. Optionally, the through-hole etching device stops etching when the second material layer on the second side of the substrate is detected. The through-hole etching device is a device for etching through-holes. Any device that can be used to etch through-holes can be included in the protection scope of the embodiments of the present application.

[0082] In some embodiments, the diameters of the first through hole and the second through hole are the same or different. Optionally, the diameters of the first through hole and the second through hole are the same, and the center line of the first through hole and the center line of the second through hole are on the same straight line. Optionally, the first through hole and the second through hole are adjacent. The present application does not limit the position and size of the specific first through hole and the second through hole.

[0083] The etching in the embodiments of the present application may be chemical etching or physical etching, which is not limited in the present application.

[0084] In the embodiment of the present application, the second material layer is used as the stop layer for deep hole etching (through hole etching), which can effectively protect the support plate (understood as the device that carries the silicon substrate) under the substrate from being damaged, thereby reducing the manufacturing cost. In addition, since the second material layer is used as the stop layer, the through hole can be directly etched in one step, without the need to thin and polish the back side to obtain a through hole that completely penetrates the substrate as in the related art. Therefore, the technical solution provided in the embodiment of the present application can make the through hole be formed in one step, thereby reducing the manufacturing cost, reducing the manufacturing steps, and improving the manufacturing efficiency.

[0085] Step 640: Etch away a portion of the first material layer corresponding to the conductor pattern of the first coplanar waveguide circuit to obtain an etched first material layer.

[0086] Different from the method of first coating a metal film and then etching away the places where no metal film is needed in the related art, in the embodiment of the present application, the places where the conductor material needs to be coated are etched away, that is, the first material layer is etched, and the first material layer corresponding to the positions where the conductor material needs to be coated on the first surface of the substrate is etched. That is, the positions on the substrate corresponding to the etched first material layer are positions where the conductor material does not need to be coated.

[0087] In some embodiments, the first coplanar waveguide circuit represents a circuit to be arranged on the first surface of the substrate. Optionally, the circuit on the first surface of the substrate is composed of a plurality of coplanar waveguide circuits. Optionally, the plurality of coplanar waveguide circuits constitute the above-mentioned first coplanar waveguide circuit. Of course, in addition to circuits such as coplanar waveguide circuits, other circuits designed on the substrate can also be prepared using the technical solutions provided in the embodiments of the present application, and the present application does not limit this. Optionally, the conductor pattern of the first coplanar waveguide circuit refers to the area where the conductors corresponding to the circuit to be arranged on the first surface of the substrate are located. The first material layer after etching is obtained by etching away the portion corresponding to the conductor pattern of the first coplanar waveguide circuit in the first material layer. That is, the substrate area exposed by the first material layer after etching is the area for plating the conductor material.

[0088] Likewise, the etching here may be physical etching or chemical etching, which is not limited in the present application.

[0089] In some embodiments, the second through hole is located at the center conductor of the coplanar waveguide circuit. Optionally, the second through hole can also be located at the ground planes on both sides of the center conductor of the coplanar waveguide circuit. Optionally, the center conductor of the coplanar waveguide circuit of the front circuit is connected to the center conductor of the coplanar waveguide circuit on the back through the second through hole. Optionally, the center conductor of the coplanar waveguide circuit of the front circuit is connected to the center conductor of the coplanar waveguide circuit on the back through the second through hole, and the ground planes on both sides of the center conductor of the coplanar waveguide circuit of the front circuit are connected to the ground planes on both sides of the center conductor of the coplanar waveguide circuit of the back through the second through hole, and after the conductor material is deposited, the connection of the front and back circuits is realized.

[0090] Step 650: Etch away a portion of the second material layer corresponding to the conductor pattern of the second coplanar waveguide circuit to obtain an etched second material layer.

[0091] In some embodiments, the second material layer is etched to etch the second material layer at positions corresponding to all places on the second surface of the substrate where the conductor material needs to be plated. That is, the positions on the substrate corresponding to the etched second material layer are positions where the conductor material does not need to be plated.

[0092] In some embodiments, the second coplanar waveguide circuit represents a circuit to be arranged on the second surface of the substrate. Optionally, the circuit on the second surface of the substrate is composed of a plurality of coplanar waveguide circuits. Optionally, the plurality of coplanar waveguide circuits constitute the above-mentioned second coplanar waveguide circuit. Of course, in addition to the coplanar waveguide circuit, other circuits designed on the substrate can also be prepared using the technical solution provided in the embodiment of the present application, and the present application does not limit this. Optionally, the conductor pattern of the second coplanar waveguide circuit refers to the area where the conductor corresponding to the circuit to be arranged on the second surface of the substrate is located. The etched second material layer is obtained by etching away the portion corresponding to the conductor pattern of the second coplanar waveguide circuit in the second material layer. That is, the substrate area exposed by the etched second material layer is the area for plating the conductor material. Optionally, the circuit arranged on the front and the circuit arranged on the back can be the same or different.

[0093] Likewise, the etching here may be physical etching or chemical etching, which is not limited in the present application.

[0094] Step 660 , depositing a conductor material on the surface of the substrate with the etched first material layer and the etched second material layer, and on the sidewall of at least one second through hole on the substrate.

[0095] In the embodiment of the present application, the surface of the substrate with the etched first material layer and the etched second material layer, and the side wall of at least one second through hole on the substrate, make it possible to prepare the front and back circuits at one time, and the circuits on the front and back sides of the substrate are connected through the conductor material at the second through hole. This is different from the preparation method of the common waveguide circuit in the related art. In the related art, the front circuit and the unopened through hole are first plated with a metal film, and the front metal film is etched to obtain the front circuit. Then the back is thinned and polished to make the hole open. At this time, an ion milling process is required to remove the layer on the surface of the metal film, and then the metal film is plated on the back again. That is, in the related art, not only is it necessary to plate the metal film twice, but also at least one ion milling process is required, so the preparation process of the related art is relatively complicated. The technical solution provided in the embodiment of the present application directly deposits the conductor material once, without the need to be divided into two film coatings, so there is no need for an ion milling process. Similarly, the preparation steps are reduced and the preparation efficiency is improved.

[0096] Conductor material refers to the material required for laying out the circuit. The present application embodiment does not limit the specific material of the conductor material, and any material that can ensure the normal operation of the circuit can be included in the protection scope of the present application embodiment. In other embodiments, semiconductor materials can also be used as deposition objects for preparing circuits. In some embodiments, the conductor material is titanium nitride.

[0097] In some embodiments, depositing the conductor material can be understood as plating the conductor material on the surface of the substrate with the etched first material layer and the etched second material layer, and on the sidewall of at least one second through hole on the substrate. The embodiments of the present application do not limit the specific method of depositing the conductor material or the method of plating the conductor material.

[0098] Step 670, removing the etched first material layer and the etched second material layer to obtain a substrate with a coplanar waveguide circuit; wherein a first coplanar waveguide circuit is formed on the first surface of the substrate with the coplanar waveguide circuit, and a second coplanar waveguide circuit is formed on the second surface, and the first coplanar waveguide circuit and the second coplanar waveguide circuit are electrically connected through a conductor material at at least one second through hole position.

[0099] In some embodiments, after depositing the conductor material, after removing the etched first material layer and the etched second material layer, the substrate and the conductor material deposited on the first side, the second side and the second through-hole side wall of the substrate are retained, that is, a substrate with front and back side circuits is obtained, and the front and back side circuits are connected. Optionally, the etched first material layer and the etched second material layer are removed to obtain a substrate with a coplanar waveguide circuit.

[0100] In some embodiments, the etched first material layer and the etched second material layer can be considered as impurities that need to be removed after the conductor material is deposited. After all impurities on the substrate surface are removed, a substrate with a coplanar waveguide circuit is obtained.

[0101] The embodiments of the present application do not limit the method of removing impurities, and impurities can be removed by chemical means or physical means. All combinations of methods for removing impurities when preparing the circuit and other steps of the scheme should be included in the protection scope of the embodiments of the present application.

[0102] The technical solution provided in the embodiment of the present application, when preparing a coplanar waveguide circuit, first etches the area where the conductor material needs to be deposited, and then deposits the conductor material, so that the circuits on both sides of the substrate can be formed at one time, greatly simplifying the preparation process.

[0103] The above steps 610 to 670 are respectively given specific examples below. It should be noted that all steps mentioned in the embodiments of the present application can be freely combined to form new embodiments. All possible embodiments formed by combination also belong to the protection scope of the present application, and the present application does not limit the combination method.

[0104] In some embodiments, the above step 610 also includes the following step 611 or step 612.

[0105] Step 611, oxidizing the first surface of the substrate to form a first material layer, and oxidizing the second surface of the substrate to form a second material layer.

[0106] In some embodiments, the substrate is a silicon substrate, and the first surface of the substrate is oxidized to obtain silicon dioxide. In this case, the first material layer is a silicon dioxide layer. In some embodiments, the oxidation treatment is thermal oxidation.

[0107] In some embodiments, the substrate is a silicon substrate, and the second surface of the substrate is oxidized to obtain silicon dioxide. In this case, the second material layer is a silicon dioxide layer. In some embodiments, the oxidation treatment is thermal oxidation.

[0108] In some embodiments, the first surface and the second surface of the substrate are oxidized simultaneously by thermal oxidation to form the first material layer and the second material layer. Optionally, due to the non-directionality of thermal oxidation, the first material layer and the second material layer can be formed by thermally oxidizing the substrate once without oxidation twice.

[0109] Step 612, coating a first material on the first surface of the substrate to form a first material layer, and coating a second material on the second surface of the substrate to form a second material layer.

[0110] In some embodiments, the substrate is a silicon substrate, and the first material layer is a silicon dioxide layer. Silicon dioxide is directly plated on the first surface of the silicon substrate to obtain the silicon dioxide layer. In some embodiments, silicon dioxide is plated on the first surface of the silicon substrate by chemical vapor deposition (CVD) to obtain the silicon dioxide layer.

[0111] In some embodiments, the substrate is a silicon substrate, and the second material layer is a silicon dioxide layer. Silicon dioxide is directly plated on the second surface of the silicon substrate to obtain the silicon dioxide layer. In some embodiments, silicon dioxide is plated on the second surface of the silicon substrate by CVD evaporation to obtain the silicon dioxide layer.

[0112] In some embodiments, the above step 620 also includes at least one of the following steps 621 to 625.

[0113] Step 621: forming a first photoresist layer on the first material layer.

[0114] In some embodiments, a photoresist is applied to the first material layer. The embodiment of the present application does not limit the manner of forming the first photoresist on the first material layer. Optionally, the first photoresist layer is formed on the first material layer by spin coating the photoresist. Optionally, the first photoresist layer is formed on the first material layer by spray coating the photoresist. Optionally, the first photoresist layer is formed on the first material layer by thick coating the photoresist.

[0115] The present application embodiment does not limit the specific type of photoresist. Optionally, any type of photoresist can be used to form the first photoresist layer. Optionally, the type of photoresist includes but is not limited to s1805, AZ6112. In addition, the application does not limit the thickness of the first photoresist layer. In some embodiments, the photoresist is AZ6130, and a possible spin coating parameter is 1000rpm spin coating 30s, so as to obtain a 6.3um thick first photoresist.

[0116] Step 622: Cover the first photoresist layer with a first mask plate, where the first mask plate is used to cover other parts except the through hole region where the at least one first through hole is located.

[0117] In some embodiments, the first mask plate is used to block other parts except the through hole area where at least one first through hole is located. Optionally, the first mask plate is a mask plate with at least one circular hole removed. Optionally, only the area of ​​several of the circular holes on the first mask plate can transmit light. Optionally, the first mask plate is prepared in advance and corresponds to the position of the second through hole to be etched on the substrate.

[0118] Step 623 , photolithography is performed on the first photoresist layer through a first mask plate to obtain an exposed first photoresist layer.

[0119] In some embodiments, the first photoresist is photolithographically processed by ultraviolet light through the first mask. Optionally, ultraviolet light passes through the transparent first mask to irradiate the first photoresist layer. The first photoresist layer undergoes a chemical reaction after being irradiated by ultraviolet light. That is, the first photoresist layer after exposure includes unexposed photoresist and exposed photoresist. Among them, the exposed photoresist is the photoresist in the area where the first through hole is located.

[0120] Step 624 , developing the exposed first photoresist layer to expose the first through-hole region on the first material layer.

[0121] In some embodiments, the exposed first photoresist layer is developed by a developer. Optionally, the exposed photoresist is dissolved in the developer, that is, the through hole region is exposed on the first material layer.

[0122] Step 625 , etching the exposed through-hole region on the first material layer using a first etching gas to form at least one first through-hole on the first material layer.

[0123] The first etching gas is a gas used to etch the first material layer. Optionally, the first etching gas and the first material layer undergo a chemical reaction to achieve etching. In some embodiments, the first etching gas is CF4. In some embodiments, a dry etching device is used to etch the exposed through-hole area on the first material layer to form at least one first through-hole on the first material layer.

[0124] In some embodiments, step 625 further includes removing the remaining first photoresist layer.

[0125] In some embodiments, the above step 630 also includes at least one of the following steps 631 to 632.

[0126] Step 631: Use a second etching gas to etch a through hole region on the first surface of the substrate that is exposed by at least one first through hole on the first material layer.

[0127] In some embodiments, the second etching gas is a gas used for etching the substrate. Optionally, the second etching gas and the substrate undergo a chemical reaction to achieve etching. In some embodiments, the second etching gas is SF6 gas.

[0128] Step 632: When the second material layer is detected, the etching is stopped to form at least one second through hole on the substrate.

[0129] In some embodiments, in addition to the second etching gas, a protective gas is also used to protect other parts of the substrate from being etched. Optionally, the protective gas is C4F8. In some embodiments, a deep silicon etching device is used to etch a high-resistance silicon base (substrate) to form a small hole with a high aspect ratio. C4F8 plays a passivation role, so that the part of the deep hole close to the surface is protected from further etching by the SF6 etching gas to form a deep hole with steep side walls. SF6 gas can react chemically with silicon to etch a small hole of a certain depth. Specifically, C4F8 gas and SF6 gas are cyclically passed into the cavity alternately until the equipment detects that the small hole penetrates the entire substrate, that is, the deep silicon etching equipment is equipped with white light detection, which can detect the change of the depth of the small hole over time. When the second material layer on the second surface is etched, the etching rate is significantly reduced, and the hole depth changes significantly, and the etching is stopped at this time.

[0130] In some embodiments, the above step 640 also includes at least one of the following steps 641 to 645.

[0131] Step 641: forming a second photoresist layer on the first material layer.

[0132] In some embodiments, a photoresist is applied to the first material layer. The embodiment of the present application does not limit the manner of forming the second photoresist on the first material layer. Optionally, the second photoresist layer is formed on the first material layer by spin coating the photoresist. Optionally, the second photoresist layer is formed on the first material layer by spray coating the photoresist. Optionally, the second photoresist layer is formed on the first material layer by thick coating the photoresist.

[0133] The present application embodiment does not limit the specific type of photoresist. Optionally, any type of photoresist can be used to form the second photoresist layer. Optionally, the type of photoresist includes but is not limited to s1805, AZ6112. In addition, the application does not limit the thickness of the second photoresist layer. In some embodiments, the photoresist is AZ6130, and a possible spin coating parameter is 1000rpm spin coating 30s, so as to obtain a 6.3um thick second photoresist.

[0134] Step 642: Cover the second photoresist layer with a second mask plate, where the second mask plate is used to cover the other parts except the part corresponding to the conductor pattern of the first coplanar waveguide circuit.

[0135] In some embodiments, the second mask is used to block the other parts except the part corresponding to the conductor pattern of the first coplanar waveguide circuit. Optionally, the second mask is a mask that removes the part corresponding to the conductor pattern of the first coplanar waveguide circuit. Optionally, only the part of the second mask corresponding to the conductor pattern of the first coplanar waveguide circuit can be transparent. Optionally, the second mask is prepared in advance and corresponds to the position on the substrate where the conductor material needs to be deposited.

[0136] Step 643, photolithography is performed on the second photoresist layer through a second mask plate to obtain an exposed second photoresist layer.

[0137] In some embodiments, the second photoresist is photolithographically processed by ultraviolet light through the second mask. Optionally, ultraviolet light passes through the transparent second mask to irradiate the second photoresist layer. The second photoresist layer undergoes a chemical reaction after being irradiated by ultraviolet light. That is, the exposed second photoresist layer includes unexposed photoresist and exposed photoresist. The exposed photoresist is the photoresist of the portion corresponding to the conductor pattern of the first coplanar waveguide circuit.

[0138] Step 644 , developing the exposed second photoresist layer to expose an area corresponding to the conductor pattern of the first coplanar waveguide circuit on the first material layer.

[0139] In some embodiments, the exposed second photoresist layer is developed by a developer. Optionally, the exposed photoresist is dissolved in the developer, that is, an area corresponding to the conductor pattern of the first coplanar waveguide circuit is exposed on the first material layer.

[0140] Step 645 , using a third etching gas to etch the area corresponding to the conductor pattern of the first coplanar waveguide circuit exposed on the first material layer to obtain an etched first material layer.

[0141] The third etching gas is a gas used to etch the first material layer. Optionally, the third etching gas and the first material layer undergo a chemical reaction to achieve etching. In some embodiments, the third etching gas is CF4. In some embodiments, a dry etching device is used to etch the area corresponding to the conductor pattern of the first coplanar waveguide circuit exposed on the first material layer, thereby exposing the conductor pattern of the first coplanar waveguide circuit on the first material layer.

[0142] In some embodiments, step 645 further includes removing the remaining second photoresist layer.

[0143] The technical solution provided in the embodiment of the present application solves the problem in the related art that the vacuum adsorption efficiency of the glue spreading process is reduced due to the through holes.

[0144] In some embodiments, the above step 650 also includes at least one of the following steps 651 to 655.

[0145] Step 651, forming a third photoresist on the second material layer.

[0146] In some embodiments, a photoresist is applied to the second material layer. The embodiment of the present application does not limit the manner of forming the third photoresist on the second material layer. Optionally, the third photoresist layer is formed on the second material layer by spin coating the photoresist. Optionally, the third photoresist layer is formed on the second material layer by spray coating the photoresist. Optionally, the third photoresist layer is formed on the second material layer by thick coating the photoresist.

[0147] The present application embodiment does not limit the specific type of photoresist. Optionally, any type of photoresist can be used to form the third photoresist layer. Optionally, the type of photoresist includes but is not limited to s1805, AZ6112. In addition, the thickness of the third photoresist layer is not limited in the present application. In some embodiments, the photoresist is AZ6130, and a possible spin coating parameter is 1000rpm spin coating 30s, so as to obtain a 6.3um thick third photoresist.

[0148] Step 652: Cover the third photoresist with a third mask, where the third mask is used to cover the other parts except the part corresponding to the conductor pattern of the second coplanar waveguide circuit.

[0149] In some embodiments, the third mask is used to block the other parts except the part corresponding to the conductor pattern of the second coplanar waveguide circuit. Optionally, the third mask is a mask that removes the part corresponding to the conductor pattern of the second coplanar waveguide circuit. Optionally, only the part of the third mask corresponding to the conductor pattern of the second coplanar waveguide circuit can be transparent. Optionally, the third mask is prepared in advance and corresponds to the position on the substrate where the conductor material needs to be deposited.

[0150] Step 653, photolithography is performed on the third photoresist layer through a third mask plate to obtain an exposed third photoresist layer.

[0151] In some embodiments, the third photoresist is photolithographically processed by ultraviolet light through a third mask. Optionally, ultraviolet light passes through a transparent third mask to irradiate the third photoresist layer. The third photoresist layer undergoes a chemical reaction after being irradiated by ultraviolet light. That is, the exposed third photoresist layer includes unexposed photoresist and exposed photoresist. The exposed photoresist is the photoresist of the portion corresponding to the conductor pattern of the second coplanar waveguide circuit.

[0152] Step 654 , developing the exposed third photoresist layer to expose an area corresponding to the conductor pattern of the second coplanar waveguide circuit on the second material layer.

[0153] In some embodiments, the exposed third photoresist layer is developed by a developer. Optionally, the exposed photoresist is dissolved in the developer, that is, an area corresponding to the conductor pattern of the second coplanar waveguide circuit is exposed on the second material layer.

[0154] Step 655 , using a fourth etching gas to etch the region corresponding to the conductor pattern of the second coplanar waveguide circuit exposed on the second material layer to obtain an etched second material layer.

[0155] The fourth etching gas is a gas used to etch the second material layer. Optionally, the fourth etching gas and the second material layer undergo a chemical reaction to achieve etching. In some embodiments, the fourth etching gas is CF4. In some embodiments, a dry etching device is used to etch the area corresponding to the conductor pattern of the second coplanar waveguide circuit exposed on the second material layer, thereby exposing the conductor pattern of the second coplanar waveguide circuit on the second material layer.

[0156] In some embodiments, step 655 further includes removing the remaining third photoresist layer.

[0157] In some embodiments, the photoresist types and thicknesses of the first photoresist layer, the second photoresist layer, and the third photoresist layer may be the same or different, and this application does not limit this.

[0158] In some embodiments, when the front and back circuits are different, the second mask plate is also different from the third mask plate. In some embodiments, when the front and back circuits are the same, the second mask plate is also the same as the third mask plate.

[0159] In some embodiments, when the material of the first material layer and the second material layer is the same, the first etching gas, the third etching gas and the fourth etching gas may be the same or different. When the material of the first material layer and the second material layer is the same, the first etching gas, the third etching gas and the fourth etching gas may be the same or different. Of course, the second etching gas is different from the other first etching gas, the third etching gas and the fourth etching gas.

[0160] The technical solution provided in the embodiment of the present application uses SiO2 instead of photoresist to perform TiN stripping to form a coplanar waveguide circuit. Compared with the coplanar waveguide circuit prepared by etching, it can effectively avoid the etching failure caused by the edge glue effect of the hole. In addition, the coplanar waveguide circuit on the front and back sides is formed at one time, which greatly reduces the process steps and does not require special protection of the front pattern.

[0161] In some embodiments, the above step 660 also includes the following step 661.

[0162] Step 661, using thermal atomic layer deposition (TAL) to deposit a conductor material on the surface of the substrate with the etched first material layer and the etched second material layer, and on the sidewall of at least one second through hole on the substrate.

[0163] In some embodiments, thermal atomic layer deposition is non-directional, which is different from the plasma atomic deposition in the related art. By using thermal atomic layer deposition, the conductor material is deposited on the surface of the substrate with the etched first material layer and the etched second material layer, and on the side wall of at least one second through hole on the substrate, which can achieve better deposition results.

[0164] In some embodiments, the conductor material is titanium nitride. Optionally, a 100 nm thick TiN film is formed at 450° C. by alternately purging TiCl4 and NH3. Since thermal atomic layer deposition has an extremely high step coverage, TiN is evaporated on the second through hole and the areas on the front and back surfaces of the substrate that are not covered by SiO2.

[0165] In some embodiments, the above step 670 also includes the following step 671.

[0166] Step 671, using a detergent to remove the etched first material layer and the etched second material layer to obtain a substrate with a coplanar waveguide circuit.

[0167] The embodiment of the present application does not limit the specific specifications of the detergent, and any detergent that can react with the first material layer and the second material layer and does not react with the substrate and the conductor material can be used to perform step 671.

[0168] In other embodiments, detergent and ultrasound are used to remove the etched first material layer and the etched second material layer to obtain a substrate with a coplanar waveguide circuit, wherein the detergent is used to remove the etched first material layer and the etched second material layer, and the ultrasound is used to remove the conductor material deposited on the sidewalls of the etched first material layer and the etched second material layer.

[0169] In some embodiments, the substrate is a silicon substrate, the first material layer and the second material layer are silicon dioxide, and the detergent is hydrofluoric acid. Optionally, the substrate is taken out and placed sideways on a cleaning basket, and SiO2 is removed by diluted hydrofluoric acid (5% concentration), and TiN on the surface of SiO2 is peeled off by high-power ultrasound (300W, 45kHz). Under high ultrasonic power, TiN on the side wall of SiO2 also falls off, and a coplanar waveguide circuit is formed on the front and back surfaces at the same time.

[0170] The technical solution provided in the embodiment of the present application utilizes the high temperature resistance of SiO2 (can withstand temperatures above 1000°C) and solubility in hydrofluoric acid, and the hydrofluoric acid resistance of TiN, so that the atomic layer deposition high temperature coating method is combined with the stripping process to obtain a one-time formed front and back coplanar waveguide circuit.

[0171] Please refer to Figure 7 , which shows a block diagram of a method for preparing a coplanar waveguide circuit provided by an embodiment of the present application;

[0172] like Figure 7As shown in 700, first, a 5um thick SiO2 is formed on the upper and lower surfaces of a 200um high-resistance silicon substrate by thermal oxidation or chemical vapor deposition evaporation, and a photoresist is spin-coated on the front and the shape of the hole is defined by photolithography, and the aperture can be set to 10um. HMDS treatment can be used between SiO2 and the photoresist to increase adhesion. A possible photoresist is AZ6130, and a possible spin coating parameter is 1000rpm spin coating for 30s, so that a 6.3um thick photoresist is obtained. Then, a dry etching device is used to etch the exposed SiO2 to form a hard mask for deep silicon perforation. A gas used to etch SiO2 can be selected as CF4. A deep silicon etching device is used to etch the high-resistance silicon substrate to form a small hole with a high aspect ratio. C4F8 gas and SF6 gas are used to cycle and alternately pass into the cavity until the device detects that the small hole penetrates the entire substrate. The SiO2 on the back of the substrate can act as a stop layer during deep silicon etching, so that through holes can be directly formed by deep silicon etching without the need for subsequent thinning and polishing processes. After deep silicon etching forms deep holes, photoresist is spun on the front side. At this time, due to the edge glue effect of the small hole, there is an area around the small hole that is not covered by the photoresist. Through front photolithography, the area that needs to be coated with a film (including the area around the small hole that is not covered by the photoresist) is exposed to expose SiO2, and then the exposed SiO2 is etched clean by dry etching. A gas for etching SiO2 can be selected as CF4. Then the back of the substrate is turned up, and photoresist is spun on the back side. Since there is a whole plane of SiO2 on the back side, the spun photoresist will not be affected by the small hole. HMDS (hexamethyldisilane) can be used to treat SiO2 and photoresist to increase adhesion. By performing photolithography on the back of the substrate, the area that needs to be coated is exposed to expose SiO2, and then dry etching is used to etch the exposed SiO2 cleanly. A gas for etching SiO2 can be CF4. The photoresist on both sides is removed cleanly through the degumming process. An optional solution is to soak the substrate in Remover PG degumming solution at 80°C for 8 hours, and then clean and blow dry with IPA. The substrate is then placed in a thermal atomic layer deposition (TALD) device, and a 100nm TiN film is formed at 450°C by alternating purges of TiCl4 and NH3. Since TAD has an extremely high step coverage, TiN will be evaporated on the through holes and the areas on the front and back surfaces of the substrate that are not covered by SiO2. Finally, the substrate is taken out and placed sideways on a cleaning basket. SiO2 is removed by diluted hydrofluoric acid (5% concentration) and high-power ultrasound (300W, 45kHz) is used to peel off the TiN on the SiO2 surface. Under high ultrasonic power, the TiN on the side wall of SiO2 also falls off, and coplanar waveguide circuits are formed on both sides at the same time.

[0173] The technical solution provided in the embodiment of the present application integrates the hard mask function of SiO2, the deep silicon through-hole stop layer function and the stripping function, thereby improving the efficiency of material use and greatly reducing the process steps. The stripping process is used instead of etching to effectively avoid the problem of etching failure caused by the edge glue effect of the hole. The front and back graphic structures are formed at one time, avoiding the need to consider protecting the other side graphic from being damaged when the front and back graphics are prepared successively. There is no need for ion milling process, which reduces the complexity of the process and has more relaxed requirements on equipment.

[0174] Please refer to Figure 8 , which shows a schematic diagram of a method for preparing a coplanar waveguide circuit provided by an embodiment of the present application.

[0175] like Figure 8 As shown, a first material layer 810 is formed on the first surface of the substrate 800, and a second material layer 820 is formed on the second surface of the substrate 800. A first photoresist layer 830 is formed on the first material layer 810, and through a first mask plate 840, an exposed first photoresist layer is obtained, and then the exposed first photoresist layer is developed to expose at least one area corresponding to the first through hole on the first photo material layer. The first material layer is etched using a first etching gas, such as Figure 8 Then, the substrate is etched by using a second etching gas through the etched first material layer to form at least one second through hole, as shown in (4). Figure 8 As shown in (6). A second photoresist layer 850 is formed on the first material layer. A second mask plate 860 is covered on the second photoresist layer. After photolithography and development again, the following is obtained: Figure 8 (8). The first material layer is etched with a third etching gas to obtain an etched first material layer. Similarly, the second side of the substrate is also the same, a third photoresist 870 is formed on the second material layer, and a third mask plate 880 is covered on the third photoresist 870. After photolithography and development again, the following is obtained: Figure 8 (11). The second material layer is etched with a fourth etching gas to obtain an etched second material layer. After cleaning and degumming, a conductor material 890 is deposited on the substrate, such as Figure 8 As shown in (14). Finally, the impurities on the surface are cleaned with a detergent to obtain the prepared coplanar waveguide circuit.

[0176] In an exemplary embodiment, a chip substrate is further provided. The chip substrate has a coplanar waveguide circuit thereon. The coplanar waveguide circuit is prepared by using the above-mentioned method for preparing the coplanar waveguide circuit.

[0177] In an exemplary embodiment, a chip is further provided, wherein a coplanar waveguide circuit is provided on a substrate of the chip, and the coplanar waveguide circuit is prepared by using the above-mentioned method for preparing the coplanar waveguide circuit.

[0178] In an exemplary embodiment, the chip is a quantum chip.

[0179] Fig. 9 A structural block diagram of a computer device provided by another exemplary embodiment of the present application is shown.

[0180] Typically, the computer device 900 includes a processor 901 and a memory 902 .

[0181] The processor 901 may include one or more processing cores, such as a 4-core processor, a 9-core processor, etc. The processor 901 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). The processor 901 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 901 may be integrated with a GPU, which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 901 may also include an AI processor, which is used to process computing operations related to machine learning.

[0182] The memory 902 may include one or more computer-readable storage media, which may be tangible and non-transitory. The memory 902 may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 902 stores a computer program, which is loaded and executed by the processor 901 to implement the above-mentioned method for preparing the coplanar waveguide circuit. In some embodiments, the computer device is a device for preparing a coplanar waveguide circuit, and is a coplanar waveguide circuit preparation device.

[0183] Those skilled in the art will understand that Fig. 9 The structure shown in the figure does not constitute a limitation on the computer device 900, and the computer device 900 may include more or less components than those shown in the figure, or combine some components, or adopt a different arrangement of components.

[0184] In an exemplary embodiment, a computer-readable storage medium is also provided, in which a computer program is stored, and when the computer program is executed by a processor, the method for preparing the coplanar waveguide circuit described above is implemented. Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random Access Memory), SSD (Solid State Drives) or an optical disk, etc. Among them, the random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0185] In an exemplary embodiment, a computer program product is also provided, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the method for preparing a coplanar waveguide circuit.

[0186] It should be noted that the relevant data collection and processing in this application should be strictly in accordance with the requirements of relevant national laws and regulations when applied in examples, and the informed consent or separate consent of the personal information subject should be obtained, and subsequent data use and processing should be carried out within the scope of authorization of laws and regulations and the personal information subject.

[0187] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0188] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a coplanar waveguide circuit, It is characterized in that The method comprises: forming a first material layer on a first surface of a substrate, and forming a second material layer on a second surface of the substrate; forming at least one first through hole in the first material layer; Based on the at least one first through hole on the first material layer, the substrate is etched to form at least one second through hole on the substrate; wherein the second material layer serves as a stop layer for etching the substrate; In the first material layer, a portion corresponding to the conductor pattern of the first coplanar waveguide circuit is etched to obtain an etched first material layer; In the second material layer, etching away a portion corresponding to the conductor pattern of the second coplanar waveguide circuit to obtain an etched second material layer; Depositing a conductor material on the surface of the substrate with the etched first material layer and the etched second material layer, and on the sidewall of at least one second through hole on the substrate; The etched first material layer and the etched second material layer are removed to obtain a substrate with a coplanar waveguide circuit; wherein the first coplanar waveguide circuit is formed on the first surface of the substrate with the coplanar waveguide circuit, and the second coplanar waveguide circuit is formed on the second surface, and the first coplanar waveguide circuit and the second coplanar waveguide circuit are electrically connected through the conductor material at the position of the at least one second through hole.

2. The method according to claim 1, It is characterized in that The forming of a first material layer on a first surface of a substrate and the forming of a second material layer on a second surface of the substrate include: Performing oxidation treatment on the first surface of the substrate to form the first material layer, and performing oxidation treatment on the second surface of the substrate to form the second material layer; or, A first material is plated on the first surface of the substrate to form the first material layer, and a second material is plated on the second surface of the substrate to form the second material layer.

3. The method according to claim 1, It is characterized in that The forming of at least one first through hole on the first material layer comprises: forming a first photoresist layer on the first material layer; Covering the first photoresist layer with a first mask plate, wherein the first mask plate is used to cover other parts except the through hole region where the at least one first through hole is located; Performing photolithography on the first photoresist layer through the first mask plate to obtain an exposed first photoresist layer; Developing the exposed first photoresist layer to expose the through hole area on the first material layer; The exposed through-hole region on the first material layer is etched using a first etching gas to form at least one first through-hole on the first material layer.

4. The method according to claim 1, It is characterized in that The etching of the substrate based on the at least one first through hole on the first material layer to form at least one second through hole on the substrate comprises: Using a second etching gas to etch a through hole region on the first surface of the substrate that is exposed by at least one first through hole on the first material layer; When the second material layer is detected, etching is stopped to form the at least one second through hole on the substrate.

5. The method according to claim 1, It is characterized in that The step of etching a portion corresponding to the conductor pattern of the first coplanar waveguide circuit in the first material layer to obtain the etched first material layer comprises: forming a second photoresist layer on the first material layer; Covering the second photoresist layer with a second mask plate, wherein the second mask plate is used to shield other parts except the part corresponding to the conductor pattern of the first coplanar waveguide circuit; Performing photolithography on the second photoresist layer through the second mask plate to obtain an exposed second photoresist layer; Developing the exposed second photoresist layer to expose an area corresponding to the conductor pattern of the first coplanar waveguide circuit on the first material layer; The exposed area of ​​the first material layer corresponding to the conductor pattern of the first coplanar waveguide circuit is etched using a third etching gas to obtain the etched first material layer.

6. The method according to claim 1, It is characterized in that The etching of the portion corresponding to the conductor pattern of the second coplanar waveguide circuit in the second material layer to obtain the etched second material layer comprises: forming a third photoresist on the second material layer; Covering the third photoresist with a third mask, wherein the third mask is used to shield other parts except the part corresponding to the conductor pattern of the second coplanar waveguide circuit; Performing photolithography on the third photoresist layer through the third mask plate to obtain an exposed third photoresist layer; developing the exposed third photoresist layer to expose an area corresponding to the conductor pattern of the second coplanar waveguide circuit on the second material layer; The exposed area of ​​the second material layer corresponding to the conductor pattern of the second coplanar waveguide circuit is etched using a fourth etching gas to obtain the etched second material layer.

7. The method according to claim 1, It is characterized in that Depositing a conductor material on the surface of the substrate with the etched first material layer and the etched second material layer, and on the sidewall of at least one second through hole on the substrate, comprises: The conductor material is deposited on the surface of the substrate with the etched first material layer and the etched second material layer, and on the sidewall of at least one second through hole on the substrate by thermal atomic layer deposition.

8. The method according to claim 1, It is characterized in that The removing of the etched first material layer and the etched second material layer to obtain a substrate with a coplanar waveguide circuit comprises: The etched first material layer and the etched second material layer are removed by using a detergent to obtain a substrate with a coplanar waveguide circuit.

9. The method according to claim 1, It is characterized in that The substrate is a silicon substrate, the first material layer is silicon dioxide, and the second material layer is silicon dioxide.

10. The method according to claim 1, It is characterized in that The conductor material is titanium nitride.

11. A chip substrate, It is characterized in that The chip substrate carries a coplanar waveguide circuit, which is prepared by the method according to any one of claims 1 to 10.

12. A chip, It is characterized in that The chip substrate has a coplanar waveguide circuit, and the coplanar waveguide circuit is prepared by the method according to any one of claims 1 to 10.

13. The chip according to claim 12, It is characterized in that The chip is a quantum chip.

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