CTLE dynamic offset voltage calibration circuit

Abstract

The present invention discloses a CTLE dynamic offset voltage calibration circuit. In order to realize real-time correction according to the change of DC gain, the gain-to-current converter of the present invention automatically adjusts the second bias current input to the programmable current source according to the gain control signal to dynamically change the reference bias current of the programmable current source. The two output ends of the programmable current source are respectively connected to the negative signal output end and the positive signal output end of the CLTE, and are used to adjust the output direction and size of the current to compensate for the offset voltage. The present invention can automatically compensate for the offset voltage to adapt to the change of the current gain without the need for a secondary calibration process.

Description

Technical Field

[0001] The invention relates to the field of communications, and in particular to a CTLE dynamic offset voltage calibration circuit. Background Art

[0002] In order to meet the growing demand for data capacity, rate and throughput in data centers, the performance requirements of RF / analog integrated circuits are becoming increasingly stringent. To reduce power consumption, the current mainstream double-rate synchronous dynamic random access memory has adopted a single-ended signal transmission mode, which places higher requirements on circuit accuracy compared to the fully differential signal transmission mode.

[0003] High-speed data links often use fully differential amplifiers, but due to process deviations and random errors, there is mismatch in integrated circuit devices, which causes the amplifier to generate an offset voltage. In actual operation, the offset voltage will be superimposed on the actual signal, changing the threshold voltage required for the amplifier output to flip, thereby affecting the signal accuracy, and in severe cases may cause bit errors.

[0004] In order to increase the information transmission rate, the receiver often uses a continuous time linear equalizer (CTLE) to alleviate problems such as inter-symbol interference and bandwidth reduction introduced by non-ideal channel characteristics. CTLE has an adjustable gain function, but the gain change will cause the offset voltage to change, making the initial calibration invalid. However, in most cases, the system cannot provide time to recalibrate the offset voltage.

[0005] In high-speed communication systems, CTLE is usually used as the first stage of the receiver. Its offset voltage needs to be calibrated when the system starts up, but it cannot be calibrated again during normal operation. Since the CTLE output offset voltage changes with the gain, adjusting the DC gain will generate a new offset voltage, thereby reducing the system accuracy.

[0006] At present, the industry mainly adopts the following methods to solve the CTLE offset voltage calibration problem: add a programmable current source array at the CTLE current source bias, and change the DC voltage at the differential output end by adjusting the current to make it equal. First, use a comparator to compare the differential output voltage, and then calculate the adjustment strategy of the programmable current source through the offset voltage calibration algorithm, and finally achieve offset voltage calibration. However, this method cannot adjust the offset voltage calibration value in real time according to the change of CTLE gain.

[0007] The dynamic offset voltage calibration method for a CTLE circuit proposed in the present invention can perform real-time correction according to a change in direct current gain without the need for recalibration. Summary of the invention

[0008] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

[0009] A CTLE dynamic offset voltage calibration circuit comprises: an analog switch connected in series between a positive signal input terminal of the CTLE and a negative signal input terminal of the CTLE, and when a control terminal of the analog switch receives an enable signal output by a calibration circuit, the analog switch is turned on; a CTLE receives a gain control signal, and a negative signal output terminal of the CTLE is connected to a non-inverting input terminal of a comparator, and a positive signal output terminal of the CTLE is connected to an inverting input terminal of the comparator, and an output terminal of the comparator is connected to the calibration circuit; the calibration circuit outputs a current adjustment control code to a programmable current source; a gain-to-current converter is connected to the calibration circuit; The gain control signal and the first bias current are received, and the second bias current is output to a programmable current source; the programmable current source, the positive output terminal of the programmable current source is connected to the positive signal output terminal of the CTLE, and the negative output terminal of the programmable current source is connected to the negative signal output terminal of the CTLE; in addition, when the gain control signal indicates that the gain of the CTLE increases, the second bias current output by the gain-to-current converter also increases; the current adjustment control code output by the calibration circuit makes: within m clock cycles, the number n of high levels output by the comparator is within a set interval including m / 2, where m is a positive integer and n is an integer.

[0010] Furthermore, the number n of high levels output by the comparator is within a setting interval including m / 2, specifically: 0.55×m>n>0.45×m.

[0011] Furthermore, the programmable current source includes the following circuit structure:

[0012] The drain of the NMOS tube M20 is connected to the second bias current, the source of the NMOS tube M20 is connected to VSS, and the drain of the NMOS tube M20 is connected to the gate of the NMOS tube M20;

[0013] The gate of the NMOS tube M20 is also connected to the gate of the NMOS tube M21, the gate of the NMOS tube M22, the gate of the NMOS tube M23, the gate of the NMOS tube M24 and the gate of the NMOS tube M25;

[0014] The source of the NMOS tube M21, the source of the NMOS tube M22, the source of the NMOS tube M23, the source of the NMOS tube M24 and the source of the NMOS tube M25 are all connected to VSS;

[0015] The drain of the NMOS tube M21, the drain of the NMOS tube M22, the drain of the NMOS tube M23, the drain of the NMOS tube M24 and the drain of the NMOS tube M25 are respectively connected to the first end of the transmission gate T1, the first end of the transmission gate T2, the first end of the transmission gate T3, the first end of the transmission gate T4 and the first end of the transmission gate T5;

[0016] The second end of the transmission gate T1, the second end of the transmission gate T2, the second end of the transmission gate T3, the second end of the transmission gate T4, and the second end of the transmission gate T5 are all connected to the first node;

[0017] The first node is connected to the source of the NMOS tube M26 and the source of the NMOS tube M27;

[0018] The drain of the NMOS tube M26 and the drain of the NMOS tube M27 lead to the positive output terminal of the programmable current source and the negative output terminal of the programmable current source respectively.

[0019] Furthermore, the gate of the NMOS transistor M26 and the gate of the NMOS transistor M27 are controlled by a pair of inverted signals; one of the pair of inverted signals belongs to a control bit in the current adjustment control code.

[0020] Further, the transmission gates T1 , T2 , T3 , T4 and T5 are controlled by the current adjustment control code.

[0021] Furthermore, for the NMOS transistor M20 , the NMOS transistor M21 , the NMOS transistor M22 , the NMOS transistor M23 , the NMOS transistor M24 , and the NMOS transistor M25 , the ratio of their channel widths is 1:1:2:4:8:16.

[0022] Furthermore, the gain-to-current converter includes the following circuit structure:

[0023] The source of the PMOS tube M30, the source of the PMOS tube M31, the source of the PMOS tube M32 and the source of the PMOS tube M33 are all connected to VDD;

[0024] The gate of the PMOS tube M30, the gate of the PMOS tube M31, the gate of the PMOS tube M32 and the gate of the PMOS tube M33 are all connected to the drain of the PMOS tube M30;

[0025] The drain of the PMOS tube M30 is connected to the first bias current;

[0026] The drain of the PMOS tube M31, the drain of the PMOS tube M32 and the drain of the PMOS tube M33 are respectively connected to the first end of the transmission gate T6, the first end of the transmission gate T7 and the first end of the transmission gate T8;

[0027] The second end of the transmission gate T6, the second end of the transmission gate T7 and the second end of the transmission gate T8 are connected together and output a second bias current;

[0028] The transmission gates T6 , T7 and T8 are controlled by the gain control signal.

[0029] Furthermore, the first bias current comes from outside the CTLE dynamic offset voltage calibration circuit.

[0030] Furthermore, the ratio of the channel widths of the PMOS transistor M30 , the PMOS transistor M31 , the PMOS transistor M32 , and the PMOS transistor M33 is 1:1:2:4.

[0031] Furthermore, when the CTLE calibration starts, an enable signal is sent to the analog switch to turn on the analog switch; when the CTLE calibration ends, the enable signal is turned off to turn off the analog switch.

[0032] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0033] (1) The present invention can achieve the offset voltage change caused by the gain change of the CTLE by only one offset voltage calibration, without the need for a re-calibration process. In order to overcome the influence of the offset voltage change with the gain, the prior art will perform real-time calibration, that is, calibration will be performed immediately after the gain of the CTLE changes. This method may interrupt the service and delay the system process. The present invention can be performed before the service starts. When the gain of the CTLE changes, the present invention can automatically compensate for the offset voltage to adapt to the current gain change without the need for a secondary calibration process.

[0034] (2) It can be used to follow the offset voltage changes of the CTLE due to temperature changes through a single offset voltage calibration.

[0035] (3) Automatic offset voltage calibration can be achieved through built-in comparator and software configuration without the need for complex external logic circuits.

[0036] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a block diagram of a CTLE dynamic offset voltage calibration circuit of the present invention;

[0038] Figure 2 This is the CTLE circuit diagram;

[0039] Figure 3 is the comparator circuit diagram;

[0040] Figure 4It is the working flow chart of the correction circuit;

[0041] Figure 5 is the circuit diagram of a programmable current source;

[0042] Figure 6 is the circuit diagram of a gain-to-current converter. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0045] Figure 1 The invention discloses a block diagram of a CTLE dynamic offset voltage calibration circuit, which includes an analog switch, a CTLE, a comparator, a gain-to-current converter, a programmable current source and a calibration circuit.

[0046] The CTLE includes a positive signal input terminal and a negative signal input terminal, and also includes a positive signal output terminal and a negative signal output terminal. In addition, an analog switch is connected in series between the positive signal input terminal and the negative signal input terminal. After the control terminal of the analog switch receives an enable signal, the analog switch is turned on, so that the positive signal input terminal and the negative signal input terminal are short-circuited. At this time, the voltage difference of the differential output of the CTLE is the offset voltage.

[0047] By way of example, the analog switch may be a transmission gate, and the analog switch receives a pair of inverse signals as control signals.

[0048] The CTLE also receives a gain control signal as an input signal. For example, the gain control signal may be a 3-bit digital code, such as A<2:0>, including: A <2> , A <1> and A <0> Furthermore, in actual use, the inverted signal of the gain control signal can also be used in combination: Ab <2> ,Ab <1> and Ab <0> The gain control signal can be used to adjust the gain of the CTLE.

[0049] The negative signal output terminal of the CTLE and the positive signal output terminal of the CTLE are connected to the same-direction input terminal of the comparator and the inverting input terminal of the comparator respectively. The comparator also receives a clock signal as an input signal.

[0050] The output terminal of the comparator is connected to the calibration circuit, and the comparator outputs a high level or a low level comparison result to the calibration circuit. The calibration circuit can output an enable signal, and the enable signal can be transmitted to the control terminal of the analog switch.

[0051] The calibration circuit generates a 6-bit current adjustment control code according to the comparison result output by the comparator. The 6-bit current adjustment control code can be recorded as Sel<5:0>, including: Sel <5> 、Sel <4> , Sel <3> 、Sel <2> 、Sel <1> and Sel <0> , and the inverting signal of the current adjustment control code: Selb <5> , Selb <4> , Selb <3> , Selb <2> , Selb <1> and Selb <0> .

[0052] The gain-to-current converter receives a first bias current and a gain control signal provided externally, and converts the gain control signal into a second bias current for changing a reference bias current of a programmable current source, thereby achieving a gain adaptive target.

[0053] Two output terminals of the programmable current source are respectively connected to the negative signal output terminal and the positive signal output terminal of the CLTE, and are used to adjust the output direction and magnitude of the current to compensate for the offset voltage.

[0054] Figure 2 This is the CTLE circuit diagram. This CTLE is a conventional CTLE. It includes a load resistor, a differential input pair consisting of two N-channel Metal Oxide Semiconductor (NMOS) tubes, two current sources, a feedback resistor and a feedback capacitor. The feedback resistor is controlled by the gain control signal to adjust the gain of the CTLE. The control ends of the differential input pair are the positive input end and the negative input end, respectively, and the connection nodes between the differential input pair and the load resistor are the negative output end and the positive output end. One end of the load resistor is connected to the device operating voltage (Voltage Drain-to-Drain, VDD), and one end of the current source is connected to the common ground voltage (Voltage Source-to-Source, VSS).

[0055] Figure 3: is a comparator circuit diagram. The comparator includes NMOS tube M0, NMOS tube M1, NMOS tube M2, NMOS tube M3 and NMOS tube M4, and also includes P-channel Metal Oxide Semiconductor (PMOS) tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, PMOS tube M9 and PMOS tube M10.

[0056] Sources of the PMOS tube M5 , the PMOS tube M6 , the PMOS tube M7 , the PMOS tube M8 , the PMOS tube M9 and the PMOS tube M10 are all connected to the device operating voltage (Voltage Drain-to-Drain, VDD).

[0057] The drains of PMOS tubes M5 and M7 are connected to the negative output terminal, the drains of PMOS tubes M6 and M8 are connected to the positive output terminal, the drain of PMOS tube M9 is connected to the source of NMOS tube M3, and the drain of PMOS tube M10 is connected to the source of NMOS tube M4.

[0058] The gate of the PMOS tube M5 is connected to the positive output terminal, and the gate of the PMOS tube M6 is connected to the negative output terminal. The gate of the PMOS tube M7 is connected to the clock signal, and the gate of the PMOS tube M8 is connected to the clock signal. The gate of the PMOS tube M9 is connected to the clock signal, and the gate of the PMOS tube M10 is connected to the clock signal. The function of the clock signal is to reset the comparator.

[0059] The gate of NMOS tube M4 is connected to the negative output terminal, the gate of NMOS tube M3 is connected to the positive output terminal, the gate of NMOS tube M2 is connected to the inverting input terminal, the gate of NMOS tube M1 is connected to the non-inverting input terminal, and the gate of NMOS tube M0 is connected to the clock signal.

[0060] The drain of NMOS tube M3 is connected to the drain of PMOS tube M5, and the drain of NMOS tube M4 is connected to the drain of PMOS tube M6. The source of NMOS tube M3 is connected to the drain of NMOS tube M1, and the source of NMOS tube M4 is connected to the drain of NMOS tube M2. The source of NMOS tube M2 and the source of NMOS tube M1 are both connected to the drain of NMOS tube M0, and the source of NMOS tube M0 is connected to VSS.

[0061] Figure 4is a flowchart of the calibration circuit. When the offset voltage calibration starts, it is initialized first, and the current adjustment control code output by the calibration circuit is set to 0, which is recorded as out=0. In this example, the current adjustment control code is 6 bits. In the present invention, the current adjustment control code output by the calibration circuit makes: within m clock cycles, the number n of high levels output by the comparator is within a set interval including m / 2, where m is a positive integer and n is an integer.

[0062] Then, the number n of high levels output by the comparator within m clock cycles is counted.

[0063] If 0.55×m>n>0.45×m holds, the calibration process ends, the current out value is used as the current adjustment control code, and the enable signal is turned off.

[0064] If n≤0.45×m, turn on the enable signal, update out=out+32, and count the number n of high levels output by the comparator within m clock cycles.

[0065] If n≥0.55×m, turn on the enable signal, update out=out+64, and count the number n of high levels output by the comparator within m clock cycles.

[0066] Next, determine whether 0.55×m>n>0.45×m is true. If true, the calibration process ends, and the current out value is used as the current adjustment control code, and the enable signal is turned off. If not true, determine whether out is greater than 32. If out>32, the calibration process ends, and the current out value is used as the current adjustment control code, and the enable signal is turned off. If out≤32, update out=out+1, and count the number of high levels output by the comparator within m clock cycles.

[0067] Then, it continues to determine whether 0.55×m>n>0.45×m is true, and updates the out value in a timely manner until 0.55×m>n>0.45×m is true, or out>32 is true. It is worth mentioning that the out value is only 6 bits, so overflow may occur when updating the out value.

[0068] Figure 5 1 is a circuit diagram of a programmable current source, which includes NMOS tube M20, NMOS tube M21, NMOS tube M22, NMOS tube M23, NMOS tube M24, NMOS tube M25, NMOS tube M26 and NMOS tube M27, and includes transmission gates T1, T2, T3, T4 and T5.

[0069] Transmission gates T1 to T5 are used to control whether the programmable current source can provide current. They are controlled by the current adjustment control code: Sel <4> 、Sel <3> 、Sel <2> 、Sel <1> and Sel <0> And the inverting signal of the current adjustment control code: Selb <4> , Selb <3> , Selb <2> , Selb <1> and Selb <0> The gate of the NMOS tube M26 and the gate of the NMOS tube M27 are respectively controlled by Sel <5> and Selb <5> , Sel <5> and Selb <5> It is the control signal for selecting the conduction direction. They are a pair of anti-phase signals. <5> A control bit in the current adjustment control code.

[0070] The second bias current comes from the gain-to-current converter. The drain of the NMOS tube M20 is connected to the second bias current, the source of the NMOS tube M20 is connected to VSS, and the drain of the NMOS tube M20 is connected to the gate of the NMOS tube M20.

[0071] The gate of the NMOS transistor M20 is also connected to the gates of the NMOS transistor M21, the gates of the NMOS transistor M22, the gates of the NMOS transistor M23, the gates of the NMOS transistor M24, and the gates of the NMOS transistor M25. The sources of the NMOS transistor M21, the source of the NMOS transistor M22, the source of the NMOS transistor M23, the source of the NMOS transistor M24, and the source of the NMOS transistor M25 are all connected to VSS.

[0072] The drain of the NMOS tube M21, the drain of the NMOS tube M22, the drain of the NMOS tube M23, the drain of the NMOS tube M24 and the drain of the NMOS tube M25 are respectively connected to the first end of the transmission gate T1, the first end of the transmission gate T2, the first end of the transmission gate T3, the first end of the transmission gate T4 and the first end of the transmission gate T5.

[0073] The second end of the transmission gate T1 , the second end of the transmission gate T2 , the second end of the transmission gate T3 , the second end of the transmission gate T4 , and the second end of the transmission gate T5 are all connected to the first node.

[0074] The first node is connected to the source of the NMOS transistor M26 and the source of the NMOS transistor M27. The drain of the NMOS transistor M26 and the drain of the NMOS transistor M27 lead to the positive output terminal of the programmable current source and the negative output terminal of the programmable current source respectively.

[0075] The positive output terminal of the programmable current source is connected to the positive signal output terminal of the CTLE, and the negative output terminal of the programmable current source is connected to the negative signal output terminal of the CTLE. In addition, for NMOS transistor M20, NMOS transistor M21, NMOS transistor M22, NMOS transistor M23, NMOS transistor M24 and NMOS transistor M25, their channel width ratios are: 1:1:2:4:8:16.

[0076] Figure 6 is a circuit diagram of a gain-to-current converter. The gain-to-current converter includes a PMOS tube M30, a PMOS tube M31, a PMOS tube M32, and a PMOS tube M33.

[0077] The source of the PMOS transistor M30 , the source of the PMOS transistor M31 , the source of the PMOS transistor M32 , and the source of the PMOS transistor M33 are all connected to VDD.

[0078] The gates of the PMOS tube M30, the gates of the PMOS tube M31, the gates of the PMOS tube M32 and the gates of the PMOS tube M33 are all connected to the drain of the PMOS tube M30. The drain of the PMOS tube M30 is connected to a first bias current. The first bias current may be from outside the CTLE dynamic offset voltage calibration circuit.

[0079] The drain of the PMOS tube M31, the drain of the PMOS tube M32 and the drain of the PMOS tube M33 are connected to the first end of the transmission gate T6, the first end of the transmission gate T7 and the first end of the transmission gate T8 respectively. The second end of the transmission gate T6, the second end of the transmission gate T7 and the second end of the transmission gate T8 are connected together and output a second bias current. The transmission gates T6, T7 and T8 are controlled by the gain control signal: A <2> , A <1> and A <0> , and the inverted signal of the gain control signal: Ab <2> ,Ab <1> and Ab <0> .

[0080] The channel width ratios of the PMOS tube M30 , the PMOS tube M31 , the PMOS tube M32 , and the PMOS tube M33 are 1:1:2:4.

[0081] When the gain of the CTLE increases, the value of the output offset voltage becomes larger. The present invention eliminates the larger offset voltage value by connecting a larger second bias current to the programmable current source; and vice versa.

[0082] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0083] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A CTLE dynamic offset voltage calibration circuit, characterized in that: include: The analog switch is connected in series between the positive signal input terminal of the CTLE and the negative signal input terminal of the CTLE. When the control terminal of the analog switch receives the enabling signal output by the calibration circuit, the analog switch is turned on. CTLE receives the gain control signal, and the negative signal output terminal of CTLE is connected to the non-inverting input terminal of the comparator, and the positive signal output terminal of CTLE is connected to the inverting input terminal of the comparator. a comparator, wherein an output terminal of the comparator is connected to the calibration circuit, and the comparator receives a clock signal as an input signal; A calibration circuit, outputting a current adjustment control code to a programmable current source; a gain-to-current converter, receiving a gain control signal and a first bias current, and outputting a second bias current to a programmable current source; A programmable current source, wherein a positive output terminal of the programmable current source is connected to a positive signal output terminal of the CTLE, and a negative output terminal of the programmable current source is connected to a negative signal output terminal of the CTLE; also, When the gain control signal indicates that the gain of the CTLE increases, the second bias current output by the gain-to-current converter also increases; The current adjustment control code output by the calibration circuit makes: within m clock cycles, the number n of high levels output by the comparator is within a set interval including m / 2, where m is a positive integer and n is an integer; The number n of high levels output by the comparator is within a setting interval including m / 2, specifically: 0.55×m>n>0.45×m.

2. The CTLE dynamic offset voltage calibration circuit according to claim 1, characterized in that: The programmable current source comprises the following circuit structure: The drain of the NMOS tube M20 is connected to the second bias current, the source of the NMOS tube M20 is connected to VSS, and the drain of the NMOS tube M20 is connected to the gate of the NMOS tube M20; The gate of the NMOS tube M20 is also connected to the gate of the NMOS tube M21, the gate of the NMOS tube M22, the gate of the NMOS tube M23, the gate of the NMOS tube M24 and the gate of the NMOS tube M25; The source of the NMOS tube M21, the source of the NMOS tube M22, the source of the NMOS tube M23, the source of the NMOS tube M24 and the source of the NMOS tube M25 are all connected to VSS; The drain of the NMOS tube M21, the drain of the NMOS tube M22, the drain of the NMOS tube M23, the drain of the NMOS tube M24 and the drain of the NMOS tube M25 are respectively connected to the first end of the transmission gate T1, the first end of the transmission gate T2, the first end of the transmission gate T3, the first end of the transmission gate T4 and the first end of the transmission gate T5; The second end of the transmission gate T1, the second end of the transmission gate T2, the second end of the transmission gate T3, the second end of the transmission gate T4, and the second end of the transmission gate T5 are all connected to the first node; The first node is connected to the source of the NMOS tube M26 and the source of the NMOS tube M27; The drain of the NMOS tube M26 and the drain of the NMOS tube M27 lead to the positive output terminal of the programmable current source and the negative output terminal of the programmable current source respectively.

3. The CTLE dynamic offset voltage calibration circuit according to claim 2, characterized in that: The gate of the NMOS tube M26 and the gate of the NMOS tube M27 are controlled by a pair of anti-phase signals; One of the pair of inverted signals belongs to a control bit in the current adjustment control code.

4. The CTLE dynamic offset voltage calibration circuit according to claim 3, characterized in that: The transmission gates T1 , T2 , T3 , T4 and T5 are controlled by a current adjustment control code.

5. The CTLE dynamic offset voltage calibration circuit according to claim 4, characterized in that: For the NMOS transistor M20 , the NMOS transistor M21 , the NMOS transistor M22 , the NMOS transistor M23 , the NMOS transistor M24 , and the NMOS transistor M25 , the ratio of their channel widths is 1:1:2:4:8:

16.

6. The CTLE dynamic offset voltage calibration circuit according to claim 5, characterized in that: The gain-to-current converter comprises the following circuit structure: The source of the PMOS tube M30, the source of the PMOS tube M31, the source of the PMOS tube M32 and the source of the PMOS tube M33 are all connected to VDD; The gate of the PMOS tube M30, the gate of the PMOS tube M31, the gate of the PMOS tube M32 and the gate of the PMOS tube M33 are all connected to the drain of the PMOS tube M30; The drain of the PMOS tube M30 is connected to the first bias current; The drain of the PMOS tube M31, the drain of the PMOS tube M32 and the drain of the PMOS tube M33 are respectively connected to the first end of the transmission gate T6, the first end of the transmission gate T7 and the first end of the transmission gate T8; The second end of the transmission gate T6, the second end of the transmission gate T7 and the second end of the transmission gate T8 are connected together and output a second bias current; The transmission gates T6 , T7 and T8 are controlled by the gain control signal.

7. The CTLE dynamic offset voltage calibration circuit according to claim 6, characterized in that: The first bias current comes from outside the CTLE dynamic offset voltage calibration circuit.

8. The CTLE dynamic offset voltage calibration circuit according to claim 7, characterized in that: The channel width ratios of the PMOS tube M30 , the PMOS tube M31 , the PMOS tube M32 , and the PMOS tube M33 are 1:1:2:

4.

9. The CTLE dynamic offset voltage calibration circuit according to claim 8, characterized in that: When CTLE calibration begins, an enable signal is sent to the analog switch to turn on the analog switch; When the CTLE calibration is finished, the enable signal is turned off to close the analog switch.

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