High-purity sinusoidal signal synthesizer based on digital predistortion

Abstract

The invention discloses a high-purity sinusoidal signal synthesis device based on digital predistortion, which is characterized in that a control word is issued to an FPGA (Field Programmable Gate Array) through an upper computer, and the FPGA analyzes a parameter index in the control word and generates the control word for controlling each circuit module and a corresponding digital sinusoidal signal according to the parameter index; then, the main DAC is used for converting the harmonic component into an analog sinusoidal signal, the amplitude and phase of the harmonic component are analyzed through ADC sampling, a digital harmonic compensation signal is generated according to the amplitude and phase, then the digital harmonic compensation signal is converted into an analog harmonic compensation signal through the calibration DAC, and the analog harmonic compensation signal is added with the analog sinusoidal signal generated by the main DAC after amplitude attenuation; harmonic distortion of an analog sinusoidal signal generated by the main DAC is reduced, and the purity of the analog sinusoidal signal is improved; and finally, sending the summed signal into a signal conditioning channel to adjust the amplitude and direct current bias of the summed signal, so that a high-purity sinusoidal signal meeting the index requirement can be obtained at an output end, and high-purity sinusoidal signal synthesis based on digital pre-distortion is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of signal synthesis, and more specifically, relates to a high-purity sinusoidal signal synthesis device based on digital predistortion. Background Art

[0002] High-purity sinusoidal signals play an important role in many scientific and technological applications. They are characterized by extremely low harmonic distortion and phase noise, which can ensure precise and accurate measurements and are indispensable in fields that require high signal fidelity and accuracy. High-purity sinusoidal signals are widely used in integrated circuit (IC) and electronic component testing, analog-to-digital converters (ADC), electromyography (EMG) signal acquisition, lock-in amplifiers and signal processing. Their integrity and clarity support the reliable performance of many advanced technologies.

[0003] High-purity sinusoidal signal synthesis technology has broad application prospects. In electronic testing, high-purity sinusoidal signals are important tools for testing equipment and system performance by providing a stable signal source for accurate measurement and calibration. In communication systems, high-purity sinusoidal signals are used as reference signals to support high-frequency data modulation and demodulation to ensure the stability of communication links. In radar systems, high-purity sinusoidal signals help improve the accuracy of target detection, allowing the system to better identify and track targets. Overall, the wide application of high-purity sinusoidal signal synthesis technology in various high-precision fields highlights its practical value and huge potential.

[0004] Research and development of high-purity, low-noise sinusoidal signal synthesis technology is essential to improve the precision and accuracy of modern scientific and industrial measurements. This technology has irreplaceable value in application fields with extremely high precision requirements due to its characteristics of reducing measurement errors, improving detection sensitivity and maintaining signal integrity. Therefore, designing a high-purity sinusoidal signal generation technology has important theoretical and practical value. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a high-purity sinusoidal signal synthesis device based on digital pre-distortion, which realizes high-purity, low-noise sinusoidal signal synthesis through a harmonic analysis algorithm, a digital pre-distortion method, a dual digital-to-analog converter (DAC) structure, etc.

[0006] To achieve the above-mentioned object of the invention, the present invention provides a high-purity sinusoidal signal synthesis device based on digital predistortion, characterized in that it includes: a host computer, a digital-to-analog converter, an analog-to-digital converter, an attenuation channel, an addition circuit, a signal conditioning channel and an FPGA;

[0007] Among them, FPGA serves as the main control unit for high-purity sinusoidal signal synthesis, dual DACs serve as the core devices for signal generation to complete the design of digital logic, ADC realizes data acquisition and transmits it back to FPGA, the attenuation channel is used to attenuate the signal amplitude, and then loads it to the adding circuit. The adding circuit adds multiple signals and sends them to the signal conditioning channel. The conditioning channel is used to adjust the signal amplitude and DC bias, so that the output end can produce a high-purity sinusoidal signal that meets the index requirements.

[0008] The object of the invention of the present invention is achieved in this way:

[0009] The invention discloses a high-purity sinusoidal signal synthesis device based on digital pre-distortion. First, a control word is sent to an FPGA through a host computer. The FPGA analyzes parameter indicators in the control word and generates control words for controlling various circuit modules and corresponding digital sinusoidal signals according to the parameter indicators. Then, a main DAC is used to convert the signal into an analog sinusoidal signal, and the amplitude and phase of the harmonic component are analyzed through ADC sampling, and a digital harmonic compensation signal is generated accordingly. Then, the signal is converted into an analog harmonic compensation signal through a calibration DAC, and the signal is added to the analog sinusoidal signal generated by the main DAC after amplitude attenuation, so as to reduce the harmonic distortion of the analog sinusoidal signal generated by the main DAC and improve its purity. Finally, the signal obtained by summing is sent to a signal conditioning channel to adjust its amplitude and direct current bias, so as to obtain a high-purity sinusoidal signal that meets the indicator requirements at the output end, thereby realizing the synthesis of high-purity sinusoidal signals based on digital pre-distortion.

[0010] At the same time, the high-purity sinusoidal signal synthesis device based on digital predistortion of the present invention also has the following

[0011] Beneficial effects:

[0012] (1) The present invention adds a signal conditioning channel at the signal output end, and can adjust the DC bias and amplitude of the synthesized high-purity sinusoidal signal through the conditioning channel to generate a high-purity sinusoidal signal that meets different amplitude, frequency, phase, and DC bias requirements, thereby expanding the scope of application of the present invention.

[0013] (2) The present invention adopts a dual DAC digital pre-distortion method based on spectrum analysis, which effectively solves the problem of reduced compensation effect caused by the generation of undesired intermodulation distortion when performing harmonic compensation in the single DAC digital pre-distortion method.

[0014] (3) The present invention first uses a main DAC to generate an analog sinusoidal signal containing harmonic distortion, and then generates an analog harmonic compensation signal through a calibration DAC to compensate for harmonic components of each order, thereby improving the purity of the synthesized sinusoidal signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1It is a structural diagram of a high-purity sinusoidal signal synthesis device based on digital pre-distortion of the present invention;

[0016] Figure 2 It is the principle block diagram of high-purity sinusoidal signal synthesis. DETAILED DESCRIPTION

[0017] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0018] Example

[0019] Figure 1 It is a structural diagram of a high-purity sinusoidal signal synthesis device based on digital pre-distortion of the present invention.

[0020] In this embodiment, if Figure 1 As shown, the present invention is a high-purity sinusoidal signal synthesis device based on digital predistortion, including: a host computer, a digital-to-analog converter, an analog-to-digital converter, an attenuation channel, an addition circuit, a signal conditioning channel and an FPGA:

[0021] The host computer is used to send control words to the FPGA to indicate the various parameters of the high-purity sinusoidal signal to be synthesized, including amplitude, frequency and phase;

[0022] The digital-to-analog converter is used to convert the digital signal into an analog signal; wherein the main DAC is used to receive the digital sinusoidal signal generated by the FPGA, and convert the digital sinusoidal signal into an analog sinusoidal signal and output it to the adding circuit; the calibration DAC is used to receive the digital harmonic compensation signal generated by the FPGA, and convert the digital harmonic compensation signal into an analog harmonic compensation signal and output it to the attenuation channel;

[0023] The analog-to-digital converter is used to sample the analog sinusoidal signal generated by the main DAC and send the sampled data to the FPGA;

[0024] The attenuation channel is used to receive the attenuation channel control word generated by the FPGA and the analog harmonic compensation signal output by the calibration DAC, and then attenuate the amplitude of the analog harmonic compensation signal according to the attenuation channel control word to prevent the analog harmonic compensation signal from amplitude distortion and reduce its quantization distortion, and then send the analog harmonic compensation signal with amplitude attenuation to the adding circuit;

[0025] The adding circuit adds the analog sinusoidal signal generated by the main DAC and the analog harmonic compensation signal after amplitude attenuation, and then sends the summed sinusoidal signal to the signal conditioning channel;

[0026] The signal conditioning channel is used to receive the conditioning channel control word generated by the FPGA and the sinusoidal signal output by the adding circuit, and then adjust the DC bias and amplitude of the sinusoidal signal according to the conditioning channel control word, and finally output a high-purity sinusoidal signal that meets the control word indicator requirements issued by the host computer;

[0027] FPGA is used to receive the control word instruction sent by the host computer, and parse out the parameter index of the high-purity sinusoidal signal to be synthesized, and then generate the control word and corresponding digital sinusoidal signal for controlling each circuit module according to the parameter index;

[0028] Among them, each control word is distributed to the corresponding circuit module, and each control word specifically includes: a sinusoidal signal control word, a harmonic compensation signal control word, an attenuation channel control word, and a conditioning channel control word;

[0029] First, the digital sinusoidal signal is converted into an analog sinusoidal signal through the main DAC. At this time, the calibration DAC is turned off. Due to the nonlinear characteristics of the DAC, the analog sinusoidal signal generated by the main DAC has various orders of harmonic distortion, and its purity is low, which needs to be further improved.

[0030] Next, the analog sine signal passes through the adding circuit, and the ADC samples the analog sine signal generated by the main DAC, and then transmits the sampled data back to the FPGA; the FPGA uses the harmonic analysis algorithm to perform spectrum analysis on the sampled analog sine signal to obtain the amplitude and phase of each order of harmonics of the analog sine signal generated by the main DAC, and then calculates the digital harmonic compensation signal based on the harmonic compensation algorithm;

[0031] Subsequently, the FPGA determines the amplitude adjustment factor G of the attenuation channel according to the digital harmonic compensation signal and starts to synthesize a high-purity sinusoidal signal. At this time, the calibration ADC is started and the analog harmonic compensation signal is sent. After the amplitude is attenuated, it is sent to the adding circuit and added with the analog sinusoidal signal containing harmonic components generated by the main DAC to generate a high-purity sinusoidal signal. Finally, the high-purity sinusoidal signal is sent to the signal conditioning channel. After adjusting its amplitude and DC bias according to the conditioning channel control word, a high-purity, low-noise sinusoidal signal that meets the parameter requirements is output.

[0032] Below we describe in detail the specific process of the harmonic analysis algorithm to perform spectrum analysis on the simulated sinusoidal signal, specifically:

[0033] Assume that the analog sinusoidal signal generated by the main DAC is x main (t);

[0034] ADC Pair x main The analog sinusoidal signal after sampling is expressed as: x[n]=x(nT s ),in, is the sampling period, f sis the sampling frequency;

[0035] Perform a fast Fourier transform on x[n] and calculate the spectrum: Where k is the frequency index of the spectrum, and N is the number of sampling points of FFT;

[0036] Calculate the amplitude and phase of each frequency component based on the real part Real and imaginary part Imag of X[k];

[0037] The amplitude expressed in unit amplitude is: Among them, because FFT only calculates the positive frequency part, in order to compensate for its symmetry, the amplitude is multiplied by 2;

[0038] The phase is: φ[k] = arg(X[k]) = atan2(Imag(X[k]), Real(X[k]))

[0039] Identify the harmonic components of each order from the spectrum: the fundamental frequency f1 corresponds to Harmonic frequency f n The corresponding indexes are: That is, there are: fundamental wave index k1, second harmonic index k2, third harmonic index k3, and so on; the fundamental wave frequency is The harmonic frequency is

[0040] Extract the amplitude of each harmonic frequency from the spectrum according to the fundamental frequency and Phase

[0041] Finally, the harmonic amplitude C of the analog sinusoidal signal generated by the main DAC can be obtained. k Phase with harmonics

[0042] Below we introduce the amplitude adjustment factor G of the attenuation channel in detail, as follows:

[0043] Since the harmonic amplitude of the analog sinusoidal signal generated by the main DAC is smaller than the fundamental amplitude, if the calibration DAC is used directly to synthesize the analog harmonic compensation signal x calibration (t), because its amplitude is too small, it will be greatly affected by the integral nonlinearity (INL) and differential nonlinearity (DNL) of the DAC itself, resulting in serious amplitude distortion of the analog harmonic compensation signal generated by it.

[0044] Therefore, in order to ensure that the analog harmonic compensation signal output by the calibration DAC itself does not have a large degree of amplitude distortion, it is necessary to ensure that the range of the digital harmonic compensation signal input to the calibration DAC is greater than a certain threshold. For different DAC chips, the threshold is different.

[0045] When the digital harmonic compensation signal is input into the calibration DAC, the analog harmonic compensation signal generated by the calibration DAC does not contain obvious amplitude distortion. The fundamental amplitude of the analog harmonic compensation signal is denoted as A. th The minimum amplitude of each harmonic of the analog sinusoidal signal generated by the main DAC is A min , where A min =A fn , A fn The FFT measures the noise floor amplitude of the DAC output signal. The amplitude adjustment factor G of the attenuation channel must meet the following conditions:

[0046] A min ·G>A th (1)

[0047] In addition, if the amplitude adjustment factor G of the attenuation channel is too large, it will cause the digital harmonic compensation signal x calibration The amplitude of (n) exceeds the maximum range of the DAC. Therefore, the amplitude adjustment factor G of the attenuation channel must also meet the following conditions:

[0048] max{x calibration (n)}·G<1(2)

[0049] max{x calibration (n)} represents the digital harmonic compensation signal x calibration (n) maximum amplitude;

[0050] Combining equations (1) and (2), we can find the value range of G as:

[0051]

[0052] Next we combine Figure 2 , the specific process of high-purity, low-noise sinusoidal signal synthesis is illustrated as follows:

[0053] When the control word from the host computer is delivered, the FPGA will parse the instruction and obtain the amplitude A, frequency ω, and phase φ of the high-purity sinusoidal signal to be synthesized, and then generate a digital sinusoidal signal x sent to the main DAC based on this. main (n):

[0054] x main (n) = A basic sin(ω basic n+φ basic )(1)

[0055] In the formula, A basic ,ω basic ,φ basic are the amplitude, angular frequency and initial phase of the digital sinusoidal signal generated by FPGA, and ω basic =ω、φ basic =φ, where A gain Amplitude adjustment factor for the signal conditioning channel.

[0056] Due to the nonlinear characteristics of DAC, the main DAC receives a single-tone digital sinusoidal signal x main The analog sinusoidal signal generated after the operation has various harmonic distortions, and its output x main (t) is:

[0057]

[0058] In the formula, A basic Represents the amplitude of the fundamental wave of the signal output by the main DAC, ω basic Indicates the frequency of the fundamental wave of the output signal, φ basic Indicates the phase of the fundamental wave of the output signal, Represents the harmonic signals of various orders generated by DAC nonlinearity, where H represents the maximum order of harmonic measurement and compensation, and A k , kω basic ,φ k They represent the amplitude, frequency and phase of the k-th order harmonic signal respectively.

[0059] At this time, the calibration DAC is turned off, and only the main DAC outputs a sinusoidal signal x containing harmonic components. main (t). At the same time, the ADC samples the sinusoidal signal and sends the sampled data to the FPGA, where the harmonic analysis algorithm calculates x samp (n):

[0060]

[0061] Among them, C basic , C k are the amplitude of the fundamental wave and the amplitude of the kth harmonic calculated by the harmonic analysis algorithm respectively. They are respectively the fundamental wave phase and the k-th harmonic phase calculated by the harmonic analysis algorithm.

[0062] After the FPGA obtains the amplitude and phase of the main DAC output fundamental wave and each order harmonic through the harmonic analysis algorithm, it can start to generate the digital harmonic compensation signal x calibration (n), and prepare to send it to the calibration DAC to be converted into an analog harmonic compensation signal output. calibration (n) can be calculated by the following formula:

[0063]

[0064] Among them, C kis the amplitude of the kth harmonic of the main DAC output analog sinusoidal signal solved by the harmonic analysis algorithm, G is the amplitude adjustment factor of the attenuation channel, φ basic is the fundamental phase, is the phase difference between the kth harmonic and the fundamental wave.

[0065] The meanings of each term in the formula are: The purpose of this item is to make the amplitudes of each order of sinusoidal components of the harmonic compensation signal consistent with the amplitudes of each order of harmonics output by the main DAC after passing through the attenuation channel with an amplitude adjustment factor of G. The purpose of this term is to sum the phase of the fundamental wave and the phase difference between the kth harmonic and the fundamental wave to obtain the phase of each order of harmonics. Adding π after the obtained phase is to make the phase of the harmonic compensation signal opposite to the phase of the harmonic of the main DAC output signal at each order of harmonic frequency, so that after the harmonic compensation signal is summed with the sinusoidal signal, the harmonic components of the sinusoidal signal are offset to achieve compensation for the harmonics.

[0066] After solving the harmonic compensation component, it is necessary to use the amplitude adjustment factor value algorithm to calculate the value of the digital sinusoidal signal x. main (n) and harmonic compensation signal x calibration (n) Rationally select the amplitude adjustment factor G of the attenuation channel so that the attenuation channel can reduce the intermodulation distortion between the harmonic compensation signals caused by the calibration DAC nonlinearity to the bottom noise, reduce the impact of the intermodulation distortion on the harmonic compensation effect, and send the amplitude adjustment factor G to the attenuation channel. Then calculate the amplitude adjustment factor A of the signal conditioning channel gain and compare it with the DC bias V dc Sent to the signal conditioning channel together.

[0067] Among them, the amplitude adjustment factor A of the signal conditioning channel gain It can be calculated by the following formula:

[0068]

[0069] At this point, the digital sinusoidal signal x input to the main DAC main (n), the digital harmonic compensation signal x input to the calibration DAC calibration (n), the amplitude adjustment factor G input to the attenuation channel, the amplitude adjustment factor A input to the conditioning channel gain All calculations are completed. At this point, you only need to start the main DAC and the calibration DAC to send analog sine signals and analog harmonic compensation signals respectively, and you can achieve the synthesis of high-purity sine signals.

[0070] Although the above describes the illustrative specific embodiments of the present invention to facilitate the understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

Claims

1. A high-purity sinusoidal signal synthesis device based on digital predistortion, characterized in that: include: Host computer, digital-to-analog converter, analog-to-digital converter, attenuation channel, adding circuit, signal conditioning channel and FPGA; The host computer is used to send control words to the FPGA, indicating various parameters of the high-purity sinusoidal signal to be synthesized, including amplitude, frequency and phase; The digital-to-analog converter is used to convert a digital signal into an analog signal; wherein the main DAC is used to receive a digital sinusoidal signal generated by the FPGA, and convert the digital sinusoidal signal into an analog sinusoidal signal and output it to the adding circuit; the calibration DAC is used to receive a digital harmonic compensation signal generated by the FPGA, and convert the digital harmonic compensation signal into an analog harmonic compensation signal and output it to the attenuation channel; The analog-to-digital converter is used to sample the analog sinusoidal signal generated by the main DAC and send the sampled data to the FPGA; The attenuation channel is used to receive the attenuation channel control word generated by the FPGA and the analog harmonic compensation signal output by the calibration DAC, and then perform amplitude attenuation on the analog harmonic compensation signal according to the attenuation channel control word, and then send the amplitude-attenuated analog harmonic compensation signal to the adding circuit; The adding circuit adds the analog sinusoidal signal generated by the main DAC and the analog harmonic compensation signal after amplitude attenuation, and then sends the summed sinusoidal signal to the signal conditioning channel; The signal conditioning channel is used to receive the conditioning channel control word generated by the FPGA and the sinusoidal signal output by the adding circuit, and then adjust the DC bias and amplitude of the sinusoidal signal according to the conditioning channel control word, and finally output a high-purity sinusoidal signal that meets the control word indicator requirements issued by the host computer; The FPGA is used to receive the control word instruction sent by the host computer, and parse the parameter index of the high-purity sinusoidal signal to be synthesized, and then generate the control word and corresponding digital sinusoidal signal for controlling each circuit module according to the parameter index; Among them, each control word is distributed to the corresponding circuit module, and each control word specifically includes: a sinusoidal signal control word, a harmonic compensation signal control word, an attenuation channel control word, and a conditioning channel control word; The digital sinusoidal signal is converted into an analog sinusoidal signal through the main DAC. At this time, the calibration DAC is turned off. After the analog sinusoidal signal passes through the adding circuit, the ADC samples the analog sinusoidal signal generated by the main DAC, and then transmits the sampled data back to the FPGA. The FPGA uses a harmonic analysis algorithm to perform spectrum analysis on the sampled analog sinusoidal signal to obtain the amplitude and phase of each order of harmonics of the analog sinusoidal signal generated by the main DAC, and then calculates the digital harmonic compensation signal through the harmonic compensation algorithm. Then, the FPGA determines the amplitude adjustment factor G of the attenuation channel according to the digital harmonic compensation signal, and starts to synthesize a high-purity sinusoidal signal. At this time, the calibration ADC is started and starts to send the analog harmonic compensation signal. After the amplitude is attenuated, it is sent to the adding circuit and added with the analog sinusoidal signal containing harmonic components generated by the main DAC to generate a high-purity sinusoidal signal. Finally, the high-purity sinusoidal signal is sent to the signal conditioning channel. After adjusting its amplitude and DC bias according to the conditioning channel control word, a high-purity, low-noise sinusoidal signal that meets the parameter requirements is output.

2. The high-purity sinusoidal signal synthesis device based on digital predistortion according to claim 1, characterized in that: The specific process of the harmonic analysis algorithm performing spectrum analysis on the simulated sinusoidal signal is as follows: (2.1) Let the analog sinusoidal signal generated by the main DAC be x main (t); (2.2), ADC to x main The analog sinusoidal signal after sampling is expressed as: x[n]=x(nT s ),in, is the sampling period, f s is the sampling frequency; (2.3) Perform fast Fourier transform on x[n] and calculate the spectrum: Where k is the frequency index of the spectrum, and N is the number of sampling points of FFT; (2.4) Calculate the amplitude and phase of each frequency component based on the real part Real and imaginary part Imag of X[k]; The amplitude expressed in unit amplitude is: Among them, because FFT only calculates the positive frequency part, in order to compensate for its symmetry, the amplitude is multiplied by 2; The phase is: φ[k] = arg(X[k]) = atan2(Imag(X[k]), Real(X[k])) Identify the harmonic components of each order from the spectrum: the fundamental frequency f1 corresponds to Harmonic frequency f n The corresponding indexes are: That is, there are: fundamental wave index k1, second harmonic index k2, third harmonic index k3, and so on; the fundamental wave frequency is The harmonic frequency is Extract the amplitude of each harmonic frequency from the spectrum according to the fundamental frequency and Phase 3. The high-purity sinusoidal signal synthesis device based on digital predistortion according to claim 1, characterized in that: The amplitude adjustment factor G of the attenuation channel satisfies: Among them, A th It indicates the fundamental amplitude of the analog harmonic compensation signal when the analog harmonic compensation signal output by the calibration DAC does not have amplitude distortion. min The minimum value of each harmonic amplitude of the analog sinusoidal signal generated by the main DAC, max{x calibration (n)} represents the digital harmonic compensation signal x calibration (n) is the maximum amplitude.

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