Memory device and memory management method for compute fast link

Abstract

The invention discloses a memory device and a memory management method for computing a fast link. A compute fast link (CXL) memory device includes: a group of memory cells configured to store data; one or more sensors configured to measure a degradation factor of the memory cell group; and a control component configured to receive a memory allocation request from a host device connected to the CXL memory device using the CXL, and perform memory allocation of the memory cell group for the host device based on a degradation state of the memory cell group according to a degradation factor of the memory cell group.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0075088 filed on June 12, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0002] The following description relates to a memory device and method having a compute express link (CXL). Background Art

[0003] Compute Express Link (CXL) is an open standard interface for high-speed communication and can provide a comprehensive interface environment that connects multiple components, such as central processing units (CPUs), memories, accelerators, and other peripherals. The scalability of CXL can form a pool of components from multiple systems. For example, a memory pool formed by multiple systems can be provided to a host through CXL memory pooling. In addition, multiple hosts can access the same memory address of the system through CXL memory sharing. Through CXL, a computing environment suitable for technologies that require high computing resources, such as artificial intelligence (AI), can be stably and easily configured. Summary of the invention

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0005] In one or more general aspects, a compute fast link (CXL) memory device includes: a memory cell group configured to store data; one or more sensors configured to measure a degradation factor of the memory cell group; and a control component configured to: receive a memory allocation request from a host device connected to the CXL memory device using CXL, and perform memory allocation of the memory cell group for the host device based on a degradation state of the memory cell group according to the degradation factor of the memory cell group.

[0006] To perform the memory allocation, the control component may be configured to: estimate a degradation state of the memory cell group based on a degradation factor of the memory cell group; and determine a memory usage schedule for wear leveling of the memory cell group based on the degradation state of the memory cell group.

[0007] In order to determine the memory use schedule, the control component may be configured to determine the memory use schedule such that degradation parameter values ​​representing degradation states of memory cell groups are evenly distributed.

[0008] The control component may be configured to determine the degradation parameter value based on either or both of bias temperature instability (BTI) and hot carrier injection (HCI) of the group of memory cells.

[0009] The operation of the memory cell group may include a static operation in a saturated state and a switching operation in an unsaturated state, and the control component may be configured to: determine the degradation parameter value using BTI in response to the memory cell group in the saturated state; and determine the degradation parameter value using HCI in response to the memory cell group in the unsaturated state.

[0010] To perform the memory allocation, the control component may be configured to: select a physical memory address from the memory addresses of the memory unit group based on the memory usage schedule; and map the physical memory address to a virtual memory address according to a memory allocation request of the host device to determine address conversion information.

[0011] The control component may be configured to migrate data stored in a memory space in a highly degraded state of the memory cell group based on the memory use schedule to a memory space in a less degraded state of the memory cell group.

[0012] The degradation factor may include any one or any combination of any two or more of an operating voltage, an operating temperature, an operating time, and an operating count of the memory cell group.

[0013] A first memory cell group of the memory cell groups may have different characteristics than a second memory cell group of the memory cell groups, and the characteristics may include any one or both of performance and life expectancy.

[0014] The memory cell group may be divided into a plurality of management groups according to a degradation management unit of any one of a page unit, a bank unit, and a rank unit, and a degradation factor may be collected and a degradation state may be estimated for each of the plurality of management groups.

[0015] A CXL memory system may include a CXL memory device and a host device.

[0016] In one or more general aspects, a host device may include: one or more processors configured to: receive a degradation factor of a memory component of the CXL memory device from a CXL memory device connected to the host device using a compute express link (CXL); estimate a degradation state of the memory component based on the degradation factor of the memory component; determine a memory usage schedule for wear leveling of the memory component based on the degradation state of the memory component; and execute a memory allocation request for the CXL memory device based on the memory usage schedule.

[0017] Regarding the process of determining the memory usage schedule, one or more processors may be configured to: determine the memory usage schedule so that degradation parameter values ​​representing degradation states of memory components are evenly distributed.

[0018] The degradation parameter value may be determined based on any one or both of bias temperature instability (BTI) and hot carrier injection (HCI) of the memory component, the operation of the memory component may include static operation in a saturated state and switching operation in an unsaturated state, and the one or more processors may be configured to: determine the degradation parameter value using BTI in response to the memory component in a saturated state; and determine the degradation parameter value using HCI in response to the memory component in an unsaturated state.

[0019] In one or more general aspects, a compute fast link (CXL) memory cartridge includes: CXL memory devices each including a memory cell group configured to store data and a sub-control component configured to control the memory cell group; one or more sensors configured to measure degradation factors of the CXL memory devices; and a control component configured to: receive a memory allocation request from a host device connected to the CXL memory cartridge using CXL, and perform memory allocation of the CXL memory device for the host device based on a degradation state of the CXL memory device according to the degradation factor of the CXL memory device.

[0020] For performing the memory allocation process, the control component may be configured to: estimate a degradation state of the CXL memory device based on a degradation factor of the CXL memory device; and determine a memory usage schedule for wear leveling of the CXL memory device based on the degradation state of the CXL memory device.

[0021] Regarding the process of determining the memory usage schedule, the control component may be configured to: determine the memory usage schedule such that degradation parameter values ​​representing degradation states of the CXL memory devices are evenly distributed.

[0022] For performing the memory allocation process, the control component may be configured to: select a physical memory address from the memory addresses of the CXL memory device based on the memory usage schedule; and map the physical memory address to the virtual memory address according to the memory allocation request of the host device to determine the address conversion information.

[0023] A CXL memory system may include a CXL memory cartridge and a host device.

[0024] In one or more general aspects, a compute express link (CXL) memory system includes: a host device configured to generate a memory allocation request; CXL memory cartridges each including a CXL memory device configured to store data and a sub-control component configured to control the CXL memory device; and a control component configured to perform memory allocation of the CXL memory cartridge for the host device based on a degradation state of the CXL memory cartridge according to a degradation factor of the CXL memory cartridge.

[0025] The CXL memory devices may each include a memory cell group configured to store data and a sub-control component configured to control the memory cell group.

[0026] For performing the memory allocation process, the control component may be configured to: estimate a degradation state of the CXL memory cartridge based on a degradation factor of the CXL memory cartridge; and determine a memory usage schedule for wear leveling of the CXL memory cartridge based on the degradation state of the CXL memory cartridge.

[0027] Regarding the process of determining the memory usage schedule, the control component may be configured to: determine the memory usage schedule such that degradation parameter values ​​representing the degradation status of the CXL memory cartridge are evenly distributed.

[0028] For performing the memory allocation process, the control component may be configured to: select a physical memory address from the memory addresses of the CXL memory cartridge based on the memory usage schedule; and map the physical memory address to the virtual memory address according to the memory allocation request of the host device to determine the address conversion information.

[0029] In one or more general aspects, a memory management method of a compute express link (CXL) memory device includes: collecting degradation factors of memory components of the CXL memory device; receiving a memory allocation request from a host device connected to the CXL memory device using CXL; and performing memory allocation of the memory components for the host device, wherein at least some portions of the memory allocation request and the memory allocation are performed based on degradation states of the memory components according to the degradation factors of the memory components.

[0030] The process of performing the memory allocation may include: estimating a degradation state of a memory component based on a degradation factor of the memory component; and determining a memory usage schedule for wear leveling of the memory component based on the degradation state of the memory component, wherein the memory allocation is performed based on the memory usage schedule.

[0031] The process of determining the memory usage schedule may include determining the memory usage schedule so that degradation parameter values ​​representing degradation states of memory components are evenly distributed.

[0032] The process of performing the memory allocation may include: selecting a physical memory address from memory addresses of a memory component based on a memory usage schedule; and mapping the physical memory address to a virtual memory address according to a memory allocation request of a host device to determine address translation information.

[0033] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 An example of a schematic structure of a host device and a Compute Express Link (CXL) memory device is shown.

[0035] Figure 2 An example of wear leveling processing taking into account the degradation factor is shown.

[0036] Figure 3 Examples of address management operations and degradation management operations are shown.

[0037] Figure 4 An example of a static interval and a conversion interval of a memory component is shown.

[0038] Figure 5A and Figure 5B An example of components associated with a CXL memory device is shown.

[0039] Fig. 6A , Figure 6B and Figure 6C An example of components associated with a CXL memory cartridge is shown.

[0040] Fig. 7A An example of components associated with a CXL memory system is shown.

[0041] Figure 7B An example of components related to wear leveling of a host device is shown.

[0042] Figure 8 An example of a management unit for task processing and degradation management is shown.

[0043] Fig. 9 An example of a degradation factor-based memory management method by a CXL memory device is shown.

[0044] Fig.10 An example of a degradation factor-based memory management method by a host device is shown.

[0045] Throughout the drawings and detailed description, unless otherwise described or provided, the same figure reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative sizes, proportions, and depictions of the elements in the drawings may be exaggerated for clarity, example, and convenience. DETAILED DESCRIPTION

[0046] A detailed description is provided below to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the method, device and / or system described herein will be clear. For example, the order of operations described herein is merely an example and is not limited to those orders set forth herein, but can be changed as will be clear after understanding the disclosure of the present application, except for operations that must occur in a specific order. In addition, for greater clarity and simplicity, the description of features known before understanding the disclosure of the present application may be omitted.

[0047] Although the terms "first", "second" and "third" or A, B, (a), (b), etc. may be used herein to describe various components, assemblies, regions, layers or parts, these components, components, regions, layers or parts are not limited by these terms. Each of these terms is not used to define, for example, the essence, order or sequence of the corresponding component, component, region, layer or part, but is only used to distinguish the corresponding component, component, region, layer or part from other components, components, regions, layers or parts. Therefore, without departing from the teachings of the examples, the first component, first component, first region, first layer or first part referred to in the examples described herein may also be referred to as the second component, second component, second region, second layer or second part.

[0048] Throughout the specification, when a component or element is described as being "connected to," "coupled to," or "engaged to" another component or element, it may be directly (e.g., in contact with the other component or element) "connected to," "coupled to," or "engaged to" the other component or element, or one or more other components or elements may reasonably exist between them. When a component or element is described as being "directly connected to," "directly coupled to," or "directly engaged to" another component or element, there may not be other elements between them. Similarly, expressions such as "between" and "directly between," and "adjacent to" and "directly adjacent to" may also be interpreted as described above.

[0049] The terms used herein are only used to describe various examples and are not used to limit the disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more. As non-limiting examples, the terms "include", "comprise" and "have" specify the presence of narrated features, quantities, operations, components, elements and / or their combinations, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or their combinations.

[0050] Unless the corresponding description and embodiments require that such a list (e.g., "at least one of A, B, and C") be interpreted as having a conjunctive meaning, the phrases "at least one of A, B, and C," "at least one of A, B, or C," etc. are intended to have a disjunctive meaning, and these phrases "at least one of A, B, and C," "at least one of A, B, or C," etc. also include examples in which there may be one or more of each of A, B, and / or C (e.g., any combination of one or more of each of A, B, and C). The use of the term "may" herein with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or may implement) means that there is at least one example or embodiment where such a feature is included or implemented, and all examples are not limited thereto.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs and in particular in the context of understanding the disclosure of the present application. Unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and in particular in the context of the disclosure of the present application, and should not be interpreted in an idealized or overly formal sense.

[0052] Hereinafter, examples will be described in detail with reference to the accompanying drawings. When describing the examples with reference to the accompanying drawings, the same drawing reference numerals denote the same elements, and repeated descriptions thereof will be omitted.

[0053] Figure 1An example of a schematic structure of a host device (e.g., of a CXL memory system 100) and a compute express link (CXL) memory device is shown. CXL is a connection technology that supports cache coherence of processors, memory extensions, and accelerators. When a processor is connected to an additional component using CXL of one or more embodiments, memory coherence between the processor's memory space and the additional component's memory space is maintained by CXL technology, and performance is improved and software stack complexity is reduced by resource sharing, thereby reducing overall system costs. Users can focus on workloads rather than memory management of accelerators. When accelerators supplement processors in supporting applications such as artificial intelligence (AI) and machine learning, CXL can be used as an open standard interface for high-speed communication. CXL can provide a comprehensive interface environment for connecting multiple components such as a central processing unit (CPU), memory, accelerators, and other peripheral devices. For example, through CXL memory pooling based on the scalability of CXL, a memory pool formed by multiple systems can be provided to the host. In addition, multiple hosts can access the same memory address of the system through CXL memory sharing.

[0054] Reference Figure 1 , the host device 110 may use the CXL interface to access the memory component 122 of the CXL memory device 120 and use the memory component 122. The CXL memory device 120 may include a control component 121 and a memory component 122. The control component 121 may provide connectivity between the host device 110 and the CXL memory device 120 and manage memory usage of the memory component 122. The memory component 122 may store data. CXL technology may be used for connection between the host device 110 and the CXL memory device 120 and / or connection between the control component 121 and the memory component 122. In a non-limiting example, reference is made to Figures 1 to 10 Each of the described control components 121, 521, 541, 631, 641, 642, 651, 720, 771, and 820 may be or may include one or more processors.

[0055] The memory components 122 may collectively represent memory types in various levels. For example, the memory components 122 may correspond to a memory cell group or a memory device. The memory cell group may represent a group including a plurality of memory cells (e.g., a memory chip). The memory device may represent a device including one or more memory modules. Each memory module may include a plurality of memory groups. The memory device may correspond to a device having a larger capacity than the memory cell group. When the memory component 122 corresponds to the memory cell group, the CXL memory device 120 may correspond to the memory device. When the memory component 122 corresponds to the memory device, the CXL memory device 120 may correspond to the memory box. The memory box may correspond to a large-capacity memory device having a larger capacity than the memory device. However, the description of the memory cell group, the memory module, the memory device, and the memory box is merely an example, and the CXL memory device 120 and the memory component 122 may correspond to memories in other levels not described herein.

[0056] The memory cell group and the memory device may be configured with a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetic random access memory (MRAM), a phase change random access memory (PRAM), a self-selection memory using an omni-directional threshold switching (OTS) material, and / or the like. However, the configuration of the memory cell group and the memory device is not limited thereto.

[0057] The control component 121 may include various control devices (such as a controller) and a CXL switch. The CXL switch and the CXL switch 130 herein may be separate devices. The control component 121 may include a control device suitable for the level of the memory component 122. For example, when the memory component 122 corresponds to a memory cell group, the control component 121 may include a memory controller. When the memory component 122 corresponds to a memory device, the control component 121 may include at least one of a server controller (e.g., a baseboard management controller (BMC)) and a CXL switch.

[0058] The host device 110 and the CXL memory device 120 may correspond to devices that are physically separated from each other. The CXL memory device 120 may correspond to a device independent of the host device 110 to provide a memory space to the host device 110. For example, as will be described in the following non-limiting example, the CXL memory device 120 may perform at least some of the degradation management functions including degradation data management and / or degradation scheduling and the address management functions including address conversion and address allocation. Although Figure 1An example is shown in which the host device 110 and the CXL memory device 120 are connected in a one-to-one manner, but a plurality of host devices and a plurality of CXL memory devices may be connected. When a plurality of host devices and a plurality of CXL memory devices are connected, the CXL memory device 120 may provide memory space to the host device 110 and host devices other than the host device 110 through memory pooling and / or memory sharing. In addition, the host device 110 may use memory space of other CXL memory devices and the CXL memory device 120 through memory pooling and / or memory sharing.

[0059] A specific memory component in the memory component 122 may have characteristics that are different from the characteristics of other memory components. The characteristics may include at least one of performance and life expectancy. For example, the memory component 122 may include a first memory component and a second memory component. The first memory component and the second memory component may have different characteristics in terms of performance and / or life expectancy. This difference may be caused by a difference in configuration specifications between the first memory component and the second memory component, or may be caused by a difference in operation between the first memory component and the second memory component. For example, when the first memory component is a model configured to exhibit higher performance than the second memory component, the performance of the first memory component may be higher than the performance of the second memory component, or when the use period of the second memory component is longer than the use period of the first memory component, the life expectancy of the first memory component may be longer than the life expectancy of the second memory component.

[0060] When the degradation of the memory components 122 proceeds in different ways, the performance and life expectancy of the memory components 122 may deteriorate. Wear-leveling may maintain the degradation levels of the memory components 122 at similar levels to improve the overall performance and life expectancy of the memory components 122. The CXL memory device 120 of one or more embodiments may perform wear leveling of the memory components 122 based on the degradation factors 124 to optimize the performance and life expectancy of the memory components 122.

[0061] The control component 121 may collect the degradation factor 124 of the memory component 122, and use the degradation factor 124 to perform wear leveling of the memory component 122. The sensor 123 may be used to collect the degradation factor 124. The sensor 123 may be provided on the memory component 122 to have a specific distribution. The degradation factor 124 may include at least one of an operating voltage, an operating temperature, an operating time, and / or an operation count of the memory component 122. The sensor 123 may include a sensing device configured to measure at least one of an operating voltage, an operating temperature, an operating time, and / or an operation count.

[0062] The degradation factor 124 may provide a reason why the performance of the memory component 122 is degraded and the expected life of the memory component 122 is shortened. For example, the degradation factor 124 may include at least one of an operating voltage, an operating temperature, an operating time, and / or an operation count of the memory component 122. The operation count may represent the number of operating clocks and / or operations. The degradation of the memory component 122 may be accelerated as the operating voltage, operating temperature, operating time, and / or operation count increase.

[0063] The host device 110 may request the CXL memory device 120 to perform memory allocation. The CXL memory device 120 may perform memory allocation for the host device 110. According to an example, the control component 121 may include a CXL switch configured to provide a CXL environment (e.g., a CXL interface) between the host device 110 and the CXL memory device 120. In a non-limiting example, the CXL switch 130 may be provided between the host device 110 and the CXL memory device 120. The CXL switch 130 may be distinguished from the CXL switch of the control component 121. The memory allocation request and the memory allocation may be performed by the CXL switch 130 and / or the CXL switch of the control component 121.

[0064] At least some portions of the memory allocation request of the host device 110 and the memory allocation of the CXL memory device 120 may be performed based on the degradation state of the memory component 122 due to the degradation factor 124. The degradation state may indicate a process of degradation. A degradation parameter value may be determined based on the degradation factor 124, and the degradation state may be estimated based on the degradation parameter value. As part of wear leveling, a memory usage schedule may be determined so that the degradation parameter values ​​of the memory component 122 are evenly distributed. Reference will be made to Figure 4 etc. describe an example of a process of deriving a degradation parameter value.

[0065] According to an example, the CXL memory device 120 (e.g., the control component 121) may estimate the degradation state of the memory component 122 based on the degradation factor 124, and a memory usage schedule for wear leveling of the memory component 122 may be determined based on the degradation state. Memory usage (e.g., memory allocation and data migration) may be performed based on the memory usage schedule. For example, memory allocation according to a memory allocation request of the host device 110 may be performed based on the memory usage schedule. The memory usage schedule may include a usage order regarding which memory space of the memory component 122 is preferentially used when the memory usage is implemented together with a task executed by the host device 110. For example, when scheduling is performed in the order of a first memory space, a second memory space, and a third memory space of the memory component 122 according to the memory usage schedule, the first memory space, the second memory space, and the third memory space may be used according to the operation order of the host device 110.

[0066] According to an example, the CXL memory device 120 (e.g., the control component 121) may provide the degradation factor 124 to the host device 110. The host device 110 may estimate the degradation state of the memory component 122 based on the degradation factor 124, and a memory usage schedule for wear leveling of the memory component 122 may be determined based on the degradation state. Memory usage (e.g., memory allocation and data migration) may be performed based on the memory usage schedule. For example, a memory allocation request for the memory component 122 may be performed based on the memory usage schedule.

[0067] The memory component 122 may be divided into a plurality of management groups according to a degradation management unit of a page unit, a memory cell unit, or a rank unit. The control component 121 may collect a degradation factor 124 of each management group. The degradation management unit may be larger than the task processing unit. The degradation management unit may correspond to a multiple (e.g., 4 times, 8 times, 16 times, etc.) of the task processing unit. For example, a 64-bit task processing unit may be used for a task processing process (e.g., data loading, data processing, data storage, etc.) of a kernel or an operating system of the host device 110, and a page unit (e.g., 512 kilobytes (Kb), 1 megabyte (Mb), or 2MB) may be used for a degradation management process (e.g., collection of degradation factors 124, storage of degradation factors 124, degradation state estimation based on degradation factors 124, memory allocation based on degradation state, data migration based on degradation state, etc.).

[0068] Figure 2 An example of wear leveling processing taking into account the degradation factor is shown. Figure 2 In operation 210, the degradation state of each management group is checked. The memory component may be divided into a plurality of management groups according to degradation management units (eg, page units, etc.). For example, Figure 2 The first management group G1 and the second management group G2 are shown. Figure 2 As shown in , according to the checked degradation states, it can be confirmed that the degradation degree of the first management group G1 is higher than that of the second management group G2.

[0069] In operation 220, memory allocation may be performed based on the degradation state. A degradation parameter value may be determined based on the degradation factor, and the degradation state may be estimated based on the degradation parameter value. Memory allocation may be performed so that the degradation parameter value is evenly distributed. Figure 2 An example of memory allocation is shown, but data migration may be performed instead of memory allocation. For wear leveling, memory allocation may be performed based on the second management group G2 in a lower degradation state than the first management group G1, and data D1 may be stored in the memory space of the second management group G2 according to the memory allocation.

[0070] The degradation balance between the first management group G1 and the second management group G2 can be maintained according to wear leveling. Figure 2 The description of management groups G1 and G2 can be applied to all management groups of memory components of a CXL memory device. A CXL memory device of one or more embodiments can maintain degradation balance of all management groups according to wear leveling of all management groups and can optimize performance and life expectancy of memory components.

[0071] Figure 3 Examples of address management operations and degradation management operations are shown. Figure 3 , address management 301 may include address translation 302 and address allocation 303 , and degradation management 305 may include degradation data management 306 and degradation scheduling 307 .

[0072] The degradation data management 306 may include the following operations: collecting data of degradation factors, estimating degradation states based on the degradation factors, and storing / managing data for the degradation factors and / or degradation states. The degradation scheduling 307 may include the operation of determining a memory usage schedule that enables wear leveling. For example, the degradation scheduling 307 may include the following operations: determining degradation parameter values ​​based on the degradation factors, and determining the memory usage schedule so that the degradation parameter values ​​are evenly distributed.

[0073] Address conversion 302 may include a conversion operation between a virtual memory address used by a host device and a physical memory address of a memory component. According to address conversion 302, a virtual memory address may be converted to a physical memory address, or a physical memory address may be converted to a virtual memory address. Address allocation 303 may include an operation of allocating an address of a memory space according to a memory allocation request of a host device. Address allocation 303 may be performed based on a memory usage schedule for wear leveling.

[0074] As reference Figure 1 As described, the CXL memory device 120 may include a control component 121 and a memory component 122, and the control component 121 may include various control devices such as a controller (e.g., a memory controller or a server controller) and a CXL switch. In addition, a CXL switch 130 may be provided between the host device 110 and the CXL memory device 120. Figure 3 The address management 301 and the degradation management 305 may be performed by the control component 121 and / or the CXL switch 130 .

[0075] For example, both address management 301 and degradation management 305 may be performed by one of control component 121 and CXL switch 130. On the other hand, some parts of address management 301 and degradation management 305 may be performed by control component 121, and other parts may be performed by CXL switch 130. When control component 121 includes a plurality of control components (e.g., a first control component and a second control component), and at least some parts of address management 301 and degradation management 305 are performed by control component 121, some parts of the at least some parts may be performed by one of the plurality of control components (e.g., the first control component), and other parts of the at least some parts may be performed by another (e.g., the second control component).

[0076] Figure 4 An example of a static interval and a transition interval of a memory component is shown. As described above, a degradation parameter value may be determined based on a degradation factor of a memory component (e.g., a management group of memory components), and a degradation state of a memory component (e.g., a management group of memory components) may be estimated based on the degradation parameter value. As part of wear leveling, a memory usage schedule may be determined so that the degradation parameter values ​​of the memory components (e.g., a management group of memory components) are evenly distributed.

[0077] According to an example, the degradation parameter value may be determined based on at least one of bias temperature instability (BTI) and hot carrier injection (HCI) of a memory component (eg, memory elements of a management group). BTI and HCI may indicate stress of a semiconductor device.

[0078] BTI may represent a degradation phenomenon of a semiconductor device due to electrical stress and a high temperature environment. Electrical stress and a high temperature environment may cause a change in the charge movement path inside the semiconductor device, and may change the electrical characteristics of the semiconductor device. BTI may include negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). NBTI may represent a degradation phenomenon of a positive metal oxide semiconductor field effect transistor (pMOSFET), wherein the semiconductor device is turned on when a negative bias is applied to the gate of the semiconductor device, and PBTI may represent a degradation phenomenon of a negative MOSFET (nMOSFET), wherein the semiconductor device is turned on when a positive bias is applied to the gate. In the case of NBTI, holes formed in a PMOS channel may be trapped in a gate oxide to cause an increase in a threshold voltage, and in the case of PBTI, electrons formed in an NMOS channel may be trapped in a gate oxide to cause an increase in a threshold voltage. BTI may shorten the life of a semiconductor device and affect the performance of the semiconductor device.

[0079] HCI may refer to a phenomenon that occurs when carriers move to a high energy state due to electrical stress and a high temperature environment. As the size of semiconductor devices decreases, HCI may occur due to carriers being accelerated by a stronger electric field. Due to the collision of carriers in a high energy state in the charge movement path, HCI may cause defects in semiconductor devices and may change the electrical characteristics of semiconductor devices. Electron-hole pairs (EHPs) generated by the collision of hot carriers accelerated by a strong electric field between the drain and source of a semiconductor device may be trapped in the gate oxide, or hot carriers may be directly trapped in the gate oxide to increase the threshold voltage. HCI may shorten the life of semiconductor devices and affect the performance of semiconductor devices.

[0080] Operations of a memory component (eg, memory elements of the memory component) may include static operations in a saturated state and switching operations in an unsaturated state. Figure 4 The graph may represent the input voltage V of the memory component. in and output voltage V out .exist Figure 4 4 , the static interval 401 may correspond to a static operation of the memory component, and the switching interval 402 may correspond to a switching operation of the memory component.

[0081] According to an example, the degradation parameter value may be determined using BTI in a static interval 401 in which the memory component is in a saturated state, and the degradation parameter value may be determined using HCI in a conversion interval 402 in which the memory component is in an unsaturated state. For example, the degradation parameter using BTI may be represented by the following equation 1, and for example, the degradation parameter using HCI may be represented by the following equation 2.

[0082] Equation 1:

[0083]

[0084] In Equation 1, ~ΔV th may represent a change in the threshold voltage of a memory component according to BTI, V may represent an operating voltage of the memory component, T may represent an operating temperature of the memory component, and t may represent an operating time and / or an operation count of the memory component. V, T, and t may correspond to a degradation factor. The change in the threshold voltage according to BTI may be estimated based on the degradation factor, and the change in the threshold voltage may be used as a degradation parameter value. For example, a memory usage schedule may be determined so that degradation parameter values ​​corresponding to changes in the threshold voltage values ​​of the memory components in the static interval 401 become uniform. For example, a memory usage schedule may be determined so that the memory usage of a memory space having a large change in the threshold voltage is reduced, and the memory usage of a memory space having a small change in the threshold voltage is increased.

[0085] Equation 2:

[0086]

[0087] In equation 2, ~ΔI on V may represent a change in the current of the memory component in the on-state according to the HCI, V may represent an operating voltage of the memory component, T may represent an operating temperature of the memory component, and t may represent an operating time and / or an operation count of the memory component. V, T, and t may correspond to a degradation factor. The change in the current in the on-state according to the HCI may be estimated based on the degradation factor, and the change in the current may be used as a degradation parameter value. For example, the memory usage schedule may be determined so that the degradation parameter values ​​corresponding to the change in the current change value of the memory component in the transition interval 402 become uniform. For example, the memory usage schedule may be determined so that the memory usage of the memory space with a large change in current is reduced, and the memory usage of the memory space with a small change in current is increased.

[0088] Figure 5A and Figure 5B 5 shows an example of components associated with a CXL memory device (eg, of the CXL memory system 500). Figure 5A, a CXL memory device 520 may include a memory cell group 522 configured to store data, a sensor 523 configured to measure a degradation factor of the memory cell group, and a control component 521 configured to receive a memory allocation request from a host device connected to the memory device using CXL, and perform memory allocation of the memory cell group for the host device based on the degradation state of the memory cell group “according to the degradation factor of the memory cell group.” According to an example, the control component 521 may correspond to a memory controller.

[0089] The control component 521 may perform address management and degradation management. Wear leveling of the memory cell group 522 may be achieved through address management and degradation management. CXL may be used for connection between the host device 510 and the CXL memory device 520 and connection between the control component 521 and the memory cell group 522.

[0090] The control component 521 may perform degradation data management and degradation scheduling for degradation management. The control component 521 may collect degradation factors of the memory cell group 522. According to an example, the control component 521 may use a fabric manager to perform degradation management. The fabric manager may be application logic for system configuration and resource allocation. The fabric manager may understand and manage the topology of components connected using CXL. The control component 521 may use a sensor 523 to collect degradation factors. The sensor 523 may generate sensor data of the memory cell group 522. The degradation factor may be determined based on the sensor data. Although Figure 5A An example is shown in which the sensor 523 and the memory cell group 522 are arranged in a one-to-one manner, but the number of the memory cell groups 522 may be different from the number of the sensors 523. For example, one sensor may be provided for a plurality of memory cell groups, or a plurality of sensors may be provided for one memory cell group. The sensor data may be processed to increase the estimation accuracy of the degradation factor for the degradation state of the memory cell group 522.

[0091] The CXL memory device 520 may further include a management memory configured to store degradation factors. The control component 521 may manage the history of the degradation factors using the management memory. The management memory may correspond to a non-volatile memory. In this case, the history of the degradation factors may be stably managed regardless of whether the power of the CXL memory device 520 is maintained. However, the memory type of the management memory is not limited thereto. The history of the degradation factors may help to increase the estimation accuracy of the degradation state. Compared to a typical CXL memory device that estimates the degradation state using a degradation factor at one point in time, the CXL memory device 520 of one or more embodiments may more accurately reflect the actual degradation state of the memory cell group 522 by estimating the degradation state using a history of degradation factors accumulated over a long period of time. By increasing the estimation accuracy of the degradation state, the CXL memory device 520 of one or more embodiments may improve the wear leveling effect.

[0092] The control component 521 may estimate the degradation state based on the degradation factor, and determine the memory usage schedule based on the degradation state. The memory usage schedule may include an allocation schedule and a migration schedule. The control component 521 may determine the memory usage schedule so that the degradation state of the memory cell group 522 (e.g., a management group of the memory cell group 522) is balanced.

[0093] The control component 521 may receive a memory allocation request from the host device 510 and perform memory allocation of the CXL memory device 520 for the host device 510. The control component 521 may perform address conversion and address allocation for address management.

[0094] The CXL memory device 520 and the host device 510 may use different addressing schemes. Physical memory addresses may be assigned to the memory space of the memory unit group 522. The physical memory addresses may correspond to actual addresses. The CXL memory device 520 may use physical memory addresses. The host device 510 may use virtual memory addresses. The memory allocation request of the host device 510 may include a virtual memory address. When there is a memory allocation request of the host device 510, the address translator of the control component 521 may map an appropriate physical memory address to a virtual memory address of the memory allocation request.

[0095] The control component 521 may map a physical memory address to a virtual memory address based on a memory usage schedule for wear leveling. The address converter may sequentially map the physical memory address according to the memory usage schedule in response to a memory allocation request of the host device 510. The address converter may select a physical memory address from the memory address of the memory unit group 522 based on the memory usage schedule, and map the selected physical memory address to a virtual memory address according to the memory allocation request of the host device 510 to determine the address conversion information. The address conversion information between the virtual memory address and the physical memory address may be managed using an address conversion table.

[0096] The control component 521 may perform memory allocation with reference to the address conversion information, and perform deallocation on the allocated physical memory address. The control component 521 may map the physical memory address to the virtual memory address with reference to the memory usage schedule, and perform memory allocation according to the corresponding physical memory address. When it is determined that the same data remaining in the same memory space will cause degradation of the corresponding memory space, the corresponding data stored in the memory space in the high degradation state in the memory cell group 522 may be migrated to the memory space in the low degradation state of the memory cell group 522 based on the memory usage schedule. The control component 521 may determine whether to perform data migration. When specifying the physical memory address of the memory space affected by data migration, the new physical memory address for the data of the corresponding physical memory address may be selected with reference to the memory usage schedule. The data of the existing physical memory address may be migrated to the memory space of the new physical memory address.

[0097] Reference Figure 5B , the CXL memory device 540 may include a control component 541, a memory cell group 542, and a sensor 543. Figure 5A Different, in Figure 5B In the embodiment of the present invention, the CXL switch 530 may be disposed between the host device 510 and the CXL memory device 540. In this case, both the address management and the degradation management may be performed by one of the control component 541 and the CXL switch 530. On the other hand, some parts of the address management and the degradation management may be performed by the control component 541, and other parts may be performed by the CXL switch 530. For example, the control component 541 may perform the degradation management, and the CXL switch 530 may perform the address management. In another example, the control component 541 may perform the degradation data management as a part of the degradation management, and the CXL switch 530 may perform the degradation scheduling and the address management together as another part of the degradation management. In addition, the description of the CXL memory device 520 may be applied to the CXL memory device 540.

[0098] Fig. 6A , Figure 6B and Figure 6C 6 shows an example of components associated with a CXL memory cartridge (eg, of a CXL memory system 600). Fig. 6A The CXL memory cartridge 630 may include CXL memory devices 632, sensors 633, and control components 631, each CXL memory device 632 including a memory cell group configured to store data and a sub-control component configured to control the memory cell group (e.g., Figure 5A Control components 521 or Figure 5B The control component 541 of the embodiment of the present invention is configured to receive a memory allocation request from a host device 610 connected to the CXL memory cartridge 630 using CXL, and to perform memory allocation of the CXL memory device 632 for the host device 610 based on the degradation state of the CXL memory device 632 “according to the degradation factor of the CXL memory device 632”. According to an example, the control component 631 may correspond to a server controller (e.g., a BMC) or a CXL switch. Each of the CXL memory devices 632 may be connected to the CXL memory cartridge 630. Figure 5A The CXL memory device 520 and Figure 5B The CXL memory device 540 corresponds to.

[0099] The control component 631 may perform address management and degradation management. The wear leveling of the CXL memory device 632 may be achieved through address management and degradation management. CXL may be used for connection between the host device 610 and the CXL memory cartridge 630 and between the control component 631 and the CXL memory device 632.

[0100] The control component 631 may collect degradation factors of the CXL memory device 632. According to an example, the control component 631 may use a fabric manager to perform degradation management. The control component 631 may use a sensor 633 to collect the degradation factors. The CXL memory cartridge 630 may further include a management memory configured to store the degradation factors. The control component 631 may use the management memory to manage the history of the degradation factors. The management memory may correspond to a non-volatile memory.

[0101] The control component 631 may estimate the degradation state of the CXL memory device 632 based on the degradation factor of the CXL memory device 632, and determine a memory usage schedule for wear leveling of the CXL memory device 632 based on the degradation state of the CXL memory device 632. The control component 631 may determine the memory usage schedule so that the degradation parameter value representing the degradation state of the CXL memory device 632 is evenly distributed. The control component 631 may select a physical memory address from the memory address of the CXL memory device 632 based on the memory usage schedule, and map the physical memory address to a virtual memory address according to a memory allocation request of the host device 610 to determine address conversion information.

[0102] Reference Figure 6B , the CXL memory cartridge 640 may include a first control component 641, a second control component 642, a CXL memory device 643, and a sensor 644. Fig. 6A The CXL Memory Cartridge 630 is different, Figure 6B The CXL memory cartridge 640 may include a plurality of control components of a first control component 641 and a second control component 642. According to an example, the first control component 641 may correspond to a CXL switch, and the second control component 642 may correspond to a server controller (eg, BMC).

[0103] Both address management and degradation management may be performed by one of the first control component 641 and the second control component 642. On the other hand, some parts of address management and degradation management may be performed by the first control component 641, and other parts may be performed by the second control component 642. For example, degradation management may be performed by the second control component 642, and address management may be performed by the first control component 641. In another example, the second control component 642 may perform degradation data management as part of degradation management, and the first control component 641 may perform degradation scheduling and address management together as another part of degradation management. In addition, Fig. 6A The description of CXL memory cartridge 630 may be applied to CXL memory cartridge 640 .

[0104] Reference Figure 6C , the CXL memory cartridge 650 may include a first control component 651, a CXL memory device 652, and a sensor 653. Fig. 6A and Figure 6B Different, in Figure 6CIn the embodiment of the present invention, the CXL switch 660 may be provided between the host device 610 and the CXL memory cartridge 650. In this case, both the address management and the degradation management may be performed by one of the control component 651 and the CXL switch 660. On the other hand, some parts of the address management and the degradation management may be performed by the control component 651, and other parts may be performed by the CXL switch 660. For example, the degradation management may be performed by the control component 651, and the address management may be performed by the CXL switch 660. In another example, the control component 651 may perform degradation data management as a part of the degradation management, and the CXL switch 660 may perform degradation scheduling and address management together as another part of the degradation management. In addition, the description of the CXL memory cartridge 630 may be applied to the CXL memory cartridge 650.

[0105] Fig. 7A An example of components associated with a CXL memory system is shown. Fig. 7A The CXL memory system 700 may include a host device 710, a plurality of CXL memory cartridges 730, and a control component 720. The host device 710 is configured to generate a memory allocation request. Each CXL memory cartridge 730 includes a CXL memory device configured to store data and a sub-control component (e.g., Fig. 6A Control components 631, Figure 6B The first control component 641 and the second control component 642, or Figure 6C The control component 720 is configured to perform memory allocation of the CXL memory cartridge 730 for the host device 710 based on the degradation state of the CXL memory cartridge 730 “according to the degradation factor of the CXL memory cartridge 730”. The CXL memory devices may each include a memory cell group configured to store data and a sub-control component (e.g., Figure 5A Control components 521 or Figure 5B According to an example, the control component 720 may correspond to a server controller (eg, a BMC) or a CXL switch. Each of the CXL memory boxes 730 may be connected to Fig. 6A CXL Memory Box 630, Figure 6B The CXL Memory Box 640 and Figure 6C The CXL memory box 650 corresponds to.

[0106] The control component 720 may perform address management and degradation management. Wear leveling of the CXL memory cartridge 730 may be achieved through address management and degradation management. CXL may be used for connection between the host device 710 and the control component 720 and connection between the control component 720 and the CXL memory cartridge 730. The control component 720 may collect a degradation factor of the CXL memory cartridge 730. According to an example, the control component 720 may use a fabric manager to perform degradation management. The control component 720 may use a sensor of the CXL memory cartridge 730 to collect the degradation factor. The control component 720 may include a management memory configured to store the degradation factor. The control component 720 may use the management memory to manage a history of the degradation factor. The management memory may correspond to a non-volatile memory.

[0107] The control component 720 may estimate the degradation state of the CXL memory cartridge 730 based on the degradation factor of the CXL memory cartridge 730, and determine a memory usage schedule for wear leveling of the CXL memory cartridge 730 based on the degradation state of the CXL memory cartridge 730. The control component 720 may determine the memory usage schedule so that the degradation parameter values ​​representing the degradation state of the CXL memory cartridge 730 are evenly distributed. The control component 720 may select a physical memory address from the memory addresses of the CXL memory cartridge 730 based on the memory usage schedule, and map the physical memory address to a virtual memory address according to a memory allocation request of a host device to determine address conversion information.

[0108] Figure 7B An example of components related to wear leveling of a host device is shown. Figure 7B , the host device 750 may use the CXL interface to access the memory component 772 of the CXL memory device 770 and use the memory component 772. The CXL memory device 770 may include a control component 771 and a memory component 772. The control component 771 may provide connectivity between the host device 750 and the CXL memory device 770 and manage memory usage of the memory component 772. The memory component 772 may store data. The CXL technology may be used for connection between the host device 750 and the CXL memory device 770 and / or connection between the control component 771 and the memory component 772.

[0109] The host device 750 may include a processor 751. The host device 750 may execute a kernel or an operating system using the processor 751. The processor 751 may execute at least some parts of address management and degradation management for memory use performed together with the kernel or the operating system. The processor 751 may receive a degradation factor of a memory component 772 of a CXL memory device 770 from a CXL memory device 770 connected to the host device 750 using CXL, estimate a degradation state of the memory component 772 based on the degradation factor of the memory component 772, determine a memory usage schedule for wear leveling of the memory component 772 based on the degradation state of the memory component 772, and execute a memory allocation request for the CXL memory device 770 based on the memory usage schedule.

[0110] The control component 771 may provide the degradation factor to the host device 750 (e.g., the processor 751, the kernel, or the operating system). The host device 750 may estimate the degradation state of the memory component 772 based on the degradation factor, and determine a memory usage schedule for wear leveling of the memory component 772 based on the degradation state. Memory usage (e.g., memory allocation or data migration) may be performed based on the memory usage schedule.

[0111] In a non-limiting example, CXL switch 760 may be disposed between host device 750 and CXL memory device 770. Address management and degradation management may be performed by processor 751, CXL switch 760, and control component 771. Wear leveling of memory component 772 may be achieved through address management and degradation management.

[0112] According to an example, the control component 771 may perform degradation data management of degradation management. The control component 771 may collect the degradation factor of the memory component 772. The control component 771 may use the sensor 773 to collect the degradation factor. The degradation factor may be determined based on the sensor data of the sensor 773. The CXL memory device 770 may further include a management memory, and the control component 771 may use the management memory to manage data of the degradation factor. The control component 771 may provide the degradation factor corresponding to the degradation information to the host device 750.

[0113] The processor 751 may perform degradation scheduling based on the degradation factor. The processor 751 may estimate the degradation state of the memory component 772 based on the degradation factor, and determine a memory usage schedule for wear leveling of the memory component 772 based on the degradation state. The memory usage schedule may include an allocation schedule and a migration schedule. The processor 751 may determine the memory usage schedule so that the degradation state of the memory component 772 (e.g., a management group of the memory component 772) is balanced. The processor 751 may generate a memory allocation request and / or a data migration request based on the memory usage schedule, and the memory allocation and / or data migration may be performed through the CXL switch 760 or the control component 771.

[0114] According to an example, a degradation query application program interface (API) may be provided to the host device 750. The processor 751 may request degradation information from the control component 771 using the degradation query API. The control component 771 may provide the degradation information to the host device 750 using the degradation query API.

[0115] Figure 8 An example of a management unit for task processing and degradation management is shown. As described above, a memory device may be divided into management groups according to degradation management units such as page units, memory bank units, or row units, and memory management based on degradation factors may be performed for each management group. Figure 8 , each of the plurality of management groups 811 may be distributed over a plurality of memory regions (e.g., memory cell groups) of the memory module 810. For example, each memory region may use a K1-bit bandwidth, and each memory module 810 may use a K2-bit bandwidth. Figure 8 In the example of , K2=K1×8 may be satisfied. For example, K1=8 and K2=64 may be satisfied. 64 bits may correspond to a task processing unit. For example, when the management group 811 uses a degradation management unit of a 512Kb page unit, the management group 811 may be formed across eight memory areas of the memory module 810. However, the numerical values ​​mentioned here are examples, and various other numerical values ​​may be used.

[0116] As described above, degradation management and wear leveling may be performed based on the management group 811 formed across a plurality of memory modules 810. Figure 8 , the control component 820 of the CXL memory device may collect the degradation factor of each of the plurality of management groups 811. The control component 820 of the CXL memory device or the host device 830 may estimate the degradation state of each of the plurality of management groups 811 based on the degradation factor. The control component 820 or the host device 830 may generate a memory usage schedule for wear leveling based on the degradation state of each of the plurality of management groups 811.

[0117] Fig. 9An example of a degradation factor-based memory management method by a CXL memory device is shown. Fig. 9 Operations 910 to 930 of the embodiment of the present invention may be performed in the order and manner shown. However, without departing from the spirit and scope of the illustrated example, the order of one or more operations may be changed and / or one or more operations may be performed in parallel or simultaneously.

[0118] Reference Fig. 9 , the CXL memory device may collect degradation factors of memory components of the CXL memory device in operation 910, receive a memory allocation request from a host device connected to the memory device using CXL in operation 920, and perform memory allocation of the memory device for the host device in operation 930. At least some parts of the memory allocation request and the memory allocation may be performed based on the degradation state of the memory device “according to the degradation factor of the memory device”.

[0119] The CXL memory device may estimate a degradation state of the memory device based on a degradation factor of the memory device, and determine a memory usage schedule for wear leveling of the memory device based on the degradation state of the memory device. Memory allocation may be performed based on the memory usage schedule.

[0120] When a memory usage schedule is determined (e.g., a memory usage schedule for wear leveling of a memory device is determined based on a degradation state of the memory device), the CXL memory device may determine the memory usage schedule so that a degradation parameter value representing the degradation state of the memory device is evenly distributed. The degradation parameter value may be determined based on at least one of a BTI and an HCI of the memory device. The operation of the memory device may include a static operation in a saturated state and a switching operation in an unsaturated state. When the memory device is in a saturated state, the degradation parameter value may be determined using the BTI, and when the memory device is in an unsaturated state, the degradation parameter value may be determined using the HCI.

[0121] When performing memory allocation in operation 930, the CXL memory device may select a device memory address (eg, a physical memory address) from memory addresses of the memory device based on the memory usage schedule and map the device memory address to a virtual memory address according to a memory allocation request of the host device to determine address conversion information.

[0122] The CXL memory device may migrate data stored in a memory space of the memory device in a highly degraded state to a memory space of the memory device in a less degraded state based on a memory usage schedule.

[0123] The CXL memory device may provide a degradation factor of the memory device to the host device. A memory allocation request may be performed based on a degradation state of the memory device estimated by the host device according to the degradation factor of the memory device.

[0124] The degradation factor may include at least one of an operating voltage, an operating temperature, an operating time, and an operation count of the memory device.

[0125] A first memory device in the memory devices may have different characteristics than a second memory device in the memory devices. The characteristics may include at least one of performance and life expectancy.

[0126] The memory device may be divided into a plurality of management groups according to a degradation management unit of a page unit, a bank unit, or a rank unit. Collection of a degradation factor and estimation of a degradation state may be performed for each of the plurality of management groups.

[0127] In addition, refer to Figures 1 to 8 and Fig.10 The description provided can be applied to Fig. 9 Memory management method.

[0128] Fig.10 An example of a degradation factor-based memory management method by a host device is shown. Fig.10 Operations 1010 to 1040 of the embodiment may be performed in the order and manner shown. However, without departing from the spirit and scope of the illustrated example, the order of one or more operations may be changed and / or one or more operations may be performed in parallel or simultaneously.

[0129] Reference Fig.10 The host device may receive a degradation factor of a memory device of the CXL memory device from a CXL memory device connected to the host device through CXL in operation 1010, estimate a degradation state of the memory device based on the degradation factor of the memory device in operation 1020, determine a memory usage schedule for wear leveling of the memory device based on the degradation state of the memory device in operation 1030, and execute a memory allocation request for the CXL memory device based on the memory usage schedule in operation 1040.

[0130] When the memory use schedule is determined in operation 1030 , the host device may determine the memory use schedule so that degradation parameter values ​​representing degradation states of the memory devices are evenly distributed.

[0131] The degradation parameter value may be determined based on at least one of the BTI and the HCI of the memory device. The operation of the memory device may include a static operation in a saturated state and a conversion operation in an unsaturated state. When the memory device is in a saturated state, the degradation parameter value may be determined using the BTI, and when the memory device is in an unsaturated state, the degradation parameter value may be determined using the HCI.

[0132] In addition, refer to Figures 1 to 9 The description provided can be applied to Fig.10 Memory management method.

[0133] Here about Figures 1 to 10Disclosed and described host device, CXL memory device, control component, memory component, sensor, CXL switch, memory cell group, CXL memory box, first control component, second control component, CXL memory system, processor, memory module, management group, host device 110, CXL memory device 120, control component 121, memory component 122, sensor 123, CXL switch 130, host device 510, CXL memory device 520, control component 521, memory cell group 522, sensor 523, CXL switch 530, CXL memory device 540, control component 541, memory cell group 542, sensor 543, host device 610, CXL memory box 630, control component 631, CXL memory device 632, sensor 633, CXL memory cartridge 640, first control component 641, second control component 642, CXL memory device 643, sensor 644, CXL memory cartridge 650, first control component 651, CXL memory device 652, sensor 653, CXL switch 660, CXL memory device 700, host device 710, control component 720, CXL memory cartridge 730, host device 750, processor 751, CXL switch 760, CXL memory device 770, control component 771, memory component 772, sensor 773, host device 830, control component 820, memory module 810, management group 811, and other devices, devices, units, modules, and components are implemented by or represent hardware components. As described above, or in addition to the above description, examples of hardware components that can be used to perform the operations described in this application include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more hardware components in the hardware components that perform the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer can be implemented by one or more processing elements (such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond in a limited manner and execute instructions to achieve the desired result). In one example, a processor or computer includes or is connected to one or more memories storing instructions or software executed by a processor or computer. The hardware components implemented by a processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) for performing the operations described in this application.Hardware components can also access, manipulate, process, create and store data in response to the execution of instructions or software. For simplicity, the singular term "processor" or "computer" can be used for the description of the examples described in this application, but in other examples, multiple processors or computers can be used, or processors or computers can include multiple processing elements or multiple types of processing elements or both. For example, a single hardware component or two or more hardware components can be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller can implement a single hardware component or two or more hardware components. As described above, or in addition to the above description, the example hardware component can have any one or more of different processing configurations, and the examples of different processing configurations include a single processor, an independent processor, a parallel processor, a single instruction single data (SISD) multiprocessing, a single instruction multiple data (SIMD) multiprocessing, a multiple instruction single data (MISD) multiprocessing, and a multiple instruction multiple data (MIMD) multiprocessing.

[0134] Figures 1 to 10 The method for performing the operations described in the present application shown in the embodiment is performed by computing hardware (e.g., by one or more processors or computers), and the computing hardware is implemented as an execution instruction or software as described above to perform the operations performed by the method described in the present application. For example, a single operation or two or more operations may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or another processor and another controller. One or more processors or a processor and a controller may perform a single operation or two or more operations.

[0135] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform methods as described above may be written as computer programs, code segments, instructions, or any combination thereof, for individually or collectively instructing or configuring one or more processors or computers to operate as machines or special-purpose computers to perform operations performed by hardware components and methods as described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) directly executed by one or more processors or computers. In another example, the instructions or software include higher-level code executed by one or more processors or computers using a parser. Instructions or software may be written in any programming language based on the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions herein, and the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions herein disclose algorithms for performing operations performed by hardware components and methods as described above.

[0136] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, as well as any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media, rather than the signal itself. As described above, or in addition to the above description, examples of non-transitory computer-readable storage media include any one or more of the following: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disk storage device, hard disk drive (HDD), solid state drive (SSD), flash memory, card-type memory (such as, multimedia card or micro card (for example, secure digital (SD) or extreme digital (XD))), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk, and any other device, any other device is configured to store instructions or software and any associated data, data files and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files and data structures to one or more processors or computers so that one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files and data structures are distributed on a networked computer system so that the instructions and software and any associated data, data files and data structures are stored, accessed and executed in a distributed manner by one or more processors or computers.

[0137] Although the present disclosure includes specific examples, it will be clear after understanding the disclosure of the present application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be descriptive only and not for limiting purposes. The description of the features or aspects in each example is considered to be applicable to similar features or similar aspects in other examples. If the described techniques are performed in a different order and / or if the components in the described systems, architectures, devices, or circuits are combined in different ways and / or replaced or supplemented by other components or their equivalents, suitable results may be achieved.

[0138] Therefore, the scope of the disclosure includes the claims and their equivalents in addition to the disclosure above and all the accompanying drawings, that is, all changes within the scope of the claims and their equivalents should be construed as being included in the disclosure.

Claims

1. A Compute Express Link (CXL) memory device, include: a memory cell group configured to store data; one or more sensors configured to measure a degradation factor of a memory cell group; as well as The control component is configured as follows: receiving a memory allocation request from a host device connected to the CXL memory device using the CXL; and Based on the degradation states of the memory cell groups according to the degradation factors of the memory cell groups, memory allocation of the memory cell groups is performed for the host device.

2. The CXL memory device according to claim 1, in, For executing the memory allocation process, the control component is configured to: estimating a degradation state of the memory cell group based on a degradation factor of the memory cell group; and A memory usage schedule for wear leveling of the memory cell groups is determined based on the degradation states of the memory cell groups.

3. The CXL memory device according to claim 2, in, For the process of determining the memory usage schedule, the control component is configured to: determine the memory usage schedule so that the degradation parameter values ​​representing the degradation states of the memory cell groups are evenly distributed.

4. The CXL memory device according to claim 3, in, The control component is configured to determine the degradation parameter value based on any one or both of bias temperature instability (BTI) and hot carrier injection (HCI) of the memory cell group.

5. The CXL memory device according to claim 4, in, The operation of the memory cell group includes a static operation in a saturated state and a switching operation in an unsaturated state, and Among them, the control component is configured as: In response to the memory cell group being in a saturated state, determining a degradation parameter value using the BTI; and In response to the group of memory cells being in an unsaturated state, a degradation parameter value is determined using the HCI.

6. The CXL memory device according to claim 2, in, For executing the memory allocation process, the control component is configured to: selecting a physical memory address from memory addresses of a memory cell group based on the memory usage schedule; and A physical memory address is mapped to a virtual memory address according to a memory allocation request of a host device to determine address translation information.

7. The CXL memory device according to claim 2, in, The control component is configured to migrate data stored in a memory space of a memory cell group in a highly degraded state to a memory space of a memory cell group in a less degraded state based on the memory use schedule.

8. A CXL memory device according to any one of claims 1 to 7, in, The degradation factor includes any one or any combination of any two or more of an operating voltage, an operating temperature, an operating time, and an operation count of the memory cell group.

9. A CXL memory device according to any one of claims 1 to 7, in, A first memory cell group in the memory cell groups has different characteristics than a second memory cell group in the memory cell groups, and Among them, characteristics include either or both of performance and life expectancy.

10. A CXL memory device according to any one of claims 1 to 7, in, The memory cell group is divided into a plurality of management groups according to a degradation management unit of any one of a page unit, a bank unit, and a rank unit, and Therein, for each of the plurality of management groups, degradation factors are collected and degradation states are estimated.

11. A CXL memory system comprising the CXL memory device according to any one of claims 1 to 10 and a host device.

12. A host device, include: One or more processors configured to: receiving, from a CXL memory device connected to the host device using a compute fast link CXL, a degradation factor of a memory component of the CXL memory device; estimating a degradation state of the memory component based on a degradation factor of the memory component; determining a memory usage schedule for wear leveling of the memory component based on a degradation state of the memory component; and Based on the memory usage schedule, a memory allocation request is executed for the CXL memory device.

13. The host device according to claim 12, in, Regarding the process of determining the memory usage schedule, the one or more processors are configured to: determine the memory usage schedule so that degradation parameter values ​​representing degradation states of memory components are evenly distributed.

14. The host device according to claim 13, in, The degradation parameter value is determined based on any one or both of bias temperature instability BTI and hot carrier injection HCI of the memory component, wherein the operation of the memory component includes a static operation in a saturated state and a switching operation in an unsaturated state, and Wherein, the one or more processors are configured to: In response to the memory component being in a saturated state, determining a degradation parameter value using the BTI; and In response to the memory component being in an unsaturated state, a degradation parameter value is determined using the HCI.

15. A Compute Express Link CXL memory box, include: a plurality of CXL memory devices, each comprising a memory cell group configured to store data and a sub-control component configured to control the memory cell group; one or more sensors configured to measure degradation factors of the plurality of CXL memory devices; as well as The control component is configured as follows: receiving a memory allocation request from a host device connected to the CXL memory cartridge using CXL; and Memory allocation of the plurality of CXL memory devices is performed for a host device based on degradation states of the plurality of CXL memory devices according to degradation factors of the plurality of CXL memory devices.

16. The CXL memory cartridge of claim 15, in, For executing the memory allocation process, the control component is configured to: estimating degradation states of the plurality of CXL memory devices based on degradation factors of the plurality of CXL memory devices; and A memory usage schedule for wear leveling of the plurality of CXL memory devices is determined based on degradation states of the plurality of CXL memory devices.

17. The CXL memory cartridge of claim 16, in, For the process of determining the memory usage schedule, the control component is configured to: determine the memory usage schedule so that degradation parameter values ​​representing degradation states of the plurality of CXL memory devices are evenly distributed.

18. The CXL memory cartridge of claim 16, in, For executing the memory allocation process, the control component is configured to: selecting a physical memory address from memory addresses of the plurality of CXL memory devices based on the memory usage schedule; and A physical memory address is mapped to a virtual memory address according to a memory allocation request of a host device to determine address translation information.

19. A CXL memory system comprising a CXL memory cartridge according to any one of claims 15 to 18 and a host device.

20. A computational fast link CXL memory system, include: a host device configured to generate a memory allocation request; a plurality of CXL memory cartridges, each comprising a plurality of CXL memory devices configured to store data and a sub-control assembly configured to control the plurality of CXL memory devices; as well as A control component is configured to perform memory allocation of the plurality of CXL memory cartridges to a host device based on degradation states of the plurality of CXL memory cartridges according to degradation factors of the plurality of CXL memory cartridges.

21. The CXL memory system of claim 20, in, The plurality of CXL memory devices each include a memory cell group configured to store data and a sub-control component configured to control the memory cell group.

22. The CXL memory system of claim 20, in, For executing the memory allocation process, the control component is configured to: estimating degradation states of the plurality of CXL memory cartridges based on degradation factors of the plurality of CXL memory cartridges; and A memory usage schedule for wear leveling of the plurality of CXL memory cartridges is determined based on the degradation states of the plurality of CXL memory cartridges.

23. The CXL memory system of claim 22, in, For the process of determining the memory usage schedule, the control component is configured to: determine the memory usage schedule so that degradation parameter values ​​representing degradation states of the plurality of CXL memory cartridges are evenly distributed.

24. The CXL memory system of claim 22, in, For executing the memory allocation process, the control component is configured to: selecting a physical memory address from memory addresses of the plurality of CXL memory cartridges based on the memory usage schedule; and A physical memory address is mapped to a virtual memory address according to a memory allocation request of a host device to determine address translation information.

25. A memory management method for a computing fast link CXL memory device, the memory management method include: collecting degradation factors of memory components of the CXL memory device; receiving a memory allocation request from a host device connected to the CXL memory device using the CXL; as well as performing memory allocation of the memory component for the host device, Wherein, at least some portions of the memory allocation request and the memory allocation are performed based on a degradation state of the memory component according to a degradation factor of the memory component.

26. The memory management method according to claim 25, in, The process of performing the memory allocation includes: estimating a degradation state of the memory component based on a degradation factor of the memory component; and determining a memory usage schedule for wear leveling of the memory component based on a degradation state of the memory component, Wherein, the memory allocation is performed based on the memory usage schedule.

27. The memory management method according to claim 26, in, The process of determining the memory usage schedule includes determining the memory usage schedule so that degradation parameter values ​​representing degradation states of memory components are evenly distributed.

28. The memory management method according to claim 26, in, The process of performing the memory allocation includes: selecting a physical memory address from memory addresses of a memory component based on the memory usage schedule; and A physical memory address is mapped to a virtual memory address according to a memory allocation request of a host device to determine address translation information.

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