Instruction execution module, chip, equipment and method applied to processor

Abstract

The invention discloses an instruction execution module applied to a processor, a chip, equipment and a method, and belongs to the technical field of chips. The instruction execution module comprises a dispatching queue and an assembly line; the dispatching queue is used for storing at least one to-be-executed memory access instruction; selecting n memory access instructions from the at least one memory access instruction to be executed, wherein n is a positive integer greater than 1; the n memory access instructions are fused to obtain a first combined instruction, and the effect of the first combined instruction is equivalent to that of the n memory access instructions; and the pipeline is used for executing the first merging instruction. The memory access instructions stored in the dispatching queue are combined to obtain the combined instruction, the number of the memory access instructions included in a single instruction can be increased, the execution efficiency of the instruction execution module on the memory access instructions can be improved under the condition that the transmission bandwidth of the memory access instructions is limited, and then the performance of the instruction execution module is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an instruction execution module, chip, device and method applied to a processor. Background Art

[0002] Memory access instructions are used to write or retrieve instruction data in the memory. A large number of memory access instructions will appear during the processor's program execution process. The processor's processing speed for memory access instructions directly affects the processor's performance.

[0003] In the related art, for a microinstruction bandwidth, the pipeline can obtain a memory access instruction through the microinstruction bandwidth in one clock cycle. Specifically, the dispatch queue dispatches the memory access instruction to the emission queue, and the emission queue emits the memory access instruction to the pipeline. The pipeline receives and executes one memory access instruction in one clock cycle.

[0004] However, in the related technology, due to the limitation of the expansion of microinstruction bandwidth, it is difficult to improve the execution efficiency of the pipeline for memory access instructions. Summary of the invention

[0005] The present application provides an instruction execution module, chip, device and method for a processor. The technical solution is as follows:

[0006] According to one aspect of an embodiment of the present application, there is provided an instruction execution module applied to a processor, the instruction execution module comprising: a dispatch queue and a pipeline;

[0007] The dispatch queue is used to store at least one memory access instruction to be executed; n memory access instructions are selected from the at least one memory access instruction to be executed, where n is an integer greater than 1; the n memory access instructions are merged into one instruction to obtain a first merged instruction, wherein the effect of the first merged instruction is equivalent to the effect of the n memory access instructions;

[0008] The pipeline is used to execute the first merge instruction.

[0009] According to one aspect of an embodiment of the present application, a chip is provided, the chip comprising a processor and the instruction execution module as described above.

[0010] According to one aspect of an embodiment of the present application, an electronic device is provided. The electronic device includes a chip, and the chip includes the instruction execution module as described above.

[0011] According to one aspect of an embodiment of the present application, there is provided an instruction execution method applied to an instruction execution module, wherein the instruction execution module comprises: an allocation queue and a pipeline, and the method comprises:

[0012] The dispatch queue stores at least one memory access instruction to be executed;

[0013] The dispatch queue selects n memory access instructions from the at least one memory access instruction to be executed, where n is an integer greater than 1;

[0014] The dispatch queue merges the n memory access instructions into one instruction to obtain a first merged instruction, wherein the effect of the first merged instruction is equivalent to the effect of the n memory access instructions;

[0015] The pipeline executes the first merge instruction.

[0016] The instruction execution module provided by the embodiment of the present application can achieve the following beneficial effects: by adding new execution logic in the dispatch queue, the effect of merging multiple memory access instructions stored in the dispatch queue into a merged instruction is achieved. The merged instruction is executed by the pipeline to achieve the same effect as executing the above-mentioned multiple memory access instructions. Relying on the relatively wide range of instruction merging provided in the dispatch queue, it is helpful to merge a large number of memory access instructions into one merged instruction, and only one merged instruction is transmitted to achieve the effect of transmitting the above-mentioned large number of memory access instructions, so that the pipeline obtains multiple memory access instructions in one clock cycle, which helps to realize the execution of multiple memory access instructions by the pipeline in one clock cycle, and improves the execution efficiency of the instruction execution module for memory access instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the architecture of an instruction execution module provided by a related technology;

[0018] Figure 2 is a schematic diagram of a binary disassembly file provided by an exemplary embodiment of the present application;

[0019] Figure 3 It is a schematic diagram of an inventive concept provided by an exemplary embodiment of the present application;

[0020] Figure 4 is a schematic diagram of an instruction execution module applied to a processor provided by an exemplary embodiment of the present application;

[0021] Figure 5 is a schematic diagram of a binary disassembly file provided by another exemplary embodiment of the present application;

[0022] Figure 6 is a schematic diagram of an instruction merging process provided by an exemplary embodiment of the present application;

[0023] Figure 7 is a schematic diagram of an instruction re-issuing process provided by an exemplary embodiment of the present application;

[0024] Figure 8is a schematic diagram of an instruction re-issuing process provided by another exemplary embodiment of the present application;

[0025] Fig. 9 is a schematic diagram of an instruction execution method applied to an instruction execution module provided by an exemplary embodiment of the present application;

[0026] Fig.10 It is a schematic diagram of an instruction execution method applied to an instruction execution module provided by another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0028] First, the terms involved in the embodiments of the present application are explained.

[0029] Memory access instructions are instructions used to store or access data. Memory access instructions can also be called load / store instructions. Memory access instructions include register identifiers and memory access addresses, where the register identifier is used to represent the register used in the process of executing the memory access instruction, and the memory access address is used to indicate the storage address of the operation data of the memory access instruction in the storage space.

[0030] Artificial Intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that machines have the functions of perception, reasoning and decision-making.

[0031] Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level and software-level technologies. Basic artificial intelligence technologies generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-trained model technology, operation / interaction systems, mechatronics, etc. Among them, pre-trained models are also called large models and basic models. After fine-tuning, they can be widely used in downstream tasks in various major directions of artificial intelligence. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0032] Artificial intelligence technology often involves a large amount of calculations. The instruction execution module provided in this application can be used to perform operations involved in artificial intelligence technology and promote the development and progress of artificial intelligence technology.

[0033] Figure 1 The present invention is a schematic diagram of the architecture of an instruction execution module provided by a related technology.

[0034] like Figure 1 As shown in the figure, the instruction execution module mainly includes decoder, map and rename, DQ (Dispatch Queue), scheduler and pipeline (including Figure 1 In the schematic diagram of the architecture, there are multiple types of DQs, and different types of DQs are used to store different types of instructions. For example, the Load / Store instruction enters the LSDQ (Load Store Dispatch Queue) 100. The DQ includes at least one entry, and each entry is used to store an instruction. Figure 1 As shown, LSDQ 100 has 10 entries, that is, LSDQ 100 can list and store at most 10 memory access instructions.

[0035] exist Figure 1 In the architecture provided, the instruction fetch and decoding process is performed by the decoder and other units to generate instructions. The generated instructions are converted from logical registers to physical registers through Map and Rename; then, the instructions are transmitted to the corresponding DQ according to the type of instruction, and the instructions are distributed to the corresponding scheduler through the DQ, and the scheduler sends the instructions to the corresponding pipeline for execution.

[0036] Optionally, Figure 1 The decoder can decode 6 microinstructions in one clock cycle, that is, the decoder is a 6-way decoder. An instruction fusion module is set next to the decoder. The instruction fusion module is used to merge the instructions decoded by the decoder in one clock cycle.

[0037] Since the decoder decodes 6 instructions in one clock cycle, the instruction fusion module can fuse up to 6 instructions. Moreover, due to the limitation of instruction types, the instruction fusion module can actually only merge two adjacent instructions. For example, the lui instruction (used to set the high 16-bit value of the constant in the register) and the load instruction. It can be seen that the architecture of the instruction execution module needs to be improved to improve the effect of the instruction merging process, thereby improving the execution efficiency of the pipeline for instructions.

[0038] Figure 2 FIG. 1 is a schematic diagram of a binary disassembly file provided by an exemplary embodiment of the present application. Figure 2 As shown, during the operation of the processor, a large number of memory access instructions 210 with continuous execution sequence need to be processed. Limited by the microinstruction bandwidth, the number of memory access instructions obtained by the pipeline in one clock cycle is limited, which affects the performance utilization of the pipeline. If the continuous memory access instructions are compressed and packaged into a merged instruction, the pressure of transmitting memory access instructions to the pipeline can be reduced, and the execution efficiency of the pipeline for memory access instructions can be improved.

[0039] Figure 3 It is a schematic diagram of the inventive concept of this application.

[0040] In the instruction execution module provided in the embodiment of the present application, a new execution logic is added to the dispatch queue, and the newly added execution logic is used to merge multiple memory access instructions stored in the dispatch queue to obtain a merged instruction. The merged instruction can be transmitted through the transmission path of the ordinary memory access instruction, so that after the pipeline receives the merged instruction, it can determine the instruction content of the above-mentioned multiple memory access instructions according to the merged instruction. That is, based on the one merged instruction, the effect of synchronously executing the above-mentioned multiple memory access instructions in one clock cycle is achieved, which saves the bandwidth consumed by transmitting multiple memory access instructions, improves the speed of the pipeline to obtain the memory access instruction, and reduces the clock cycle that the pipeline needs to wait for to obtain the memory access instruction, which helps to improve the execution efficiency of the memory access instruction.

[0041] Since the pipeline may have instruction execution exceptions during the instruction execution process, and redirection and other operations are required between instructions with timing violations, the decoder generates multiple instructions in one clock cycle and cannot be executed immediately in the subsequent clock cycle, and memory access instructions will accumulate in the dispatch queue. Therefore, the number of entries in the dispatch queue used to store memory access instructions needs to be greater than or equal to the number of decoders generated by the decoder in one clock cycle. Instruction merging in the dispatch queue provides a broad instruction selection window for the instruction merging process, improves the range of memory access instructions that can be selected during the instruction merging process, helps to merge more memory access instructions into one merged instruction, and helps the pipeline obtain more memory access instructions in one clock cycle, thereby further improving the pipeline's processing efficiency for memory access instructions.

[0042] The instruction execution module provided in the embodiment of the present application can be used as a complete high-performance processor, or a part of a high-performance processor can be encapsulated in a chip. The chip can be an AI chip for model training, a chip for image processing, a chip for video processing, etc. The present application does not limit the type of chip used by the instruction execution module.

[0043] The chip corresponding to the instruction execution module provided in the embodiment of the present application can also be applied to ITS (Intelligent Traffic System). Intelligent transportation system, also known as intelligent transportation system (Intelligent Transportation System), is to effectively and comprehensively apply advanced science and technology (information technology, computer technology, data communication technology, sensor technology, electronic control technology, automatic control theory, operations research, artificial intelligence, etc.) to transportation, service control and vehicle manufacturing, strengthen the connection between vehicles, roads and users, and thus form a comprehensive transportation system that ensures safety, improves efficiency, improves the environment and saves energy. For example, the instruction execution device provided in the embodiment of the present application can be applied to various scenarios such as cloud technology, artificial intelligence, smart transportation, assisted driving, etc., to improve the speed at which the processor executes memory access instructions in the intelligent transportation system, thereby prompting the data processing performance of the processor.

[0044] From the perspective of CPU (Central Processing Unit) design, the most critical part affecting CPU performance is the processing of memory access instructions, that is, the design of the memory access unit. The efficiency of the execution of memory access instructions directly determines the performance of the CPU. In the CPU design process, for the design scheme using Dispatch Queue, a further compression function of memory access instructions can be implemented based on DispatchQueue. Compared with the design scheme of fusing memory access instructions in the decoder, the instruction execution module provided in the embodiment of the present application can be used as a supplement to further improve CPU performance.

[0045] Figure 4 4 is a schematic diagram of an instruction execution module applied to a processor provided by an exemplary embodiment of the present application. The instruction execution module 400 includes: a dispatch queue 410 and a pipeline 430;

[0046] The dispatch queue 410 is used to store at least one memory access instruction to be executed; select n memory access instructions from the at least one memory access instruction to be executed, where n is an integer greater than 1; merge the n memory access instructions into one instruction to obtain a first merged instruction, and the effect of the first merged instruction is equivalent to the effect of the n memory access instructions.

[0047] In some embodiments, a memory access instruction refers to an instruction for implementing data loading or data storage. Optionally, the types of memory access instructions include load instructions and store instructions, the load instruction is used to obtain data stored in the memory access address, and the store instruction is used to store data in the storage space corresponding to the memory access address.

[0048] The instructions that can be merged in the embodiment of the present application are conventional memory access instructions, such as LB (Load Byte), LW (Load Word), LH (Load Half-word) and LD (Load Double-word) in the load instructions. The memory access instructions used to implement the lock grabbing mechanism are not suitable for instruction merging.

[0049] Exemplarily, the memory access instruction is generated by the decoder in the processor decoding the instruction data stored in the instruction buffer and performing renaming processing through the renaming module. After completing the renaming of the instruction, the renaming module sends the instruction to the corresponding dispatch queue according to the type of the instruction.

[0050] Optionally, the instruction content of the memory access instruction includes: an instruction identifier, a register number and a memory access address, wherein the instruction identifier is used to indicate the type of the memory access instruction, and the register number is used to represent the register used when the pipeline executes the memory access instruction.

[0051] Exemplarily, the register number is the number of the physical register. The physical register refers to the register that actually exists in the processor. During the renaming process, the renaming module maps the logical register in the memory access instruction to the physical register. The logical register refers to the callable register provided to the software in the instruction set. There is a mapping relationship between the logical register and the physical register, and the renaming module stores the mapping relationship.

[0052] Optionally, the memory access instruction belongs to a uop (Micro Operation).

[0053] In some embodiments, the dispatch queue 410 is used to store at least one memory access instruction to be executed. The dispatch queue is also called a scheduling queue, an allocation queue, etc.

[0054] Optionally, only memory access instructions are stored in the dispatch queue, and other types of instructions are not stored. Exemplarily, after the renaming module completes the renaming process of the instruction, the instruction is sent to the corresponding dispatch queue according to the type of the instruction. For example, the memory access instruction is sent to the dispatch queue 410, and the operation instruction is allocated to other dispatch queues of the processor. In this case, the dispatch queue 410 can be an LSDQ.

[0055] Optionally, both memory access instructions and operation instructions are stored in the dispatch queue 410. The instruction type stored in the dispatch queue 410 is set according to actual needs, and this application does not limit it here.

[0056] In some embodiments, the memory access instruction to be executed refers to the memory access instruction that has not been executed by the pipeline. The memory access instruction to be executed is waiting to be sent to the pipeline for execution. Optionally, the dispatch queue 410 determines the storage entry of the memory access instruction to be executed in the dispatch queue 410 according to the execution timing of at least one memory access instruction to be executed. Among them, the execution timing of the memory access instruction refers to the order of the memory access instruction in the instruction stream, and the instruction stream refers to the serial arrangement order between the instructions when the instructions are executed sequentially. The instructions at the front of the instruction stream are executed before the instructions at the back of the instruction stream.

[0057] In addition, by adding new execution logic in the dispatch queue 410, n memory access instructions can be selected from at least one memory access instruction to be executed stored in the dispatch queue, and the n memory access instructions can be merged into one instruction to obtain a merged instruction.

[0058] Optionally, the dispatch queue 410 includes s entries for storing memory access instructions, where s is a positive integer. For example, s is equal to 16 or 32. s is also called the capacity of the dispatch queue. The larger the value of s is, on the one hand, the more memory access instructions to be executed can be accommodated in the dispatch queue 410, the wider the merging range when merging instructions is performed, and the more memory access instructions can be selected; on the other hand, the larger the value of s is, the longer it takes to select n memory access instructions from the dispatch queue 410, and the larger the volume occupied by the dispatch queue 410 in the hardware. The value of s is determined by compromise based on actual performance requirements, and the specific value of s is not limited here.

[0059] In order to avoid pipeline blockage that causes the upstream decoder to be unable to continue decoding and generate new instructions, the capacity of the dispatch queue is usually greater than the number of instructions generated by the decoder in one clock cycle. That is, the memory access instructions to be executed stored in the dispatch queue are unlocked by the decoder in different clock cycles. Therefore, compared to performing instruction merging in the decoder, the embodiment of the present application performs instruction merging in the dispatch queue, which improves the scope of instruction merging, so that the instruction merging process has more optional memory access instructions, which helps to expand the field of view of the instruction merging process and helps to represent more memory access instructions through merging instructions.

[0060] Optionally, n is a positive integer greater than or equal to 1. For example, n is equal to 6, that is, the first merge instruction includes 6 memory access instructions. Exemplarily, the value of n changes dynamically. In any clock cycle of the instruction execution module, at least one of the following situations will occur: the memory access instruction to be executed leaves the dispatch queue 410, and the new memory access instruction to be executed is added to the dispatch queue 410. It can be seen that at least one memory access instruction to be executed stored in the dispatch queue 410 changes dynamically. Therefore, in different clock cycles, the number of memory access instructions suitable for generating the merge instruction selected from at least one memory access instruction to be executed will also change.

[0061] In one example, n has a maximum value and a minimum value. That is, the number of memory access instructions selected from at least one memory access instruction does not exceed the maximum value of n, and the minimum value is not less than the minimum value of n. For example, the maximum value is 6, and the minimum value is 2.

[0062] In some cases, the maximum value of n is affected by the instruction merging method. In order to ensure that the dispatch queue 410 can use the transmission path of one memory access instruction to dispatch the first merged instruction, the first merged instruction does not exceed the bandwidth used to transmit the memory access instruction. That is, the maximum value of n is used to control the generated merged instruction to not exceed the microinstruction bandwidth used to transmit one memory access instruction. In addition, the maximum value of n is affected by the processing capability of the pipeline for memory access instructions, and the maximum value of n is less than or equal to the upper limit of the memory access instructions that the pipeline can execute in one clock cycle.

[0063] Optionally, the n memory access instructions are of the same instruction type. For example, the n memory access instructions are all load instructions. For another example, the n memory access instructions are all store instructions.

[0064] Optionally, the n memory access instructions are n memory access instructions whose execution sequence is continuous among at least one memory access instruction to be executed. In one example, the execution sequence of the memory access instructions can be represented by instruction numbers, where a smaller number indicates an earlier execution sequence of the memory access instruction, and a larger number indicates a later execution sequence of the memory access instruction, and the n memory access instructions are numbered [0, n-1].

[0065] In some embodiments, the first merge instruction is used to characterize the instruction content of n memory access instructions. In other words, the instruction content of n memory access instructions can be determined according to the first merge instruction. Sending the first merge instruction to the pipeline 430 is equivalent to sending n memory access instructions to the pipeline 430. The difference between the two is that sending the first merge instruction to the pipeline 430 only takes up 1 microinstruction bandwidth in one clock cycle, and sending n memory access instructions to the pipeline 430 separately takes up n clock cycles at most. Merging n memory access instructions improves the efficiency of the pipeline in obtaining memory access instructions.

[0066] Instruction fusion is equivalent to compressing and packaging n memory access instructions so that the first merged instruction obtained can represent the instruction content of the n memory access instructions, so as to achieve the effect of the pipeline executing n memory access instructions in one clock cycle.

[0067] Optionally, in the process of merging n memory access instructions into one instruction, the dispatch queue 410 generates the instruction content of the first merged instruction based on the instruction content of the n memory access instructions, thereby obtaining the first merged instruction. Subsequently, the first merged instruction is emitted to the pipeline 430 instead of emitting n memory access instructions to the pipeline 430 separately. Exemplarily, the data path used when emitting the first merged instruction is the same as the data path used when emitting one memory access instruction. Therefore, this architecture has little impact on other parts of the existing instruction execution architecture, and can directly improve the architecture of the existing instruction execution module when making major changes.

[0068] In some embodiments, the instruction execution module further includes: RS (Reservation Station). The reservation station is used to transfer the instructions to be executed between the dispatch queue and the pipeline. Exemplarily, the instructions to be executed dispatched by the dispatch queue are received by the reservation station, and the pipeline 430 used to execute the instructions to be executed and the clock cycle for transmitting the instructions to be executed to the pipeline 430 are determined. The reservation station transmits the instructions to be executed to the pipeline 430, and then the pipeline 430 executes the instructions to be executed.

[0069] Optionally, the type of the instruction to be executed includes at least one of the following: a merge instruction, and other memory access instructions other than the n memory access instructions in at least one memory access instruction to be executed. The merge instruction is obtained by fusing multiple memory access instructions. For example, the first merge instruction in the above embodiment belongs to a merge instruction.

[0070] The reservation station is also called a scheduler, etc. The reservation station in the embodiment of the present application is used to complete the function of issuing memory access instructions to the pipeline. The reservation station is represented by different names in different processor types, and this application does not explain these names one by one.

[0071] It should be noted that if n memory access instructions are merged to generate a first merge instruction, the dispatch queue 410 only needs to send the first merge instruction to the reservation station, and will not send n memory access instructions to the reservation station separately, so as to avoid any of the n memory access instructions being executed repeatedly, resulting in errors in the program running results.

[0072] Since there is a maximum limit on n of the n memory access instructions, and the n memory access instructions selected from at least one memory access instruction to be executed must meet the instruction merging condition, there may be memory access instructions that cannot be merged in at least one memory access instruction to be executed, and such memory access instructions are other memory access instructions. The dispatch queue 410 needs to dispatch these other memory access instructions separately. That is, the other memory access instructions are transmitted to the pipeline through a microinstruction bandwidth.

[0073] Optionally, the dispatch queue 410 is coupled to the reservation station, and the reservation station is coupled to the pipeline 430. Exemplarily, the port width between the dispatch queue 410 and the reservation station is a microinstructions, indicating that in one clock cycle, the dispatch queue 410 sends at most a microinstructions to the reservation station. a is a positive integer, such as a is equal to 4.

[0074] As described above, memory access instructions belong to microinstructions, and the size of the merged instruction generated by instruction merging does not exceed 1 microinstruction. Therefore, in one clock cycle, the dispatch queue 410 dispatches at most a merged instruction to the reservation station, sends at least one other memory access instruction, or no instruction to be executed occurs. For example, a is equal to 4, and the dispatch queue 410 dispatches 2 merged instructions and 1 memory access instruction to the reservation station.

[0075] In some embodiments, the instruction execution module includes at least one reservation station, and different reservation stations are used to transmit different types of memory access instructions. Optionally, the instruction execution module includes at least a load instruction reservation station (Load RS) and a store instruction reservation station (Store RS).

[0076] The load reservation station is used to issue load instructions, and the storage reservation station is used to issue storage instructions. Exemplarily, if the first merge instruction includes n load instructions, the dispatch queue 410 dispatches the first merge instruction to the load reservation station; if the first merge instruction includes n storage instructions, the dispatch queue 410 dispatches the first merge instruction to the storage reservation station.

[0077] Exemplarily, the port width between the reservation station and the pipeline 430 is b microinstructions, which means that in one clock cycle, the reservation station sends at most b microinstructions to the pipeline 430. b is a positive integer, such as b equals 4. For example, the reservation station sends 1 merge instruction and 2 memory access instructions to the pipeline in one clock cycle.

[0078] Pipeline 430 is used to execute the first merge instruction.

[0079] In some embodiments, the pipeline 430 is used to execute the first merge instruction to achieve synchronous execution of n memory access instructions. The first pipeline 430 can also be used to execute other memory access instructions.

[0080] The synchronous execution of n memory access instructions can be understood as: the pipeline obtains the instruction contents of n memory access instructions according to the first merge instruction within one clock cycle, and executes the n access instructions in sequence according to the execution sequence of the n memory access instructions. Compared with the related art, a microinstruction path can only send one memory access instruction to the same pipeline 430 in each clock cycle. In the embodiment of the present application, the first merge instruction is sent to the pipeline 430, so that the pipeline 430 obtains n memory access instruction pipelines in the same clock cycle, thereby realizing the synchronous execution of n memory access instructions in the same clock cycle.

[0081] In some embodiments, the instruction execution module 400 includes multiple pipelines, wherein there are at least two types of pipelines in the multiple pipelines, and the two types of pipelines are used to execute different types of memory access instructions. Optionally, the multiple pipelines include a load instruction pipeline (Load Pipeline) for executing load instructions and a store instruction pipeline (Store Pipeline) for executing store instructions.

[0082] The instruction execution module 400 may also include a calculation pipeline, etc., which is not limited in this application.

[0083] When the n memory access instructions are load instructions, pipeline 430 is a load pipeline, and the load reservation station sends the first merge instruction to the load pipeline. When the n memory access instructions are store instructions, pipeline 430 is a store pipeline, and the store reservation station sends the first merge instruction to the store pipeline.

[0084] Figure 5It is a schematic diagram of a binary disassembly file provided by an exemplary embodiment of the present application.

[0085] From the binary disassembly file fed back by the performance testing tool (Dhrystone Benchmark), it can be seen that there are a large number of stack push and pop operations in the process of implementing function calls in the processor. In other words, there are a large number of continuous memory access instructions (such as Figure 5 According to statistics, about 36% of the memory access instructions of some existing central processing units are continuous memory access instructions. It can be seen that the execution efficiency of memory access instructions has a crucial impact on the performance of the processor in executing tasks.

[0086] The instruction execution module provided by the embodiment of the present application has a wider range of optional memory access instructions during the instruction merging process. Without affecting the working cycle of the pipeline, multiple memory access instructions are merged into one merged instruction as much as possible, reducing the limitation of the port width of the microinstruction on the transmission of the multiple memory access instructions to the pipeline. By transmitting a merged instruction to the pipeline, the pipeline obtains multiple instruction contents in one clock cycle, which helps to improve the efficiency of the pipeline in obtaining and executing memory access instructions.

[0087] In summary, the embodiment of the present application provides an instruction execution module, which achieves the effect of fusing multiple storage instructions stored in the dispatch queue into a merged instruction by adding new execution logic in the dispatch queue. The merged instruction is executed by the pipeline to achieve the same effect as executing the above-mentioned multiple storage instructions. Relying on the relatively broad instruction merging range provided in the dispatch queue, it is helpful to merge a large number of memory access instructions into one merged instruction, and only one merged instruction is transmitted to achieve the effect of transmitting the above-mentioned large number of memory access instructions, so that the pipeline obtains multiple memory access instructions in one clock cycle, which helps to realize the execution of multiple memory access instructions by the pipeline in one clock cycle, and improves the execution efficiency of the instruction execution module for memory access instructions.

[0088] The functional components of the dispatch queue are introduced and explained through several embodiments below.

[0089] In some embodiments, a dispatch queue includes: a first buffer and an instruction fusion unit; the first buffer is used to store at least one memory access instruction to be executed; the instruction fusion unit is used to select n memory access instructions with continuous execution sequence from at least one memory access instruction to be executed as n memory access instructions based on an instruction merging condition, wherein the instruction merging condition includes that the n memory access instructions have the same instruction type, and the instruction type includes at least one of the following: load instruction, store instruction; the instruction fusion unit is further used to fuse the n memory access instructions into one instruction according to the instruction contents of the n memory access instructions to obtain a first merged instruction.

[0090] In some embodiments, at least one memory access instruction to be executed is stored in the first buffer. Optionally, the first buffer stores at least one memory access instruction to be executed in a queue data structure. That is, for the memory access instructions to be executed that are obtained earlier in the dispatch queue, these memory access queues to be executed are stored at the head of the first buffer, and for the memory access instructions to be executed that are obtained later in the dispatch queue, these memory access queues to be executed are stored at the end of the first buffer. Optionally, the dispatch queue gives priority to dispatching the memory access queue to be executed at the head of the queue.

[0091] Optionally, the first buffer is an existing functional unit in the dispatch queue. The newly added execution logic on the dispatch queue is embodied in the instruction fusion unit. That is, by adding an instruction fusion unit to the dispatch queue in the related art, n merged instructions in at least one memory access instruction stored in the dispatch queue can be merged to generate a first merged instruction.

[0092] The instruction fusion unit is used to select n memory access instructions and generate a first merged instruction. Optionally, the instruction fusion unit is coupled to the first buffer. Exemplarily, the instruction fusion unit determines the instruction content of at least one memory access instruction to be executed through the first buffer; based on the instruction content, determines whether at least one memory access instruction to be executed complies with the instruction merging condition, so as to select n memory access instructions from the at least one memory access instruction to be executed, and executes the process of generating the first merged instruction according to the n memory access instructions.

[0093] In order to ensure that the first merged instruction can be successfully executed and reduce the number of exceptions during instruction execution, when determining n instructions from at least one memory access instruction to be executed, the instruction merge condition needs to be followed. Instruction merge addition is the basis for selecting n instructions from at least one memory access instruction stored in the first buffer.

[0094] In some embodiments, the instruction merging condition includes at least that the instruction types of the n memory access instructions are the same. For example, the n instructions are n load instructions that are executed sequentially. For another example, the n instructions are n store instructions that are executed sequentially. That is, the n memory access instructions refer to n memory access instructions of the same type that are executed sequentially.

[0095] As can be seen from the above embodiments, the instruction execution module may include a loading pipeline and a storage pipeline, and the loading instruction and the storage instruction need to be executed in different pipelines. When selecting multiple memory access instructions based on the instruction merging condition, it is ensured that the instruction types of the selected multiple memory access instructions are the same, so that the merged instruction obtained by merging the multiple memory access instructions can be successfully executed by the same pipeline, which helps to reduce the number of abnormalities in the execution process of the merged instruction.

[0096] In some embodiments, the instruction merging condition further includes at least one of the following: the labels of the physical registers of the m memory access instructions are continuous; among the n memory access instructions, there is a stable offset between the memory access addresses of any two memory access instructions with adjacent execution sequences.

[0097] Optionally, the existence of a stable offset between the memory access addresses of any two memory access instructions executed sequentially adjacently means that the memory access addresses of the n memory access instructions are continuous. Optionally, the stable offset means that the offsets between the memory access addresses of any two memory access instructions executed sequentially adjacently are equal.

[0098] For example, for storage instruction 1, memory access instruction 2 and memory access instruction 3 among n memory access instructions, the memory access address of memory access instruction 1 is 200 (sp), the memory access address of memory access instruction 2 is 192 (sp), and the memory access address of memory access instruction 3 is 184 (sp); then the offset of the memory access address of memory access instruction 2 relative to the memory access address of memory access instruction 1 is 8, and the offset of the memory access address of memory access instruction 3 relative to the memory access address of memory access instruction 2 is 8, that is, there is a stable offset between the memory access addresses of memory access instruction 1, memory access instruction 2 and memory access instruction 3.

[0099] In some other embodiments, among the n memory access instructions, there are a first memory access instruction and a second memory access instruction; wherein the execution timing of the first memory access instruction and the second memory access instruction is continuous, and the offset between the memory access address of the first memory access instruction and the memory access address of the second memory access instruction is not equal to the stable offset. In this case, an exception may occur during the pipeline execution of the first merge instruction, and the instruction execution module also includes a processing mechanism for such an exception. For the specific content of the process, please refer to the following embodiment.

[0100] Optionally, the label of the physical register is used to characterize the physical register of the memory access instruction. The physical register of the memory access instruction refers to the physical register used in the process of executing the memory access instruction. For example, when the memory access instruction is a load instruction, the physical register of the memory access instruction is used to store the data read from the memory access address. For another example, when the memory access instruction is a store instruction, the physical register of the store instruction is used to store the data that needs to be stored in the memory access address, that is, the data in the physical register of the store instruction is stored in the storage area corresponding to the memory access address.

[0101] It should be noted that the physical register number of the memory access instruction is determined by the reservation station. For the specific method of determining the physical register of the memory access instruction, please refer to the relevant technology, which is not limited here.

[0102] In some embodiments, the instruction fusion unit includes: at least one level of comparator and an instruction generator; for the first level comparator in the at least one level of comparator, the kth comparator in the first level comparator is used to determine the comparison result of the kth comparator according to the memory access instructions respectively stored in the 2kth entry and the 2k+1th entry in the first buffer, wherein the entries of the first buffer are used to store memory access instructions, k is a positive integer less than or equal to 0.5*s, s is the total number of entries included in the first buffer, and the comparison result of the kth comparator is used to characterize the compliance of the memory access instructions respectively stored in the 2kth entry and the 2k+1th entry with the instruction merging condition; if there is an i-th level comparator in the at least one level of comparator, i is a positive integer greater than 1, then the j-th comparator in the i-th level comparator is used to determine the comparison result of the j-th comparator according to the comparison result of the 2j-1th comparator in the i-1th level comparator and the comparison result of the 2jth comparator, and the comparison result of the j-th comparator is used to characterize the (j-1)*2 i-1 +1 entry to j*2 i-1 The memory access instructions respectively stored in the entries meet the instruction merging condition; the instruction generator is used to select n memory access instructions from at least one memory access instruction according to the comparison results of at least one level of comparator; according to the instruction contents of the n memory access instructions, the n memory access instructions are merged to obtain a first merged instruction.

[0103] In some embodiments, the comparator is a combinational logic for determining whether a memory access instruction complies with an instruction merge condition. Optionally, a comparator is used to compare a limited number of memory access instructions. For example, one comparator is used to compare whether two adjacent memory access instructions comply with an instruction merge condition.

[0104] Optionally, the comparator has two inputs and one output. In an embodiment of the present application, the two inputs of the comparator include instruction types of two memory access instructions, and the output of the comparator is whether the two memory access instructions comply with the instruction merging condition.

[0105] The compliance with the instruction merging condition includes: compliance with the instruction merging condition and non-compliance with the instruction merging condition. If the compliance of two memory access instructions with the instruction merging condition is: non-compliance with the instruction condition, the two memory access instructions cannot participate in the same instruction merging process, that is, the two memory access instructions cannot be merged into one merged instruction.

[0106] Exemplarily, if the instruction types of two adjacent memory access instructions are the same, the comparator determines that the two adjacent memory access instructions meet the instruction merging condition; if the instruction types of the memory access instructions of two adjacent memory access instructions are different, the comparator determines that the two adjacent memory access instructions do not meet the instruction merging condition. Among them, the two adjacent memory access instructions refer to the memory access instructions stored in two adjacent entries in the first buffer. That is, when the first buffer stores the memory access instructions according to the execution sequence, the execution sequence of the memory access instructions stored in the two adjacent entries is adjacent. At this time, the comparator only needs to compare whether the types of the two adjacent memory access instructions are consistent.

[0107] Optionally, when the instruction merging condition also includes the existence of a stable offset between the memory access addresses of any two memory access instructions with adjacent execution timings, the two inputs of the comparator include the instruction types of the two memory access instructions and the memory access addresses of the two memory access instructions, and the output of the comparator is the compliance of the two memory access instructions with the instruction merging condition. If the instruction types of the two adjacent memory access instructions are the same, and the memory access address offsets of the two memory access instructions are stable offsets, the comparator determines that the two adjacent memory access instructions meet the instruction merging condition.

[0108] In some embodiments, a plurality of comparators are provided in the instruction fusion unit, and the plurality of comparators form a hierarchical structure. For example, the plurality of comparators form at least one comparator hierarchy, and at least one comparator hierarchy is in a tree structure. Exemplarily, each comparator in the same comparator hierarchy executes the comparison logic in parallel, that is, each comparator included in the same comparator hierarchy executes the comparison logic in the same time period. Exemplarily, the inputs of each comparator in the same comparator hierarchy are different.

[0109] Optionally, the first-level comparator refers to a comparator at the lowest level in at least one comparator hierarchy, and for any comparator belonging to the first-level comparator, the comparator is used to determine whether the memory access instructions stored in the two entries in the first buffer meet the instruction merging condition. In other words, any comparator in the first-level comparator corresponds to two entries in the first buffer, and the comparator is used to determine whether the memory access instructions stored in the two corresponding entries respectively meet the instruction compliance condition.

[0110] Exemplarily, any comparator in the first-stage comparator corresponds to two adjacent entries in the first buffer. For example, the first buffer includes 16 entries, namely e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15 and e16, and the first-stage comparator includes 8 comparators, wherein comparator 1 corresponds to entries e1 and e2; comparator 2 corresponds to entries e3 and e4; comparator 3 corresponds to entries e5 and e6, and so on.

[0111] Exemplarily, the number of comparators included in the first-stage comparator is proportional to the total number s of entries included in the first buffer. The greater the total number of entries included in the first buffer, the greater the number of comparators included in the first-stage comparator; the fewer the total number of entries included in the first buffer, the fewer the number of comparators included in the first-stage comparator. For example, the number of comparators included in the first-stage comparator is equal to half of the total number of entries included in the first buffer.

[0112] Optionally, in the case where the instruction fusion unit includes multiple levels of comparators, for two adjacent levels of comparators, the two inputs of the higher-level comparator are the outputs of the lower-level comparators. For example, for any comparator in the i-th level of comparators, the input of the comparator is the output of the two comparators in the i-1th level, where i is a positive integer greater than 1.

[0113] The output of the comparator is called the comparison result. Exemplarily, the comparison result includes result information. The comparison result also includes at least one of the following: instruction type information, offset. Among them, the result information meets the instruction merge condition, or does not meet the instruction merge condition. In the case where the result information meets the instruction merge condition. The comparison result also includes instruction type information, and the instruction type information is used to characterize the instruction type of the memory access instruction corresponding to the comparator. Exemplarily, the instruction type information includes: load instruction and store instruction.

[0114] When the result information meets the instruction merging condition, the comparison result also includes an offset, which is used to represent the offset value between the memory access addresses of two memory access instructions with adjacent execution timings among the multiple memory access instructions corresponding to the comparator.

[0115] In some embodiments, if the instruction fusion unit includes at least one level of comparators including an i-th level comparator, where i is a positive integer greater than 1, the j-th comparator in the i-th level comparator is used to determine the comparison result of the j-th comparator according to the comparison result of the 2j-1-th comparator in the i-1-th level comparator and the comparison result of the 2j-th comparator, and the comparison result of the j-th comparator is used to represent the (j-1)*2 i-1 +1 entry to j*2 i-1 Each entry stores the memory access instructions and the compliance with the instruction merging conditions.

[0116] Optionally, the jth comparator obtains two instruction type information from the comparison result of the 2j-1th comparator and the comparison result of the 2jth comparator. If the two instruction type information are of the same type, the result information included in the comparison result of the jth comparator meets the instruction merging condition. Optionally, when the result information in the comparison result of the jth comparator meets the instruction merging condition, the comparison result of the jth comparator also includes the (j–1)*2th instruction type information in the first buffer. i-1 +1 entry to j*2 i-1 Each entry stores the instruction type of the memory access instruction.

[0117] In some embodiments, the instruction generator is used to select n memory access instructions from at least one memory access instruction based on the comparison results of at least one level of comparator, and merge the n memory access instructions according to the instruction contents of the n memory access instructions to obtain a first merged instruction.

[0118] Optionally, the instruction generator selects a comparator with the highest level from at least one level of comparators and determines that the result information included in the comparison result meets the instruction merging conditions as the target comparator. The instruction generator uses the memory access instructions stored in the multiple entries corresponding to the target comparator in the first buffer as n memory access instructions.

[0119] Optionally, fusing n memory access instructions into one instruction means: compressing and packaging the instruction contents of the n memory access instructions to obtain a first merged instruction. For the instruction contents of the first merged instruction, please refer to the following embodiments.

[0120] By setting a plurality of comparators in the instruction fusion unit and arranging the plurality of comparators in a hierarchical manner, it is helpful to improve the speed of determining n memory access instructions from at least one memory access instruction and shorten the time consumption of the instruction fusion process.

[0121] The following describes the instruction content of the first merge instruction through several embodiments.

[0122] In some embodiments, the instruction content of the first merged instruction includes: basic operation information, used to indicate the basic memory access instruction with the earliest execution timing among n memory access instructions; register information, used to represent the physical registers of the n memory access instructions, and the physical registers of the memory access instructions are used to record the memory access data corresponding to the memory access instructions during the execution of the memory access instructions; memory access address information, used to represent the memory access addresses of the n memory access instructions, and the memory access addresses of the memory access instructions are used to store the memory access data indicated by the memory access instructions, or to provide the memory access data for the memory access instructions to read.

[0123] In some embodiments, the instruction content of the memory access instruction includes: an instruction type identifier, a register number, and a memory access address. The first merge instruction can represent the instruction content of n memory access instructions. Among them, the register number is used to uniquely identify the physical register. The numbers of different physical registers are not repeated.

[0124] In some embodiments, the time taken to complete the execution of the first merge instruction in the pipeline is less than or equal to one clock cycle. The execution of the first merge instruction in the pipeline means determining the instruction contents of n memory access instructions based on the first merge instruction and executing the n memory access instructions in the pipeline.

[0125] Exemplarily, the pipeline determines the instruction content of n memory access instructions one by one. For example, after the i-th memory access instruction among the n memory access instructions is executed, the pipeline determines the instruction content of the i+1-th memory access instruction and executes the i+1-th memory access instruction, where i is a positive integer less than or equal to n.

[0126] Exemplarily, after receiving the first merge instruction, the pipeline first determines the instruction contents of n memory access instructions, and executes the n memory access instructions in parallel in the current clock cycle. The parallel execution of n memory access instructions can be understood as: the pipeline executes and completes the n memory access instructions one by one according to the execution sequence within one clock cycle. For example, n is equal to 6, and according to the execution sequence from first to last, the n memory access instructions are: memory access instruction 1, memory access instruction 2, memory access instruction 3, memory access instruction 4, memory access instruction 5 and memory access instruction 6. Then, the pipeline determines the instruction contents of the above 6 memory access instructions within one clock cycle, and executes the above 6 memory access instructions starting from memory access instruction 1.

[0127] In some embodiments, the first merge instruction includes register information and memory access address information. Optionally, the register information is used to directly indicate the physical registers of the n memory access instructions; the memory access address information is used to directly indicate the memory access addresses of the n memory access instructions. For example, the register information includes the label of the physical register of each of the n memory access instructions, and the memory access address information includes the memory access instruction of each of the n memory access instructions.

[0128] In some other embodiments, the first merged instruction includes: basic operation information, register information, and memory access address information. Optionally, the basic operation information is used to characterize the basic memory access instruction among the n memory access instructions, the basic memory access instruction refers to the memory access instruction with the earliest execution sequence among the n memory access instructions, the register information is used to: characterize the label of the physical register of the selected memory access instruction based on the physical register of the basic memory access instruction; the memory access address information is used to: characterize the memory access address of the selected memory access instruction based on the memory access address of the basic memory access instruction. Among them, the selected memory access instruction refers to: the memory access instruction other than the basic memory access instruction among the n memory access instructions.

[0129] Optionally, the execution timing of the basic memory access instruction takes precedence over the execution timing of the selected memory access instruction.

[0130] Exemplarily, after receiving the first merge instruction, the pipeline determines the instruction content of the basic memory access instruction according to the basic operation information in the first merge instruction, and the pipeline executes the basic memory access instruction according to the instruction content of the basic memory access instruction. In addition, the pipeline can also determine the instruction content of the selected memory access instruction based on the instruction content of the basic memory access instruction, so as to execute n memory access instructions in parallel in one clock cycle.

[0131] Of course, the basic memory access instruction refers to any memory access instruction among the n memory access instructions. For example, the basic memory access instruction refers to the memory access instruction with the latest execution sequence among the n memory access instructions, which is not limited in this application.

[0132] Optionally, the register information is used to represent the physical register of the selected memory access instruction, and the offset label of the physical register of the basic memory access instruction; the access address information is used to represent the memory access address of the selected memory access instruction, and the address offset of the memory access address of the basic memory access instruction.

[0133] In this embodiment, based on the basic memory access instruction, the register information and the memory access address information are encoded, which can reduce the number of bits used by the register information and the memory access address information. Encoding in this way helps to control the data volume of the instruction content of the merge instruction, so that the merge instruction can be represented by a smaller number of bits, and it is convenient to use the microinstruction bandwidth used to transmit the memory access instruction in the instruction execution module to dispatch and transmit the merge instruction, thereby reducing the modification of the instruction transmission port of the instruction execution module.

[0134] The following describes several encoding formats of register information supported by the instruction execution module in the embodiment of the present application.

[0135] Example 1: The occupation status of one physical register is represented by one bit.

[0136] In some embodiments, register information is represented by m bits, different bits among the m bits correspond to different physical registers, one bit among the m bits corresponding to the physical register of the selected memory access instruction represents an occupied state, and the other bits among the m bits represent an idle state. The selected memory access instruction refers to a memory access instruction among the n memory access instructions except the basic memory access instruction.

[0137] The register information may be represented as Phy_reg_off.

[0138] Optionally, m is a positive integer, and the value of m is positively correlated with the total number of entries included in the first buffer. The smaller the total number of entries included in the first buffer, the smaller m is; the larger the total number of entries included in the first buffer, the larger m is. Exemplarily, m is greater than or equal to the total number of entries included in the first buffer. For example, the total number of entries included in the first buffer is 16, and m=16.

[0139] Optionally, for any one of the m bits, the bit corresponds to a label of a physical register, that is, the bit corresponds to a physical register. Any one of the m bits corresponds to a physical register one-to-one. For example, the label of the physical register of the x-th bit among the m bits is X, where x is a positive integer less than or equal to m. There is a mapping relationship between X and x, such as X=x.

[0140] Exemplarily, the number of the physical register corresponding to the m bits is related to the number of the physical register of the basic memory access instruction.

[0141] For example, the offset of the index of the physical register corresponding to the first bit of the m bits (i.e., the lowest bit of the m bits) relative to the index of the physical register corresponding to the basic memory access instruction is 1. Assuming that the index of the physical register corresponding to the basic memory access instruction is P80, the index of the physical register corresponding to the first bit of the m bits is P81, the index of the physical register corresponding to the second bit of the m bits is P82, and so on.

[0142] For another example, the number of the physical register corresponding to the first bit of the m bits is the number of the physical register of the basic memory access instruction, that is, the first bit corresponds to the physical register of the basic memory access instruction. Assuming that the number of the physical register corresponding to the basic memory access instruction is P80, the number of the physical register corresponding to the first bit of the m bits is P80, the number of the physical register corresponding to the second bit of the m bits is P81, and so on.

[0143] Optionally, for any one of the m bits, the bit may indicate an idle state or an occupied state. The specific value of the bit may be "0" or "1", wherein one of "0" and "1" indicates an idle state, and the other indicates an occupied state.

[0144] Exemplarily, "1" indicates an occupied state, and "0" indicates an idle state. For example, for the first bit among m bits, if the value of the bit is equal to 1, the physical register corresponding to the bit is in an occupied state. That is to say, there is a memory access instruction 1 among the n memory access instructions, and the memory access instruction 1 uses the physical register corresponding to the bit.

[0145] Optionally, there are n-1 bits among the m bits to indicate an occupied state, and m-n+1 bits among the m bits except for n-1 bits indicate an idle state. For example, in the above example of "the offset of the number of the physical register corresponding to the first bit among the m bits (i.e., the lowest bit among the m bits) relative to the number of the physical register corresponding to the basic memory access instruction is equal to 1", there are n-1 bits among the m bits to indicate an occupied state, and m-n+1 bits among the m bits except for n-1 bits indicate an idle state.

[0146] Optionally, n bits among the m bits represent the occupied state, and mn bits represent the idle state. For example, in the above example of "the number of the physical register corresponding to the first bit among the m bits is the number of the physical register of the basic memory access instruction", n bits among the m bits represent the occupied state, and mn bits represent the idle state.

[0147] In some embodiments, m bits are represented by a bit field, wherein a bit field refers to a data structure composed of binary bits. That is, register information is represented by a bit field. Optionally, the bit field includes m binary bits, and m binary bits are m bits. One binary bit in the bit field corresponds to the number of a physical register. That is, according to the specific value of the binary bit, the number of the physical register used by the n memory access instructions can be determined.

[0148] Table 1 Correspondence between binary bits in the bit field and the labels of physical registers

[0149] bit field Bit 15 … Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The physical register number P95 … P85 P84 P83 P82 P81

[0150] As shown in Table 1, taking m=16 as an example, the bit field includes 16 binary bits, which are represented as Bit 0, Bit 1, ..., Bit 15 from low to high. Each binary bit corresponds to the label of a physical register. Optionally, the value of the label of the physical register corresponding to the binary bit in the low order is less than the value of the label of the physical register corresponding to the binary bit in the high order.

[0151] In the example corresponding to Table 1, the physical register of the basic memory access instruction is labeled P80, the physical register corresponding to binary bit Bit 0 is labeled P81, the physical register corresponding to binary bit Bit 2 is labeled P82, and so on. This setting makes it easy to calculate the correspondence between m bits and the labels of the physical registers, which helps to simplify the processing logic of the pipeline in the process of determining the physical registers of n memory access instructions according to the register information.

[0152] Optionally, the specific value of the binary bit indicates whether the corresponding physical register is in an occupied state. Exemplarily, if the specific value of the binary bit is "1", it indicates that the physical register corresponding to the binary bit is in an occupied state; if the specific value of the binary bit is "0", it indicates that the physical register corresponding to the binary bit is in an idle state, that is, the physical registers of the n memory access instructions do not include the physical register corresponding to the binary bit.

[0153] The register information generated by the above encoding format can represent n memory access instructions with continuous physical register numbers, and can also represent n memory access instructions with discontinuous physical register numbers. The following two embodiments are used to introduce the encoding format of register information when the physical register numbers of n memory access instructions are continuous and the physical register numbers of n memory access instructions are discontinuous.

[0154] Table 2 shows a bit field encoding format 1 of register information provided by an exemplary embodiment of the present application.

[0155] Table 2 Bit field encoding format of register information 1

[0156]

[0157] It should be noted that the information inside “()” in the table contents in Table 2 and Tables 3 and 4 below is displayed for ease of understanding. In fact, the register information is composed of only a few bits, that is, the register information does not actually include the content displayed in “()” in the second row of the table.

[0158] In this example, the instruction merging conditions include: the instruction types of n memory access instructions are the same, and the physical registers of the n memory access instructions are consecutive; m=16, n=6, the physical register of the basic memory access instruction is labeled P80, and in the bit field corresponding to the m bits: the physical register corresponding to the binary bit Bit 0 is labeled P81, the physical register corresponding to the binary bit Bit 1 is labeled P82, the physical register corresponding to the binary bit Bit 2 is labeled P83, and so on. Assume that the physical registers of the selected memory access instructions in the n memory access instructions are labeled P81, P82, P83, P84, and P85 respectively. This means that the specific values ​​of the binary bits Bit0, Bit1, Bit2, Bit3, and Bit4 in the bit field are "1", and the specific values ​​of the remaining 11 high-order binary bits in the bit field are all 1. The m bits can be represented as h0003, where h represents 16 binary bits.

[0159] Table 3 shows a bit field encoding format 2 of a register provided by an exemplary embodiment of the present application.

[0160] Table 3 Bit field encoding format of register information 2

[0161]

[0162] In this example, the instruction merging conditions include: the instruction types of n memory access instructions are the same; m=16, n=6, the physical register of the basic memory access instruction is labeled P80, and in the bit field corresponding to the m bits: the physical register corresponding to the binary bit Bit 0 is labeled P81, the physical register corresponding to the binary bit Bit 1 is labeled P82, the physical register corresponding to the binary bit Bit 2 is labeled P83, and so on. Assume that among the n memory access instructions, the physical registers of the remaining five selected memory access instructions in the execution sequence from earliest to latest are labeled P83, P87, P88, P89, and P92. This means that the specific values ​​of the binary bits Bit 2, Bit 6, Bit 7, Bit 8, and Bit 11 in the bit field are "1"; the specific values ​​of the remaining 11 high-order binary bits in the bit field are all 0, such as Bit[1:0] in Table 3 represents the binary bits Bit 0 and Bit 1, and the specific values ​​of the binary bits Bit 0 and Bit 1 are 0.

[0163] This encoding method of register information can represent register information with fewer bits, which helps to avoid merging instructions that exceed the transmission bandwidth of one microinstruction.

[0164] Example 2: The occupation status of a physical register is indicated by k bits.

[0165] In some embodiments, the register information is represented by (n-1)*k bits, k=ceil(log2s), ceil() represents rounding up, s is the total number of entries in the first buffer included in the allocation queue for storing memory access instructions, the k bits corresponding to the selected memory access instruction in the register information are used to represent the label of the physical register of the memory access instruction, and the selected memory access instruction refers to the memory access instruction other than the basic memory access instruction among the n memory access instructions.

[0166] ceil() means rounding up. For example, when s is 9, ceil(log2S)=4, and when s is 8, ceil(log2S)=3.

[0167] Optionally, for any selected memory access instruction, the corresponding k bits are used to represent the label of the physical register of the selected memory access instruction. For example, if the k bits corresponding to a selected memory access instruction are 0111, it means that the label of the physical register of the selected memory access instruction is 7.

[0168] Optionally, for any selected memory access instruction, the corresponding k bits are used to represent the physical register of the selected memory access instruction, relative to the offset number of the physical register of the basic memory access instruction. For example, if the physical register of the basic memory access instruction is numbered P80, and the k bits corresponding to a selected memory access instruction are 0011, it means that the physical register of the selected memory access instruction is numbered P83, (83=80+3).

[0169] In some embodiments, the n-1 selected memory access instructions in the register information correspond to k bits respectively, and are arranged according to the execution sequence of the selected memory access instructions. For example, the lowest k bits in the register information are used to represent the physical register of the selected memory access instruction with the earliest execution sequence.

[0170] In one example, n is equal to 6, and m is equal to 16. Then, in the encoding format of the register information provided in Example 2, the register information includes (6-1))*ceil(log216)=20 bits.

[0171] Table 4 shows a bit field encoding format 3 of register information provided by an exemplary embodiment of the present application.

[0172] Table 4 Bit field encoding format of register information 3

[0173]

[0174] In this example, the instruction merging conditions include: the instruction types of the n memory access instructions are the same, and the execution timing of the n memory access instructions is continuous; m=16, n=6, the physical register of the basic memory access instruction is labeled P80, and the 5 selected memory access instructions are instruction 1, instruction 2, instruction 3, instruction 4, and instruction 5 in order of execution timing from earliest to latest. As shown in Table 4, the k bits corresponding to instruction 1 are "0001", the k bits corresponding to instruction 2 are "0010", the k bits corresponding to instruction 3 are "0011", the k bits corresponding to instruction 4 are "0100", and the k bits corresponding to instruction 5 are "0101"; the binary representation of the 20 bits of register information is "01010100001100100001".

[0175] This encoding format helps reduce the number of bits used to represent register information when the maximum value of n is small.

[0176] The identification form of the memory access address information is introduced and explained through several embodiments below.

[0177] In some embodiments, the memory access address information includes offset information, and the offset information is used to characterize the relative offset between the memory access addresses of n memory access instructions.

[0178] The memory access address refers to the physical address of the memory access, and the memory access address corresponds to a storage unit in the memory. That is, data can be stored in the storage unit, or data can be written to the storage unit through the memory access address. Optionally, the memory access address is used to indicate the offset address of the memory access address of the selected memory access instruction relative to the base memory access address.

[0179] Optionally, the offset information includes: the offset direction of the memory access address of any selected memory access instruction relative to the memory access address of the basic memory access instruction, and the offset of the memory access address of any selected memory access instruction relative to the memory access address of the basic memory access instruction. In other words, the offset information includes n-1 offset sub-information, and for any one of the n-1 offset sub-information, the offset sub-information is used to characterize the offset direction of the memory access address of a selected memory access instruction relative to the memory access address of the basic memory access instruction, and the offset of the memory access address of the selected memory access instruction relative to the memory access address of the basic memory access instruction.

[0180] By encoding the offset information in this way, the representation of each selected memory access instruction is relatively flexible, reducing restrictions on selecting memory access instructions, helping to increase the number of memory access instructions selected from the dispatch queue, making the effect of executing the merge instruction equivalent to more memory access instructions, and helping to improve the pipeline's execution efficiency of memory access instructions.

[0181] Exemplarily, the offset information includes: the offset direction of the memory access address of the third memory access instruction relative to the memory access address of the basic memory access instruction, and the offset of the memory access address of the third memory access instruction relative to the memory access address of the basic memory access instruction. The third memory access instruction refers to the memory access instruction that is adjacent to the execution sequence of the basic memory access instruction among the n-1 other selected memory access instructions. In this case, the offset directions of the memory addresses of the n-1 other selected memory access instructions relative to the memory address of the basic memory access instruction are the same, and, among the n memory access instructions, the offsets between the memory addresses of two memory access instructions that are adjacent in execution sequence are equal.

[0182] Characterizing the instruction addresses of n-1 selected memory access instructions by using offset information helps to reduce the number of bits occupied by the memory access address information, and also helps to quickly obtain the instruction addresses of the n selected memory access instructions based on the offset information.

[0183] In some embodiments, the offset information includes direction information and an offset value; the direction information is used to characterize the offset direction of the memory access address of the selected memory access instruction relative to the memory access address of the basic memory access instruction, and the offset direction includes at least one of the following: left offset, right offset; the offset value is used to characterize the offset between the memory access addresses of any two memory access instructions with adjacent execution timing among n memory access instructions.

[0184] The offset information may be represented as Offset_bit.

[0185] Optionally, the offset direction is used to characterize the positional relationship between the memory access address of the selected memory access instruction and the memory access address of the basic memory access instruction. The left offset means that the memory access address of the selected memory access instruction is located to the left of the memory access address of the basic memory access instruction, that is, the value of the memory access address of the basic memory access instruction is smaller than the value of the memory access address of the basic memory access instruction; when arranged from early to late according to the execution sequence, the memory addresses of the n memory access instructions decrease in sequence.

[0186] Among them, the right offset means that the memory access address of the selected memory access instruction is located on the right side of the memory access address of the basic memory access instruction, that is, the value of the memory access address of the basic memory access instruction is greater than the value of the memory access address of the basic memory access instruction; when arranged from early to late according to the execution sequence, the memory access addresses of n memory access instructions increase successively.

[0187] Exemplarily, the offset direction is represented by 1 bit. For example, a specific value of the bit "0" indicates an offset to the left, and a specific value of the bit "1" indicates an offset to the right. For another example, a specific value of the bit "1" indicates an offset to the left, and a specific value of the bit "0" indicates an offset to the right.

[0188] Optionally, the offset value is a positive integer. Exemplarily, the offset value is equal to the absolute value of the difference between the memory access address of the third memory access instruction and the memory access address of the basic memory access instruction.

[0189] Exemplarily, the offset value is represented by ceil(log2 log2(O+1)) bits. Wherein, O represents the offset value. Exemplarily, O is equal to 8, and the offset value is represented by 2 bits. In this embodiment, the offset information is represented by at least ceil(log2log2(O+1))+1 bits.

[0190] Table 5 Coding format of offset information.

[0191] Offset information 0b111 0b110 0b101 0b100 0b011 0b010 0b001 0b000 Actual offset -8 -4 -2 invalid +8 +4 +2 invalid

[0192] As shown in Table 5, in one example, the basic memory access instruction is: ld p80,200(sp), where ld indicates that the instruction type is a load instruction, p80 indicates the label of the physical register, and 200(sp) indicates the memory access address of the basic memory access instruction.

[0193] The third memory access instruction is ld p80,192(sp), and among the n memory access instructions, the offset values ​​of the memory access addresses of the adjacent memory access instructions are equal, then the offset value is equal to 8, and the offset value is represented by 2 bits. The offset direction is to the left, and the offset direction is represented by 1 bit, then the offset information is represented by 3 bits, specifically: 0b111, where 0b represents binary coding, bit3 represents the offset direction, and bit[2:1] is 0b11, indicating that the offset value is 8.

[0194] The following describes the generation process of the first merge instruction through an example.

[0195] Figure 6 It is a schematic diagram of an instruction merging process provided by an exemplary embodiment of the present application.

[0196] like Figure 6 As shown, in the decoding stage, six instructions are obtained from the previous level for decoding, and in the renaming stage, the registers of the decoded 6 instructions are renamed to obtain the memory access instructions to be executed. In the dispatch stage, the memory access instructions to be executed are written into the LSDQ. Subsequently, in the dispatch stage, the memory access instructions stored in the dispatch queue include, from early to late in execution timing: 0: Ld p80, 200 (sp); 1: Ld p81, 192 (sp); 2: Ld p82, 184 (sp); 3: Ld p83; 176 (sp); 4: Ld p84, 168 (sp); 5: Ld p85, 160 (sp); 6: Ld p20, 8 (p80); 7: Ld p3, 16 (p92); 8: st p12, 0 (p1).

[0197] Optionally, the instruction fusion unit is at the Dispatch2RS level, and the instruction fusion unit selects the first six of the eight memory access instructions to be executed as n memory access instructions, and generates a first merge instruction MergeUop0 according to the six memory access instructions. The first merge instruction includes basic operation information: Ld p80,200 (sp), register information Phy_reg_off: 16'h0003 and memory access address information: Offset_addr: 3'b11.

[0198] like Figure 6, assuming that the port width between Dispatch2RS and Load RS is 4uops, since the MergeUop0 obtained by instruction fusion corresponds to the first six Load instructions, this MergeUop occupies 1uop in the port. The remaining 3uops of 4uops are idle and can be used to transmit the load instruction Ld p20, (p80) and the load instruction Ld p3, 16 (p92). Therefore, 6+2 instructions can be dispatched to Load RS in one clock cycle. Since instruction 8 in LSDQ is a store instruction, instruction 8 cannot be dispatched to Load RS in the same clock cycle, but needs to be dispatched to Store RS in the next clock cycle.

[0199] The following describes some of the contents related to the reservation station through several embodiments.

[0200] In some embodiments, the instruction execution module also includes: a reservation station; a reservation station, used to use a microinstruction bandwidth to transmit a first merge instruction to the pipeline; the reservation station is also used to determine an abnormal memory access instruction based on an abnormal execution signal sent from a reorder cache, the abnormal execution signal is used to indicate an abnormal memory access instruction in the first merge instruction, and the abnormal memory access instruction is not successfully executed in the pipeline; re-transmitting the memory access instructions that have not started to be executed among n memory access instructions to the pipeline, and the execution timing of the memory access instructions that have not started to be executed lags behind the execution timing of the abnormal memory access instruction.

[0201] In some embodiments, the instruction execution module further includes a reorder cache, which is used to determine the actual execution timing of the memory access instruction in the pipeline. In the case of an exception in the memory access instruction executed by the pipeline, the reorder cache is also used to broadcast an abnormal execution signal and re-determine the actual execution timing for the memory access instruction that has not been executed in the pipeline.

[0202] In the instruction execution module provided in the embodiment of the present application, new logic is added to the reservation station to deal with the exceptions that occur during the execution of the merge instruction. From the above content, it can be seen that after the pipeline receives the merge instruction, it can determine the instruction content of the multiple selected memory access instructions based on the merge instruction, and execute n memory access instructions in one clock cycle. When a memory access instruction among the n memory access instructions fails to execute in the pipeline, the reservation station needs to re-transmit the memory access instructions that have not been executed in the n memory access instructions.

[0203] Optionally, the abnormal execution signal refers to a flash signal emitted by the reorder buffer. In the case where an exception occurs when the pipeline executes the first merge instruction, the reorder buffer broadcasts the abnormal execution signal. The abnormal execution signal is used to indicate that the memory access instruction in which the exception occurs is executed. For example, the abnormal execution information is used to characterize the sequence number of the abnormal memory access instruction among n memory access instructions.

[0204] For example, the first merge instruction is generated by fusing n memory access instructions, and the first merge instruction of the pipeline actually executes n memory access instructions. When the t-th memory access instruction among the n memory access instructions emits an exception during pipeline execution, the pipeline stops executing the memory access instructions that have not been executed in the n memory access instructions, and the reorder buffer broadcasts an abnormal execution signal related to the t-th memory access instruction. That is, the t-th memory access instruction among the n instructions is an abnormal memory access instruction. Exemplarily, the abnormal memory access instruction is a memory access instruction with an abnormal memory access address.

[0205] For example, when the instruction merging condition does not include a stable offset between the memory access addresses of memory access instructions that are executed sequentially adjacent, the n memory access instructions may include a selected memory access instruction with an abnormal memory access address, so that the pipeline cannot successfully execute the memory access instruction. At this time, the newly added execution logic in the reservation station needs to start working.

[0206] Optionally, the reservation station records the abnormal execution signal sent by the reorder cache, and determines the abnormal memory access instruction from the n memory access instructions based on the abnormal execution information; then the reservation station retransmits the memory access instructions that have not started to be executed among the n memory access instructions to the pipeline, and the execution timing of the memory access instructions that have not started to be executed lags behind the execution timing of the abnormal memory access instruction.

[0207] Exemplarily, the memory access instruction that has not started execution refers to the memory access instruction whose execution timing lags behind the execution timing of the abnormal memory access instruction among the n memory access instructions. For example, if the abnormal memory access instruction is the tth memory access instruction among the n memory access instructions, then the memory access instruction that has not started execution indicates the memory access instructions from the t+1th to the nth memory access instructions among the n memory access instructions. It should be noted that the abnormal memory access instruction cannot be regarded as the memory access instruction that has not started execution.

[0208] Optionally, the reservation station sends the memory access instructions that have not started execution to the pipeline one by one. For example, the reservation station sends one memory access instruction that has not started execution using one micro-instruction bandwidth.

[0209] Optionally, the reservation station merges multiple memory access instructions that have not started to be executed into one instruction to obtain a second merged instruction, and the reservation station sends the second merged instruction to the pipeline.

[0210] By adding new logic to the reservation station, the failure of abnormal memory access instructions to execute in the pipeline can be handled, which helps to maintain the execution order of memory access instructions in the pipeline.

[0211] In some embodiments, the reservation station includes: an exception search unit and an instruction re-fusion unit; the exception search unit is used to determine an abnormal memory access instruction from n memory access instructions based on an abnormal execution signal; the instruction re-fusion unit is used to fuse at least two memory access instructions that have not started execution among the n memory access instructions into one instruction to obtain a second merged instruction, the effect of the second merged instruction is equivalent to the effect of the at least two memory access instructions that have not started execution, and transmitting the second merged instruction to the pipeline occupies one microinstruction bandwidth.

[0212] The reservation station then issues a second merge instruction to the pipeline.

[0213] Optionally, the exception search unit is used to determine the abnormal memory access instruction from the n memory access instructions according to the instruction sequence number included in the abnormal execution signal, and determine the instruction content of at least one memory access instruction that has not started to be executed according to the first merge instruction.

[0214] Exemplarily, the exception search unit determines the sequence number of the fourth memory access instruction according to the instruction sequence number included in the abnormal execution signal, and determines the instruction content of the fourth memory access instruction according to the first merge instruction. The fourth memory access instruction is the earliest one among the multiple memory access instructions that have not started execution.

[0215] Optionally, the structure of the instruction re-fusion unit is similar to the above instruction fusion unit, and please refer to the above embodiment for details, which will not be described in detail here. Exemplarily, the execution timing of at least two memory access instructions that have not started to be executed is continuous.

[0216] It can be seen from the above embodiments that the instruction content of the first merge instruction includes basic operation information, register information and memory access address. The instruction content of the fourth memory access instruction can be calculated based on the above three information and the sequence number of the fourth memory access instruction in n memory access instructions.

[0217] Subsequently, the instruction re-fusion unit uses the fourth memory access instruction as the basic memory access instruction among at least two memory access instructions that have not yet started execution, and determines the register information and memory access address information of the second merged instruction based on the register information and memory access address information of the first memory access instruction to obtain the instruction content of the second merged instruction.

[0218] Figure 7 The figure is a schematic diagram of an instruction re-issuing process provided by an exemplary embodiment of the present application.

[0219] In this embodiment, n is equal to 6, and the n memory access instructions include memory access instruction 1, memory access instruction 2, direction instruction 3, memory access instruction 4, memory access instruction 5 and memory access instruction 6 in order of execution from earliest to latest. The dispatch queue merges the 6 memory access instructions into one instruction to obtain the first merge instruction, and then transmits the first merge instruction to the load pipeline through the load reservation station. After receiving the first merge instruction, the load pipeline determines the instruction content of the n memory access instructions according to the first merge instruction, and starts execution from the basic memory access instruction (memory access instruction 1) among the n memory access instructions within a certain clock cycle. If the memory access instruction 4 is executed abnormally in the load pipeline, the load pipeline notifies the reorder cache that the memory access instruction 4 transmits an exception, and the reorder cache broadcasts an abnormal execution signal. The load reservation station determines that the memory access instruction 4 is executed abnormally in the pipeline according to the abnormal execution signal, and merges the memory access instruction 5 and the memory access instruction 6 into the second merge instruction, and the load reservation station transmits the second merge instruction to the load pipeline.

[0220] By performing secondary packaging on multiple memory access instructions that have not yet started execution, it helps to reduce the clock cycles for re-issuing the multiple memory access instructions that have not yet started execution to the pipeline, so that the secondary packaging of the multiple memory access instructions that have not yet started execution can be completed within one clock cycle of the pipeline. In the event of an exception in the execution of the memory access instruction value, it helps to ensure the execution efficiency of the pipeline for the memory access instruction.

[0221] Figure 8 The figure is a schematic diagram of an instruction re-issuing process provided by an exemplary embodiment of the present application.

[0222] In this embodiment, n is equal to 6, and the n memory access instructions include: memory access instruction 1, memory access instruction 2, direction instruction 3, memory access instruction 4, memory access instruction 5 and memory access instruction 6 according to the execution sequence from earliest to latest. The dispatch queue merges the 6 memory access instructions into one instruction to obtain the first merge instruction, and then transmits the first merge instruction to the load pipeline through the load reservation station. After receiving the first merge instruction, the load pipeline determines the instruction content of the n memory access instructions according to the first merge instruction, and starts to execute from the basic memory access instruction (memory access instruction 1) among the n memory access instructions within a certain clock cycle. If the memory access instruction 4 is executed abnormally in the load pipeline, the load pipeline notifies the reorder cache that the memory access instruction 4 transmits an abnormality, and the reorder cache broadcasts an abnormal execution signal. The load reservation station determines that the memory access instruction 4 is executed abnormally in the pipeline according to the abnormal execution signal, and determines that the memory access instructions that have not started to be executed among the n memory access instructions include: memory access instruction 5 and memory access instruction 6. The load reservation station transmits memory access instruction 5 and memory access instruction 6 to the load pipeline respectively.

[0223] Although memory access instruction 5 and memory access instruction 6 are not merged again in this embodiment, since the memory access instruction 1, memory access instruction 2 and memory access instruction 3 of the first merged instruction have been executed in the same clock cycle, compared with not compressing and packaging the memory access instructions, n memory access instructions are issued separately at one time, which shortens the clock cycles consumed by the pipeline to execute memory access instruction 1, memory access instruction 2 and memory access instruction 3.

[0224] In some embodiments, the reservation station also includes a second buffer, which is used to temporarily store the first merge instruction and other memory access instructions except n memory access instructions in at least one candidate memory access instruction; each entry in the second buffer is used to store the instruction content of a merge instruction, or the instruction content of another memory access instruction; the instruction content includes: instruction identification information, register label information, immediate value information and synchronous execution information, the instruction identification is used to represent the instruction type of the instruction stored in the entry, the register information is used to represent the physical register of the instruction stored in the entry, the memory access address information is used to represent the memory access address of the instruction stored in the entry, and the synchronous execution information is used to represent the number of memory access instructions executed synchronously in the pipeline.

[0225] Because the reservation station needs to store the first merge instruction before issuing the first merge instruction, the entry in the reservation station for storing instructions also needs to be modified accordingly.

[0226] In some embodiments, the entries in the second buffer are used to store instruction types including: single memory access instruction, first merge instruction, second merge instruction. Table 6 is a schematic table of the format of entries in a reservation station provided by an exemplary embodiment of the present application.

[0227] Table 6 Format of entries in the reservation station

[0228] Instruction identification information Register Information Immediate information Synchronous execution information

[0229] Since multiple memory access instructions are merged into one merged instruction (including the first merged instruction and the second merged instruction), the merged instruction only occupies one entry in the reservation station. Therefore, the entry in the reservation station needs to adapt to the instruction content of the merged instruction.

[0230] For each entry in the second buffer, the entry includes instruction identification information (Opcode), register number information, immediate value information and synchronous execution information. Optionally, the instruction identification information is also used to represent the instruction identification of the instruction stored in the entry, and the instruction identification can be the sequence number of the memory access instruction in the instruction stream.

[0231] Optionally, the register number information of the merged instruction includes the number of the physical register of the basic memory access instruction corresponding to the merged instruction, and the register information of the merged instruction. Optionally, the immediate value information of the merged instruction includes the memory access address of the basic memory access instruction corresponding to the merged instruction, and the memory access address information of the merged instruction.

[0232] Among them, the register label information needs to be expanded. For example, multiple bits are added to the bit field (p80) of the register information to encode the physical register labels of n memory access instructions. For example, 16 bits are added to the bit field of the register information. The immediate value information needs to be expanded, such as adding 3 bits to the bit field of the immediate value information to encode the difference between n memory access addresses. The synchronous execution information also needs to be expanded, such as adding 15 bits to the bit field of the synchronous execution information to encode up to 16 instructions to be executed simultaneously.

[0233] Exemplarily, for an entry storing a memory access instruction, a zero padding operation is performed on the high bits of the bit fields of each information in the entry to ensure that the memory access instruction and the merge instruction have the same format in the entry.

[0234] By adjusting the format of the entries in the second buffer, the entries in the adjusted second buffer can correctly record the merge instruction.

[0235] In some embodiments, a merge instruction can retrieve data (64B) of a cache line at one time, that is, the bandwidth of the data processing stage in the instruction execution module to access the data cache is widened to 64B, so as to meet the data access requirements when the pipeline executes multiple memory access instructions in the merge instruction in parallel in one clock cycle.

[0236] In some embodiments, the instruction execution module also includes: a write-back cache and a write-back buffer, which are used to write the execution result of the instruction to be written back to the general register through a first write-back path, and the first write-back path is adapted to the pipeline to execute a single memory access instruction in one clock cycle; the write-back buffer is also used to write the execution results of different instructions to be written back to the general register through the first write-back path and the second write-back path when there is a second write-back path between the write-back buffer and the general register, and the second write-back path is adapted to the execution speed change generated by the pipeline based on the first merge instruction; wherein the instruction to be written back refers to the memory access instruction that has been executed in the pipeline.

[0237] Optionally, after the memory access instruction is executed in the pipeline, the pipeline transfers the execution result of the instruction to be written back to the write-back buffer, and the write-back buffer writes the execution result of the instruction to be written back to the general register. In the related art, the pipeline only executes one memory access instruction in one clock cycle, so the write-back pressure of the write-back buffer is relatively small. Optionally, there is a first write-back path between the write-back buffer and the general register. The first write-back path is adapted to the speed at which the pipeline generates an execution result of the instruction to be written back in one clock cycle. In other words, the first write-back path refers to the write-back path set between the write-back buffer and the general register before the instruction execution device proposed in the present application appears.

[0238] The instruction to be written back refers to a memory access instruction that has been executed in the pipeline. Optionally, the instruction to be written back includes: any one of the n memory access instructions that has been executed by the pipeline. Since the pipeline can execute multiple memory access instructions in one clock cycle according to the first merge instruction. That is, in one clock cycle, the pipeline generates n execution results of the instructions to be written back, resulting in a possible blockage when writing these execution results into the general register.

[0239] In one example, the instruction execution module writes the instructions to be written back into the general register one by one according to the first write-back path that has been established between the write-back buffer and the general register. That is, in the instruction execution module provided by the present application, there is no need to change the data path between the write-back buffer and the general register, and the write-back register writes the execution results of each instruction to be written back into the general register according to the order in which each instruction to be written back is executed in the pipeline.

[0240] The second write-back path refers to a newly added write-back path between the write-back buffer and the general register in order to improve the efficiency of pipeline execution of memory access instructions. Optionally, the write-back processes of the first write-back path and the second write-back path do not interfere with each other.

[0241] In another example, when a second write-back path is added between the write-back buffer and the general register, the instruction execution module can use the first write-back path and the second write-back path at the same time to write the execution results of multiple instructions to be written back to the general register in parallel, thereby improving the efficiency of writing back. This setting helps to reduce the occurrence of blocking.

[0242] In some embodiments, the instruction execution module also includes a write-back buffer and a buffer bypass network, the write-back buffer is coupled to the buffer bypass network, and the buffer bypass network is coupled to the read port of the pipeline; the buffer bypass network is used to transmit the execution result of the instruction to be written back to the read port of the pipeline before the execution result of the instruction to be written back is written back to the general register, and the instruction to be written back refers to a memory access instruction executed in the pipeline.

[0243] For example, when an execution unit in the pipeline needs to use the execution result of the instruction to be written back, but the execution result of the instruction to be written back is still queued to be written back to the general register, the execution unit obtains the execution result of the instruction to be written back from the write-back buffer through the register bypass network. This setting helps to reduce the clock cycles that the execution unit needs to wait for data to be obtained, and helps to improve the execution efficiency of instructions.

[0244] The following is an example to introduce the instruction execution module.

[0245] The instruction execution module includes: dispatch queue, reservation station, pipeline, and write-back register.

[0246] A dispatch queue is used to store at least one memory access instruction to be executed; n memory access instructions are selected from the at least one memory access instruction to be executed; the n memory access instructions are merged into one instruction to obtain a first merged instruction, and the effect of the first merged instruction is equivalent to the effect of the n memory access instructions.

[0247] Exemplarily, the maximum value of n is equal to 6, and the minimum value is equal to 2.

[0248] Optionally, the dispatch queue includes: a first buffer and an instruction fusion unit; the first buffer is used to store at least one memory access instruction to be executed; the instruction fusion unit is used to select n memory access instructions with continuous execution sequence from at least one memory access instruction to be executed based on an instruction merging condition as the n memory access instructions, and the instruction type includes at least one of the following: a load instruction and a store instruction; the instruction fusion unit is also used to fuse the n memory access instructions into one instruction according to the instruction contents of the n memory access instructions to obtain a first merged instruction.

[0249] Exemplarily, among the n memory access instructions, there is a stable offset between the memory access addresses of any two memory access instructions that are executed adjacently in timing.

[0250] In some embodiments, the instruction content of the first merge instruction includes: basic operation information, register information and memory access address information.

[0251] The basic operation information includes the instruction content of the basic memory access instruction among the n memory access instructions. The register information is represented by (n-1)*k bits, k=ceil(log2s), ceil() represents rounding up, s is the total number of entries in the first buffer included in the dispatch queue for storing memory access instructions, and the k bits corresponding to the selected memory access instruction in the register information are used to represent the label of the physical register of the memory access instruction. The selected memory access instruction refers to the memory access instruction other than the basic memory access instruction among the n memory access instructions. The memory access address information includes: direction information and offset value; direction information is used to represent the memory access address of the selected memory access instruction, relative to the offset direction of the memory access address of the basic memory access instruction, the offset direction includes at least one of the following: left offset, right offset, the selected memory access instruction refers to the memory access instruction other than the basic memory access instruction among the n memory access instructions; offset value is used to represent the offset between the memory access addresses of any two memory access instructions with adjacent execution timing among the n memory access instructions.

[0252] a reservation station for issuing a first merge instruction to the pipeline using a microinstruction bandwidth;

[0253] A pipeline is used to execute a first merge instruction.

[0254] The reservation station is also used to determine the abnormal memory access instruction based on the abnormal execution signal sent from the reorder cache, the abnormal execution signal is used to indicate the abnormal memory access instruction in the first merge instruction, and the abnormal memory access instruction is not successfully executed in the pipeline; re-transmit the memory access instruction that has not started to be executed among the n memory access instructions to the pipeline, and the execution timing of the memory access instruction that has not started to be executed lags behind the execution timing of the abnormal memory access instruction.

[0255] A write-back buffer, used to write the execution result of the instruction to be written back to the general register through a first write-back path, the first write-back path being adapted to the pipeline executing a single memory access instruction in one clock cycle; the write-back buffer is also used to write the execution results of different instructions to be written back to the general register through the first write-back path and the second write-back path respectively when there is a second write-back path between the write-back buffer and the general register, the second write-back path being adapted to the execution speed change of the pipeline generated based on the first merge instruction;

[0256] In some embodiments, the write-back buffer is coupled to a buffer bypass network, and the buffer bypass network is coupled to a pipeline read port; the buffer bypass network is used to transmit the execution result of the instruction to be written back to the pipeline read port before the execution result of the instruction to be written back is written back to the general register, and the instruction to be written back refers to the memory access instruction executed in the pipeline. The instruction execution module provided by the present application helps to improve the execution efficiency of the memory access instruction, thereby improving the performance of the processor.

[0257] It should be noted that in this embodiment, "ld" and "Ld" have the same meaning, both indicating that the instruction type of the memory access instruction is a load instruction. In the above embodiment, the load instruction is used as an example to illustrate the scheme. In fact, the memory access instruction can also be a storage instruction, which is not repeated here.

[0258] The following is an embodiment of the method of the present application. For details not disclosed in the embodiment of the method of the present application, please refer to the embodiment of the instruction execution module of the present application. Fig. 9 This is a flowchart of an instruction processing method applied to an instruction execution module provided by an exemplary embodiment of the present application. The instruction execution module includes: an allocation queue and a pipeline; the instruction processing method applied to the instruction execution module includes the following steps:

[0259] Step 910: The dispatch queue stores at least one memory access instruction to be executed.

[0260] Step 920: The dispatch queue selects n memory access instructions from at least one memory access instruction to be executed, where n is an integer greater than 1.

[0261] Step 930 , the dispatch queue merges the n memory access instructions into one instruction to obtain a first merged instruction, and the effect of the first merged instruction is equivalent to the effect of the n memory access instructions.

[0262] Step 940: The pipeline executes the first merge instruction.

[0263] In some embodiments, a queue is allocated, comprising: a first buffer and an instruction fusion unit; the first buffer stores at least one memory access instruction to be executed; step 920 comprises: the instruction fusion unit selects n memory access instructions with continuous execution sequence from at least one memory access instruction to be executed based on an instruction merging condition as n memory access instructions, wherein the instruction merging condition comprises that the n memory access instructions have the same instruction type, and the instruction type comprises at least one of the following: a load instruction, a store instruction; step 930 comprises: the instruction fusion unit fuses the n memory access instructions according to the instruction contents of the n memory access instructions to obtain a first merged instruction.

[0264] In some embodiments, the instruction merging condition further includes at least one of the following: the labels of the physical registers of the n memory access instructions are continuous; among the n memory access instructions, there is a stable offset between the memory access addresses of any two memory access instructions with adjacent execution sequences.

[0265] In some embodiments, the instruction fusion unit includes: at least one level of comparator and an instruction generator; step 910 includes, sub-step 912, for the first level comparator in the at least one level of comparator, the kth comparator in the first level comparator, according to the memory access instructions respectively stored in the 2kth entry and the 2k+1th entry in the first buffer, determining the comparison result of the kth comparator, wherein the entries of the first buffer are used to store memory access instructions, k is a positive integer less than or equal to 0.5*s, and s is the total number of entries included in the first buffer , the comparison result of the kth comparator is used to characterize the memory access instructions stored in the 2kth entry and the 2k+1th entry respectively, and the compliance with the instruction merging condition; if there is an i-th level comparator in at least one level of comparators, i is a positive integer greater than 1, then the j-th comparator in the i-th level comparator determines the comparison result of the j-th comparator according to the comparison result of the 2j-1th comparator in the i-1th level comparator and the comparison result of the 2jth comparator, and the comparison result of the j-th comparator is used to characterize the (j-1)*2th comparator in the first buffer. i-1 +1 entry to j*2 i-1 The memory access instructions stored in the entries are respectively compared to see whether the instruction merging condition is met; in sub-step 914, the instruction generator selects n memory access instructions from at least one memory access instruction according to the comparison results of at least one level of comparator, and merges the n memory access instructions according to the instruction contents of the n memory access instructions to obtain a first merged instruction.

[0266] In some embodiments, the instruction content of the first merged instruction includes: basic operation information, used to indicate the basic memory access instruction with the earliest execution timing among n memory access instructions; register information, used to represent the physical registers of the n memory access instructions, and the physical registers of the memory access instructions are used to record the memory access data corresponding to the memory access instructions during the execution of the memory access instructions; memory access address information, used to represent the memory access addresses of the n memory access instructions, and the memory access addresses of the memory access instructions are used to store the memory access data indicated by the memory access instructions, or to provide the memory access data for the memory access instructions to read.

[0267] In some embodiments, register information is represented by m bits, different bits among the m bits correspond to different physical registers, one bit among the m bits corresponding to the physical register of the selected memory access instruction represents an occupied state, and the other bits among the m bits represent an idle state. The selected memory access instruction refers to a memory access instruction among the n memory access instructions except the basic memory access instruction.

[0268] In some embodiments, the register information is represented by (n-1)*k bits, k=ceil(log2s), ceil() represents rounding up, s is the total number of entries in the first buffer included in the allocation queue for storing memory access instructions, the k bits corresponding to the selected memory access instruction in the register information are used to represent the label of the physical register of the memory access instruction, and the selected memory access instruction refers to the memory access instruction other than the basic memory access instruction among the n memory access instructions.

[0269] In some embodiments, the memory access address information includes offset information, and the offset information is used to characterize the relative offset between the memory access addresses of n memory access instructions.

[0270] In some embodiments, the offset information includes direction information and an offset value; the direction information is used to characterize the offset direction of the memory access address of the selected memory access instruction relative to the memory access address of the basic memory access instruction, and the offset direction includes at least one of the following: left offset, right offset, and the selected memory access instruction refers to the memory access instruction other than the basic memory access instruction among the n memory access instructions; the offset value is used to characterize the offset between the memory access addresses of any two memory access instructions with adjacent execution timing among the n memory access instructions.

[0271] Fig.10 It is a schematic diagram of an instruction execution method applied to an instruction execution module provided by another exemplary embodiment of the present application.

[0272] In some embodiments, the instruction execution module further includes: a reservation station; the reservation station uses a microinstruction bandwidth to send a first merge instruction to the pipeline; Fig. 9 The method shown also includes: step 950, the reservation station determines the abnormal memory access instruction based on the abnormal execution signal sent from the reorder cache, the abnormal execution signal is used to indicate the abnormal memory access instruction in the first merge instruction, and the abnormal memory access instruction is not successfully executed in the pipeline; step 950, the reservation station re-transmits the memory access instruction that has not started to be executed among the n memory access instructions to the pipeline, and the execution timing of the memory access instruction that has not started to be executed lags behind the execution timing of the abnormal memory access instruction.

[0273] In some embodiments, the reservation station includes: an exception search unit and an instruction re-fusion unit; step 950 includes sub-step 952, the exception search unit determines the abnormal memory access instruction from n memory access instructions based on the abnormal execution signal; sub-step 956, the instruction re-fusion unit fuses at least two memory access instructions that have not started execution among the n memory access instructions to obtain a second merged instruction, the effect of the second merged instruction is equivalent to the effect of the at least two memory access instructions that have not started execution, and transmitting the second merged instruction to the pipeline occupies one microinstruction bandwidth.

[0274] In some embodiments, the reservation station also includes a second buffer, which temporarily stores the first merge instruction and other memory access instructions except n memory access instructions in at least one candidate memory access instruction; each entry in the second buffer is used to store the instruction content of a merge instruction, or the instruction content of another memory access instruction; the instruction content includes: instruction identification information, register label information, immediate number information and synchronous execution information, the instruction identification is used to represent the instruction type of the instruction stored in the entry, the register label information is used to represent the physical register of the instruction stored in the entry, the immediate number information is used to represent the memory access address of the instruction stored in the entry, and the synchronous execution information is used to represent the number of memory access instructions executed synchronously in the pipeline.

[0275] In some embodiments, the instruction execution module further includes: a write-back buffer; Fig. 9 The method shown also includes step 960, wherein the write-back buffer writes the execution result of the instruction to be written back to the general register through the first write-back path, and the first write-back path is adapted to the pipeline to execute a single memory access instruction in one clock cycle; in the case where there is a second write-back path between the write-back buffer and the general register, the write-back buffer writes the execution results of different instructions to be written back to the general register through the first write-back path and the second write-back path, respectively, and the second write-back path is adapted to the execution speed change generated by the pipeline based on the first merge instruction; wherein the instruction to be written back refers to the memory access instruction that has been executed in the pipeline.

[0276] In some embodiments, the instruction execution module further includes a write-back buffer and a buffer bypass network, the write-back buffer is coupled to the buffer bypass network, and the buffer bypass network is coupled to the read port of the pipeline; Fig. 9 The method shown also includes step 970, where the buffer bypass network transmits the execution result of the instruction to be written back to the read port of the pipeline before the execution result of the instruction to be written back is written back to the general register. The instruction to be written back refers to the memory access instruction executed in the pipeline.

[0277] For the specific content of this embodiment, please refer to the above embodiment, which will not be repeated here.

[0278] The embodiment of the present application also provides a chip, which includes the instruction execution module as described above. Optionally, the chip includes an instruction execution module and a memory. The chip is a processor chip and can be integrated in the processor to complete the instruction execution method.

[0279] The embodiment of the present application also provides an electronic device, which includes the instruction execution module as described above. Optionally, the electronic device includes a chip, which includes a memory and an instruction execution module. The instruction execution module is used to execute instructions using the solution provided in the above embodiment to complete the process of instruction fusion and execution of the merged instruction.

[0280] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0281] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent switching, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An instruction execution module applied to a processor, characterized in that: The instruction execution module includes: a dispatch queue and a pipeline; The dispatch queue is used to store at least one memory access instruction to be executed; select n memory access instructions from the at least one memory access instruction to be executed, where n is an integer greater than 1; merge the n memory access instructions into one instruction to obtain a first merged instruction, wherein the effect of the first merged instruction is equivalent to the effect of the n memory access instructions; The pipeline is used to execute the first merge instruction.

2. The instruction execution module according to claim 1, characterized in that: The dispatch queue includes: a first buffer and an instruction fusion unit; The first buffer is used to store the at least one memory access instruction to be executed; The instruction fusion unit is used to select n memory access instructions with continuous execution time sequence from the at least one memory access instruction to be executed as the n memory access instructions based on an instruction merging condition, wherein the instruction merging condition includes that the n memory access instructions have the same instruction type, and the instruction type includes at least one of the following: a load instruction and a store instruction; The instruction fusion unit is further used to fuse the n memory access instructions into one instruction according to the instruction contents of the n memory access instructions to obtain the first merged instruction.

3. The instruction execution module according to claim 2, characterized in that: The instruction merging condition also includes at least one of the following: The labels of the physical registers of the n memory access instructions are continuous; Among the n memory access instructions, there is a stable offset between the memory access addresses of any two memory access instructions that are executed adjacently in timing.

4. The instruction execution module according to claim 2, characterized in that: The instruction fusion unit includes: at least one level of comparator and an instruction generator; For a first-level comparator in the at least one-level comparator, a k-th comparator in the first-level comparator is used to determine a comparison result of the k-th comparator according to memory access instructions respectively stored in a 2k-th entry and a 2k+1-th entry in the first buffer, wherein the entry of the first buffer is used to store the memory access instruction, k is a positive integer less than or equal to 0.5*s, s is the total number of entries included in the first buffer, and the comparison result of the k-th comparator is used to characterize whether the memory access instructions respectively stored in the 2k-th entry and the 2k+1-th entry meet the instruction merging condition; If there is an i-th comparator in the at least one level of comparators, i is a positive integer greater than 1, then the j-th comparator in the i-th level of comparators is used to determine the comparison result of the j-th comparator according to the comparison result of the 2j-1-th comparator in the i-1-th level of comparators and the comparison result of the 2j-th comparator, and the comparison result of the j-th comparator is used to characterize the (j-1)*2 i-1 +1 entry to j*2 i-1 The memory access instructions respectively stored in the entries and the compliance of the instruction merging condition; The instruction generator is used to select the n memory access instructions from the at least one memory access instruction according to the comparison results of the at least one level of comparator, and merge the n memory access instructions according to the instruction contents of the n memory access instructions to obtain the first merged instruction.

5. The instruction execution module according to claim 1, characterized in that: The content of the first merge instruction includes: Basic operation information, used to indicate a basic memory access instruction among the n memory access instructions, wherein the basic memory access instruction refers to a memory access instruction with the earliest execution sequence among the n memory access instructions; Register information, used to characterize the physical registers of the n memory access instructions, the physical registers of the memory access instructions being used to record memory access data corresponding to the memory access instructions during the execution of the memory access instructions; The memory access address information is used to represent the memory access addresses of the n memory access instructions, and the memory access addresses of the memory access instructions are used to store the memory access data indicated by the memory access instructions to be stored, or to provide the memory access data for the memory access instructions to read.

6. The instruction execution module according to claim 5, characterized in that: The register information is represented by m bits, different bits among the m bits correspond to different physical registers, one bit among the m bits corresponding to the physical register of the selected memory access instruction represents an occupied state, and the other bits among the m bits represent an idle state, and the selected memory access instruction refers to the memory access instruction among the n memory access instructions except the basic memory access instruction.

7. The instruction execution module according to claim 5, characterized in that: The register information is represented by (n-1)*k bits, k=ceil(log2s), ceil() represents rounding up, s is the total number of entries in the first buffer included in the dispatch queue for storing the memory access instructions, and the k bits corresponding to the selected memory access instruction in the register information are used to represent the label of the physical register of the memory access instruction. The selected memory access instruction refers to the memory access instruction among the n memory access instructions except the basic memory access instruction.

8. The instruction execution module according to claim 5, characterized in that: The memory access address information includes offset information, and the offset information is used to characterize the relative offset between the memory access addresses of the n memory access instructions.

9. The instruction execution module according to claim 8, characterized in that: The offset information includes direction information and an offset value; The direction information is used to represent the memory access address of the selected memory access instruction, relative to the offset direction of the memory access address of the basic memory access instruction, the offset direction including at least one of the following: left offset, right offset, the selected memory access instruction refers to the memory access instruction other than the basic memory access instruction among the n memory access instructions; The offset value is used to represent the offset between the memory access addresses of any two memory access instructions with adjacent execution sequences among the n memory access instructions.

10. The instruction execution module according to claim 1, characterized in that: The instruction execution module further includes: a reservation station; The reservation station is used to issue the first merge instruction to the pipeline using a microinstruction bandwidth; The reservation station is further used to determine an abnormal memory access instruction based on an abnormal execution signal sent from the reorder cache, wherein the abnormal execution signal is used to indicate an abnormal memory access instruction in the first merge instruction, and the abnormal memory access instruction is not successfully executed in the pipeline; and retransmit the memory access instruction that has not started to be executed among the n memory access instructions to the pipeline, and the execution timing of the memory access instruction that has not started to be executed lags behind the execution timing of the abnormal memory access instruction.

11. The instruction execution module according to claim 10, characterized in that: The reservation station includes: an exception search unit and an instruction re-fusion unit; The abnormality search unit is used to determine the abnormal memory access instruction from the n memory access instructions based on the abnormal execution signal; The instruction re-fusion unit is used to fuse at least two memory access instructions that have not started to be executed among the n memory access instructions into one instruction to obtain a second merged instruction. The effect of the second merged instruction is equivalent to the effect of the at least two memory access instructions that have not started to be executed. Sending the second merged instruction to the pipeline occupies one of the microinstruction bandwidths.

12. The instruction execution module according to claim 10, characterized in that: The reservation station further includes a second buffer, the second buffer being used to temporarily store the first merge instruction and other memory access instructions among the at least one candidate memory access instruction except the n memory access instructions; Each entry in the second buffer is used to store the instruction content of a merged instruction, or the instruction content of one of the other memory access instructions; the instruction content includes: instruction identification information, register label information, immediate number information and synchronous execution information, the instruction identification is used to represent the instruction type of the instruction stored in the entry, the register label information is used to represent the physical register of the instruction stored in the entry, the immediate number information is used to represent the memory access address of the instruction stored in the entry, and the synchronous execution information is used to represent the number of memory access instructions executed synchronously in the pipeline.

13. The instruction execution module according to claim 1, characterized in that: The instruction execution module also includes: a write-back buffer; The write-back buffer is used to write the execution result of the instruction to be written back to the general register through a first write-back path, and the first write-back path is adapted to the pipeline to execute a single memory access instruction in one clock cycle; The write-back buffer is further configured to, when a second write-back path exists between the write-back buffer and the general register, write back execution results of different instructions to be written back to the general register through the first write-back path and the second write-back path, respectively, the second write-back path being adapted to an execution speed change of the pipeline generated based on the first merge instruction; The to-be-written-back instruction refers to a memory access instruction that has been executed in the pipeline.

14. The instruction execution module according to claim 1, characterized in that: The instruction execution module further includes a write-back buffer and a buffer bypass network, wherein the write-back buffer is coupled to the buffer bypass network, and the buffer bypass network is coupled to the read port of the pipeline; The buffer bypass network is used to transmit the execution result of the instruction to be written back to the read port of the pipeline before the execution result of the instruction to be written back is written back to the general register. The instruction to be written back refers to the memory access instruction executed in the pipeline.

15. A chip, characterized in that: The chip includes a memory and an instruction execution module as described in any one of claims 1 to 14.

16. An electronic device, characterized in that: The electronic device comprises a processor, and the processor comprises the instruction execution module as described in any one of claims 1 to 14.

17. A command execution method applied to a command execution module, characterized in that: The instruction execution module includes: a dispatch queue and a pipeline, and the method includes: The dispatch queue stores at least one memory access instruction to be executed; The dispatch queue selects n memory access instructions from the at least one memory access instruction to be executed, where n is an integer greater than 1; The dispatch queue merges the n memory access instructions into one instruction to obtain a first merged instruction, wherein the effect of the first merged instruction is equivalent to the effect of the n memory access instructions; The pipeline executes the first merge instruction.

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