Method for judging PCIe fault position, server and electronic equipment

Abstract

The embodiment of the invention provides a method for judging a PCIe fault position, a server and electronic equipment. In the embodiment of the invention, firstly, the obtained PCIe tree structure information is sent to the BMC through the BIOS so as to be subsequently used for fault positioning; and then the BIOS reports the PCIe equipment fault signal to the BMC when detecting the PCIe equipment fault signal, so that the BMC determines a target PCIe link where the target PCIe equipment is located in the PCIe tree structure based on BDF information of the target PCIe equipment indicated by the PCIe equipment fault signal and PCIe tree structure information, and thus the fault PCIe equipment is positioned based on AER register information of all PCIe equipment on the target PCIe link. According to the method and the device, the situation that fault analysis is carried out only through the AER register information of the PCIe device which reports the fault, so that the PCIe device which actually fails is difficult to position can be avoided, and the accuracy of PCIe fault position positioning is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method, server, and electronic device for determining a PCIe fault location. Background Art

[0002] With the continuous development of technology, the number of high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) devices configured in current servers is gradually increasing, and the management and maintenance of these PCIe devices are becoming more and more important.

[0003] In actual applications, the baseboard management controller (BMC) only collects the Advanced Error Reporting (AER) register information of the PCIe device that reports the fault. However, in fact, the PCIe device that reports the fault is not necessarily the PCIe device that actually fails, but may be another PCIe device. In this case, since the BMC only records the AER register information of the PCIe device that reports the fault, it will be difficult to locate the PCIe device that actually fails. Summary of the invention

[0004] In view of this, the present application provides a method, a server, and an electronic device for determining a PCIe fault location to improve the accuracy of locating a PCIe fault location.

[0005] The present application embodiment provides a method for determining a PCIe fault location, the method being applied to a server, the method comprising:

[0006] A high-speed serial computer expansion bus standard Peripheral Component Interconnect Express (PCIe) tree structure is constructed through a Basic Input Output System (BIOS) in a server, and PCIe tree structure information of the PCIe tree structure is sent to a BMC in the server; wherein the PCIe tree structure includes N nodes connected according to a hierarchical connection relationship, N is the number of PCIe devices deployed on the server, and N is greater than 1; each node in the PCIe tree structure is characterized by the bus number-device number-function number (BusNumber, Device Number, Function Number, BDF) information of one of the PCIe devices deployed on the server, and the BDF information of any PCIe device is used to uniquely identify the PCIe device; the hierarchical connection relationship means that, for any PCIe device, the PCIe device of the upper layer of the PCIe device refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device of the lower layer of the PCIe device refers to the PCIe device connected to the downstream port of the PCIe device;

[0007] When a PCIe device fault signal is detected by BIOS, the AER register information of the target PCIe device indicated by the PCIe device fault signal is sent to the BMC; the AER register information of any PCIe device refers to the information recorded in the AER register of the PCIe device, and the AER register information at least includes the BDF information of the PCIe device;

[0008] Determine a target PCIe link from a PCIe tree structure through the BMC based on the BDF information of the target PCIe device; the target PCIe link refers to the shortest path from a root node to a terminal node in the PCIe tree structure that passes through a node represented by the BDF information of the target PCIe device;

[0009] AER register information of all PCIe devices on the target PCIe link is obtained through the BMC, so as to locate the faulty PCIe device based on the obtained AER register information.

[0010] The embodiment of the present application further provides a server, which is deployed with a BMC, a BIOS, and N PCIe devices, where N is greater than 1;

[0011] BIOS is used to construct a PCIe tree structure, and send PCIe tree structure information of the PCIe tree structure to the BMC in the server; wherein the PCIe tree structure includes N nodes connected according to a hierarchical connection relationship; each node in the PCIe tree structure is represented by the BDF information of one of the PCIe devices deployed on the server, and the BDF information of any PCIe device is used to uniquely identify the PCIe device; the hierarchical connection relationship means that for any PCIe device, the PCIe device of the previous level of the PCIe device refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device of the next level of the PCIe device refers to the PCIe device connected to the downstream port of the PCIe device;

[0012] The BIOS is further configured to, when a PCIe device fault signal is detected, send AER register information of a target PCIe device indicated by the PCIe device fault signal to the BMC; the AER register information of any PCIe device refers to information recorded in the AER register of the PCIe device, and the AER register information at least includes BDF information of the PCIe device;

[0013] The BMC is used to determine a target PCIe link from a PCIe tree structure based on the BDF information of the target PCIe device; the target PCIe link refers to the shortest path from a root node to a terminal node in the PCIe tree structure that passes through a node represented by the BDF information of the target PCIe device;

[0014] The BMC is further used to obtain AER register information of all PCIe devices on the target PCIe link, so as to locate the faulty PCIe device based on the obtained AER register information.

[0015] The present application also provides an electronic device, the electronic device comprising:

[0016] Processor; and

[0017] A computer-readable storage medium stores computer program instructions, which, when executed by a processor, cause the processor to execute the steps of the above method.

[0018] An embodiment of the present application further provides a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes the steps in the above method.

[0019] It can be seen from the above technical scheme that in the embodiment of the present application, a PCIe tree structure is first constructed through BIOS and the PCIe tree structure information is sent to the BMC for subsequent use in locating the PCIe fault position; thereafter, when a PCIe device fault signal is detected through BIOS, the PCIe device fault signal is reported to the BMC so that the BMC determines the target PCIe link where the target PCIe device is located in the PCIe tree structure based on the BDF information and PCIe tree structure information of the target PCIe device indicated by the PCIe device fault signal. In this way, by locating the faulty PCIe device based on the AER register information of all PCIe devices on the target PCIe link, it is possible to avoid the situation where the actual faulty PCIe device is difficult to locate due to fault analysis only through the AER register information of the reported faulty PCIe device, thereby improving the accuracy of PCIe fault position positioning. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in the specification and constitute a part of this application, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

[0021] Figure 1 A flow chart of the method provided in an embodiment of the present application.

[0022] Figure 2 A schematic diagram of the PCIe tree structure provided in an embodiment of the present application.

[0023] Figure 3 Another method flow chart provided for an embodiment of the present application.

[0024] Figure 4 A schematic diagram of the server structure provided in an embodiment of the present application.

[0025] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application and to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings.

[0027] See also Figure 1 , Figure 1 A flow chart of a method provided in an embodiment of the present application. The method is applied to a server, which is deployed with at least BIOS, BMC, and N PCIe devices, where N is greater than 1.

[0028] like Figure 1 As shown, the process may include the following steps:

[0029] Step 101: construct a PCIe tree structure through the BIOS in the server, and send PCIe tree structure information of the PCIe tree structure to the BMC in the server.

[0030] In this embodiment, the PCIe tree structure refers to the topological structure of the PCIe system composed of N PCIe devices in the server. The PCIe tree structure includes N nodes connected according to a hierarchical connection relationship, as described above, where N is the number of PCIe devices deployed on the server. Each node in the PCIe tree structure is represented by the BDF information of one of the PCIe devices deployed on the server, and the BDF information of any PCIe device is used to uniquely identify the PCIe device.

[0031] In this embodiment, the above-mentioned hierarchical connection relationship means: for any PCIe device, the PCIe device of the upper level of the PCIe device refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device of the lower level of the PCIe device refers to the PCIe device connected to the downstream port of the PCIe device.

[0032] As an embodiment, there are many specific implementation methods for constructing the PCIe tree structure through the BIOS in the server in step 101, such as: first, traverse the configuration space of all PCIe devices on the server through the BIOS in the server to obtain the BDF information of each PCIe device from the configuration space of each PCIe device, and the physical connection relationship between each PCIe device and other connected PCIe devices; then, construct the PCIe tree structure based on the obtained BDF information of each PCIe device and the physical connection relationship between each PCIe device and other connected PCIe devices. Here, the physical connection relationship between any PCIe device and other connected PCIe devices refers to which port (such as upstream port or downstream port) of the PCIe device is connected to the other connected PCIe devices.

[0033] As an embodiment, the PCIe tree structure information of the PCIe tree structure is sent to the BMC in the server. In a specific implementation, for example, the constructed PCIe tree structure is encapsulated into a file in a setting file format (i.e., PCIe tree structure information) and sent to the BM in the server. The setting file format here can be, for example, a json format, etc., which is not specifically limited in this embodiment. In this embodiment, the PCIe tree structure information is sent to the BMC in the server for subsequent use in locating the faulty PCIe device.

[0034] Step 102: When the BIOS detects a PCIe device fault signal, the AER register information of the target PCIe device indicated by the PCIe device fault signal is sent to the BMC.

[0035] In this embodiment, the AER register information of any PCIe device refers to the information recorded in the AER register of the PCIe device. The AER register information includes at least the BDF information of the PCIe device. Among them, AER is a feature of the PCIe specification, which is used to improve the diagnosis and troubleshooting capabilities of PCIe devices when errors occur. AER allows PCIe devices to generate error reports when errors occur, such as the type of error, location information, and other related error details. The error report can be recorded and tracked through the log system of the operating system to assist management and maintenance personnel in diagnosing and troubleshooting errors of PCIe devices.

[0036] As an embodiment, the PCIe device fault signal is generated by one of the PCIe devices deployed on the server and sent to the BIOS when a data processing error event is detected. Based on this, the PCIe device fault signal at least includes the BDF information of the PCIe device that generates the PCIe device fault signal; based on this, the target PCIe device is the PCIe device that generates the PCIe device fault signal. As for how to detect the data processing error event, this embodiment does not make specific restrictions. For example, the PCIe device can determine that a data processing error event is detected when it detects the error of abnormal data transmission.

[0037] In this embodiment, as an embodiment, when a PCIe device detects an error, the corresponding error information is recorded in the AER register of the PCIe device, and then the PCIe device generates a hardware interrupt signal (i.e., a PCIe device fault signal) to notify the BIOS. The BIOS can obtain the BDF information of the PCIe device based on the mapping relationship between the interrupt vector indicated by the configured hardware interrupt signal and the BDF information. In other words, the PCIe device can be considered as the target PCIe device indicated by the PCIe device fault signal; then, the BIOS can obtain the AER register information of the PCIe device from the configuration space of the BDF information of the PCIe device based on the BDF information of the PCIe device and send it to the BMC. As for how to obtain the AER register information of the PCIe device from the configuration space of the BDF information of the PCIe device based on the BDF information of the PCIe device, the following will be described by example, and will not be repeated here.

[0038] Step 103: Determine the target PCIe link based on the BDF information and PCIe tree structure information of the target PCIe device through the BMC.

[0039] In this embodiment, based on the above description, the PCIe tree structure information indicates the BDF information of each PCIe device and the hierarchical connection relationship between each PCIe device. Based on this, the target PCIe link can be determined by the BMC based on the BDF information of the target PCIe device and the PCIe tree structure information. The target PCIe link here refers to the shortest path from the root node to the terminal node in the PCIe tree structure through the node represented by the BDF information of the target PCIe device. Among them, the root node in the PCIe tree structure refers to the PCIe device directly connected to the central processing unit (CPU) in the server among the N PCIe devices deployed on the server.

[0040] As an embodiment, the above-mentioned determination of the target PCIe link based on the BDF information and PCIe tree structure information of the target PCIe device by BMC can be specifically implemented as follows: firstly, at least one shortest path from the root node to the terminal node in the PCIe tree structure is obtained, and then, the shortest path from the root node to the terminal node that passes through the node represented by the BDF information of the target PCIe device is used as the target PCIe link. This embodiment can quickly determine the link where the target PCIe device is located by constructing a PCIe tree structure, thereby effectively reducing the time for searching for the PCIe devices to be collected and improving the efficiency of locating the faulty PCIe device.

[0041] For example, see Figure 2 The PCIe tree structure shown in the figure has two PCIe devices directly connected to the CPU, namely, PCIe devices corresponding to node 1 and node 2; Figure 2 In the example, the root nodes are node 1 and node 1, and the terminal nodes are node 7, node 8, node 10, and node 11; based on this, the shortest paths from the root node to the terminal node include: shortest path 1 consisting of node 1-node 3-node 7, shortest path 2 consisting of node 1-node 4-node 8, shortest path 3 consisting of node 1-node 4-node 9-node 11, shortest path 4 consisting of node 2-node 5, and shortest path 5 consisting of node 2-node 6-node 10, a total of 5 shortest paths.

[0042] like Figure 2As shown, assuming that node 4 is the node represented by the BDF information of the target PCIe device, then the shortest paths passing through node 4 in the five shortest paths in the PCIe tree structure include shortest path 2 and shortest path 3, that is, shortest path 2 and shortest path 3 are both target PCIe links. On this basis, all PCIe devices on the target PCIe link can be considered to refer to the PCIe devices corresponding to nodes 1, 4, 8, 9 and 11 respectively.

[0043] Step 104: Obtain AER register information of all PCIe devices on the target PCIe link through the BMC to locate the faulty PCIe device based on the obtained AER register information.

[0044] In this embodiment, when the BIOS detects a PCIe device fault signal, the target PCIe device indicated by the PCIe device fault signal (i.e., the PCIe device that generates the PCIe device fault signal) is not necessarily the PCIe device that actually fails, but may be other PCIe devices on the PCIe link (i.e., the target PCIe link) where the target PCIe device is located. Therefore, in order to ensure that the failed PCIe device can be accurately located, it is not necessary to obtain the AER register information of all PCIe devices in the server, and only the AER register information of all PCIe devices on the PCIe link where the target PCIe device is located needs to be obtained for location analysis of the failed PCIe device.

[0045] As for how to obtain the AER register information of all PCIe devices on the target PCIe link through the BMC in step 104, and how to locate the faulty PCIe device based on the obtained AER register information, the following will be described with examples and will not be repeated here.

[0046] So far, completed Figure 1 The process shown.

[0047] pass Figure 1It can be seen from the illustrated process that in the embodiment of the present application, a PCIe tree structure is first constructed through the BIOS and the PCIe tree structure information is sent to the BMC for subsequent use in locating the PCIe fault position; thereafter, when the BIOS detects a PCIe device fault signal, the PCIe device fault signal is reported to the BMC so that the BMC determines the target PCIe link where the target PCIe device is located in the PCIe tree structure based on the BDF information and PCIe tree structure information of the target PCIe device indicated by the PCIe device fault signal. In this way, by locating the faulty PCIe device based on the AER register information of all PCIe devices on the target PCIe link, it is possible to avoid the situation where the actual faulty PCIe device is difficult to locate due to fault analysis only through the AER register information of the reported faulty PCIe device, thereby improving the accuracy of PCIe fault location positioning.

[0048] The PCIe tree structure in step 101 is described below:

[0049] As an embodiment, the number of root nodes in the PCIe tree structure is determined by the channel width of the PCIe interface configured with the CPU of the server; wherein the channel width refers to the number of channels used for data transmission.

[0050] In this embodiment, there are many specific implementation methods for determining the number of root nodes in the above PCIe tree structure depending on the channel width of the PCIe interface configured with the server's CPU. For example, as an embodiment, the channel width of the PCIe interface configured with the server's CPU is first obtained as x, that is, the PCIe interface configured with the CPU includes x data transmission channels, wherein a PCIe device is configured to use y data transmission channels for data transmission. Based on this, it can be obtained that the number of PCIe devices that can be connected to the PCIe interface configured with the CPU is x / y, that is, the number of root nodes in the above PCIe tree structure is x / y (that is, the ratio of x to y).

[0051] For example, assuming that the channel width of the PCIe interface configured on the CPU of the server is 16, wherein a PCIe device is configured to use 2 data transmission channels for data transmission, then the number of root nodes in the PCIe tree structure is 16 / 2=8.

[0052] The following describes how to obtain the AER register information of all PCIe devices on the target PCIe link through the BMC in the above step 104:

[0053] As an embodiment, in step 104, the AER register information of all PCIe devices on the target PCIe link is obtained through the BMC. There are many ways to implement it in practice, for example, see Figure 3 As shown, the specific implementation may include the following steps:

[0054] Step 301: Obtain BDF information of all PCIe devices on a target PCIe link from PCIe tree structure information.

[0055] Step 302: for each BDF information obtained, obtain AER register information from the configuration space of the PCIe device corresponding to the BDF information based on the AER register address corresponding to the BDF information through a PCI configuration access interface for directly accessing the configuration space of the PCIe device.

[0056] In this embodiment, the PCI configuration access interface may refer to a PCI Cfg interface, which is not specifically limited in this embodiment.

[0057] In this embodiment, the AER register address corresponding to any BDF information is obtained from the configured AER register address-BDF information mapping relationship; wherein the AER register address refers to the address of the AER register in the configuration space of the PCIe device corresponding to the BDF information.

[0058] The following describes how to locate the faulty PCIe device based on the AER register information obtained in the above step 104:

[0059] In this embodiment, after obtaining the AER register information of all PCIe devices on the target PCIe link, the faulty PCIe device can be located based on all the AER register information obtained. As an embodiment, the AER register information also includes correctable error records and / or uncorrectable error records; based on this, the above-mentioned positioning of the faulty PCIe device based on all the AER register information obtained can be, for example, in specific implementation: based on the correctable error records and / or uncorrectable error records in the obtained AER register information, the faulty PCIe device is located from all the PCIe devices on the target PCIe link. As for how to locate the faulty PCIe device based on the correctable error records and / or uncorrectable error records in the obtained AER register information, this embodiment does not make any specific limitation.

[0060] As an embodiment, for any PCIe device, before obtaining the AER register information of the PCIe device, it is possible to check whether the PCIe device supports AER. For example, it is possible to check whether there is an AER extended capability record in the configuration space of the PCIe device and whether the AER extended capability record contains information indicating support for AER. If so, it is determined that the PCIe device supports AER. If not, it is determined that the PCIe device does not support AER. Afterwards, if the PCIe device supports AER, the AER register information of the PCIe device can continue to be obtained from the configuration space of the PCIe device. If the PCIe device does not support AER, the PCIe device is skipped, that is, the AER register information is not obtained from the configuration space of the PCIe device.

[0061] At this point, the description of the method provided in the embodiment of the present application is completed. The following describes the server provided in the embodiment of the present application:

[0062] See also Figure 4 , Figure 4 This is a schematic diagram of the server structure provided in the embodiment of the present application. Figure 4 As shown, the server 400 includes: BIOS 401, BMC 402, and N PCIe devices 403, where N is greater than 1;

[0063] BIOS 401 is used to construct a PCIe tree structure and send PCIe tree structure information of the PCIe tree structure to BMC 402 in server 400; wherein the PCIe tree structure includes N nodes connected according to a hierarchical connection relationship; each node in the PCIe tree structure is represented by BDF information of one of the PCIe devices 403 deployed on server 400, and the BDF information of any PCIe device is used to uniquely identify the PCIe device; the hierarchical connection relationship means that for any PCIe device, the PCIe device of the previous level of the PCIe device refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device of the next level of the PCIe device refers to the PCIe device connected to the downstream port of the PCIe device;

[0064] BIOS 401 is also used to send AER register information of a target PCIe device indicated by the PCIe device fault signal to BMC 402 when a PCIe device fault signal is detected; the AER register information of any PCIe device refers to information recorded in the AER register of the PCIe device, and the AER register information at least includes BDF information of the PCIe device;

[0065] BMC 402 is used to determine a target PCIe link based on the BDF information of the target PCIe device and the PCIe tree structure information; the target PCIe link refers to the shortest path from the root node to the terminal node in the PCIe tree structure that passes through the node represented by the BDF information of the target PCIe device;

[0066] The BMC 402 is further configured to obtain AER register information of all PCIe devices on the target PCIe link, so as to locate the faulty PCIe device based on the obtained AER register information.

[0067] As an embodiment, the number of root nodes in the PCIe tree structure is determined by the channel width of the PCIe interface configured with the central processing unit (CPU) of the server; the channel width refers to the number of channels used for data transmission.

[0068] As an embodiment, the PCIe device fault signal is generated by one of the PCIe devices deployed in the server and sent to the BIOS when a data processing error event is detected.

[0069] As an embodiment, the PCIe device fault signal at least includes BDF information of the PCIe device that generates the PCIe device fault signal; the target PCIe device is the PCIe device that generates the PCIe device fault signal.

[0070] As an embodiment, obtaining AER register information of all PCIe devices on the target PCIe link through the BMC includes:

[0071] Obtain the BDF information of all PCIe devices on the target PCIe link from the PCIe tree structure information;

[0072] For each BDF information obtained, the AER register information is obtained from the configuration space of the PCIe device corresponding to the BDF information based on the AER register address corresponding to the BDF information through a PCI configuration access interface used to directly access the configuration space of the PCIe device; the AER register address corresponding to the BDF information is obtained from the configured AER register address-BDF information mapping relationship, and the AER register address refers to the address of the AER register in the configuration space of the PCIe device corresponding to the BDF information.

[0073] As an embodiment, the AER register information also includes a correctable error record and / or an uncorrectable error record;

[0074] Locating the faulty PCIe device based on the obtained AER register information includes: locating the faulty PCIe device from all PCIe devices on the target PCIe link based on the correctable error record and / or uncorrectable error record in the obtained AER register information.

[0075] So far, completed Figure 4 Description of the structure of the server shown.

[0076] The implementation process of the functions and effects of each module in the above-mentioned server is specifically described in the implementation process of the corresponding steps in the above-mentioned method, which will not be repeated here.

[0077] For the server embodiment, since it basically corresponds to the method embodiment, the relevant parts refer to the partial description of the method embodiment. The server embodiment described above is only schematic, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present application scheme. Those of ordinary skill in the art can understand and implement it without paying creative labor.

[0078] See also Figure 5 , is a schematic diagram of the hardware structure of an electronic device provided by an exemplary embodiment of the present application. The electronic device may include a processor 501, a communication interface 502, a computer-readable storage medium 503 and a communication bus 504. The processor 501, the communication interface 502 and the computer-readable storage medium 503 communicate with each other through the communication bus 504. Among them, computer program instructions are stored on the computer-readable storage medium 503; the processor 501 can execute the steps of the method described in the above embodiment by executing the computer program instructions stored on the computer-readable storage medium 503. The electronic device may also include other hardware according to the actual function of the electronic device, which will not be described in detail.

[0079] Correspondingly, an embodiment of the present application further provides a computer-readable storage medium, on which a number of computer program instructions are stored. When the computer program instructions are executed by a processor, the method disclosed in the above example of the present application can be implemented.

[0080] Exemplarily, the computer-readable storage medium may be any electronic, magnetic, optical or other physical storage device that may contain or store information, such as executable instructions, data, etc. For example, the computer-readable storage medium may be: RAM (Radom Access Memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk (such as optical disk, DVD, etc.), or similar storage medium, or a combination thereof. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit.

[0081] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for determining a PCIe fault location, characterized in that: The method is applied to a server and includes: A high-speed serial computer expansion bus standard PCIe tree structure is constructed through the basic input and output system BIOS in the server, and the PCIe tree structure information of the PCIe tree structure is sent to the baseboard management controller BMC in the server; wherein the PCIe tree structure includes N nodes connected according to a hierarchical connection relationship, wherein N is the number of PCIe devices deployed on the server, and N is greater than 1; each node in the PCIe tree structure is characterized by the bus number-device number-function number BDF information of one of the PCIe devices deployed on the server, and the BDF information of any PCIe device is used to uniquely identify the PCIe device; the hierarchical connection relationship means that for any PCIe device, the PCIe device of the upper layer of the PCIe device refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device of the lower layer of the PCIe device refers to the PCIe device connected to the downstream port of the PCIe device; When the BIOS detects a PCIe device fault signal, the advanced error report AER register information of the target PCIe device indicated by the PCIe device fault signal is sent to the BMC; the AER register information of any PCIe device refers to the information recorded in the AER register of the PCIe device, and the AER register information at least includes the BDF information of the PCIe device; Determine a target PCIe link by the BMC based on the BDF information of the target PCIe device and the PCIe tree structure information; the target PCIe link refers to the shortest path from the root node to the terminal node in the PCIe tree structure that passes through the node represented by the BDF information of the target PCIe device; The AER register information of all PCIe devices on the target PCIe link is obtained through the BMC, so as to locate the faulty PCIe device based on the obtained AER register information.

2. The method according to claim 1, characterized in that The number of root nodes in the PCIe tree structure depends on the channel width of the PCIe interface configured with the central processing unit (CPU) of the server; the channel width refers to the number of channels used for data transmission.

3. The method according to claim 1, characterized in that The PCIe device fault signal is generated by one of the PCIe devices deployed on the server when a data processing error event is detected and sent to the BIOS.

4. The method according to claim 3, characterized in that The PCIe device fault signal at least includes BDF information of the PCIe device that generates the PCIe device fault signal; and the target PCIe device is the PCIe device that generates the PCIe device fault signal.

5. The method according to claim 1, characterized in that Obtaining AER register information of all PCIe devices on the target PCIe link through the BMC includes: Obtaining BDF information of all PCIe devices on the target PCIe link from the PCIe tree structure information; For each BDF information obtained, the AER register information is obtained from the configuration space of the PCIe device corresponding to the BDF information based on the AER register address corresponding to the BDF information through a PCI configuration access interface used to directly access the configuration space of the PCIe device; the AER register address corresponding to the BDF information is obtained from the configured AER register address-BDF information mapping relationship, and the AER register address refers to the address of the AER register in the configuration space of the PCIe device corresponding to the BDF information.

6. The method according to claim 1, characterized in that The AER register information also includes correctable error records and / or uncorrectable error records; Locating the faulty PCIe device based on the obtained AER register information includes: locating the faulty PCIe device from all PCIe devices on the target PCIe link based on the correctable error record and / or uncorrectable error record in the obtained AER register information.

7. A server, characterized in that: The server is deployed with a baseboard management controller BMC, a basic input and output system BIOS, and N high-speed serial computer expansion bus standard PCIe devices, where N is greater than 1; The BIOS is used to construct a PCIe tree structure, and send PCIe tree structure information of the PCIe tree structure to the BMC in the server; wherein the PCIe tree structure includes N nodes connected according to a hierarchical connection relationship; each node in the PCIe tree structure is represented by the bus number-device number-function number BDF information of one of the PCIe devices deployed on the server, and the BDF information of any PCIe device is used to uniquely identify the PCIe device; the hierarchical connection relationship means that for any PCIe device, the PCIe device of the previous level of the PCIe device refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device of the next level of the PCIe device refers to the PCIe device connected to the downstream port of the PCIe device; The BIOS is also used to, when a PCIe device fault signal is detected, send the advanced error report AER register information of the target PCIe device indicated by the PCIe device fault signal to the BMC; the AER register information of any PCIe device refers to the information recorded in the AER register of the PCIe device, and the AER register information at least includes the BDF information of the PCIe device; The BMC is used to determine a target PCIe link based on the BDF information of the target PCIe device and the PCIe tree structure information; the target PCIe link refers to the shortest path from the root node to the terminal node in the PCIe tree structure that passes through the node represented by the BDF information of the target PCIe device; The BMC is further used to obtain AER register information of all PCIe devices on the target PCIe link, so as to locate the faulty PCIe device based on the obtained AER register information.

8. The server according to claim 7, characterized in that: The number of root nodes in the PCIe tree structure depends on the channel width of the PCIe interface configured by the central processing unit CPU of the server; the channel width refers to the number of channels used for data transmission; and / or, The PCIe device fault signal is generated by one of the PCIe devices deployed on the server and sent to the BIOS when a data processing error event is detected; and / or, The PCIe device fault signal at least includes BDF information of the PCIe device that generates the PCIe device fault signal; The target PCIe device is a PCIe device that generates the PCIe device fault signal; and / or, Obtaining the AER register information of all PCIe devices on the target PCIe link through the BMC includes: obtaining the BDF information of all PCIe devices on the target PCIe link from the PCIe tree structure information; for each BDF information obtained, obtaining the AER register information from the configuration space of the PCIe device corresponding to the BDF information based on the AER register address corresponding to the BDF information through a PCI configuration access interface for directly accessing the configuration space of the PCIe device; the AER register address corresponding to the BDF information is obtained from a configured AER register address-BDF information mapping relationship, and the AER register address refers to the address of the AER register in the configuration space of the PCIe device corresponding to the BDF information; and / or, The AER register information also includes correctable error records and / or uncorrectable error records; locating the faulty PCIe device based on the obtained AER register information includes: locating the faulty PCIe device from all PCIe devices on the target PCIe link based on the correctable error records and / or uncorrectable error records in the obtained AER register information.

9. An electronic device, characterized in that: include: processor; as well as A computer-readable storage medium, wherein computer program instructions are stored in the computer-readable storage medium, and when the computer program instructions are executed by the processor, the processor executes the steps in any one of the methods of claims 1 to 6.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, which, when executed by a processor, enable the processor to perform the steps of any one of the methods of claims 1 to 6.

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