NVMe permanent memory allocation method and NVMe controller

Abstract

The invention provides an NVMe permanent memory allocation method and an NVMe controller, and is applied to the technical field of data storage, and the method comprises the steps that a host end reads permanent memory configuration information of the NVMe controller of an equipment end of NVMe equipment, and the permanent memory configuration information is information of configuring a permanent memory function by the equipment end in a power-on initialization stage; configuring each protocol register of the NVMe controller, and enabling a permanent memory function of a device end; and when the waiting duration after the permanent memory function of the device end is enabled is greater than or equal to the preset waiting duration in the permanent memory configuration information, taking the double-rate synchronous dynamic random access memory in the NVMe solid state disk of the device end as the permanent memory of the host end, so that the host end performs read-write operation on the permanent memory. According to the scheme, the double-rate synchronous dynamic random access memory of the equipment end is used as the permanent memory of the host end, so that the problems of memory shortage of the host end, memory power failure and data loss are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to an NVMe permanent memory allocation method and an NVMe controller. Background Art

[0002] With the rapid development of computer technology, especially its widespread application in cloud computing, big data, the Internet of Things and other fields, the demand for storage on the host side such as terminal products (such as smart phones, tablets, personal computers, etc.) and server systems (such as data centers, cloud computing platforms) is increasing.

[0003] The host's demand for storage is not only reflected in storage capacity, but also puts forward higher requirements for storage reliability, speed, security, etc. However, when responding to these demands, the host generally faces challenges such as insufficient memory and data loss due to power failure. Summary of the invention

[0004] In view of this, an embodiment of the present application provides an NVMe permanent memory allocation method and an NVMe controller. The solution provided by the present application can provide permanent memory for the host side, thereby alleviating the pressure of insufficient memory on the host side and solving the problem of data loss due to power failure of the host side memory.

[0005] To achieve the above objectives, the present application provides the following technical solutions:

[0006] An NVMe persistent memory allocation method, comprising:

[0007] When the host determines that the device is an NVMe device, the host reads the persistent memory configuration information of the NVMe controller of the device, where the persistent memory configuration information is information for configuring the persistent memory function of the device during the power-on initialization phase;

[0008] Configure various protocol registers of the NVMe controller in the device end, and enable the persistent memory function of the device end;

[0009] The waiting time after enabling the persistent memory function of the device side is counted in real time. When the waiting time is greater than or equal to the preset waiting time in the persistent memory configuration information, the double rate synchronous dynamic random access memory in the NVMe solid state drive of the device side is used as the persistent memory of the host side, so that the host side can perform read and write operations on the persistent memory.

[0010] In the above method, optionally, the host performs a write operation on the persistent memory, including:

[0011] The host terminal sends a write operation request to the device terminal;

[0012] The device side sends the write operation request to the host write demultiplexing component in the NVMe controller of the device side, so that the host write demultiplexing component performs address resolution on the write operation request;

[0013] The host write demultiplexing component sends the parsed write operation request to the redirection controller in the NVMe controller;

[0014] The redirection controller obtains the first cache data from the host side based on the parsed write operation request, writes the first cache data into the elastic cache component in the NVMe controller, and determines whether the elastic cache component meets the preset first processing condition; when the elastic cache component meets the preset first processing condition, the redirection controller initiates a read cache operation on the elastic cache component to read the second cache data from the elastic cache component;

[0015] The redirection controller initiates the write device arbitrator component in the NVMe controller to arbitrate the write request of the second cache data;

[0016] When the write request of the second cache data passes arbitration, the second cache data is written into the permanent memory.

[0017] In the above method, optionally, the host performs a read operation on the persistent memory, including:

[0018] The host terminal sends a read operation request to the device terminal;

[0019] The device side sends the read operation request to the host read demultiplexing component in the NVMe controller of the device side, so that the host read demultiplexing component performs address resolution on the read operation request;

[0020] The host read demultiplexing component sends the parsed read operation request to the redirection controller in the NVMe controller;

[0021] After receiving the parsed read operation request, the redirection controller initiates a read request to the permanent memory, and reads the third cache data from the permanent memory based on the read request, uses the read device arbitrator component in the NVMe controller to arbitrate the third cache data, and writes the arbitrated third cache data into the elastic cache component in the NVMe controller, and determines whether the elastic cache component meets a preset first processing condition. When it is determined that the elastic cache component meets the first processing condition, the redirection controller initiates a read cache operation to the elastic cache component to obtain fourth cache data from the elastic cache component, and sends the fourth cache data to the host end.

[0022] In the above method, optionally, the determining whether the elastic cache component satisfies a preset first processing condition includes:

[0023] Determining whether the amount of data cached in the elastic cache component exceeds a preset cache detection line;

[0024] When the amount of data cached in the elastic cache component does not exceed the preset cache detection line, determining whether the statistical duration for which the elastic cache component is continuously in a non-empty state is greater than a preset duration;

[0025] When the statistical length of time that the elastic cache component is continuously in a non-empty state is not greater than a preset length of time, determining that the elastic cache component does not meet the first processing condition;

[0026] When the amount of data cached in the elastic cache component exceeds a preset cache detection line, or the statistical time length for which the elastic cache component is continuously in a non-empty state is greater than or equal to a preset time length, it is determined that the elastic cache component meets the first processing condition.

[0027] In the above method, optionally, sending the fourth cache data to the host end includes:

[0028] The redirection controller sends the fourth cache data to the first AXI interface in the NVMe controller through the host read-connect multiplexing component, so that the first AXI interface sends the fourth cache data to the host end through the PICe interface.

[0029] The above method may optionally further include:

[0030] When power is lost on the device side, the solid-state hard disk controller in the device side flushes the cached data in the permanent memory and the configuration information of the permanent memory to the preset non-volatile memory, so that when the device side is powered on next time, the cached data in the non-volatile memory is loaded into the permanent memory of the device side, and the permanent memory of the device side is configured based on the configuration information in the non-volatile memory.

[0031] An NVMe controller is provided at a device end, and includes:

[0032] a first AXI interface, a host demultiplexing module, a persistent memory controller, a device arbiter module, a second AXI interface, and a protocol register component;

[0033] The first AXI interface is used to connect to the PICe interface of the host side and perform data transmission with the host side;

[0034] The host demultiplexing module is used to perform address resolution on the operation request sent by the host, and send the resolved operation request to the persistent memory controller;

[0035] The permanent memory controller is used to perform read and write control on the double rate synchronous dynamic random access memory in the host side and the device side as the permanent memory of the host side based on the received operation request;

[0036] The device arbitrator module is used to arbitrate requests generated when the persistent memory controller performs read and write control;

[0037] The second AXI interface is used to connect to the interface of the double rate synchronous dynamic random access memory of the device end, and perform data transmission with the double rate synchronous dynamic random access memory;

[0038] The protocol register component includes a plurality of registers, which are used to implement read and write control of each of the registers.

[0039] The above-mentioned NVMe controller, optionally, the host demultiplexing module includes:

[0040] A host read demultiplexing component and a host write demultiplexing component;

[0041] The host read demultiplexing component is used to perform address resolution on an operation request of a read operation type sent by the host end;

[0042] The host write demultiplexing component is used to perform address resolution on an operation request of a write operation type sent by the host.

[0043] The above-mentioned NVMe controller, optionally, the persistent memory controller includes:

[0044] Configuration register component, redirection controller and elastic cache component;

[0045] The configuration register component is used to redirect address mapping registers of command configuration registers of the host side, the device side and the redirection controller;

[0046] The redirection controller is used to convert a write permanent memory request output by a host write demultiplexing component in the host demultiplexing module into a write request for the elastic cache component, and write permanent memory data corresponding to the write permanent memory request into the elastic cache component; to convert a read permanent memory request output by a host read demultiplexing component in the host demultiplexing module into a read request for the elastic cache component, read permanent memory data corresponding to the read permanent memory request from the elastic cache component, and send the read permanent memory data to the host read demultiplexing component; and to initiate a write request to the write device arbitrator component in the device arbitrator module according to the amount of data written to the elastic cache component, and to initiate a read request to the read device arbitrator component in the device arbitrator module according to the read permanent memory request.

[0047] The above-mentioned NVMe controller, optionally, the device arbitrator module includes:

[0048] a read device arbitrator component and a write device arbitrator component;

[0049] The read device arbitrator component is used to arbitrate various types of read requests;

[0050] The write device arbitrator component is used to arbitrate various write requests.

[0051] Compared with the prior art, this application has the following advantages:

[0052] The present application provides an NVMe permanent memory allocation method and an NVMe controller, the scheme includes: when the host side determines that the device side is an NVMe device, the host side reads the permanent memory configuration information of the NVMe controller of the device side, and the permanent memory configuration information is the information for configuring the permanent memory function of the device side during the power-on initialization phase; configure the various protocol registers of the NVMe controller in the device side, and enable the permanent memory function of the device side; real-time statistics of the waiting time after enabling the permanent memory function of the device side, when the waiting time is greater than or equal to the preset waiting time in the permanent memory configuration information, the double rate synchronous dynamic random access memory in the NVMe solid state drive of the device side is used as the permanent memory of the host side, so that the host side can read and write to the permanent memory. By applying the scheme provided by the present application, the double rate synchronous dynamic random access memory of the NVMe solid state drive of the device side can be used as the permanent memory of the host side, thereby solving the problem of insufficient memory on the host side, and solving the problem of data loss when the memory is powered off. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0054] Figure 1 A flowchart of an NVMe persistent memory allocation method provided in an embodiment of the present application;

[0055] Figure 2 A flowchart for determining whether an elastic cache component meets a preset first processing condition provided in an embodiment of the present application;

[0056] Figure 3 A schematic diagram of the structure of an NVMe controller provided in an embodiment of the present application;

[0057] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] In this application, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0060] Terminology explanation:

[0061] PCIe: Peripheral Component Interconnect Express, high-speed peripheral component interconnect;

[0062] PMR: Persistent Memory Region, permanent memory;

[0063] CPU: Central Processing Unit, central processing unit;

[0064] NVMe: Non Volatile Memory Express, non-volatile storage;

[0065] CQ: Completion Queue, completion queue;

[0066] SQ: Submission Queue, submission queue;

[0067] DMA: Direct Memory Access, direct memory access;

[0068] NAND particles: a type of non-volatile memory, which means that the written data can still be saved in the case of power failure, and is in fixed blocks rather than single bytes;

[0069] CMB: ControllerMemoryBuffer, refers to the read and write storage buffer inside the SSD controller;

[0070] DDR: Double Data Rate, double data rate synchronous dynamic random access memory, also known as DDR SDRAM;

[0071] PMRCAP register: Persistent Memory Region Capacity register, permanent memory capacity register, used to indicate the specific support capabilities of the PMR feature on the device side;

[0072] PMRCTL register: Persistent Memory Region Control register, permanent memory control register, used to indicate the specific enable configuration of the PMR feature of the host side to the configuration side;

[0073] PMRSTS register: Persistent Memory Status register, permanent memory status register, used to indicate the PMR status of the device side;

[0074] PMREBS register: Persistent Memory Region Elastic Buffer Size register, permanent memory elastic buffer size register, used to indicate the elastic buffer size inside the device-side PMR;

[0075] PMRSWTP register: Persistent Memory Region Sustained Write Throughput register, permanent memory sustained write throughput register, used to indicate the PMR sustained write throughput that the device can provide;

[0076] PMRMSC register: Persistent Memory Region Memory Space register, permanent memory storage space register, used to indicate the device-side PMR storage space base address and enable configuration.

[0077] As can be seen from the background technology, the current host side has an increasing demand for storage, and the host side faces problems such as insufficient memory and data loss during power failure.

[0078] In order to solve the above problems, the present application provides an NVMe persistent memory allocation method, which is used to provide a high-speed persistent memory for the host side, thereby expanding the memory of the host side, solving the pressure of insufficient memory on the host side, and the data of the provided persistent memory is not lost when the power is off, and at the same time solves the problem of data loss after the host side memory loses power.

[0079] Before explaining the solution provided by the present application, the NVMe protocol to which the present application is applied is first introduced. The permanent memory (PMR, Persistent Memory Region) technology in the MVMe protocol is a storage area that can be permanently read and written by the host side, which is provided by the device side. Its main features are that the data is not lost after power failure, the controller is reset, and the data is not lost after enabling / disabling the permanent memory function, and the host side is provided with a storage area with memory-level read and write speed. This storage area can be directly mapped to the BAR (Base Address Register) space of PCIe according to the PCIe protocol, and can be read and written directly through PCIe without the need for NVMe IO commands, and the operation is fast and efficient. The low latency, non-volatility, and multi-addressable characteristics of the permanent memory enable it to cope well with frequent high-speed read and write access scenarios and enterprise-level application scenarios such as power supply anomalies or system downtime.

[0080] Reference Figure 1 , which is a flowchart of an NVMe persistent memory allocation method provided in an embodiment of the present application. For specific steps, refer to Figure 1 S101-S103 in the specification are as follows:

[0081] S101. When the host determines that the device is an NVMe device, the host reads the persistent memory configuration information of the NVMe controller of the device, where the persistent memory configuration information is information for configuring the persistent memory function of the device during the power-on initialization phase.

[0082] The host side can be regarded as the Host, and the device side is the Device, also known as the slave side.

[0083] The host queries the device. When the queried device includes an NVMe controller, it can be determined that the device is an NVMe device.

[0084] The host side reads the persistent memory configuration information from the persistent memory protocol controller of the NVMe controller on the device side; preferably, the persistent memory protocol controller is a certain type of protocol controller, which can be understood as a protocol controller associated with the persistent memory; the persistent memory protocol controller includes but is not limited to a PMRCAP register, a PMREBS register, and a PMRSWTP register, etc.

[0085] The persistent memory configuration information of the NVMe controller on the device side includes but is not limited to the configuration information of the PMRCAP register, the PMREBS register and the PMRSWTP register, including but not limited to whether the device side supports the PMR function, the minimum waiting time after the PMR function is enabled, the size of the PMR elastic cache, and the bandwidth of the PMR.

[0086] The host side reads the PMRCAP register, PMREBS register, and PMRSWTP register of the device side to obtain the persistent memory configuration information of the device side. The persistent memory configuration information can also be expressed as PMR information.

[0087] The PMRCAP register mainly describes whether the device supports the PMR function and the minimum waiting time after enabling the PMR function; the PMREBS register is mainly used to indicate the capacity of the PMR elastic cache; the PMRSWTP register is used to represent the maximum bandwidth value that the device-side PMR can provide.

[0088] During the power-on initialization phase of the device, the device firmware CPU configures the PMRCAP register, PMREBS register, and PMRSWTP register to configure whether the device supports the PMR function, the minimum waiting time after the PMR function is enabled, the size of the PMR elastic cache, and the bandwidth of the PMR.

[0089] S102: The host configures various protocol registers of the NVMe controller on the device side and enables the persistent memory function on the device side.

[0090] Preferably, the various protocol registers of the NVMe controller configured here are the PMRCTL register and the PMRMSC register; the PMRCTL register and the PMRMSC register of the device side are configured; by configuring the PMRCTL register and the PMRMSC register, the PMR function of the device side can be enabled and the PMR status of the device side can be reflected. After the configuration is completed, the permanent memory function of the device side is enabled.

[0091] The PMRCTL register is used by the host to enable the PMR function on the device side; the PMRMSC register is used to represent the base address of the PMR storage space and the base address enable control.

[0092] It should be noted that the PMRCAP register, PMREBS register, PMRSWTP register, PMRCTL register and PMRMSC register are all PMR-related protocol registers defined in the NVMe protocol. In addition to the above registers, it also includes the PMRSTS register. The PMRSTS register is a PMR status register that is used to reflect the PMR error status, PMR health status, whether the PMR is ready, and other information for the host to query.

[0093] S103, the host side counts the waiting time after enabling the persistent memory function of the device side in real time. When the waiting time is greater than or equal to the preset waiting time in the persistent memory configuration information, the double rate synchronous dynamic random access memory in the NVMe solid state drive of the device side is used as the persistent memory of the host side, so that the host side can perform read and write operations on the persistent memory.

[0094] In the method provided in the embodiment of the present application, after enabling the permanent memory function of the device side, the host side needs to wait. When the waiting time of the host side is greater than or equal to the preset waiting time in the permanent memory configuration information, the double-rate synchronous dynamic random access memory in the NVMe solid-state drive of the device side can be used as the permanent memory of the host side, and the host side can initiate a PMR read and write request.

[0095] It should be noted that the preset waiting time in the persistent memory configuration information is the minimum waiting time configured in the PMRCAP register.

[0096] Furthermore, the above steps S101-S103 can also be regarded as a process of allocating DDR capacity from the NVMe solid-state drive on the device side for use as permanent memory on the host side.

[0097] In the method provided by the embodiment of the present application, when the host side determines that the device side is an NVMe device, the host side reads the permanent memory configuration information of the device side, and the permanent memory configuration information is the information for configuring the permanent memory function of the device side during the power-on initialization phase; configures each protocol register of the device side, and enables the permanent memory function of the device side; real-time statistics of the waiting time after enabling the permanent memory function of the device side, when the waiting time is greater than or equal to the preset waiting time in the permanent memory configuration information, the double rate synchronous dynamic random access memory in the NVMe solid state drive of the device side is used as the permanent memory of the host side, so that the host side can read and write the permanent memory. This application configures the NVMe protocol registers of the device side, enables the permanent memory function of the device side, and after the waiting time exceeds the preset waiting time in the permanent memory configuration information of the device side, the double rate synchronous dynamic random access memory in the NVMe solid state drive of the device side is used as the permanent memory of the host side, thereby alleviating the pressure of insufficient memory on the host side and solving the problem of data loss caused by power failure of the host side memory.

[0098] The process of writing to the persistent memory by the host is described as follows:

[0099] The host side prepares a write operation request and write operation data, and the write operation request and write operation data are packaged into a PCIe TLP packet by the host side PCIe and transmitted to the first AXI interface of the NVMe controller on the device side through the device side PICe, and then reach the host write demultiplexing component in the NVMe controller after passing through the first AXI interface, so that the host write demultiplexing component performs address resolution on the write operation request to obtain the AXI write address channel write request, and then the host write demultiplexing component sends the AXI write address channel write request to the redirection controller in the NVMe controller; the redirection controller responds to the AXI write address channel write request and receives the first cache data sent by the host side. It should be noted that the host side sends the write operation data (i.e., the first cache data) to the PCIe device side through the same transmission path as the write operation request through the PCIe TLP packet, and sends it to the redirection controller through the host write demultiplexing component of the NVMe controller on the device side. The redirection controller writes the first cache data into the elastic cache component of the NVMe controller; further, it is determined whether the elastic cache component satisfies a preset first processing condition. When the elastic cache component satisfies the preset first processing condition, the redirection controller initiates a read cache operation on the elastic cache component to read the second cache data from the elastic cache component; the redirection controller also initiates a write arbitration request to the write device arbitrator component in the NVMe controller to arbitrate the write arbitration request for the second cache data; when the write arbitration request for the second cache data passes the arbitration, that is, is authorized, a write request to the DDR on the device side is initiated to write the second cache data into the DDR, that is, write the second cache data into the permanent memory.

[0100] Reference Figure 2 , which is a flowchart for determining whether an elastic cache component meets a preset first processing condition provided in an embodiment of the present application, is specifically described as follows:

[0101] S201, determine whether the amount of data cached in the elastic cache component exceeds the preset cache detection line; when the amount of data cached in the elastic cache component does not exceed the preset cache detection line, execute S202; when the amount of data cached in the elastic cache component exceeds the preset cache detection line, execute S204.

[0102] The cache detection line can be set according to actual needs. Preferably, the cache detection line can be understood as the maximum value of the cache or the maximum cache capacity. The cache detection line can detect whether the amount of cached data has exceeded the limit.

[0103] S202, determine whether the statistical length of time that the elastic cache component is continuously in a non-empty state is greater than or equal to a preset length of time; when the statistical length of time that the elastic cache component is continuously in a non-empty state is not greater than the preset length of time, execute S203; when the statistical length of time that the elastic cache component is continuously in a non-empty state is greater than the preset length of time, execute S204.

[0104] When the elastic cache component is in a non-empty state, it indicates that there is cache data in the elastic cache component. Determining whether the statistical duration of the elastic cache component in a non-empty state is greater than the preset duration is essentially to perform a non-empty timeout detection on the elastic cache component. When the statistical duration is greater than the preset duration, the timeout mechanism is triggered and a read operation on the elastic cache component is initiated. Furthermore, the duration statistics are started when the elastic cache component is non-empty; after initiating a read operation on the elastic cache component, the statistical duration can be cleared to prepare for the next statistics.

[0105] S203: Determine whether the elastic cache component does not meet the first processing condition.

[0106] S204: Determine whether the elastic cache component meets the first processing condition.

[0107] By setting a cache detection line of the elastic cache component, the present application can detect whether the data cached in the elastic cache component exceeds the amount. When the amount exceeds the amount, the data in the elastic cache component is read out in time so that there is storage space to save the data that needs to be stored later; by setting a timeout detection mechanism, the cache time of the data in the elastic cache component can be limited. When the cache time is too long, the data in the elastic cache component is read out so that subsequent data can be written into the elastic cache component. In short, by setting a cache detection line and a timeout detection, the overflow of the data cached in the elastic cache component is avoided, resulting in data loss, and the elastic cache component can maintain the data space that can be stored, so as to maintain the storage activity of the elastic cache component.

[0108] It should be noted that the process of the host side performing a read operation on the persistent memory is described as follows:

[0109] The host sends a read operation request TLP packet to the device through PCIe. After the read operation request passes through the PCIe interface and the first AXI interface in sequence, it reaches the host read demultiplexing component in the NVMe controller on the device side, so that the host read demultiplexing component performs address resolution on the read operation request, obtains the first AXI read address channel request, and sends the first AXI read address channel request to the redirection controller in the NVMe controller; after receiving the first AXI read address channel request, the redirection controller initiates a second AXI read address channel request to the permanent memory (or the DDR in the NVMe controller), and sends the second AXI read address channel request to the second AXI controlled by the NVMe through the read device arbitrator component. The interface is used to make the second AXI read address channel request reach the permanent memory (i.e., DDR), thereby obtaining the third cache data corresponding to the second AXI read address channel request in the permanent memory, and then the third cache data is sent to the read device arbiter component through the second AXI interface. The third cache data arbitrated by the read device arbiter component is written into the elastic cache component, and it is determined whether the elastic cache component meets the preset first processing condition. When it is determined that the elastic cache component meets the first processing condition, the redirection controller initiates a read cache operation to the elastic cache component to obtain the fourth cache data from the elastic cache component. The fourth cache data reaches the host end after passing through the first AXI interface and the PICe interface in sequence, and a read operation is completed.

[0110] Preferably, the relevant description of the process of determining whether the elastic cache component meets the first processing condition in the read operation process can refer to the description of determining whether the elastic cache component meets the first processing condition in the above-mentioned write operation process, and will not be repeated here.

[0111] Preferably, in the embodiment provided by the present application, when power is lost on the device side, the solid-state drive controller (i.e., SSD controller) firmware in the device side flushes the cached data in the permanent memory (i.e., the DDR area serving as the PMR) and the configuration information of the permanent memory to the preset non-volatile memory (i.e., NAND particles), so that when the device side is powered on next time, the cached data in the non-volatile memory (i.e., NAND particles) is loaded into the permanent memory of the device side, and the permanent memory of the device side is configured based on the configuration information in the non-volatile memory, thereby solving the problem of data loss caused by power loss on the host side.

[0112] Reference Figure 3, is a schematic diagram of the structure of an NVMe controller provided in an embodiment of the present application, wherein the NVMe controller is disposed at the device end so as to control the double rate synchronous dynamic random access memory in the NVMe solid state drive at the device end as the permanent memory at the host end. Figure 3 Take the NVMe controller as an example to explain the structure of the controller. The relevant description is as follows:

[0113] The NVMe controller includes: a first AXI interface 301, a host demultiplexing module 302, a persistent memory controller 303, a device arbitrator module 304, a second AXI interface 305 and a protocol register component 306.

[0114] The first AXI interface is used to connect to the PICe interface of the host side and perform data transmission with the host side.

[0115] The host demultiplexing module is used to perform address resolution on the operation request sent by the host, and send the resolved operation request to the permanent memory controller.

[0116] The permanent memory controller is used to perform read and write control on the double rate synchronous dynamic random access memory as the permanent memory of the host side in the host side and the device side based on the received operation request;

[0117] The device arbitrator module is used to arbitrate requests generated when the persistent memory controller performs read and write control.

[0118] The second AXI interface is used to connect to the interface of the double rate synchronous dynamic random access memory on the device side and perform data transmission with the double rate synchronous dynamic random access memory.

[0119] The protocol register component includes a plurality of registers for implementing read and write control of each register. Preferably, the register here can be a protocol register.

[0120] It should be noted that the first AXI interface and the second AXI interface in the NVMe controller are AXI slave interfaces, which are responsible for the AXI interface protocol processing connected to the POC. The protocol register component is used to implement the read and write control of the NVMe protocol register in the NVMe controller, and the PMR register specified by the protocol is also in this component.

[0121] Reference Figure 3 The host demultiplexing module includes: a host read demultiplexing component and a host write demultiplexing component.

[0122] The host read and demultiplexing component is used to perform address resolution on the operation command of the read operation type sent by the host side; the host read and demultiplexing component is also responsible for mapping the address of the host read operation to CMB, PMR, NVMe protocol register, and error address module, wherein the error address module is applicable to the error handling module where the host read operation address is an illegal address, so as to achieve the purpose of not hanging the bus when an error occurs. If the NVMe controller does not support CMB, one CMB interface is missing.

[0123] The host write demultiplexing component is used to perform address resolution on the operation command with the operation type of write operation sent by the host side; the host write demultiplexing component is also responsible for mapping the address of the host write operation to the CMB register, PMR register, NVMe protocol register, and error address module, wherein the error address module is applicable to the error handling module where the host write operation address is an illegal address, so as to achieve the purpose of not hanging the bus when an error occurs. If the NVMe controller does not support CMB, one CMB interface is missing.

[0124] Furthermore, the device arbitrator module includes: a read device arbitrator component and a write device arbitrator component; wherein the read device arbitrator component may also be referred to as a device read arbitrator, and the write device arbitrator component may also be referred to as a device write arbitrator.

[0125] The read device arbitrator component is used to arbitrate various read requests; the read device arbitrator component is responsible for the following arbitration:

[0126] 1) NVMe requests to read CQ entries from the DDR on the device side; 2) NVMe DMA requests to read user data from the DDR on the device side; 3) NVMe requests to read NVMe firmware commands from the DDR on the device side; 4) Host side requests to read PMR on the device side; The arbitrator is a round-robin arbitrator or a weighted round-robin arbitrator. The arbitrator is a round-robin arbitrator or a weighted round-robin arbitrator.

[0127] The specific examples of arbitration performed by the read device arbitrator component are as follows:

[0128] Embodiment 1: A weighted round-robin arbiter is used. The weight of each request source of the arbiter is configured by the CPU register when the NVMe controller is powered on and initialized. The value of the weight of each register is set autonomously by the firmware. It is recommended to set it according to 2:1:2:2. The reason is that the transmission data length corresponding to the request for NVMe to read the CQ entry is very small, the bandwidth requirement is low, and it needs to be responded to with priority and has little impact on the bandwidth. The data length of the request for NVMe DMA data is longer, the bandwidth requirement is large, and the priority is low, so it can be set to 1. The length of the NVMe firmware command read from the DDR on the device side is small, and it needs to be responded to with priority and has little impact on the bandwidth. The read PMR read data request on the host side has a higher priority, the amount of data accessed at a single time is not large, and the bandwidth requirement is medium, so it can be set to 2.

[0129] Embodiment 2: NVMe CQ entries and NVMe firmware commands are not placed in the DDR on the device side, but in the on-chip cache SRAM outside the NVMe controller. At this time, there are only two requests for NVMe DMA to read user data from the DDR on the device side and the host side to read the PMR request on the device side; weighted arbitration is performed, and round-robin arbitration or weighted arbitration can be used. If a weighted arbitrator is used, the weight value is set autonomously by the firmware, and it is recommended to be set as 1:2.

[0130] The write device arbitrator component is used to arbitrate various write requests; the write device arbitrator component is responsible for the following arbitration: 1) NVMe SQ command writes DDR request on the device side; 2) NVMe user data writes DDR request on the device side; 3) PMR request on the host side writes to the device side; the arbitrator is a round-robin arbitrator or a weighted round-robin arbitrator.

[0131] The specific example of arbitration that the write device arbitrator component is responsible for is as follows:

[0132] Embodiment 1: A weighted round-robin arbiter is used. The weight of each request source of the arbiter (i.e., the party that initiates a request to the arbiter) is configured by the CPU register when the NVMe controller is powered on and initialized. The value of the weight of each register is set autonomously by the firmware. It is recommended to set it according to 2:1:2. The reason is that the transmission data length corresponding to the request of the NVMe SQ command is very small, the bandwidth requirement is low, and it needs to be responded to first and has little impact on the bandwidth. The data length of the NVMe DMA data request is longer, the bandwidth requirement is large, and the priority is lower, so it can be set to 1. The host-side write PMR read data request has a higher priority, the amount of data accessed at a single time is not large, and the bandwidth requirement is medium, so it can be set to 2.

[0133] Embodiment 2: NVMe SQ commands are not written to the DDR on the device side, but to the on-chip cache SRAM outside the NVMe controller. At this time, only two requests are weighted for arbitration;

[0134] Embodiment 3: The NVMe SQ command is not written into the DDR on the device side, but is written into the shared SRAM inside the NVMe controller for placing the SQ command. At this time, only two requests are weightedly arbitrated.

[0135] Furthermore, the persistent memory controller may be referred to as a PMR controller. Furthermore, the persistent memory controller includes: a configuration register component, a redirection controller, and an elastic cache component.

[0136] The configuration register component is used to redirect the address mapping register of the command configuration register of the host side, the device side and the redirection controller. Further, the configuration register component is used to implement the firmware in the device-side SSD controller to the command configuration register of the controller in the DMA mode, the host side and the device side redirection address mapping register, so as to associate the calculated configuration PMR base address with the device-side DDR address to form a one-to-one mapping relationship.

[0137] The redirection controller is used to convert a write permanent memory request output by a host write demultiplexing component in a host demultiplexing module into a write request to an elastic cache component, and write permanent memory data corresponding to the write permanent memory request into the elastic cache component; to convert a read permanent memory request output by a host read demultiplexing component in a host demultiplexing module into a read request to the elastic cache component, read permanent memory data corresponding to the read permanent memory request from the elastic cache component, and send the read permanent memory data to the host read demultiplexing component; and to initiate a write request to a write device arbitrator component in a device arbitrator module according to the amount of data written to the elastic cache component, and to initiate a read request to a read device arbitrator component in the device arbitrator module according to a read permanent memory request.

[0138] Furthermore, the elastic cache component is composed of two independent readable and writable 8KB SRAMs, which can be divided into elastic cache 1 and elastic cache 2, and the read and write operations are controlled by the redirection controller. The read operation of the elastic cache component is controlled by waterline detection and timeout non-empty detection. The waterline check and timeout non-empty detection are in a logical relationship of or. Further, the waterline detection is equivalent to the content of using the cache detection line to detect the amount of data cached in the elastic cache component in the above text; the timeout non-empty detection is equivalent to the content of judging whether the statistical duration of the elastic cache component being in a non-empty state is greater than the preset duration in the above text. The waterline (equivalent to the cache detection direction mentioned above) is configured through registers and set to a value such as 256B or 512B. When the waterline is exceeded, an operation of reading the elastic cache component is initiated. If the current elastic cache is not empty and has not reached the waterline, but the timeout mechanism has been triggered, a read operation of the elastic cache component is also initiated. The timeout mechanism starts timing when the elastic cache component is not empty. When the waterline is reached or the timeout is triggered, the timeout is reset and an operation of reading the elastic cache component is initiated. The timeout period (equivalent to the preset period in the step of determining whether the statistical duration of the elastic cache component being continuously in a non-empty state is greater than the preset period) is configured by the CPU (i.e., the firmware in the SSD controller) through registers.

[0139] The redirection controller can implement four functions:

[0140] 1) Convert the write PMR request output by the host write demultiplexing component into a write request for the elastic cache component, and further obtain that the write PMR request output by the host write demultiplexing component is equivalent to the write operation request parsed by the host write demultiplexing component above, write the write PMR data corresponding to the PMR request into the elastic cache 1 of the elastic cache component, and back-pressure the PCIe end when the elastic cache 1 is full. It should be noted that the write PMR data is transmitted to the PMR through the PICe interface from the host end, and then written into the elastic cache 1. The write PMR data here can be understood as the data corresponding to the write operation request sent by the host end. Convert the read PMR request output by the host read demultiplexing component into a read request for the elastic cache component, read the PMR data from the elastic cache 2 and send it to the host read demultiplexing component, so as to be subsequently sent to the host end. The read PMR request output by the host read demultiplexing component here is equivalent to the read operation request parsed by the host read demultiplexing component above;

[0141] 2) Initiate a request to the write device arbiter component according to the amount of data written to the elastic cache component, and initiate a read request to the read device arbiter component according to the PMR read request;

[0142] 3) Respond to the configuration register-based redirection mapping data sending request issued by the firmware in the SSD controller on the device side. The data source can come from the configuration register or from the elastic cache component;

[0143] 4) Respond to the redirected data read / write request in the DMA mode based on the configuration register issued by the firmware in the device-side SSD controller, write the data from elastic cache 2 to the host side or write the data to elastic cache 1 through DMA control. Furthermore, elastic cache 1 is used to cache host write data; elastic cache 2 is used to cache host read data.

[0144] An NVMe controller provided in an embodiment of the present application is a high-performance PMR control device. By using the NVMe controller, some DDR capacity of the NVMe solid-state hard disk on the device side can be allocated for use as permanent memory on the host side, thereby alleviating the pressure of insufficient memory on the host side and solving the problem of data loss after power failure of the host memory.

[0145] An embodiment of the present application also provides a storage medium, which includes stored instructions, wherein when the instructions are executed, the device where the storage medium is located is controlled to execute the above-mentioned NVMe permanent memory allocation method.

[0146] The present application also provides an electronic device, whose structural diagram is as follows: Figure 4 As shown, it specifically includes a memory 601 and one or more instructions 602, wherein the one or more instructions 602 are stored in the memory 601 and are configured to be executed by one or more processors 603 to execute the one or more instructions 602 to perform the above-mentioned NVMe permanent memory allocation method.

[0147] It should be noted that the information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0148] The specific implementation processes and derivative methods of the above-mentioned embodiments are all within the protection scope of the present invention.

[0149] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.

[0150] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0151] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for allocating NVMe persistent memory. It is characterized in that include: When the host determines that the device is an NVMe device, the host reads the persistent memory configuration information of the NVMe controller of the device, where the persistent memory configuration information is information for configuring the persistent memory function of the device during the power-on initialization phase; Configure various protocol registers of the NVMe controller in the device end, and enable the persistent memory function of the device end; The waiting time after enabling the persistent memory function of the device side is counted in real time. When the waiting time is greater than or equal to the preset waiting time in the persistent memory configuration information, the double rate synchronous dynamic random access memory in the NVMe solid state drive of the device side is used as the persistent memory of the host side, so that the host side can perform read and write operations on the persistent memory.

2. The method according to claim 1, It is characterized in that The host performs a write operation on the persistent memory, including: The host terminal sends a write operation request to the device terminal; The device side sends the write operation request to the host write demultiplexing component in the NVMe controller of the device side, so that the host write demultiplexing component performs address resolution on the write operation request; The host write demultiplexing component sends the parsed write operation request to the redirection controller in the NVMe controller; The redirection controller obtains the first cache data from the host side based on the parsed write operation request, writes the first cache data into the elastic cache component in the NVMe controller, and determines whether the elastic cache component meets the preset first processing condition; when the elastic cache component meets the preset first processing condition, the redirection controller initiates a read cache operation on the elastic cache component to read the second cache data from the elastic cache component; The redirection controller initiates the write device arbitrator component in the NVMe controller to arbitrate the write request of the second cache data; When the write request of the second cache data passes arbitration, the second cache data is written into the permanent memory.

3. The method according to claim 1, It is characterized in that The host performs a read operation on the persistent memory, including: The host terminal sends a read operation request to the device terminal; The device side sends the read operation request to the host read demultiplexing component in the NVMe controller of the device side, so that the host read demultiplexing component performs address resolution on the read operation request; The host read demultiplexing component sends the parsed read operation request to the redirection controller in the NVMe controller; After receiving the parsed read operation request, the redirection controller initiates a read request to the permanent memory, and reads the third cache data from the permanent memory based on the read request, uses the read device arbitrator component in the NVMe controller to arbitrate the third cache data, and writes the arbitrated third cache data into the elastic cache component in the NVMe controller, and determines whether the elastic cache component meets a preset first processing condition. When it is determined that the elastic cache component meets the first processing condition, the redirection controller initiates a read cache operation to the elastic cache component to obtain fourth cache data from the elastic cache component, and sends the fourth cache data to the host end.

4. The method according to any one of claims 2 or 3, It is characterized in that The determining whether the elastic cache component satisfies a preset first processing condition includes: Determining whether the amount of data cached in the elastic cache component exceeds a preset cache detection line; When the amount of data cached in the elastic cache component does not exceed the preset cache detection line, determining whether the statistical duration for which the elastic cache component is continuously in a non-empty state is greater than a preset duration; When the statistical length of time that the elastic cache component is continuously in a non-empty state is not greater than a preset length of time, determining that the elastic cache component does not meet the first processing condition; When the amount of data cached in the elastic cache component exceeds a preset cache detection line, or the statistical time length for which the elastic cache component is continuously in a non-empty state is greater than or equal to a preset time length, it is determined that the elastic cache component meets the first processing condition.

5. The method according to claim 3, It is characterized in that The sending the fourth cache data to the host end includes: The redirection controller sends the fourth cache data to the first AXI interface in the NVMe controller through the host read-connect multiplexing component, so that the first AXI interface sends the fourth cache data to the host end through the PICe interface.

6. The method according to claim 1, It is characterized in that Also includes: When power is lost on the device side, the solid-state hard disk controller in the device side flushes the cached data in the permanent memory and the configuration information of the permanent memory to the preset non-volatile memory, so that when the device side is powered on next time, the cached data in the non-volatile memory is loaded into the permanent memory of the device side, and the permanent memory of the device side is configured based on the configuration information in the non-volatile memory.

7. An NVMe controller, It is characterized in that The NVMe controller is arranged at the device end, and the NVMe controller comprises: a first AXI interface, a host demultiplexing module, a persistent memory controller, a device arbiter module, a second AXI interface, and a protocol register component; The first AXI interface is used to connect to the PICe interface of the host side and perform data transmission with the host side; The host demultiplexing module is used to perform address resolution on the operation request sent by the host, and send the resolved operation request to the persistent memory controller; The permanent memory controller is used to perform read and write control on the double rate synchronous dynamic random access memory in the host side and the device side as the permanent memory of the host side based on the received operation request; The device arbitrator module is used to arbitrate requests generated when the persistent memory controller performs read and write control; The second AXI interface is used to connect to the interface of the double rate synchronous dynamic random access memory of the device end, and perform data transmission with the double rate synchronous dynamic random access memory; The protocol register component includes a plurality of registers, which are used to implement read and write control of each of the registers.

8. The NVMe controller according to claim 7, It is characterized in that The host demultiplexing module comprises: A host read demultiplexing component and a host write demultiplexing component; The host read demultiplexing component is used to perform address resolution on an operation request of a read operation type sent by the host end; The host write demultiplexing component is used to perform address resolution on an operation request of a write operation type sent by the host.

9. The NVMe controller according to claim 7, It is characterized in that The persistent memory controller comprises: Configuration register component, redirection controller and elastic cache component; The configuration register component is used to redirect address mapping registers of command configuration registers of the host side, the device side and the redirection controller; The redirection controller is used to convert a write permanent memory request output by a host write demultiplexing component in the host demultiplexing module into a write request for the elastic cache component, and write permanent memory data corresponding to the write permanent memory request into the elastic cache component; to convert a read permanent memory request output by a host read demultiplexing component in the host demultiplexing module into a read request for the elastic cache component, read permanent memory data corresponding to the read permanent memory request from the elastic cache component, and send the read permanent memory data to the host read demultiplexing component; and to initiate a write request to the write device arbitrator component in the device arbitrator module according to the amount of data written to the elastic cache component, and to initiate a read request to the read device arbitrator component in the device arbitrator module according to the read permanent memory request.

10. The NVMe controller according to claim 7, It is characterized in that The device arbitrator module comprises: a read device arbitrator component and a write device arbitrator component; The read device arbitrator component is used to arbitrate various types of read requests; The write device arbitrator component is used to arbitrate various write requests.

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