Storage device and recovery operation method thereof

Abstract

The invention discloses a storage device and a recovery operation method thereof. The memory device includes a flash memory including a selected word line and an adjacent word line adjacent to the selected word line; and a memory controller configured to supply a select read voltage to a selected word line and a pass voltage to the adjacent word line during a read operation, the pass voltage being higher than the select read voltage, the memory controller is further configured to determine whether the selected word line is a hot spot read word line based on a degradation level of the adjacent word line, and perform a word line recovery operation on the adjacent word line when the selected word line is a hot spot read word line.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0075157 filed on June 12, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the present disclosure described herein relate to a semiconductor memory device, and more particularly, to a memory device including a read reclamation module and a reclamation operation method thereof. Background Art

[0003] Semiconductor memory can be divided into two main types: volatile memory and non-volatile memory. Compared with non-volatile memory, volatile memory (e.g., dynamic random access memory (DRAM) or static random access memory (SRAM)) generally provides faster read and write speeds. However, once the power is turned off, the data in volatile memory is lost. In contrast, non-volatile memory saves data even when there is no power.

[0004] Flash memory is a common form of non-volatile memory that can store multiple bits of data (usually two or more) in a single memory cell. Flash memory can have at least one erased state and multiple programmed (eg, written) states determined by threshold voltage distributions.

[0005] Flash memory contains read margins between each of its programmed states to ensure data integrity. However, the threshold voltage of a flash memory cell may shift due to various reasons, such as coupling noise, pass voltage disturbance, program voltage disturbance, or read pass voltage disturbance. These changes may cause the threshold voltage of the memory cell to increase, resulting in an overlap between the first programmed state and the second programmed state.

[0006] During a read operation in a flash memory, a select read voltage may be provided to a selected word line, and a high voltage read pass voltage may be provided to an unselected word line. If a high voltage read pass voltage is repeatedly applied to an unselected word line, it may stress the memory cell, resulting in an increase in the memory cell threshold voltage. As a result, a read failure may occur during a read operation. Summary of the invention

[0007] Example embodiments of the present disclosure provide a memory device that may selectively perform a block reclamation operation or a word line reclamation operation during a hotspot read operation.

[0008] Example embodiments of the present disclosure provide a memory device that can reduce read disturbance caused by a read failure and reduce the number of write operations of a flash memory by performing a word line reclamation operation instead of a block reclamation operation.

[0009] According to an embodiment of the present disclosure, a storage device is provided, which includes: a flash memory, including a selected word line and an adjacent word line adjacent to the selected word line; and a memory controller, which is configured to: provide a selection read voltage to the selected word line during a read operation, and provide a pass voltage to the adjacent word line, the pass voltage being higher than the selection read voltage, wherein the memory controller is further configured to: determine whether the selected word line is a hotspot read word line based on a degradation level of the adjacent word line, and when the selected word line is the hotspot read word line, perform a word line recovery operation on the adjacent word line.

[0010] According to an embodiment of the present disclosure, a storage device is provided, which includes: a flash memory including a first word line and a second word line adjacent to the first word line; and a memory controller, configured to: provide a selection read voltage to the first word line during a read operation, and provide a pass voltage to the second word line, the pass voltage being higher than the selection read voltage, wherein the memory controller is further configured to: determine whether the first word line is a hotspot read word line based on a degradation level of the second word line, and perform a block recovery operation or a word line recovery operation based on whether the first word line is the hotspot read word line.

[0011] According to an embodiment of the present disclosure, a recycling operation method of a storage device including a flash memory is provided, the recycling operation method comprising: determining whether a second word line adjacent to a first word line of the flash memory is a degraded word line; when the second word line is a degraded word line, determining whether the first word line is a hotspot read word line; and when the first word line is a hotspot read word line, performing a word line recycling operation on the second word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0013] Figure 1 is a block diagram illustrating a storage device according to an example embodiment of the present disclosure.

[0014] Figure 2 It is shown Figure 1 A block diagram of a memory device shown in FIG.

[0015] Figure 3 It is shown Figure 2 A circuit diagram of an example embodiment of a memory block of a memory cell array is shown in FIG.

[0016] Figure 4 It is shown Figure 3 A circuit diagram of a cell string selected by a first string selection line among cell strings of a memory block shown in FIG.

[0017] Figure 5 It is shown Figure 4 Graph of an example embodiment of a threshold voltage distribution of a memory cell shown in .

[0018] Figure 6 It is shown Figure 1 A block diagram of an example embodiment of a memory controller in FIG.

[0019] Figure 7 It is shown Figure 6 Schematic diagram of the block recycling operation method of the read recycling module shown in .

[0020] Figure 8 It is shown Figure 6 Schematic diagram of the word line reclamation operation method of the read reclamation module shown in .

[0021] Fig. 9 It is used to explain Figure 6 A flowchart of the operating method of the read recovery module is shown in .

[0022] Fig.10 It is shown Figure 6 Flowchart of the word line reclamation operation of the read reclamation module shown in .

[0023] Fig.11 is a block diagram illustrating a memory controller performing a read reclaim operation using a cache memory.

[0024] Fig.12 It is used to explain Fig.11 Flowchart of the word line reclamation operation of the read reclamation module shown in .

[0025] Fig.13 is a diagram illustrating a random interval proximity check (RINC) operation of a memory device according to an example embodiment of the present disclosure.

[0026] Fig.14 is a flowchart illustrating a RINC operation of a memory device according to an example embodiment of the present disclosure.

[0027] Fig.15 is a diagram illustrating an example embodiment of a flash memory having a multi-stack structure.

[0028] Fig.16 is a block diagram illustrating an example of a storage device implemented as a solid state drive (SSD) according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Hereinafter, exemplary embodiments of the present disclosure will be described in detail.

[0030] Figure 11 is a block diagram showing a storage device according to an example embodiment of the present disclosure. The storage device 1000 may be a flash memory storage device based on flash memory. For example, the storage device 1000 may be implemented as a solid state drive (SSD), a universal flash storage (UFS), a memory card, etc.

[0031] Reference Figure 1 , the memory device 1000 may include a memory device 1100 and a memory controller 1200. The memory device 1100 may receive an input / output signal IO from the memory controller 1200 through an input / output line, receive a control signal CTRL through a control line, and receive external power PWR through a power line. The memory device 1000 may store data in the memory device 1100 under the control of the memory controller 1200.

[0032] The memory device 1100 may include a memory cell array 1110 and a peripheral circuit 1115. The memory cell array 1110 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may have a vertical three-dimensional (3D) structure. Each memory block may include a plurality of memory cells. Multi-bit data may be stored in each memory cell. For example, more than one bit (typically two or three bits) may be stored in a single memory cell by assigning multiple voltage levels to represent different data states.

[0033] In terms of design layout structure, the memory cell array 1110 may be located (eg, disposed) next to or above the peripheral circuit 1115. The structure in which the memory cell array 1110 is located above the peripheral circuit 1115 may be referred to as a cell-on-periphery (COP) structure.

[0034] In an example embodiment, the memory cell array 1110 may be manufactured as a chip separate from the peripheral circuit 1115. Then, an upper chip including the memory cell array 1110 and a lower chip including the peripheral circuit 1115 may be connected to each other by a bonding method. This structure may be referred to as a chip-to-chip (C2C) structure.

[0035] The peripheral circuit 1115 may include an analog circuit and / or a digital circuit required to store data in the memory cell array 1110 or read data stored in the memory cell array 1110. The peripheral circuit 1115 may receive external power PWR through a power line and generate various levels of internal power.

[0036] The peripheral circuit 1115 may receive a command, an address, and / or data from the memory controller 1200 through an input / output line. The peripheral circuit 1115 may store data in the memory cell array 1110 according to the control signal CTRL. Alternatively or additionally, the peripheral circuit 1115 may read the data stored in the memory cell array 1110 and provide the read data to the memory controller 1200.

[0037] The memory controller 1200 may include a read recovery module 2000. The read recovery module 2000 may be implemented as a circuit in hardware. In addition, the memory controller 1200 may also be implemented as a circuit in hardware. If a memory block is read repeatedly, the error bit may increase due to phenomena such as read interference. Before an uncorrectable error occurs in the data stored in the memory block, the operation of moving the data stored in the memory block to another memory block is called a read recovery operation.

[0038] Figure 2 It is shown Figure 1 A block diagram of an example embodiment of a memory device is shown in FIG. Figure 2 , the memory device 1100 may include a memory cell array 1110 and a peripheral circuit 1115 (see Figure 1 ). The peripheral circuit 1115 may include an address decoder 1120, a page buffer circuit 1130, a data input / output circuit 1140, a word line voltage generator 1150, and a control logic 1160. Each of the address decoder 1120, the word line voltage generator 1150, and the control logic 1160 may be implemented as a circuit in hardware.

[0039] The memory cell array 1110 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may be composed of a plurality of pages. Each page may include a plurality of memory cells. Each memory cell may store multi-bit data (e.g., two or more bits). Each memory block may correspond to an erase unit, and each page may correspond to a read unit and / or a write unit.

[0040] The memory cell array 1110 may be formed in a direction perpendicular to the substrate. The gate electrode layer and the insulating layer may be alternately disposed on the substrate. Each memory block (e.g., BLK1) may be connected to one or more string selection lines SSL, a plurality of word lines WL1 to WLm, and one or more ground selection lines GSL. When WLk is the selected word line sWL, the remaining word lines (WL1 to WLk-1, WLk+1 to WLm) are unselected word lines uWL.

[0041] The address decoder 1120 may be connected to the memory cell array 1110 through the string selection line SSL, the ground selection line GSL, and the word lines WL1 to WLm. The address decoder 1120 may select a word line during programming or during a read operation. The address decoder 1120 may receive a word line voltage VWL from the word line voltage generator 1150 and provide a program voltage or a read voltage to the selected word line.

[0042] The page buffer circuit 1130 may be connected to the memory cell array 1110 through the bit lines BL1 to BLz. The page buffer circuit 1130 may temporarily store data to be stored in the memory cell array 1110 or data read from the memory cell array 1110. The page buffer circuit 1130 may include page buffers PB1 to PBz connected to corresponding bit lines. Each page buffer may include a plurality of latches to store or read multi-bit data.

[0043] The input / output circuit 1140 may be internally connected to the page buffer circuit 1130 through a data line, and externally connected to a memory controller through input / output lines IO1 to IOn (refer to Figure 1 , 1200). The input / output circuit 1140 may receive program data from the memory controller 1200 during a program operation. In addition, the input / output circuit 1140 may provide data read from the memory cell array 1110 to the memory controller 1200 during a read operation.

[0044] The word line voltage generator 1150 may receive internal power from the control logic 1160 and generate a word line voltage VWL required to read data or write data. The word line voltage VWL may be provided to a selected word line (sWL) or an unselected word line (uWL) through the address decoder 1120 .

[0045] The word line voltage generator 1150 may include a program voltage generator 1151 and a pass voltage generator 1152. The program voltage generator 1151 may generate a program voltage Vpgm provided to a selected word line sWL during a program operation. The pass voltage generator 1152 may generate a pass voltage Vpass provided to the selected word line sWL and unselected word lines uWL.

[0046] The word line voltage generator 1150 may include a read voltage generator 1153 and a read pass voltage generator 1154. The read voltage generator 1153 may generate a selection read voltage Vrd provided to a selected word line sWL during a read operation. The read pass voltage generator 1154 may generate a read pass voltage Vrdps provided to an unselected word line uWL. The read pass voltage Vrdps may be a voltage sufficient to turn on a memory cell connected to an unselected word line uWL during a read operation.

[0047] The control logic 1160 may control operations (such as reading, writing, and erasing) of the memory device 1100 using a command CMD, an address ADDR, and a control signal CTRL provided from the memory controller 1200. The address ADDR may include a block selection address for selecting a memory block, a row address for selecting a page, and a column address for selecting a memory cell.

[0048] Figure 3 It is shown Figure 2 A circuit diagram of an example embodiment of a memory block BLK1 of a memory cell array shown in FIG. Figure 3 In the memory block BLK1, a plurality of cell strings STR11 to STR8z may be formed between the bit lines BL1 to BLz and the common source line CSL. Each cell string includes a string selection transistor SST, a plurality of memory cells MC1 to MCm, and a ground selection transistor GST.

[0049] The string selection transistor SST may be connected to the string selection lines SSL1 to SSL8. The ground selection transistor GST may be connected to the ground selection lines GSL1 to GSL8. The string selection transistor SST may be connected to the bit lines BL1 to BLz, and the ground selection transistor GST may be connected to the common source line CSL.

[0050] The first to m-th word lines WL1 to WLm may be connected to a plurality of memory cells MC1 to MCm along a row direction. The first to z-th bit lines BL1 to BLz may be connected to a plurality of memory cells MC1 to MCm along a column direction. The first to z-th page buffers PB1 to PBz may be connected to the first to z-th bit lines BL1 to BLz.

[0051] The first word line WL1 may be arranged above the first to eighth ground selection lines GSL1 to GSL8. A plurality of first memory cells MC1 arranged at the same height from the substrate may be connected to the first word line WL1. A second word line WL2 may be arranged above the first word line WL1. A plurality of second memory cells MC2 arranged at the same height from the substrate may be connected to the second word line WL2. In a similar manner, a plurality of third memory cells MC3 to a plurality of m-th memory cells MCm arranged at the same height from the substrate may be connected to the third to m-th word lines WL3 to WLm, respectively.

[0052] Figure 4 It is shown Figure 31 , a circuit diagram of a cell string selected by a first string selection line SSL1 among cell strings of a memory block BLK1 shown in . The eleventh cell string STR11 to the 1zth cell string STR1z may be selected by the first string selection line SSL1. The eleventh cell string STR11 to the 1zth cell string STR1z may be connected to the first bit line BL1 to the zth bit line BLz, respectively. The first page buffer PB1 to the zth page buffer PBz may be connected to the first bit line BL1 to the zth bit line BLz, respectively.

[0053] The eleventh cell string STR11 may be connected to the first bit line BL1 and the common source line CSL. The eleventh cell string STR11 may include a string selection transistor SST selected by the first string selection line SSL1, first to m-th memory cells MC1 to MCm connected to the first to m-th word lines WL1 to WLm, and a ground selection transistor GST selected by the first ground selection line GSL1. The twelfth cell string STR12 may be connected to the second bit line BL2 and the common source line CSL. The 1zth cell string STR1z may be connected to the zth bit line BLz and the common source line CSL.

[0054] The first word line WL1 and the mth word line WLm may be edge word lines (edge ​​WL). For example, the first word line WL1 may be a bottom edge word line, and the mth word line WLm may be a top edge word line. The second word line WL2 and the (m-1)th word line WLm-1 may be edge adjacent word lines. The kth word line WLk may be a selected word line sWL. The (k-1)th word line WLK-1 and the (k+1)th word line WLk+1 may be adjacent word lines adjacent to the selected word line. If the kth word line WLk is the selected word line sWL, the remaining word lines WL1 to WLK-1 and WLk+1 to WLm may be unselected word lines uWL.

[0055] The first memory cell MC1 and the mth memory cell MCm may be edge memory cells. The second memory cell MC2 and the (m-1)th memory cell MCm-1 may be edge adjacent memory cells. The kth memory cell MCk may be a selected memory cell sMC. The (k-1)th memory cell MCk-1 and the (k+1)th memory cell MCk+1 may be memory cells (adjacent MCs) adjacent to the selected memory cell sMC. If the kth memory cell MCk is the selected memory cell sMC, the remaining memory cells MC1 to MCk-1 and MCk+1 to MCm may be unselected memory cells uMC.

[0056] A group of memory cells selected by one string selection line and connected to one word line may be one page. For example, memory cells selected by the first string selection line SSL1 and connected to the k-th word line WLk may be one page. For example, eight pages may be configured on the k-th word line WLk. Among the eight pages, the page connected to the first string selection line SSL1 is a selected page, and the pages connected to the second string selection line SSL2 to the eighth string selection line SSL8 are unselected pages.

[0057] Figure 5 It is shown Figure 4 Graph of an example embodiment of a threshold voltage distribution of memory cells shown in . The horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of memory cells. Figure 5 An example of storing 3-bit data in one memory cell is shown. The 3-bit memory cell can have one of eight states (E0, P1 to P7) according to the threshold voltage distribution. E0 represents an erase state, and P1 to P7 represent program states.

[0058] During a read operation, a selection read voltage Vrd1 to Vrd7 may be provided to a selected word line sWL, and a pass voltage Vps and / or a read pass voltage Vrdps may be provided to an unselected word line uWL. The pass voltage Vps and / or the read pass voltage Vrdps may be a voltage sufficient to turn on a memory cell. For example, the pass voltage Vps may be provided to an adjacent word line WLk±1, and the read pass voltage Vrdps may be provided to an unselected word line other than the adjacent word line. For example, the read pass voltage Vrdps may be provided to unselected word lines WLk+2 to WLm.

[0059] The first selection read voltage Vrd1 may be a voltage level between the erase state E0 and the first program state P1. The second selection read voltage Vrd2 may be a voltage level between the first program state P1 and the second program state P2. In this manner, the seventh selection read voltage Vrd7 may be a voltage level between the sixth program state P6 and the seventh program state P7.

[0060] When the first selection read voltage Vrd1 is applied, the memory cell in the erase state E0 may be a turn-on cell, and the memory cell in the first programming state P1 to the seventh programming state P7 may be a turn-off cell. When the second selection read voltage Vrd2 is applied, the memory cell in the erase state E0 and the first programming state P1 may be a turn-on cell, and the memory cell in the second programming state P2 to the seventh programming state P7 may be a turn-off cell. In this way, when the seventh selection read voltage Vrd7 is applied, the memory cell in the erase state E0 and the first programming state P1 to the sixth programming state P6 may be a turn-on cell, and the memory cell in the seventh programming state P7 may be a turn-off cell.

[0061] During a read operation, the kth word line WLk may be selected. A power supply voltage may be applied to the string selection line SSL1 and the ground selection line GSL1, and the string selection transistor SST and the ground selection transistor GST may be turned on. In addition, a selection read voltage Vrd may be provided to the selected word line sWL, and a read pass voltage Vrdps and / or a pass voltage Vps may be provided to the unselected word line uWL.

[0062] When a read operation is repeatedly performed on the kth word line WLk, a high voltage read pass voltage Vrdps may be repeatedly provided to the remaining word lines. In this case, read interference may occur in the remaining word lines, resulting in distortion of their threshold voltages. When the selection read voltage Vrd is provided, the memory cell connected to the kth word line WLk may be a cut-off cell. In other words, when the threshold voltage of the kth memory cell is higher than the selection read voltage Vrd, the kth memory cell may be a cut-off cell. When the kth memory cell is a cut-off cell, the channel may be separated in the kth memory cell. In other words, the lower channel of the kth memory cell may receive a ground voltage from the common source line CSL, and the upper channel of the kth memory cell may have a negative channel voltage Vneg.

[0063] In the case where the kth memory cell is inserted between the lower channel and the upper channel, a channel voltage difference may occur between the lower channel and the upper channel. The presence of the voltage difference across the channel may cause hot carrier injection (HCI) in the adjacent memory cell MCk±1. Therefore, the threshold voltage of the memory cell connected to the adjacent word line WLk±1 may be distorted. For example, the threshold voltage of the memory cell in the erased state E0 may rise to enter the programmed state (e.g., P1).

[0064] Figure 6 It is shown Figure 1 A block diagram of an example embodiment of a memory controller in FIG. Figure 6, the memory controller 1200 may include a host interface 1201, a flash memory interface 1202, a control unit 1210, a working memory 1220, and an error correction code (ECC) circuit 1240. The working memory 1220 may drive a flash translation layer (FTL) 1230. Each component of the memory controller 1200 may be implemented as a circuit in hardware.

[0065] The memory controller 1200 may further include various components. For example, the memory controller 1200 may include a buffer memory for temporarily storing data generated by a read operation or a write operation of the flash memory 1100. The memory controller 1200 may further include a buffer control module for controlling the buffer memory, or a command generation module for generating a command (CMD) for controlling a memory operation according to a request from the host 1500, etc.

[0066] The host interface 1201 may provide an interface between the host 1500 and the memory controller 1200. The host interface 1201 may include various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), IEEE1394, Universal Serial Bus (USB), Secure Digital (SD), Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Storage (UFS), Compact Flash (CF), etc.).

[0067] The flash memory interface 1202 may provide an interface between the flash memory 1100 and the memory controller 1200. For example, write data may be sent to the flash memory 1100 and read data may be received from the flash memory 1100 through the flash memory interface 1202. The flash memory interface 1202 may provide commands and addresses to the flash memory 1100. The flash memory interface 1202 may provide data read from the flash memory 1100 to the memory controller 1200.

[0068] The control unit 1210 may include a central processing unit or a microprocessor, and may control the overall operation of the memory controller 1200. The control unit 1210 may drive firmware loaded in the working memory 1220 to control the memory controller 1200.

[0069] The working memory 1220 may be implemented using various types of memories such as DRAM, SRAM, or phase change RAM (PRAM). The working memory 1220 may drive a flash translation layer (FTL) 1230 under the control of the control unit 1210 .

[0070] The flash translation layer 1230 may be loaded from the flash memory 1100 to the working memory 1220 during a boot operation of the storage device 1000. According to the functions implemented by the firmware, the flash translation layer 1230 may include an address mapping module 1231, a garbage collection module 1232, a wear leveling module 1233, and / or a read recovery module 2000. The read recovery module 2000 may be a circuit.

[0071] The address mapping module 1231 may perform address mapping operations on a page-by-page or block-by-block basis. The page address mapping operation is an operation of converting a logical page address received from the file system into a physical page address in the flash memory 1100. To this end, a page-level address mapping table must be maintained in the working memory 1220. The page address mapping operation may provide good garbage collection performance, but requires a large address mapping table.

[0072] The block address mapping operation is an operation of converting a logical block address received from the file system into a physical block address in the flash memory 1100. Pages belonging to the same logical block may belong to the same physical block. To this end, a block-level address mapping table must be maintained in the working memory 1220. The block address mapping operation requires a small address mapping table, but may require additional garbage collection operations to be performed.

[0073] The flash translation layer 1230 may perform a hybrid mapping operation that combines the advantages of a page address mapping operation and a block address mapping operation. The flash translation layer 1230 may perform a hybrid mapping operation based on a log buffer. The hybrid mapping operation based on the log buffer requires a small memory space while providing good garbage collection performance.

[0074] The garbage collection module 1232 may perform garbage collection operations by referring to the address mapping table. The garbage collection module 1232 may use the address mapping table to protect one or more free blocks. The garbage collection module 1232 may use the address mapping table to move one or more valid data stored in a source block to a target block. The garbage collection module 1232 may create a free block by erasing a source block from which all valid data has been moved.

[0075] The wear leveling module 1233 can manage the wear level of the memory cells of the flash memory 1100. The memory cells may degrade due to write operations and erase operations, etc. Degraded memory cells may cause defects. The wear leveling module 1233 can prevent specific cell areas from wearing out faster than other cell areas by managing the program-erase cycle of the memory cell array 1110. The wear leveling module 1233 can control the address mapping module 1231 so that the program-erase time is equally allocated to the cell areas of the memory cell array 1110.

[0076] The read reclaim module 2000 may perform a read reclaim operation. The read reclaim operation is an operation of moving data stored in a memory block to another memory block before an uncorrectable error occurs in the data stored in the memory block. The read reclaim module 2000 may perform a block reclaim operation and / or a word line reclaim operation.

[0077] The read reclaim module 2000 can perform block reclaim operations on a memory block basis. Figure 7 The block reclamation operation is explained in more detail in FIG. The read reclamation module 2000 may perform word line reclamation operations on a word line basis. Figure 8 The word line reclamation operation is explained in more detail in .

[0078] The read reclaim module 2000 may selectively perform block reclaim operations and word line reclaim operations. In addition, the garbage collection module 1232 may perform block reclaim operations, and the read reclaim module 2000 may perform word line reclaim operations. In the case of a hotspot read mode, a word line reclaim operation may be performed on the adjacent word line that experiences the most severe read disturbance.

[0079] The ECC circuit 1240 may generate ECC to correct a failed bit or an erroneous bit of data received from the flash memory 1100. The ECC circuit 1240 may perform error correction coding on the data provided to the flash memory 1100 to form data to which parity bits are added. The parity bits may be stored in the flash memory 1100.

[0080] The ECC circuit 1240 may perform error correction decoding on data output from the flash memory 1100. The ECC circuit 1240 may use parity check to correct errors. The ECC circuit 1240 may use coded modulation (such as low-density parity check (LDPC) code, Bose, Chaudhuri and Hocquenghem (BCH) code, turbo code, Reed-Solomon code, convolutional code, recursive systematic code (RSC), trellis coded modulation (TCM) and block coded modulation (BCM)) to correct errors.

[0081] The ECC circuit 1240 may have an error correction allowable range. For example, the ECC circuit 1240 may correct up to 40 bits of error for a 2K byte page of data. In this case, the maximum allowable range of error correction by the ECC circuit 1240 is 40 bits. In other words, if an error exceeding 40 bits occurs, the ECC circuit 1240 cannot correct the error in the page. A page whose error cannot be corrected is referred to as a defective page. A memory cell in which an error occurs in a defective page is referred to as a defective cell.

[0082] During a read operation, the flash memory 1100 may provide a selection read voltage Vrd to a selected word line sWL, and provide a pass voltage Vps or a read pass voltage Vrdps to an unselected word line uWL. The pass voltage Vps may be provided to an adjacent word line WLk±1. The read pass voltage Vrdps may be provided to the remaining unselected word lines uWL. Figure 5 As shown in , the pass voltage Vps may be higher than the read pass voltage Vrdps.

[0083] In the case of the hotspot read mode, a read operation may be repeatedly performed on a selected word line (eg, WLk). When the read operation on WLk is repeatedly performed, the select read voltage (see Figure 5 , Vrd1, Vrd2, ..., Vrd7) are provided to WLk, and a pass voltage Vps may be applied to WLk±1. A read pass voltage Vrdps may be applied to the remaining unselected word lines uWL. When a hotspot read operation is performed, memory cells connected to adjacent word lines WLk±1 may degrade rapidly.

[0084] Figure 7 It is shown Figure 6 The flash memory 1100 may perform a block reclamation operation under the control of the read reclamation module 2000 .

[0085] Reference Figure 7 , the flash memory 1100 may include memory blocks BLKa to BLKd. A hotspot read operation may be performed in the a-th memory block BLKa. Due to the hotspot read operation on the selected word line WLk, read interference may occur in the adjacent word line WLk±1. The read recovery module 2000 may check the degradation state of the memory cells in the adjacent word line WLk±1 and perform a block recovery operation to prevent a read failure due to read interference.

[0086] If the read recovery module 2000 determines that the memory cell connected to the adjacent word line WLk±1 of the ath memory block BLKa is degraded, the read recovery module 2000 may move the data of the memory cell connected to the adjacent word line WLk±1 to the bth memory block BLKb through a block recovery operation. Due to the hotspot read operation on the selected word line WLk in the bth memory block BLKb, read interference may occur again in the adjacent word line WLk±1. The read recovery module 2000 may perform a block recovery operation on the cth memory block BLKc to prevent read failure. When degradation occurs in the cth memory block BLKc, the read recovery module 2000 may move the data of the memory cell connected to the adjacent word line WLK±1 to the dth memory block BLKd through a block recovery operation.

[0087] The read recovery module 2000 can prevent read failures due to read disturbances through block recovery operations without distinguishing the host read mode. The read recovery module 2000 can perform a block recovery operation when a specific read count is reached. For example, when 1000 read operations are performed on the selected word line WLk of the a-th memory block BLKa, the read recovery module 2000 can perform a block recovery operation on the b-th memory block BLKb.

[0088] Figure 8 It is shown Figure 6 The read recovery module 2000 can distinguish the hotspot read mode under the control of the read recovery module 2000 and perform the word line recovery operation.

[0089] Reference Figure 8 , the flash memory 1100 may include memory blocks BLKa and BLKb. The read recovery module 2000 may perform a recovery operation only on a specific word line based on the hotspot read mode. For example, the read recovery module 2000 may perform a word line recovery operation only on adjacent word lines WLk±1.

[0090] If a read operation is repeatedly performed on a selected word line WLk by a hotspot read mode, degradation due to read disturbance may progress faster in the adjacent word lines WLk±1 than in the selected word line WLk. When degradation of memory cells connected to the adjacent word lines WLk±1 progresses sufficiently, the number of error bits of memory cells connected to the selected word line WLk may be low.

[0091] However, in cases other than the hotspot read mode, even if the read operation is repeated, the degradation levels of the memory cells due to the read interference of the selected word line WLk and the adjacent word lines WLk±1 may be similar. In other words, when the degradation of the memory cells connected to the adjacent word lines WLk±1 is sufficiently advanced, the number of error bits in the memory cells connected to the selected word line WLk may be relatively higher than the number of error bits in the case of the hotspot read mode.

[0092] The read recovery module 2000 may determine a hotspot read mode (or determine whether the selected word line WLk is a hotspot read word line) based on the degradation level of the selected word line WLk, and perform a word line recovery operation on the adjacent word line WLk±1. The read recovery module 2000 may move data stored in the adjacent word line WLk±1 of the a-th memory block BLKa to the b-th memory block BLKb. The read recovery module 2000 may reduce the write amplification factor (WAF) and improve the quality of service (QoS) by performing a recovery operation only on the degraded adjacent word line WLk±1.

[0093] Fig. 9 It is used to explain Figure 6 The flowchart of the operation method of the read reclamation module is shown in FIG. The read reclamation module 2000 can perform a block reclamation operation and / or a word line reclamation operation. Fig. 9 The read reclamation module 2000 is shown to perform a word line reclamation operation using the number of error bits of adjacent word lines.

[0094] In operation S110, the read recovery module 2000 may select WLk. WLk may be a selected word line on which a read operation is repeatedly performed by a hotspot read mode. When a read operation is performed by a hotspot read mode, a selection read voltage Vrd may be repeatedly provided to WLk. Since the selection read voltage Vrd is relatively lower than the pass voltage Vps or the read pass voltage Vrdps, the memory cell connected to WLk may have a relatively low degree of degradation.

[0095] In operation S120, the read recovery module 2000 may determine the degradation level of WLk±1. WLk±1 may be a neighboring word line immediately adjacent to the selected word line WLk on which the read operation is repeatedly performed by the hotspot read mode. The read recovery module 2000 may determine the degradation level of WLk±1 based on whether the number of error bits of the memory cells connected to WLk±1 is greater than a first threshold value Th1.

[0096] The number of error bits in the memory cells connected to WLk±1 can be determined in several ways. For example, the read recovery module 2000 can use the ECC circuit 1240 in the memory controller 1200 to determine the number of error bits of WLk±1. Alternatively, the read recovery module 2000 can use the pass / fail check logic within the flash memory 1100 to determine the number of error bits.

[0097] If the number of error bits of WLk±1 is not greater than the first threshold Th1 (No), the read recovery module 2000 may not perform a word line recovery operation. If the number of error bits of WLk±1 is greater than the first threshold Th1 (Yes), the read recovery module 2000 may perform operation S130.

[0098] In operation S130, the read recovery module 2000 may determine whether the selected word line WLk is a hotspot read word line. If the selected word line WLk is not a hotspot read word line (No), the read recovery module 2000 may not perform a word line recovery operation. If the selected word line WLk is a hotspot read word line (Yes), the read recovery module 2000 may perform operation S140.

[0099] When a user repeatedly reads data from a specific file, the host may request a hotspot read from the memory device 1000. The read reclaim module 2000 may receive a read request from the host and determine whether a selected word line WLk is a hotspot read word line.

[0100] In operation S140, the read recovery module 2000 may perform a word line recovery operation on the adjacent word lines WLk±1. If a read operation is repeatedly performed on the selected word line WLk through the hotspot read mode, degradation due to read disturbance at the adjacent word lines WLk±1 may rapidly proceed.

[0101] The read recovery module 2000 may determine a hotspot read mode based on the degradation level of the selected word line WLk, and perform a word line recovery operation on the adjacent word lines WLk±1. The read recovery module 2000 may determine whether WLk is a hotspot read word line based on whether the number of error bits of the memory cells connected to the selected word line WLk is greater than a predetermined threshold. In one embodiment, if the number of error bits of WLk is greater than a predetermined threshold, the read recovery module 2000 may determine that WLk is a hotspot read word line. The read recovery module 2000 may reduce WAF and improve QoS by performing a recovery operation only on the degraded adjacent word lines WLk±1.

[0102] Fig.10 It is shown Figure 6 The flowchart of the word line reclamation operation of the read reclamation module is shown in FIG. The read reclamation module 2000 may use the read counts of the neighboring word lines to perform the word line reclamation operation.

[0103] In operation S210, the read reclaim module 2000 may select WLk. WLk may be a selected word line on which a read operation is repeatedly performed through a hotspot read mode.

[0104] In operation S220, the read recovery module 2000 may determine whether the read count of the adjacent word line WLk±1 is greater than the second threshold Th2. If the read count of the adjacent word line WLk±1 is not greater than the second threshold Th2 (No), the read recovery module 2000 may not perform the word line recovery operation. If the read count of the adjacent word line WLk±1 is greater than the threshold Th2 (Yes), the read recovery module 2000 may perform operation S230.

[0105] The read count of the memory cells connected to the adjacent word line WLk±1 may be determined in several ways. For example, the read recovery module 2000 may receive the read count of the adjacent word line WLk±1 from the host 1500. The read recovery module 2000 may calculate the read count using a read count circuit within the memory controller 1200. Alternatively, the read recovery module 2000 may determine the read count using a read count circuit in the flash memory 1100.

[0106] In operation S230, the read recovery module 2000 may determine whether the selected word line WLk is a hotspot read word line. The read recovery module 2000 may receive a read request from the host and determine whether the selected word line WLk is a hotspot read word line. If the selected word line WLk is not a hotspot read word line (No), the read recovery module 2000 may not perform a word line recovery operation. If the selected word line WLk is a hotspot read word line (Yes), the read recovery module 2000 may perform a word line recovery operation (i.e., operation S240).

[0107] In operation S240, the read reclamation module 2000 may perform a word line reclamation operation on the adjacent word lines WLk±1. If a read operation is repeatedly performed on the selected word line WLk through the hotspot read mode, degradation due to read disturbance at the adjacent word lines WLk±1 may rapidly proceed.

[0108] The read recovery module 2000 may determine a hotspot read mode based on the degradation level of the selected word line WLk, and perform a word line recovery operation on the adjacent word line WLk±1. The read recovery module 2000 may determine whether WLk is a hotspot read word line based on whether the read count of the memory cell connected to the selected word line WLk is greater than a predetermined threshold. In one embodiment, if the read count of WLk is greater than a predetermined threshold, the read recovery module 2000 may determine that WLk is a hotspot read word line. The read recovery module 2000 may reduce WAF and improve QoS by performing a recovery operation only on the degraded adjacent word line WLk±1.

[0109] Fig.11 is a block diagram showing a memory controller that performs a read reclaim operation using a cache memory. Fig.11 , the memory controller 1200 may include a host interface 1201, a flash memory interface 1202, a control unit 1210, a working memory 1220, an ECC circuit 1240, and a cache memory 1250. The working memory 1220 may drive a flash translation layer (FTL) 1230.

[0110] The flash translation layer 1230 may include an address mapping module 1231, a garbage collection module 1232, a wear leveling module 1233, and a read reclamation module 2000. The read reclamation module 2000 may perform a read reclamation operation. The read reclamation operation is an operation of moving data stored in a memory block to another memory block before an uncorrectable error occurs in the data stored in the memory block.

[0111] The read reclaim module 2000 may perform a block reclaim operation and / or a word line reclaim operation. The read reclaim module 2000 may selectively perform a block reclaim operation and a word line reclaim operation. In addition, the garbage collection module 1232 may perform a block reclaim operation, and the read reclaim module 2000 may perform a word line reclaim operation. In the case of a hotspot read mode, a word line reclaim operation may be performed on the adjacent word line that experiences the most severe read disturbance.

[0112] The cache memory 1250 may be implemented using various types of memory such as DRAM, SRAM, or PRAM. The read recovery module 2000 may perform a word line recovery operation on the adjacent word lines WLk±1 during a hotspot read operation, and store the data of the memory cells connected to the selected word line WLk in the cache memory 1250. The cache memory 1250 may store the data of the selected word line WLk that is repeatedly read during the hotspot read operation. The memory controller 1200 may increase the read speed and effectively reduce the read disturbance to the unselected word line uWL.

[0113] Fig.12 It is used to explain Fig.11 The flowchart of the word line reclamation operation of the read reclamation module is shown in FIG. The read reclamation module 2000 may use a cache memory to perform the word line reclamation operation.

[0114] In operation S310, the read reclaim module 2000 may select WLk. WLk may be a selected word line on which a read operation is repeatedly performed through a hotspot read mode.

[0115] In operation S320, the read recovery module 2000 may determine the degradation level of WLk±1. The read recovery module 2000 may determine whether the adjacent word line WLK±1 is a degraded word line. For example, the degradation of the adjacent word line WLk±1 may be determined using the number of error bits or read counts of memory cells connected to the adjacent word line WLk±1.

[0116] like Fig. 9 As described in , if the number of error bits in the adjacent word line is greater than the first threshold Th1, the read recovery module 2000 may determine degradation. Fig.10 As described in , if the read count of the adjacent word line is greater than the second threshold Th2, the read recovery module 2000 may determine degradation. If the adjacent word line WLK±1 is not degraded (No), the read recovery module 2000 may not perform the word line recovery operation. If the adjacent word line WLk±1 is degraded, the read recovery module 2000 may perform operation S330 (Yes).

[0117] In operation S330, the read recovery module 2000 may determine whether the selected word line WLk is a hotspot read word line. The read recovery module 2000 may receive a read request from the host and determine whether the selected word line WLk is a hotspot read word line. If the selected word line WLk is not a hotspot read word line (No), the read recovery module 2000 may not perform a word line recovery operation. If the selected word line WLk is a hotspot read word line (Yes), the read recovery module 2000 may perform a word line recovery operation (i.e., operation S340).

[0118] In operation S340, the read recovery module 2000 may perform a word line recovery operation on the adjacent word line WLk±1. If the read operation is repeatedly performed on the selected word line WLk by the hotspot read mode, degradation due to read interference at the adjacent word line WLk±1 may proceed rapidly. The read recovery module 2000 may determine the hotspot read mode by the degradation level of the selected word line WLk, and perform a word line recovery operation on the adjacent word line WLk±1.

[0119] In operation S350, the read recovery module 2000 may move the data of the selected word line WLk to the cache memory 1250. The read recovery module 2000 may perform a word line recovery operation on the adjacent word lines WLk±1, and then store the data of the selected word line WLk in the cache memory 1250. The cache memory 1250 may store the data of the selected word line WLk that is repeatedly read during the hotspot read operation. The memory controller 1200 may increase the read speed and effectively reduce the read disturbance to the unselected word line uWL.

[0120] Fig.13 is a diagram illustrating a RINC operation of a memory device according to an example embodiment of the present disclosure. The read reclaim module 2000 may perform a random interval proximity check (RINC) operation.

[0121] The RINC operation may refer to a reliability verification operation performed based on environmental information such as the number of error bits or a read count. Here, the environmental information may include program-erase cycles, program counts, erase counts, the number of error bits generated during a read operation, an error rate, threshold voltage variation information, wear level information, degradation information, data input / output time information, temperature information, location information, structure information, state information of neighboring cells, and the like.

[0122] The RINC operation may be a dummy read operation of at least one adjacent word line or at least one open word line. The open word line may represent an unselected word line on which a programming operation is not performed. When there is a read request from a host, whether to perform a read reclaim operation may be determined based on degradation information such as the number of error bits and / or a read count of a corresponding memory block.

[0123] For example, when the read count exceeds a predetermined value, the RINC operation may include a read reclaim operation. Here, the predetermined value may be a random value with a distribution. For example, the predetermined value may be an average value of a predetermined unit. The predetermined value may change during each read reclaim operation.

[0124] Reference Fig.13 , the storage device 1000 may perform a dummy read operation of RINC. Here, the dummy read operation may be part of a reliability verification operation (RINC operation). Unlike performing the dummy read operation in predetermined units according to a read count, the dummy read operation may be performed in variable units.

[0125] For example, in the read stream, a first dummy read operation may be performed after an interval having a read count of 234. A second dummy read operation may be performed after an interval having a read count of 36. A third dummy read operation may be performed after an interval having a read count of 456. And a fourth dummy read operation may be performed after an interval having a read count of 130. A fourth dummy read operation may be performed before an interval having a read count of 196.

[0126] The dummy read operation may be managed differently according to the program-erase cycle of the memory block. According to the program-erase cycle, the initial read count of the dummy read operation or the interval of the dummy read operation may vary. In addition, the dummy read operation may be managed differently according to the region of the memory cell. For example, the initial read count of the dummy read operation or the interval of the dummy read operation may be different according to a single-level cell (SLC) region, a multi-level cell (MLC) region, and a triple-level cell (TLC) region.

[0127] Fig.14 is a flowchart illustrating a RINC operation of a memory device according to an example embodiment of the present disclosure. Fig.14 A RINC operation is shown for checking for read disturb and performing word line reclamation.

[0128] When there are repeated read requests from the host, the data stored in the flash memory 1100 may cause read interference. The flash memory 1100 may perform a RINC operation to prevent read failures caused by read interference. The flash memory 1100 may check the degradation state of the memory cell and determine whether to perform a read recovery operation. If the memory cell is determined to be sufficiently degraded, the flash memory 1100 may reduce the read interference by rewriting the data to another memory block via a read recovery operation.

[0129] In operation S410, the read recovery module 2000 may perform a RINC read operation to select WLk. WLk may be a selected word line for which a read operation is repeatedly performed through a hotspot read mode. When a read operation is performed through the hotspot read mode, a selection read voltage Vrd may be repeatedly provided to the selected word line WLk.

[0130] In operation S420, the read recovery module 2000 may determine whether the adjacent word line WLK±1 is a degraded word line. For example, the number of error bits or the read count of the memory cells connected to the adjacent word line may be used to determine whether the adjacent word line is degraded. If the adjacent word line WLK±1 is not a degraded word line (No), the read recovery module 2000 may repeatedly perform operation S410. When the adjacent word line WLk±1 is degraded (Yes), the read recovery module 2000 may perform operation S430.

[0131] In operation S430, the read recovery module 2000 may determine whether the selected word line WLk is a hotspot read word line. The read recovery module 2000 may receive a read request from the host and determine whether the selected word line WLk is a hotspot read word line. If the selected word line WLk is not a hotspot read word line, the read recovery module 2000 may perform a block recovery operation without performing a word line recovery operation.

[0132] In operation S435, when the selected word line WLk is not a hotspot read word line, the read reclaim module 2000 may register (or designate) block reclaim. In operation S437, if the read count RC of the selected word line WLk is equal to the third threshold Th3, the read reclaim module 2000 may perform a block reclaim operation.

[0133] In operation S440, if the selected word line WLk is a hotspot read word line, the read recovery module 2000 may perform a word line recovery operation on the adjacent word lines WLk±1. The read recovery module 2000 may determine a hotspot read mode by the degradation level of the selected word line WLk, and perform a word line recovery operation on the adjacent word lines WLk±1. The read recovery module 2000 may reduce WAF and improve QoS by performing a recovery operation only on the degraded adjacent word lines WLk±1.

[0134] Fig.15 is a diagram showing an example embodiment of a flash memory having a multi-stack structure. Fig.15 , the flash memory 3000 may have a first stack ST1 and a second stack ST2. The first stack ST1 may be located at the bottom, and the second stack ST2 may be located at the top.

[0135] The column of the flash memory 3000 can be formed by joining the first stack ST1 and the second stack ST2. A plurality of dummy word lines (e.g., Dummy1 WL and Dummy2 WL) may be included at the junction of the first stack ST1 and the second stack ST2. The first stack ST1 may be located between the common source line CSL and the first dummy word line Dummy1 WL. The second stack ST2 may be located between the second dummy word line Dummy2 WL and the bit line BL.

[0136] The first stack ST1 may include a ground selection line GSL, a first edge word line Edge1 WL, and a first stack word line Stack1 WL. The second stack ST2 may include a string selection line SSL, a second stack word line Stack2 WL, and a second edge word line Edge2 WL. The memory cells connected to the first edge word line Edge1 WL and the second edge word line Edge2 WL may store bit data different from other memory cells. For example, the memory cells connected to the first edge word line Edge1 WL and the second edge word line Edge2 WL may be SLC or MLC, and the memory cells connected to other word lines may be TCL or QLC.

[0137] If the selected word line WLk of the first stack ST1 is a hotspot read word line, the read recovery module 2000 may perform a word line recovery operation on the adjacent word lines WLk±1. The read recovery module 2000 may determine a hotspot read mode by the degradation level of the selected word line WLk and perform a word line recovery operation on the adjacent word lines WLk±1.

[0138] The read reclaim module 2000 can move data stored in the degraded adjacent word line WLk±1 of the first stack ST1 to a predetermined word line of the second stack ST2 through a word line reclaim operation. The read reclaim module 2000 can reduce WAF and improve QoS by performing a word line reclaim operation in a flash memory having a multi-stack structure.

[0139] Fig.16 is a block diagram illustrating an example of a storage device implemented as a solid state drive (SSD) according to an example embodiment of the present disclosure. Fig.16 , the SSD 4000 includes a plurality of flash memories 4101 to 4104 and an SSD controller 4200 .

[0140] The first flash memory 4101 and the second flash memory 4102 may be connected to the SSD controller 4200 through a first channel (CH1). The third flash memory 4103 and the fourth flash memory 4104 may be connected to the SSD controller 4200 through a second channel (CH2). The number of channels connected to the SSD controller 4200 may be more than two. And the number of flash memories connected to one channel may be more than two.

[0141] The SSD controller 4200 may include a host interface 4201, a flash memory interface 4202, a buffer interface 4203, a control unit 4210, and a working memory 4220. The SSD controller 4200 may be connected to the host 1500 through the host interface 4201. The SSD controller 4200 may write data to or read data from the flash memory at the request of the host 1500.

[0142] The SSD controller 4200 may be connected to the plurality of flash memories 4101 to 4104 through a flash memory interface 4202, and connected to the buffer memory 1300 through a buffer interface 4203. The flash memory interface 4202 may provide data temporarily stored in the buffer memory 1300 to the flash memory through corresponding channels CH1 and CH2. And the buffer interface 4203 may transfer data read from the flash memories 4101 to 4104 to the buffer memory 1300.

[0143] The control unit 4210 may analyze and process a signal input from the host 1500. The control unit 4210 may control the host 1500 through the host interface 4201 or control the flash memories 4101 to 4104 through the flash memory interface 4202. The control unit 4210 may control operations of the flash memories 4101 to 4104 according to firmware for driving the SSD 4000.

[0144] The SSD controller 4200 may manage data to be stored in the flash memories 4101 to 4104. The SSD controller 4200 may back up data stored in the working memory 4220 or the buffer memory 1300 to the flash memories 4101 to 4104 during a sudden power-off operation.

[0145] The SSD controller 4200 may include the above-mentioned read recovery module 2000 in the control unit 4210. The read recovery module 2000 may perform a word line recovery operation in each flash memory 4101 to 4104 or between different flash memories. The read recovery module 2000 may determine a hotspot read mode based on the degradation level of the selected word line and perform a word line recovery operation on adjacent word lines.

[0146] A memory device according to an example embodiment of the present disclosure may determine whether a hotspot read operation is performed based on the degradation level of a selected word line and perform a word line reclaim operation on adjacent word lines. According to the present disclosure, by performing a reclaim operation only on degraded adjacent word lines, WAF may be reduced and QoS may be improved.

[0147] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A storage device, include: A flash memory including a selected word line and an adjacent word line adjacent to the selected word line; as well as a memory controller configured to: provide a select read voltage to a selected word line during a read operation and provide a pass voltage to the adjacent word line, the pass voltage being higher than the select read voltage, The memory controller is further configured to determine whether the selected word line is a hotspot read word line based on a degradation level of the selected word line, and when the selected word line is a hotspot read word line, perform a word line recycling operation on the adjacent word line.

2. The storage device according to claim 1, in, Flash memory includes: A first memory block includes a selected word line and the adjacent word line; and A second memory block, data of the adjacent word line is moved to the second memory block during a word line reclamation operation.

3. The storage device according to claim 2, in, The memory controller determines whether the selected word line is a hot read word line based on the number of error bits of the selected word line.

4. The storage device according to claim 2, in, The memory controller determines whether the selected word line is a hot read word line based on the read count of the selected word line.

5. The storage device according to claim 2, in, The memory controller also includes a cache memory, Therein, the memory controller performs a word line reclaim operation and then moves data of the selected word line to the cache memory.

6. The storage device according to claim 5, in, The memory controller determines whether the selected word line is a hot read word line based on the number of error bits or the read count of the selected word line.

7. The storage device according to claim 2, in, When the selected word line is not a hotspot read word line, the memory controller moves data of the first memory block to the second memory block through a block reclaim operation.

8. The storage device according to claim 7, in, The memory controller includes a read reclamation module, and If the selected word line is not a hotspot read word line, when the read count of the selected word line reaches a predetermined threshold, the read recycling module moves the data of the first memory block to the second memory block through a block recycling operation.

9. The storage device according to claim 2, in, The memory controller includes a garbage collection module, If the selected word line is not a hotspot read word line, when the read count of the selected word line reaches a predetermined threshold, the garbage collection module moves the data of the first memory block to the second memory block through a block recycling operation.

10. The storage device according to claim 2, in, Flash memory has a multi-stack structure. wherein the first memory block is in a first stack, Therein, the second memory block is in a second stack located on top of the first stack.

11. A storage device, include: A flash memory comprising a first word line and a second word line adjacent to the first word line; as well as a memory controller configured to: provide a select read voltage to a first word line and provide a pass voltage to a second word line during a read operation, the pass voltage being higher than the select read voltage, The memory controller is further configured to determine whether the first word line is a hotspot read word line based on a degradation level of the first word line, and perform a block reclaim operation or a word line reclaim operation based on whether the first word line is a hotspot read word line.

12. The storage device according to claim 11, in, The memory controller performs a wordline reclamation operation when the first wordline is a hotspot read wordline, and the memory controller performs a block reclamation operation when the first wordline is not a hotspot read wordline.

13. The storage device according to claim 11, in, The memory controller determines whether the first word line is a hot read word line based on the number of error bits of the first word line.

14. The storage device according to claim 11, in, The memory controller determines whether the first word line is a hot read word line based on the read count of the first word line.

15. The storage device according to claim 11, in, The memory controller also includes a cache memory, The memory controller performs a word line reclaim operation and then moves data of the first word line to the cache memory.

16. A method for recycling a storage device comprising a flash memory, the method comprising: include: determining whether a second word line adjacent to a first word line of the flash memory is a degraded word line; When the second word line is a degraded word line, determining whether the first word line is a hotspot read word line; and When the first word line is a hotspot read word line, a word line reclamation operation is performed on the second word line.

17. The recycling operation method according to claim 16, further comprising: include: When the first word line is not a hotspot read word line, a block reclaim operation is performed.

18. The recovery operation method according to claim 16, in, Whether the second word line is a degraded word line is determined based on the number of error bits of the second word line.

19. The recovery operation method according to claim 16, in, Whether the second word line is a degraded word line is determined based on the read count of the second word line.

20. The recycling operation method according to claim 16, further comprising: include: After performing a word line reclaim operation on the second word line, data of the first word line is moved to the cache memory.

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