Data processing in memory system

Abstract

A method for a memory system is disclosed. The memory system may include a memory controller and a memory device. The method may include receiving data including bits and to be written to a memory device; counting a first number of bits corresponding to the first state and a second number of bits corresponding to the second state; and executing a flipping operation in response to the fact that the second bit number of the bits is greater than the first bit number of the bits.

Description

Technical Field

[0001] The present application relates to a data processing technique in a memory system. Background Art

[0002] Storage class memory (SCM) can be used as a new layer of memory / storage in the computer memory hierarchy between dynamic random-access memory (DRAM) and NAND flash memory. SCM provides fast non-volatile memory for the processor, which is slightly slower than DRAM but significantly faster than NAND flash memory. The capacity of SCM is equivalent to the size of NAND flash drives and can be addressed at byte granularity. Technologies such as phase change memory (PCM), resistive random-access memory (ReRAN), magnetic random-access memory (MRAM), carbon nanotube random access memory, etc. can be used in SCM. Summary of the invention

[0003] Aspects of the present disclosure provide a method for a memory system. The memory system may include a memory controller and a memory device. The method may include: receiving data to be written into a memory device, the memory device including a memory cell, each memory cell having a first state and a second state, the data including bits, each of the bits corresponding to one of the first state and the second state; counting the first bit number of bits corresponding to the first state and the second bit number of bits corresponding to the second state in the received data; determining whether to perform a first flip operation on the received data based on the second bit number of bits corresponding to the second state and the first bit number of bits corresponding to the first state; in response to the difference that the second bit number of bits corresponding to the second state is greater than the first bit number of bits corresponding to the first state being greater than a threshold, performing a first flip operation to flip the bits in the received data; and storing the received data with the flipped bits to the memory device.

[0004] In an embodiment, the method may further include: storing the received data to a storage device without flipping the bits in the received data in response to the following: a second bit number of bits corresponding to the second state is not greater than a first bit number of bits corresponding to the first state, or the difference between the second bit number of bits corresponding to the second state and the first bit number of bits corresponding to the first state is less than a threshold.

[0005] In an embodiment, the method may further include: generating a flip flag indicating whether a first flip operation has been performed on the received data; and storing the flip flag to a storage device. In an example, the method may further include: reading received data with a flip bit and a flip flag from a storage device, the flip flag indicating whether a first flip operation has been performed on the received data; determining whether to perform a second flip operation on the received data with the flip bit based on the flip flag indicating whether the first flip operation has been performed on the received data; and in response to the flip flag indicating that the first flip operation has been performed on the received data, performing a second flip operation to flip the previously flipped bit in the received data.

[0006] In an example, storing received data with flipped bits to a storage device includes: encoding the received data with flipped bits to generate error correction code (ECC) parity information; and storing the ECC parity information to the storage device. In an example, reading received data with flipped bits from a storage device includes: reading ECC parity information from the storage device; and recovering the received data with flipped bits based on the ECC parity information.

[0007] In an embodiment, the memory device is a phase change memory (PCM) device, and the first state and the second state of the memory cell of the memory device correspond to the crystalline state and the amorphous state of the PCM device, respectively. In an embodiment, the memory device is one of the following: a resistive random access memory, a magnetic random access memory, a carbon nanotube random access memory, and a dynamic random access memory.

[0008] Aspects of the present disclosure also provide a memory system, including: a memory device; and a memory controller including a circuit system. The circuit system can be configured to: receive data to be written into the memory device at the memory controller, the memory device including a storage unit, each storage unit having a first state and a second state, the data including bits, each of the bits corresponding to one of the first state and the second state; count the first bit number of bits corresponding to the first state and the second bit number of bits corresponding to the second state in the received data; determine whether to perform a first flip operation on the received data based on the second bit number of bits corresponding to the second state and the first bit number of bits corresponding to the first state; in response to the difference that the second bit number of bits corresponding to the second state is greater than the first bit number of bits corresponding to the first state is greater than a threshold, perform a first flip operation to flip the bits in the received data; and store the received data with the flipped bits to the memory device.

[0009] An aspect of the present disclosure provides a non-transitory computer-readable medium storing instructions. When the instructions are executed by a processing device, the processing device executes the above method of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be increased or reduced for clarity of discussion.

[0011] Figure 1 A block diagram of a computer system 100 having a memory device according to some aspects of the present disclosure is shown.

[0012] Figure 2 An example of a PCM device 200 according to an embodiment of the present disclosure is shown.

[0013] Figure 3 Temperature profiles 301 - 303 are shown for a reset operation, a set operation, and a read operation in a PCM cell.

[0014] Figure 4 A schematic diagram showing storage information distribution of a storage unit according to an embodiment of the present disclosure is shown.

[0015] Figure 5A A schematic diagram of a codeword 500A according to an embodiment of the present disclosure is shown.

[0016] Figure 5B An example of the layout of the spare data 502 according to an embodiment of the present disclosure is shown.

[0017] Figure 6A flow chart of a data processing process 600 according to an embodiment of the present disclosure is shown.

[0018] Figure 7 Another flow chart of a data processing process 700 according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0019] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the present disclosure may also be used for various other applications. The functions and structural features described in the present disclosure may be combined, adjusted, and modified with each other in a manner not specifically depicted in the accompanying drawings, so that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0020] Typically, a term can be understood at least in part from its use in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, again, terms such as "a", "an" or "the" can be understood to convey singular usage or to convey plural usage, which depends at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but on the contrary, additional factors that are not necessarily explicitly described can be allowed to exist, again, this depends at least in part on the context.

[0021] Figure 1 A block diagram of a computer system 100 having a storage device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data to or receive data from the memory device 104. The memory device 104 may be any memory device disclosed in the present disclosure.

[0022] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. The memory controller 106 can be configured to control the operation of the memory device 104, for example, read, erase and program operations (write operations). The memory controller 106 can also be configured to manage various functions regarding the data stored in the memory device 104 or the data to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) regarding the data read from or written to the memory device 104. Any other suitable function can also be performed by the memory controller 106.

[0023] The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with an external device through at least one of various interface protocols (e.g., USB protocol, multimedia card (MMC) protocol, peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.).

[0024] In some embodiments, the memory system 102 does not include the memory controller 106, and the host 108 is directly coupled to the memory device 104. The memory controller 106 may be located in the host 108. Alternatively, the host 108 may not include the memory controller 106, but may be configured to perform functions similar to those performed by the memory controller 106, as described above or below.

[0025] In various embodiments, the memory device 104 may be based on various memory technologies. In some embodiments, the memory device 104 uses storage class memory (SCM) technology. Examples of SCM technology include phase change memory (PCM), resistive random access memory (ReRAN), magnetic random access memory (MRAM), carbon nanotube random access memory, etc.

[0026] PCM is based on phase change materials. This material can exist in two different phases: an amorphous phase and a crystalline phase. The amorphous phase has a higher resistivity than the crystalline phase. Therefore, these two phases can represent two different memory states of a single-level cell (SLC). By appropriate light or electrical heating, the amorphous phase can be set to the crystalline phase, or the crystalline phase can be reset to the amorphous phase. In some examples, some phase change materials can be controlled to change between more than two states with different resistance levels. Therefore, multi-level cells (MLC) can be realized. Examples of phase change materials may include GeSbTe (GST), N-doped GST, GaSbGe, GeBiTe, physical vapor deposition (PVD) GST, GeTe / SbTe, etc. In some embodiments, phase change chalcogenides are used for PCM.

[0027] ReRAM exploits the physical phenomenon of resistance switching. For example, a dielectric object can experience a change in resistance across the terminals of the dielectric object when subjected to an electric current or an electric field. Switching from a high resistance state to a low resistance state is a set operation, while switching from a low resistance state to a high resistance state is a reset operation. In some examples, the cells of ReRAM (called memristors) can have a metal-insulator-metal structure.

[0028] MRAM can store data using magnetic charge. For example, an MRAM cell can include two magnetic elements stacked one on top of the other. One magnetic element has a fixed magnetic polarity, while the other magnetic element has a switchable (programmable) polarity. Depending on the switchable polarity, the MRAM cell can exhibit parallel magnetic moments of the magnetic elements (with low resistance) or antiparallel magnetic moments of the magnetic elements (with high resistance). The resistance of the cell can be measured by passing a current through the write line to induce a magnetic field across the cell.

[0029] Carbon nanotube random access memory is based on the placement of carbon nanotubes deposited on a chip-like substrate. For example, in a two-terminal cell, the intersecting nanotubes between two electrodes can be either touching or slightly separated. The resistance of the nanotubes that are touching is low, while the resistance of the separated nanotubes is high. The appropriate voltage can be applied to the two terminals to switch the cell between a low-resistance state and a high-resistance state.

[0030] The memory device 104 may include one or more memory cell arrays. In some embodiments, the memory cells of the memory cell array may be SLCs, each SLC having two possible memory states and thus may store one bit of data. For example, a first memory state "0" may correspond to a first resistance range, and a second memory state "1" may correspond to a second resistance range. In some embodiments, the memory cells of the memory array may be MLCs capable of storing more than a single bit of data in more than two memory states. For example, an MLC may store two bits per cell (also referred to as a double-level cell (DLC)), three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)).

[0031] In some embodiments, the memory device 104 is a dynamic random access memory (DRAM). In an example, the memory cells of such a DRAM can be made of capacitors and transistors. The capacitor can be charged or discharged. These two states can represent two values ​​of a bit, 0 and 1. The memory refresh circuit can be configured to periodically rewrite the data in the capacitor.

[0032] According to aspects of the present disclosure, the memory controller 106 may be configured to perform data processing to convert the data from an original form to a target form before writing the data to the storage device 104. The target form is friendlier to the storage device 104 than the original form of the data. For example, the storage device 104 employs PCM technology. The storage cells in the storage device 104 use an amorphous phase to represent the binary digit (bit) 0, and use a crystalline phase to represent the binary digit (bit) 1. Writing the number 0 involves more reset operations, while writing the number 1 involves more set operations. According to the present disclosure, the reset operation applies a stronger current and high temperature to the phase change material in the storage cell, and therefore has a greater negative impact on the durability of the storage cell than the set operation, and also consumes more power. Therefore, the digital sequence to be written to the storage device 104 preferably includes more 1s than 0s.

[0033] In order to improve the durability of the memory cell and save power, the memory controller 106 can be configured to investigate the number of 1s and 0s in the sequence of numbers (or bits) in the data. In some embodiments, when the number of 0 bits is greater than the number of 1 bits, the memory controller 106 can use an inverter to flip the bits in the sequence. For example, as a result of the flip or inversion operation, a 0 bit becomes a 1 bit, and a 1 bit becomes a 0 bit. The resulting sequence will include more 1 bits than 0 bits. Writing such a sequence will produce fewer reset operations (the reset operation transforms the crystalline phase into an amorphous phase) than writing the original sequence.

[0034] A flip flag may be generated and stored in the memory device 104 along with the corresponding data segment. The flip flag may indicate whether a bit flip operation has been applied to the corresponding data. When the data segment is read, the associated flip flag may also be retrieved from the memory device 104. The memory controller 106 may determine whether to perform a reverse transformation on the corresponding data to obtain the original data based on the value of the flip flag.

[0035] Although PCM is used in some examples to explain data conversion schemes, the inventive concepts of the present disclosure are not limited to any particular memory technology. Various memory technologies may employ different materials, device structures, or operating principles, and corresponding memory devices may have different properties. Whenever a memory device exhibits a preference for a particular bit pattern (0 or 1) in data (e.g., a percentage of 0 bits and 1 bits), and the preference may be motivated by a variety of possible reasons such as saving power, improving durability, or any other reason, the data conversion scheme disclosed herein may be employed.

[0036] Figure 2 2 shows an example of a PCM device 200 according to an embodiment of the present disclosure. The PCM device 200 may communicate with a memory controller (eg, Figure 1The PCM device 200 communicates with the memory controller 106 in the memory bank. Data and addresses can be transmitted between the PCM device 200 and the memory controller. The PCM device 200 includes a die having a set of memory banks 202. Each memory bank 202 includes a memory array 204 (also referred to as a memory cell array) having memory cells arranged in rows and columns. The memory array 204 can be divided into a plurality of memory sub-arrays 208 for efficient wiring and low power consumption. In some embodiments, each memory cell or at least one memory cell in the memory cell includes a PCM cell. As described above, the PCM cell can be programmed to a set state or a reset state to store data. Each memory cell is connected to a bit line 210 and a word line 212. Each memory bank 202 includes a data buffer / sense amplifier 214, a column decoder / bit line driver 216, and a row decoder / word line driver 218. In some examples, additional peripheral circuits ( Figure 2 not shown).

[0037] The data buffer / sense amplifier 214 may be configured to receive a signal from a memory controller (e.g., Figure 1 The data buffer / sense amplifier 214 may read data from the memory cell array 204 and program (write) data to the memory cell array 204 in response to control signals of the memory controller 106 of the memory controller 106. In one example, the data buffer / sense amplifier 214 may store a codeword of programming data (write data) to be programmed into the memory cell array 204. In another example, the data buffer / sense amplifier 214 may perform a program verification operation to ensure that the data has been correctly programmed into the selected memory cell coupled to the selected word line 212. In yet another example, the data buffer / sense amplifier 214 may also sense a low power signal from the bit line 210 representing a data bit stored in the memory cell and amplify the small voltage swing to a recognizable logic level in a read operation.

[0038] The column decoder / bit line driver 216 may be connected to the memory cell array 204 via bit lines and select / drive one or more bit lines to perform operations on the memory cells coupled to the selected bit lines. The row decoder / word line driver 218 may be connected to the memory cell array 204 via word lines and select / drive one or more word lines to perform operations on the memory cells coupled to the selected word lines.

[0039] Figure 3Temperature profiles 301-303 for a reset operation, a set operation, and a read operation in a PCM cell are shown. For example, a PCM cell is used to store information based on a large resistivity contrast between a high-resistance amorphous state and a low-resistance amorphous state of a phase change material. Electrical pulses can be used to program (set or reset) and read the PCM cell. The electrical pulses can generate Joule heat to induce a phase change in the phase change material during a reset or set operation.

[0040] In order to reset the PCM cell to the amorphous phase, a high current pulse may be applied to the programming region for a short period of time (e.g., 50 ns or less). The programming region may be melted and then rapidly quenched. Temperature curve 301 corresponds to this reset operation. As shown, the peak portion of temperature curve 301 is above the melting temperature. Such high temperatures may negatively affect the durability of the PCM cell. In an example, frequently applying high temperatures may change the properties of the phase change material, thereby reducing or eliminating the resistivity contrast between the amorphous state and the crystalline state.

[0041] In order to set the PCM cell to the crystalline phase, a medium current pulse may be applied for a longer time to anneal the programming region compared to the reset operation. The temperature curve 302 corresponds to the set operation. As shown, the corresponding temperature may be above the crystallization temperature and below the melting temperature. Compared to the reset operation, the operating temperature in the set operation is lower and may therefore have less negative impact on the durability of the PCM cell. Moreover, the power consumption in the set operation may be less than the power consumption in the reset operation. The data mode conversion technology disclosed herein can reduce the number of reset operations in the programming operation of a PCM-based memory device. Therefore, the data mode conversion technology has the advantages of improving the durability of the corresponding memory device and saving power.

[0042] To read the state of a PCM cell, a small electrical bias is applied to measure the resistance without disturbing the phase change material in the programmed region. Temperature curve 303 corresponds to this read operation.

[0043] Figure 4 A schematic diagram of storage information distribution of a storage cell according to an embodiment of the present disclosure is shown. The horizontal axis represents the electrical parameter value (e.g., resistance value) of the memory state of the corresponding storage cell. The vertical axis represents the number of storage cells corresponding to different electrical parameter values. The storage cell may belong to a storage device 104 based on various memory technologies. For example, the storage cell may belong to a storage device of an SCM.

[0044] A memory cell may have at least two memory states corresponding to bit 1 and bit 0, such as Figure 44. Distribution 401 represents the storage information distribution of the memory cells in the memory state of bit 1. Distribution 402 represents the storage information distribution of the memory cells in the memory state of bit 0. On average, the memory cells in the memory state of bit 0 have larger electrical parameter values ​​than the memory cells in the memory state of bit 1. A portion of the memory cells of bit 0 has smaller electrical parameter values ​​than a portion of the memory cells of bit 1.

[0045] Figure 5A Schematic diagram of a codeword 500A according to an embodiment of the present disclosure is shown. The codeword 500A includes a first part (M pages of user data 501) and a second part (N pages of spare data 502). The codeword 500A may be generated by a data processing process. For example, in Figure 1 In the example, the memory controller 106 can receive data to be written to the storage device 104 from the host 108. The memory controller 106 can then process the data before the programming operation. During the data processing process, various processing operations can be performed for various purposes. For example, an error correction code (ECC) encoding process can be performed to generate ECC parity information. For example, a compression process can be performed to compress the data. For example, the data can be reshaped into another form to reduce read latency. For example, for the purpose of wear leveling, the data may be remapped to a specific storage area. For example, a cyclic redundancy check (CRC) code can be generated for error detection.

[0046] The data received from the host 108 may be part of the M-page user data 501. Alternatively, a transformed copy of the received data may be part of the M-page user data. Information related to or resulting from the various processing operations described above may be generated and included in the N-page spare data 502. The M-page user data 501 and the N-page spare data 502 are associated with each other and written to the memory device 104. During the read process, the memory controller 106 may process the user data 501 based on the spare data 502 to output the data in its original form.

[0047] Figure 5B An example of a layout of spare data 502 according to an embodiment of the present disclosure is shown. Spare data 502 may include ECC parity information 504. The rest of spare data 502 may be used to store various metadata, CRC, and the like.

[0048] In some embodiments, the data conversion scheme disclosed herein is used to process data to be programmed into Figure 1 The storage device 104 or Figure 2The memory controller 106 may receive data of the memory device 200 in the received data. For example, when the number of 0 bits in the received data is greater than the number of 1 bits, the memory controller 106 may flip the bits in the data. When the number of 0 bits in the received data is not greater than the number of 1 bits, or the number of 0 bits is greater than the number of 1 bits but the difference is not greater than the threshold, the memory controller 106 may determine not to perform a flip operation. Therefore, a flip flag may be generated to indicate whether a flip operation is performed on the data.

[0049] In some embodiments, when the difference between the number of 0 bits and the number of 1 bits in the received data is greater than a threshold, the memory controller 106 may flip the bits in the data. Therefore, a flip flag may be generated to indicate that a flip operation is performed on the data.

[0050] In the above embodiment, the data to be programmed to the memory device 104 may be part of the user data 501, either in original form or in converted form, depending on whether the flip operation has been performed. The flip flag may be part of the spare data 502. During a read operation, the memory controller 106 may efficiently determine whether to perform a flip operation to recover the data or skip a fill operation based on the flip flag obtained from the spare data 502.

[0051] Figure 6 FIG. 6 is a flowchart of a data processing process 600 according to an embodiment of the present disclosure. The process 600 may be performed by Figure 1 The memory controller 106 in the memory system 102 in the example executes the process 600. The process 600 may start from S601 and proceed to S610.

[0052] At S610, the number of 1 bits and 0 bits in the data to be stored is counted. For example, the memory controller 106 can receive raw data from the host 108. The memory controller 106 can count the number of digital 1s and the number of digital 0s in the raw data. For example, the memory controller 106 can be configured with a counter. The counter can be implemented using appropriate hardware, software (firmware) or a combination thereof. In an example, instead of counting the bits in the raw data from the host 108, the memory controller 106 can count the bits in the data generated by the previous processing operation. For example, the raw data is transformed (e.g., shaped, compressed, etc.) into another form. The data conversion process 600 can be performed on the transformed data.

[0053] At S620, it is determined whether the number of 0 bits is greater than the number of 1 bits based on the result of S610. When the number of 0 bits is greater than the number of 1 bits, the process 600 proceeds to S630. Otherwise, the process 600 proceeds to S650.

[0054] In some embodiments, at S620, a predefined threshold is used to control the flow of process 600. Specifically, it is determined whether the number of 0 bits is greater than the number of 1 bits, and whether the difference between the number of 0 bits and the number of 1 bits is greater than the threshold. If so, process 600 proceeds to S630. Otherwise, process 600 proceeds to S650. For example, a bit flip operation may cause delays and increase power consumption. If the difference between the number of 0 bits and the number of 1 bits is less than the threshold, the benefit of inverting the bit may not be worth the cost of the bit flip operation. Therefore, the flip operation can be skipped.

[0055] At S630, the bits in the data may be flipped. In some embodiments, all bits in the data may be flipped. In some embodiments, a portion of the bits may be flipped. For example, the bits at a specific position in the data may be flipped. The resulting data may be included in the user data. In an embodiment, the user data may then be subjected to an ECC process performed by an ECC encoder to generate ECC parity information. The ECC parity information may be included in the spare data. The user data and the spare data may be stored in the memory device 104 later. In some embodiments, the memory controller 106 may be configured with an inverter to perform a flip operation. The inverter may be implemented using appropriate hardware, software (firmware), or a combination thereof.

[0056] At S640, a flip flag is set. For example, the flip flag uses one bit to indicate that the flip operation has been performed. In the example, the value of the flip flag is set to 1 to indicate that the flip operation has been performed. The flip flag can be included in the spare data and stored in the storage device 104. The process 600 can proceed to S699 and terminate at S699.

[0057] At S650, a flip flag is set. For example, the flip flag uses one bit to indicate that a flip operation has not been performed. In an example, the value of the flip flag is set to 0 to indicate that a flip operation has not been performed. Similarly, the flip flag can be included in the spare data and stored in the memory device 104. The process 600 can proceed to S699 and terminate at S699. In some examples, the flip flag uses bit 0 to indicate that a flip operation has been performed, and uses bit 1 to indicate that a flip operation has not been performed.

[0058] Figure 7 FIG. 7 is another flow chart of a data processing process 700 according to an embodiment of the present disclosure. The process 700 may be performed by Figure 1 The memory controller 106 in the memory system 102 in the example executes. The process 700 may start from S701 and proceed to S710.

[0059] At S710, by performing an ECC decoding process by an ECC decoder, data read from the storage device 104 can be successfully decoded. For example, a codeword (e.g., codeword 500A) can be read from the storage device 104. The codeword may include a user data portion and a spare data portion. The spare data may include ECC parity information. The ECC decoder may recover the user data based on the ECC parity information and the user data.

[0060] At S720, it can be determined whether a flip operation has been performed on the user data based on the value of the flip flag. For example, the flip flag can be part of the spare data obtained at S710. In some embodiments, if the flip flag has a bit value of 1, it can be determined that a flip operation has been performed. If the flip flag has a bit value of 0, it can be determined that a flip operation has not been performed. When a flip operation has been performed, the process 700 proceeds to S730. Otherwise, the process 700 proceeds to S740.

[0061] At S730, the bits in the recovered user data obtained at S710 may be flipped at the inverter to obtain inverted data. In the case where the inverted data is the original data received from the host 108, the inverted data may be transmitted to the host 108. In the case where the inverted data is a transformed form from the original data, further operations (e.g., decompression, inverse operations of previous shaping operations, etc.) may be performed to obtain the original data received from the host 108.

[0062] At S740, the original data obtained at S730 or included in the user data at S710 may be transferred to a system memory (eg, a read buffer) of the host 108. The process 700 may proceed to S799 and terminate at S799.

[0063] The memory controller in the memory system may be configured to perform various functions according to one or more embodiments or examples described herein. The memory controller may include a general-purpose processor or a specially designed circuit to implement the various functions, components or processes described in various embodiments herein. For example, the memory controller may include a processing circuit system that is configured to perform the functions and processes described herein in conjunction with or without software. In various examples, the processing circuit system may be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable gate array (FPGA), a digital enhanced circuit or a comparable device or a combination thereof.

[0064] In some other examples, the processing circuit system can be a central processing unit (CPU) configured to execute program instructions to perform the various functions and processes described herein. For example, the memory controller may include a memory configured to store program instructions. When executing the program instructions, the processing circuit system can perform functions and processes. The memory can also store other programs or data, such as an operating system, an application program, etc. The memory can include a non-temporary storage medium, such as a read-only memory (ROM), a random access memory (RAM), a flash memory, a solid-state memory, etc.

[0065] The processes and functions described herein can be implemented as computer programs, which, when executed by one or more processors, can cause one or more processors to perform the corresponding processes and functions. The computer program can be stored or distributed on a suitable medium (e.g., an optical storage medium or solid-state medium provided with other hardware or as part of other hardware). The computer program can also be distributed in other forms, for example, via the Internet or other wired or wireless telecommunications systems. For example, a computer program can be obtained and loaded into a device, including obtaining the computer program through a physical medium or a distributed system (including, for example, from a server connected to the Internet).

[0066] A computer program can be accessed from a computer-readable medium that provides program instructions used by or associated with a computer or any instruction execution system. A computer-readable medium may include any device that stores, communicates, propagates, or transmits a computer program for use by or associated with an instruction execution system, device, or equipment. A computer-readable medium may be a magnetic, optical, electronic, electromagnetic, infrared, or semiconductor system (or device or equipment) or a propagation medium. A computer-readable medium may include a computer-readable non-transitory storage medium, such as a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read-only memory (ROM), a magnetic disk, and an optical disk. A computer-readable non-transitory storage medium may include all types of computer-readable media, including magnetic storage media, optical storage media, flash memory media, and solid-state storage media.

[0067] Although aspects of the present disclosure have been described in conjunction with the specific embodiments of the present disclosure proposed as examples, these examples may be substituted, modified and varied. Therefore, the embodiments set forth herein are intended to be illustrative rather than restrictive. Some changes may be made without departing from the scope of the claims set forth below.

Claims

1. A method for a memory system including a memory device, the method comprising: receiving data to be written into the memory device, the memory device comprising memory cells, each memory cell having a first state and a second state, the data comprising bits, each of the bits corresponding to one of the first state and the second state; Counting a first number of bits corresponding to the first state and a second number of bits corresponding to the second state in the received data; In response to the second bit number of bits corresponding to the second state being greater than the first bit number of bits corresponding to the first state, performing a first flipping operation to flip the bits in the received data; as well as The received data with the flipped bit is stored to the memory device.

2. The method according to claim 1, further comprising: In response to the difference that the second number of bits corresponding to the second state is greater than the first number of bits corresponding to the first state being greater than a threshold, performing the first flipping operation to flip the bits in the received data.

3. The method according to claim 1, further comprising: In response to: storing the received data to the memory device without flipping the bits in the received data: the second number of bits corresponding to the second state is not greater than the first number of bits corresponding to the first state, or The difference between the second number of bits corresponding to the second state and the first number of bits corresponding to the first state is smaller than a threshold.

4. The method according to claim 1, further comprising: generating a flip flag indicating whether the first flip operation has been performed on the received data; as well as The flip flag is stored in the storage device.

5. The method according to claim 4, further comprising: reading the received data having the flip bit and the flip flag from the memory device, the flip flag indicating whether the first flip operation has been performed on the received data; determining whether to perform a second flip operation on the received data having the flip bit based on the flip flag indicating whether the first flip operation has been performed on the received data; as well as In response to the flip flag indicating that the first flip operation has been performed on the received data, the second flip operation is performed to flip previously flipped bits in the received data.

6. The method according to claim 5, wherein: Storing the received data with the flipped bit to the storage device comprises: encoding the received data with the flipped bits to generate error correction code (ECC) parity information; and The ECC parity information is stored in the storage device.

7. The method according to claim 6, wherein: Reading the received data having the flipped bit from the memory device comprises: reading the ECC parity information from the storage device; and The received data having the flipped bits is restored based on the ECC parity information.

8. The method according to claim 1, wherein: The memory device is a phase change memory (PCM) device, and the first state and the second state of the memory cell of the memory device correspond to a crystalline state and an amorphous state of the PCM device, respectively.

9. A memory system comprising: A memory device comprising a memory cell, and A memory controller comprising circuitry configured to: receiving data to be written into the memory device, each memory cell having a first state and a second state, the data comprising bits, each of the bits corresponding to one of the first state and the second state; Counting a first number of bits corresponding to the first state and a second number of bits corresponding to the second state in the received data; In response to the second bit number of bits corresponding to the second state being greater than the first bit number of bits corresponding to the first state, performing a first flipping operation to flip the bits in the received data; as well as The received data with the flipped bit is stored to the memory device.

10. The memory system according to claim 9, wherein: The circuit system is also configured to: In response to the difference that the second number of bits corresponding to the second state is greater than the first number of bits corresponding to the first state being greater than a threshold, performing the first flipping operation to flip the bits in the received data.

11. The memory system according to claim 9, wherein: The circuit system is also configured to: In response to: storing the received data to the memory device without flipping the bits in the received data: the second number of bits corresponding to the second state is not greater than the first number of bits corresponding to the first state, or The difference between the second number of bits corresponding to the second state and the first number of bits corresponding to the first state is smaller than a threshold.

12. The memory system according to claim 9, wherein: The circuit system is also configured to: generating a flip flag indicating whether the first flip operation has been performed on the received data; and The flip flag is stored in the storage device.

13. The memory system according to claim 12, wherein: The circuit system is also configured to: reading the received data having the flip bit and the flip flag from the memory device, the flip flag indicating whether the first flip operation has been performed on the received data; determining whether to perform a second flip operation on the received data having the flip bit based on the flip flag indicating whether the first flip operation has been performed on the received data; as well as In response to the flip flag indicating that the first flip operation has been performed on the received data, the second flip operation is performed to flip previously flipped bits in the received data.

14. The memory system according to claim 13, wherein: The circuit system is also configured to: encoding the received data with the flipped bits to generate error correction code (ECC) parity information; and The ECC parity information is stored in the storage device.

15. The memory system of claim 14, wherein: The circuit system is also configured to: reading the ECC parity information from the storage device; and The received data having the flipped bits is restored based on the ECC parity information.

16. The memory system according to claim 9, wherein: The memory device is a phase change memory (PCM) device, and the first state and the second state of the memory cell of the memory device correspond to a crystalline state and an amorphous state of the PCM device, respectively.

17. A non-transitory computer readable medium storing instructions which, when executed by a processing device, cause the processing device to perform a method for a memory system comprising: receiving data to be written into a memory device of the memory system, the memory device comprising memory cells, each memory cell having a first state and a second state, the data comprising bits, each of the bits corresponding to one of the first state and the second state; Counting a first number of bits corresponding to the first state and a second number of bits corresponding to the second state in the received data; In response to the second bit number of bits corresponding to the second state being greater than the first bit number of bits corresponding to the first state, performing a first flipping operation to flip the bits in the received data; as well as The received data with the flipped bit is stored to the memory device.

18. The non-transitory computer readable medium of claim 17, wherein: The method further comprises: In response to: storing the received data to the memory device without flipping the bits in the received data: the second number of bits corresponding to the second state is not greater than the first number of bits corresponding to the first state, or The difference between the second number of bits corresponding to the second state and the first number of bits corresponding to the first state is smaller than a threshold.

19. The non-transitory computer readable medium of claim 17, wherein: The method further comprises: generating a flip flag indicating whether the first flip operation has been performed on the received data; and The flip flag is stored in the storage device.

20. The non-transitory computer readable medium of claim 19, wherein: The method further comprises: reading the received data having the flip bit and the flip flag from the memory device, the flip flag indicating whether the first flip operation has been performed on the received data; determining whether to perform a second flip operation on the received data having the flip bit based on the flip flag indicating whether the first flip operation has been performed on the received data; and In response to the flip flag indicating that the first flip operation has been performed on the received data, the second flip operation is performed to flip previously flipped bits in the received data.

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