Error rate management in non-uniform memory arrays

Abstract

A plurality of control circuits are configured to be individually connected to arrays, each including a plurality of non-volatile memory cells. Each non-volatile memory cell includes a programmable resistive element. Each control circuit is configured with a separate address offset. The plurality of control circuits are configured to: receive read addresses in parallel from the memory controller; applying the respective individual address offset to the read address to generate a respective offset address; reading a portion of the data from the corresponding offset address; and transmitting the data read from the offset address to the memory controller to perform error correction code (ECC) decoding of a portion of the data.

Description

[0001] Priority declaration

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 505,300, filed by Houssameddine et al. on May 31, 2023, entitled “ERROR RATE MANAGEMENT IN NON-UNIFORM MEMORY ARRAYS,” which is incorporated herein by reference in its entirety. Background Art

[0003] Memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0004] An example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, as opposed to some other memory technologies that use charge to store data. Generally speaking, MRAM includes a large number of magnetic memory cells formed on a semiconductor substrate, where each memory cell represents (at least) one data bit. Data bits are written to the memory cells by changing the magnetization direction of the magnetic elements within the memory cells, and the bits are read by measuring the resistance of the memory cells (low resistance typically represents a "0" bit and high resistance typically represents a "1" bit). As used herein, the magnetization direction is the direction in which the magnetic moments are oriented.

[0005] Although MRAM is a promising technology, various phenomena may cause errors in the data stored in MRAM. Such errors can be corrected using error correction codes (ECC). Correcting errors using ECC may require significant resources and take a significant amount of time. In some cases, the data may have too many errors to be corrected using a given ECC scheme. Such data may be considered uncorrectable by the ECC or "UE". It is challenging to manage the effects of errors in an efficient manner so that ECC-corrected data can be reliably and efficiently generated from the data stored in MRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Like numbered elements refer to common parts in different figures.

[0007] Figure 1 is a block diagram of one embodiment of a memory system connected to a host.

[0008] Figure 2is a block diagram of one embodiment of a front end processor circuit. In some embodiments, the front end processor circuit is part of a controller.

[0009] Figure 3 is a block diagram of one embodiment of a back-end processor circuit. In some embodiments, the back-end processor circuit is part of a controller.

[0010] Figure 4 is a block diagram of one embodiment of a memory package.

[0011] Figure 5 is a block diagram of one embodiment of a memory die.

[0012] Fig. 6A and Figure 6B An example of a control circuit coupled to a memory structure via wafer-to-wafer bonding is shown.

[0013] Fig. 7A One embodiment of a portion of a memory array forming a cross point architecture is depicted in oblique view.

[0014] Figure 7B and Figure 7C They presented Fig. 7A Side and top views of the junction structure in .

[0015] Fig.7D One embodiment of a portion of a two-level memory array forming a cross-point architecture is depicted in oblique view.

[0016] Figure 8 One embodiment of the structure of an MRAM memory cell is shown.

[0017] Fig. 9 One embodiment of an MRAM memory cell design to be implemented in a cross-point array is shown in more detail.

[0018] Fig. 10A and Fig. 10B Writing to an MRAM memory cell by using a spin torque transfer (STT) mechanism is demonstrated.

[0019] Fig.11A and Fig. 11B Embodiments for incorporating a threshold switch selector into an MRAM memory array having a cross-point architecture are presented.

[0020] Fig.12 and Fig.13 shows the functions used in the read operation. Fig.11A and Fig. 11B A set of waveforms of the current and voltage of the layer 1 unit.

[0021] Fig.14 An example of the voltage of an MRAM device when a threshold switch selector switches from an off state to an on state is shown.

[0022] Fig.15 An example of current flow in an MRAM device when a threshold switch selector switches from an off state to an on state is shown.

[0023] Fig.16 Examples of memory cells at different locations in the module are shown.

[0024] 17A to 17D An exemplary structure including multiple media is shown.

[0025] FIG. 18A to FIG. 18B An example of reading a medium using a common address is shown.

[0026] Fig.19 An example is shown using different individual address offsets in each medium.

[0027] Fig. 20 An example is shown in which a different read address is sent to each medium.

[0028] Fig.21 An example of using offsets to read different modules of the same media at different locations is shown.

[0029] Fig. 22 An example of a method including applying an address offset to generate an offset address is shown.

[0030] Fig.23 An example of a method including a portion of reading data from a first offset address and a second offset address is shown.

[0031] Fig.24 An example of a method including writing data at an offset address is shown. DETAILED DESCRIPTION

[0032] In a memory array having a cross-point architecture, a first set of conductive lines extends across the surface of a substrate, and a second set of conductive lines is formed above the first set of conductive lines, extending above the substrate in a direction perpendicular to the first set of conductive lines. The memory cell is located at the intersection junction of the two sets of conductive lines. An embodiment of the memory cell may include a programmable resistive element, such as an MRAM memory cell, connected in series with a selector switch. One type of selector switch is a threshold switch selector (such as a bidirectional threshold switch), which can be implemented in a small amount of area relative to other switching elements (such as transistors) without the need for additional control lines. If the voltage is above a certain level, a threshold voltage is applied across the threshold switch selector, and the threshold switch selector will switch to a conductive state.

[0033] Data can be read from multiple MRAM memory cells and sent to the ECC circuit for decoding. Errors may occur in such data for a variety of reasons. Data from MRAM memory cells in some structures may be affected by "snapback interference" caused by a relatively high current called "snapback current". The snapback current may be affected by many factors, including the distance of a given memory cell from the word line driver and the bit line driver (for example, the length of the electrical connection from the memory cell to the word line driver and to the bit line driver), which may cause the snapback-related effects to be non-uniform. For example, memory cells (near cells) closer to the word line driver and / or the bit line driver may have higher snapback currents and may be more affected by snapback interference than memory cells (far cells) farther away from the word line driver and / or the bit line driver. Therefore, data from near memory cells may have a higher error rate than data from far memory cells. Other phenomena may also produce non-uniform effects.

[0034] In one embodiment, data that is ECC encoded and decoded together (e.g., as an ECC codeword) may be located at different corresponding locations in different arrays (e.g., some data in near cells and some data in far cells), so that the error rates of memory cells at multiple locations are combined, which can provide an average error rate and can mitigate the impact of non-uniform error rates in the memory array. This can provide a relatively uniform error rate across different ECC codewords, so that the risk to the UE is relatively low. For example, different media (e.g., different memory dies) can apply different address offsets to addresses so that each medium accesses a corresponding memory array at a different location.

[0035] Figure 1 1 is a block diagram of one embodiment of a memory system 100 connected to a host 120. The memory system 100 can implement the techniques presented herein for managing error rates. Many different types of memory systems can be used with the techniques presented herein. Exemplary memory systems include: a solid state drive ("SSD"); a memory card including dual inline memory modules (DIMMs) for DRAM replacement; and an embedded memory device; however, other types of memory systems can also be used.

[0036] Figure 1The memory system 100 includes a controller 102, a non-volatile memory 104 for storing data, and a local memory (e.g., DRAM / ReRAM / MRAM) 106. The controller 102 includes a front-end processor (FEP) circuit 110 and one or more back-end processor (BEP) circuits 112. In one embodiment, the FEP circuit 110 is implemented on an application-specific integrated circuit (ASIC). In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. In other embodiments, a unified controller ASIC can combine both front-end functions and back-end functions. The ASIC for each of the BEP circuit 112 and the FEP circuit 110 is implemented on the same semiconductor, so that the controller 102 is manufactured as a system on chip ("SoC"). The FEP circuit 110 and the BEP circuit 112 each include their own processor. In one embodiment, the FEP circuit 110 and the BEP circuit 112 are used as a master-slave configuration, where the FEP circuit 110 is a master device and each BEP circuit 112 is a slave device. For example, the FEP circuit 110 implements a flash translation layer (FTL) or a media management layer (MML) that performs memory management (e.g., garbage collection, wear leveling, etc.), logical to physical address translation, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of the SSD (or other non-volatile storage system). The BEP circuit 112 manages memory operations in the memory package / die based on requests from the FEP circuit 110. For example, the BEP circuit 112 can implement read, erase, and program processes. In addition, the BEP circuit 112 can perform buffer management, set specific voltage levels required by the FEP circuit 110, perform error correction (ECC), control the switch mode interface to the memory package, etc. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packages.

[0037] In one embodiment, the non-volatile memory 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Therefore, the controller 102 is connected to one or more non-volatile memory dies. In one embodiment, each memory die in the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package may include other types of memory, such as storage class memory (SCM) or phase change memory (PCM) based on resistive random access memory (such as ReRAM, MRAM, FeRAM or RRAM). In other embodiments, a BEP or FEP may be included on the memory die.

[0038] The controller 102 communicates with the host 120 via an interface 130 that implements a protocol such as NVM Express (NVMe) or Compute Express Link (CXL) using a JEDEC standard double data rate or low power double data rate (DDR or LPDDR) interface (such as DDR5 or LPDDR5). To work with the memory system 100, the host 120 includes a host processor 122, a host memory 124, and a PCIe interface 126 connected along a bus 128. The host memory 124 is the physical memory of the host and can be DRAM, SRAM, MRAM, non-volatile memory, or another type of storage device. The host 120 is external to the memory system 100 and separate from the memory system. In one embodiment, the memory system 100 is embedded in the host 120.

[0039] Figure 2 is a block diagram of one embodiment of the FEP circuit 110 . Figure 2 A PCIe interface 150 is shown that communicates with the host 120, and a host processor 152 that communicates with the PCIe interface. The host processor 152 can be any type of processor known in the art that is suitable for implementation. The host processor 152 communicates with a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit, usually between cores in a SoC. NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of SoCs and the power efficiency of complex SoCs. The wires and links of NOC are shared by many signals. Since all links in NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to increase, NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and in communication with NOC 154 are memory processor 156, SRAM 160, and DRAM controller 162. DRAM controller 162 is used to operate and communicate with DRAM (e.g., DRAM 106). SRAM 160 is local RAM memory used by memory processor 156. Memory processor 156 is used to run FEP circuits and perform various memory operations. Also in communication with the NOC are two PCIe interfaces 164 and 166. Figure 2In the embodiment of the present invention, the SSD controller will include two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or less than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0040] The FEP circuit 110 may also include a flash translation layer (FTL), or more generally a media management layer (MML) 158, which performs memory management (e.g., garbage collection, wear leveling, load balancing, etc.), logical to physical address translation, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of the SSD or other non-volatile storage system. The media management layer (MML) 158 may be integrated as part of the memory management that may handle memory errors and interact with the host interface. Specifically, the MML may be a module in the FEP circuit 110 and may be responsible for the internals of memory management. Specifically, the MML 158 may include an algorithm in the memory device firmware that converts writes from the host to memory structures of the die (e.g., the next Figure 5 6). MML 158 may be needed because: 1) the memory may have limited endurance; 2) the memory structure may only be written to multiple pages; and / or 3) the memory structure may not be written unless it is erased as a block. MML 158 understands these potential limitations of the memory structure, which may not be visible to the host. Therefore, MML 158 attempts to convert writes from the host to writes to the memory structure.

[0041] Figure 3 is a block diagram of one embodiment of the BEP circuit 112 . Figure 3 A method for communicating with the FEP circuit 110 (e.g., Figure 2The PCIe interface 200 communicates with one of the PCIe interfaces 164 and 166 of the NOCs. The PCIe interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs can be combined into a large NOC. Each NOC (202 / 204) is connected to the SRAM (230 / 260), the buffer (232 / 262), the processor (220 / 250) and the data path controller (222 / 252) through an XOR engine (224 / 254) and an ECC engine (226 / 256). The ECC engine 226 / 256 is used to perform error correction, as known in the art. The XOR engine 224 / 254 is used to perform XOR on the data so that the data can be combined and stored in a recoverable manner in the presence of programming errors. The data path controller 222 is connected to the interface module for communicating with the memory package via four channels. Therefore, top NOC 202 is associated with interface 228 for four channels for communicating with memory package, and bottom NOC 204 is associated with interface 258 for four additional channels for communicating with memory package. Each interface 228 / 258 includes four switching mode interfaces (TM interfaces), four buffers and four schedulers. For each channel, there is a scheduler, buffer and TM interface. The processor can be any standard processor known in the art. Data path controller 222 / 252 can be a processor, FPGA, microprocessor or other type of controller. XOR engine 224 / 254 and ECC engine 226 / 256 are dedicated hardware circuits, referred to as hardware accelerators. In other embodiments, XOR engine 224 / 254 and ECC engine 226 / 256 can be implemented in software. Scheduler, buffer and TM interface are hardware circuits.

[0042] Figure 4 1 is a block diagram of one embodiment of a memory package 104 including a plurality of memory dies 292 connected to a memory bus (data lines and chip enable lines) 294. The memory bus 294 is connected to a switch mode interface 296 for communicating with the TM interface of the BEP circuit 112 (see, e.g., Figure 3 ). In some embodiments, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may have one or more memory dies. In one embodiment, each memory package includes eight or 16 memory dies; however, other numbers of memory dies may also be implemented. In another embodiment, the switching interface is changed to JEDEC standard DDR or LPDDR, with or without changes such as relaxed timing settings or smaller page sizes. The technology described herein is not limited to any particular number of memory dies.

[0043] Figure 5 5 is a block diagram depicting an example of a memory system 500 that can implement the techniques described herein. The memory system 500 includes a memory array 502, which can include any of the memory cells described below. The array terminal lines of the memory array 502 include individual word line layers organized into rows, and individual bit line layers organized into columns. However, other orientations can also be implemented. The memory system 500 includes a row control circuit system 520, the output 508 of which is connected to the corresponding word lines of the memory array 502. The row control circuit system 520 receives a set of M row address signals and one or more various control signals from the system control logic circuit 560, and can generally include circuits such as a row decoder 522, an array terminal driver 524 (e.g., a word line driver), and a block selection circuit system 526 for both read operations and write operations. The memory system 500 also includes a column control circuit system 510, the input / output 506 of which is connected to the corresponding bit lines of the memory array 502. Although only a single block is shown for memory array 502, a memory die may include multiple arrays or "tiles" that can be accessed individually. Column control circuitry 510 receives a set of N column address signals and one or more various control signals from system control logic 560, and may generally include circuits such as column decoders 512, array terminal receivers or drivers 514 (e.g., bit line drivers), block select circuitry 516, and read / write circuitry and I / O multiplexers.

[0044] The system control logic unit 560 receives data and commands from the host, and provides output data and status to the host. In other embodiments, the system control logic unit 560 receives data and commands from a separate controller circuit, and provides output data to the controller circuit, wherein the controller circuit communicates with the host. In some embodiments, the system control logic unit 560 may include a state machine that provides a die-level control of memory operation. In one embodiment, the state machine can be programmed by software. In other embodiments, the state machine does not use software and is fully implemented in hardware (e.g., electrical circuit). In another embodiment, the state machine is replaced by a microcontroller, wherein the microcontroller is on or outside the memory chip. The system control logic unit 560 may also include a power control module, which controls the power and voltage of the rows and columns supplied to the memory array 502 during memory operation, and may include a charge pump and a regulator circuit for generating a regulated voltage. The system control logic unit 560 may include one or more state machines, registers, and other control logic units for controlling the operation of the memory system 500. Figure 5Such registers are shown at 561 and may be used, for example, to store data such as offsets that may be used when accessing (e.g., reading or writing) memory cells of the memory array 502. In some embodiments, all elements of the memory system 500, including the system control logic 560, may be formed as part of a single die. In other embodiments, some or all of the system control logic 560 may be formed on different dies.

[0045] For purposes of this document, the phrase "one or more control circuits" may include the controller, state machine, microcontroller, and / or other control circuitry represented by system control logic 560, or other similar circuitry for controlling non-volatile memory.

[0046] In one embodiment, the memory structure 502 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed over a single substrate (such as a wafer). The memory structure may include any type of non-volatile memory integrally formed in one or more physical levels of memory cells having active regions disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping.

[0047] In another embodiment, the memory structure 502 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0048] The exact type of memory array architecture or memory cell included in the memory structure 502 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 326. No specific non-volatile memory technology is required to implement the new claimed embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 502 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit transfer torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 502 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0049] An example of a ReRAM crosspoint memory includes a reversible resistance switching element arranged in a crosspoint array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0050] Another example is a magnetoresistive random access memory (MRAM) that uses magnetic storage elements to store data. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the storage memory by the external magnetic field. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cells, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0051] Phase change memory (PCM) exploits the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms with only a programming current pulse. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or non-continuous) vibrations or pulse trains of sound, current, voltage light or other waves. The memory element within each selectable memory cell or bit may include an additional series element as a selector, such as a bidirectional threshold switch or a metal insulator substrate.

[0052] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those of ordinary skill in the art.

[0053] You can Figure 5The elements of the memory system 500 are grouped into two parts: the memory structure 502 of the memory cells; and the peripheral circuit system, including all other elements. An important characteristic of the memory circuit is its capacity, which can be increased by increasing the area of ​​the memory die of the memory system 500 reserved for the memory structure 502; however, this reduces the area of ​​the memory die available for the peripheral circuit system. This can place quite severe restrictions on these peripheral elements. For example, the need to fit the sense amplifier circuits within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic component 560, the reduction in available area may limit the available functions that can be implemented on the chip. Therefore, in the design of the memory die of the memory system 500, a basic trade-off needs to be made between the amount of area dedicated to the memory structure 502 and the amount of area dedicated to the peripheral circuit system.

[0054] Another area where the memory structure 502 and the peripheral circuitry often conflict is in the processing involved in forming these areas, as these areas often involve different processing technologies and the trade-offs when implementing different technologies on a single die. For example, when the memory structure 502 is a NAND flash memory, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuitry in the system control logic 560 often employ PMOS devices. The processing operations used to manufacture a CMOS die will differ in many respects from processing operations optimized for NMOS flash memory, NAND memory, or other memory cell technologies.

[0055] To improve these limitations, the embodiments described below can Figure 5The components of the memory structure 502 can be separated into separately formed dies, and then these dies are bonded together. More specifically, the memory structure 502 can be formed on one die, and some or all of the peripheral circuit elements (including one or more control circuits) can be formed on a separate die. For example, the memory die can be formed only by memory elements, such as a memory cell array of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types. Then some or all of the circuit systems in the peripheral circuit system (even including elements such as decoders and sense amplifiers) can be moved to a separate die. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about CMOS elements that have now been moved to an independent peripheral circuit system die that can be optimized for CMOS processing. This provides more room for peripheral elements, and if the peripheral elements are restricted to the edge of the same die that accommodates the memory cell array, additional capabilities that may not be easily bonded can now be combined. Two dies can then be bonded together in a bonded multi-die memory circuit, where the array on one die is connected to the peripheral elements on the other memory circuit. For example, although the following description will focus on bonded memory circuits with one memory die and one peripheral circuit die, other embodiments may use more dies, such as two memory dies and one peripheral circuit die.

[0056] Fig. 6A and Figure 6B Shows Figure 5 An alternative arrangement of the arrangement of may be implemented using wafer-to-wafer bonding to provide bonded die pairs for memory system 600. Fig. 6A An example of peripheral circuitry is shown, including control circuits formed in a peripheral circuit or control die 611 coupled to a memory structure 602 formed in a memory die 601. Figure 5 Like 502, memory die 601 may include multiple independently accessible arrays or "tiles". Common components and Figure 5Similarly labeled (e.g., 502 is now 602, 510 is now 610, and so on). As can be seen, system control logic 659, row control circuitry 620, and column control circuitry 610 (which may be formed by CMOS processes) are located in control die 611. Additional elements (such as functionality from controller 102) may also be moved to control die 611. System control logic 659, row control circuitry 620, and column control circuitry 610 may be formed by conventional processes (e.g., CMOS processes) such that adding elements and functionality more commonly found on memory controller 102 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 102 may also be used to fabricate system control logic 659, row control circuitry 620, and column control circuitry 610). Thus, while removing such circuitry from a die (such as the memory die of memory system 500) may reduce the number of steps required to manufacture such a die, adding such circuitry to a die (such as control die 611) may not require any additional process steps.

[0057] Fig. 6A Column control circuitry 610 on a control die 611 is shown coupled to a memory structure 602 on a memory die 601 via an electrical path 606. For example, electrical path 606 can provide electrical connections between a column decoder 612, a driver circuitry 614, a block selector 616, and the bit lines of the memory structure 602. The electrical paths can extend from the column control circuitry 610 in the control die 611 through pads on the control die 611 that are bonded to corresponding pads of the memory die 601 that are connected to the bit lines of the memory structure 602. Each bit line of the memory structure 602 can have a corresponding electrical path in electrical path 606, including a pair of bond pads connected to the column control circuitry 610. Similarly, row control circuitry 620 (including a row decoder 622, an array driver 624, and a block selector 626) is coupled to the memory structure 602 via an electrical path 608. Each electrical path 608 may correspond to a word line, a dummy word line, or a select gate line.Additional electrical paths may also be provided between the control die 611 and the memory die 601.

[0058] Figure 6B6 is a block diagram showing more details about the arrangement of one embodiment of an integrated memory component 600 formed by a bonded die pair. A memory die 601 contains an array 602 of memory cells. The memory die 601 may have additional arrays (e.g., multiple modules, each module including an array). A representative bit line (BL) and a representative word line (WL) 666 are depicted for the array 602. Each array 602 may have thousands or tens of thousands of such bit lines. In one embodiment, an array represents a group of connected memory cells that share a common set of continuous word lines and continuous bit lines.

[0059] The control die 611 includes a plurality of bit line drivers 650. In some embodiments, each bit line driver 650 is connected to one bit line or can be connected to multiple bit lines. The control die 611 includes a plurality of word line drivers 660(1) to 660(n). The word line drivers 660 are configured to provide voltages to the word lines. In this example, there are "n" word lines for each array or plane of memory cells. In one embodiment, if the memory operation is programming or reading, one word line within the selected block is selected for the memory operation. In one embodiment, if the memory operation is erasing, all word lines within the selected block are selected for erasing. The word line drivers 660 provide voltages to the word lines in the memory die 601. As described above with respect to Fig. 6A As discussed, the control die 611 may also include a charge pump, a voltage generator, and Figure 6B Similar components not shown in FIG. 6A may be used to provide voltages for the word line driver 660 and / or the bit line driver 650 .

[0060] The memory die 601 has a plurality of bonding pads 670a, 670b on a first major surface 682 of the memory die 601. There may be "n" bonding pads 670a to receive voltages from corresponding "n" word line drivers 660(1) to 660(n). There may be one bonding pad 670b for each bit line associated with the array 602. The reference numeral 670 will be used to generally refer to the bonding pads on the major surface 682.

[0061] In some embodiments, each data bit and each parity bit of the codeword are transmitted through different bonding pad pairs 670b, 674b. The bits of the codeword can be transmitted in parallel through bonding pad pairs 670b, 674b. This provides very efficient data transmission relative to, for example, transmitting data between the memory controller 102 and the integrated memory component 600. For example, the data bus between the memory controller 102 and the integrated memory component 600 can, for example, provide 8, 16, 32 or more bits to be transmitted simultaneously. However, the data bus between the memory controller 102 and the integrated memory component 600 is not limited to these examples. In some embodiments, this ECC can be implemented on a memory die.

[0062] The control die 611 has a number of bonding pads 674a, 674b on a first major surface 684 of the control die 611. There may be "n" bonding pads 674a to deliver voltages from corresponding "n" word line drivers 660(1) to 660(n) to the memory die 601. There may be one bonding pad 674b for each bit line associated with the array 602. Reference numeral 674 will be used to generally refer to the bonding pads on the major surface 682. Note that there may be bonding pad pairs 670a / 674a and bonding pad pairs 670b / 674b. In some embodiments, bonding pads 670 and / or 674 are flip chip bonding pads.

[0063] In one embodiment, the pattern of bonding pads 670 matches the pattern of bonding pads 674. Bonding pads 670 are bonded (e.g., flip chip bonded) to bonding pads 674. Thus, bonding pads 670, 674 electrically and physically couple memory die 601 to control die 611. In addition, bonding pads 670, 674 permit internal signal transmission between memory die 601 and control die 611. Thus, memory die 601 and control die 611 are bonded together using bonding pads. Although Fig. 6A One control die 611 is depicted bonded to one memory die 601 , but in another embodiment, one control die 611 is bonded to multiple memory dies 601 .

[0064] As used herein, "internal signaling" refers to signaling between the control die 611 and the memory die 601. Internal signaling permits the circuitry on the control die 611 to control memory operations in the memory die 601. Thus, the bonding pads 670, 674 may be used for memory operation signaling. As used herein, "memory operation signaling" refers to any signal related to memory operations in the memory die 601. Memory operation signaling may include, but is not limited to, providing voltage, providing current, receiving voltage, receiving current, sensing voltage, and / or sensing current.

[0065] The bonding pads 670, 674 may be formed of, for example, copper, aluminum, and alloys thereof. There may be a liner between the bonding pads 670, 674 and the main surface (682, 684). The liner may be formed of, for example, a titanium / titanium nitride stack. The bonding pads 670, 674 and the liner may be applied by vapor deposition and / or electroplating techniques. The bonding pads and the liner together may have a thickness of 720 nm, but in other embodiments the thickness may be greater or less.

[0066] Metal interconnects and / or vias may be used to electrically connect various components in the die to bonding pads 670, 674. Several conductive paths that may be implemented with metal interconnects and / or vias are described. For example, a sense amplifier may be electrically connected to bonding pad 674b via via 664. Fig. 6A , electrical path 606 may correspond to via 664, bonding pad 674b, and bonding pad 670b. There may be thousands of such sense amplifiers, vias, and bonding pads. Note that BL does not necessarily connect directly to bonding pad 670b. Word line driver 660 may be electrically connected to bonding pad 674a via via 662. Fig. 6A , electrical path 608 can correspond to via 662, bonding pad 674a, and bonding pad 670a. Note that via 662 can include a separate conductive path for each word line driver 660(1) to 660(n). Likewise, there can be a separate bonding pad 674a for each word line driver 660(1) to 660(n). The word lines in block 2 of memory die 601 can be electrically connected to bonding pad 670a via via 664. Figure 6B , for corresponding "n" word lines in a block, there are "n" vias 664. For each via 664, there may be a separate pair of bonding pads 670a, 674a.

[0067] Relative to Figure 5 , Fig. 6A The on-die control circuitry may also include additional functionality within its logic elements, including both more general capabilities commonly found in memory controller 102, and some CPU capabilities, but also application-specific features.

[0068] In the following, the system control logic 560 / 660, the column control circuit system 510 / 610, the row control circuit system 520 / 620 and / or the controller 102 (or circuits with equivalent functions), in combination with Figure 5 Depicted in or Fig. 6A All or a subset of other circuits on the control die 611 in the Figure 5Similar elements in the examples may be considered to be part of one or more control circuits that perform the functions described herein. The control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, FGA, ASIC, integrated circuit, or other types of circuits.

[0069] In the following discussion, Figure 5 and Fig. 6A The memory array 502 / 602 will be discussed primarily in the context of a cross-point architecture, but much of the discussion can be applied more generally. In a cross-point architecture, a first set of conductors or lines (such as word lines) extend in a first direction relative to an underlying substrate, and a second set of conductors or lines (such as bit lines) extend in a second direction relative to an underlying substrate. Memory cells are located at the intersection of word lines and bit lines. The memory cells at these intersections can be formed according to any of a variety of techniques, including those described above. The following discussion will focus primarily on embodiments based on a cross-point architecture using MRAM memory cells.

[0070] Fig. 7A One embodiment of a portion of a memory array forming a cross point architecture is depicted in oblique view. Fig. 7A The memory array 502 / 602 is Figure 5 The memory array 502 or Fig. 6A An example of a specific implementation of a memory array 602 in which a memory die may include multiple such array structures. The bit lines BL1-BL5 are arranged along a first direction (shown as extending into the page) relative to an underlying substrate (not shown) of the die, and the word lines WL1-WL5 are arranged along a second direction perpendicular to the first direction. Fig. 7A is an example of a horizontal cross-point structure in which both word lines WL1-WL5 and BL1-BL5 extend in a horizontal direction relative to the substrate, and memory cells (two of which are indicated at 701) are oriented so that current through the memory cells (such as at I 单元 In a memory array having additional layers of memory cells, such as described below with respect to Fig.7D As discussed, there will be corresponding additional layers of bit lines and word lines.

[0071] like Fig. 7AAs depicted, the memory array 502 / 602 includes a plurality of memory cells 701. The memory cells 701 may include rewritable memory cells, such as may be implemented using ReRAM, MRAM, PCM, FeRAM, or other materials with programmable resistance. The following discussion will focus on MRAM memory cells, but much of the discussion may apply more generally. The current in the memory cells of the first memory level is shown as arrows I 单元 Upward flow is indicated, but current can flow in either direction, as discussed in more detail below.

[0072] Figure 7B and Figure 7C They presented Fig. 7A Side and top views of the junction structure in . Figure 7B The side view shows a bottom line or word line WL1, and top lines or bit lines BL1-BL n MRAM memory cells are located at the intersection between each top and bottom line, but PCM, FeRAM, ReRAM or other technologies could be used. Figure 7C Is to show M bottom lines WL1-WL M and N top lines BL1-BL N A top view of a cross-point structure of FIG. 1. In a binary implementation, the MRAM cell at each cross-point can be programmed to one of two resistance states: a high resistance state and a low resistance state. More details on implementations of MRAM memory cell designs and their programming techniques are given below.

[0073] Fig. 7A The cross-point array of shows an embodiment with one layer of word lines and bit lines, where the MRAM or other memory cells are located at the intersection of two sets of conductive lines. To increase the storage density of the memory tube core, multiple layers of such memory cells and conductive lines can be formed. The two-layer example in Fig.7D Displayed in.

[0074] Fig.7D One embodiment of a portion of a two-level memory array forming a cross-point architecture is depicted in oblique view. Fig. 7A As shown, Fig.7D The first layer 718 memory cells 701 of the array 502 / 602 are shown, connected to the first layer word lines WL 1,1 -WL 1,4 The second layer memory cells 720 are formed above the bit lines BL1-BL5 and at the intersections of these bit lines and the second set of word lines WL 2,1 -WL 2,4 Although Fig.7DTwo layers of memory cells 718 and 720 are shown, but the structure can be extended upward through additional alternating layers of word lines and bit lines. Depending on the embodiment, Fig.7D The word lines and bit lines of the array can be biased for a read operation or a program operation so that the current in each layer flows from the word line layer to the bit line layer or circulates in the opposite direction. The two layers can be constructed to have current flowing in the same direction in each layer for a given operation, such as from bit line to word line for reading, or to have current flowing in opposite directions, such as from word line to bit line for layer 1 reading, and from bit line to word line for layer 2 reading.

[0075] The use of a cross point architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each cross point can be resistive type memory cells, where data values ​​are encoded as different resistance levels. Depending on the implementation, the memory cells can be binary valued, have a low resistance state or a high resistance state, or be multi-level cells (MLCs), which can have additional resistance intermediate between the low resistance state and the high resistance state. The cross point arrays described herein can be used as Figure 4 The memory die 292 of the present invention may be used to replace the local memory 106, or both. The resistive type memory cells may be formed according to many of the above-mentioned technologies, such as ReRAM, FeRAM, PCM, or MRAM. The following discussion is primarily presented in the context of a memory array using a cross-point architecture with binary-valued MRAM memory cells, but much of the discussion may be more generally applicable.

[0076] Figure 8 One embodiment of the structure of an MRAM memory cell is shown. The voltage applied across the memory cell (between the corresponding word line and bit line of the memory cell) is represented as a voltage source V 施加 813. The memory cell includes a bottom electrode 801, a pair of magnetic layers (reference layer 803 and free layer 807) separated by a separation layer or tunneling layer (in this example, magnesium oxide (MgO) 805), and then a top electrode 811 separated from the free layer 807 by a spacer 809. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 803 and the free layer 807: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have opposite orientations, the memory cell will be in an antiparallel (AP) high resistance state (HRS). MLC implementations will include additional intermediate states. The orientation of the reference layer 803 is fixed, and in Fig.15 The reference layer 803 is also referred to as a fixed layer or a pinned layer.

[0077] Data is written to the MRAM memory cell by programming the free layer 807 to have the same orientation or the opposite orientation. The reference layer 803 is formed so that it will maintain its orientation when programming the free layer 807. The reference layer 803 can have a more complex design including a synthetic antiferromagnetic layer and additional reference layers. For simplicity, the drawings and discussion omit these additional layers and focus only on the fixed magnetic layer that is primarily responsible for the tunneling magnetoresistance in the cell.

[0078] Fig. 9 One embodiment of an MRAM memory cell design to be implemented in a cross point array is shown in more detail. When placed in a cross point array, the top and bottom electrodes of the MRAM memory cell will be two layers of adjacent conductive layers of the array, such as the top and bottom conductive lines of a two level array or a dual layer array. In the embodiment shown here, the bottom electrode is the word line 901 of the memory cell and the top electrode is the bit line 911 of the memory cell, but in some embodiments these can be reversed by reversing the orientation of the memory element. Between the word line 901 and the bit line 911 are the reference layer 903 and the free layer 907, which are also separated by the MgO barrier 905. In Fig. 9 In the embodiment shown, a MgO cap 908 is also formed on top of the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO cap 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. On either side of the memory cell structure are liners 921 and 923, where these liners can be part of the same structure, but in Fig. 9 A portion of fill material 925, 927 is shown on either side of the pads 921, 923 to fill the otherwise empty area of ​​the cross-point structure.

[0079] With respect to the free layer design 907, embodiments include CoFe or CoFeB alloys with a thickness of about 1 nm to 2 nm, where an Ir layer may be interspersed in the free layer near the MgO barrier 905, and the free layer 907 may be doped with Ta, W, or Mo. Embodiments of the reference layer 903 may include a double layer of CoFeB and CoPt multilayers coupled with an Ir or Ru spacer 902. The MgO capping layer 908 is optional, but may be used to increase the anisotropy of the free layer 907. The conductive spacer may be a conductive metal such as Ta, W, Ru, CN, TiN, and TaN, among others.

[0080] To sense the data state stored in an MRAM, a voltage V is applied across the memory cell. 施加 To read an MRAM memory cell, the voltage difference V 施加can be applied in either direction; however, MRAM memory cells have directionality, so in some cases, reading in one direction takes precedence over reading in the other direction. For example, the optimal current amplitude to write a bit to AP (high resistance state, HRS) can be 50% or more greater than the optimal current amplitude to write to P (low resistance state), so the bit error rate (read disturb) is less likely if reading AP (2AP). Some of these cases and the resulting directionality of the read are discussed below. The directionality of the bias specifically enters into some embodiments of MRAM memory cell programming, such as with respect to Fig. 10A and Fig. 10B Further discussion.

[0081] The following discussion will focus on the vertical spin-transfer torque MRAM memory cell, where Figure 8 and Fig. 9 The free layer 807 / 907 includes a switchable magnetization direction that is perpendicular to the plane of the free layer. Spin transfer torque ("STT") is an effect that can modify the orientation of magnetic layers in a magnetic tunnel junction using a spin-polarized current. Charge carriers (such as electrons) have a property called spin, which is a small amount of angular momentum inherent to the carrier. The current is generally non-polarized (e.g., composed of 50% spin-up and 50% spin-down electrons). A spin-polarized current is a current in which there are more electrons of either spin (e.g., a majority of spin-up electrons or a majority of spin-down electrons). A spin-polarized current can be generated by passing an electric current through a thick magnetic layer (reference layer). If the spin-polarized current is directed into a second magnetic layer (free layer), the angular momentum can be transferred to the second magnetic layer, thereby changing the magnetization direction of the second magnetic layer. This is called spin transfer torque. Fig. 10A and Fig. 10B The use of spin transfer torque to program or write to an MRAM memory is shown. The advantages of spin transfer torque magnetic random access memory (STT MRAM) are lower power consumption and better scalability compared to MRAM variants (such as switching MRAM). Compared to other MRAM implementations, STT switching technology requires relatively low power, which virtually eliminates the problem of adjacent bit interference and has more favorable scaling for higher memory cell densities (MRAM cell size is reduced). The latter problem also favors STT MRAM, where the free layer magnetization and the reference layer magnetization are oriented perpendicular to the film plane, rather than in-plane.

[0082] Since the STT phenomenon is easier to describe in terms of electron behavior, Fig. 10A and Fig. 10B and its discussion are given in terms of electron current, where the direction of the write current is defined as the direction of electron flow. Fig. 10A and Fig. 10BThe term "write current" refers to the electron current. When electrons are negatively charged, the electron current will be in the opposite direction to the conventionally defined current, so that the electron current will flow from a lower voltage level to a higher voltage level, rather than the conventional current flowing from a higher voltage level to a lower voltage level.

[0083] Fig. 10A and Fig. 10B Writing to an MRAM memory cell using an STT mechanism is shown, depicting a simplified schematic representation of an example of an STT switching MRAM memory cell 1000, where both the reference layer magnetization and the free layer magnetization are in perpendicular directions. The memory cell 1000 includes a magnetic tunnel junction (MTJ) 1002, which includes an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier (TB) 1014, which acts as an insulating layer between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 1010 is a free layer FL, and its magnetization direction is switchable. The lower ferromagnetic layer 1012 is a reference (or fixed) layer RL, and its magnetization direction is not switchable. When the magnetization in the free layer 1010 is parallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively low. When the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively high. The data ("0" or "1") in the memory cell 1000 is read by measuring the resistance of the memory cell 1000. In this regard, the electrical conductors 1006 / 1008 attached to the memory cell 1000 are used to read the MRAM data. By design, both the parallel configuration and the antiparallel configuration remain stable in the quiescent state and / or during a read operation (at a sufficiently low read current).

[0084] For both the reference layer RL 1012 and the free layer FL 1010, the magnetization directions are in perpendicular directions (ie, perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). Fig. 10A and Fig. 10B As shown, the magnetization direction of the reference layer RL 1012 is up, and the magnetization direction of the free layer FL 1010 can be switched between up and down, which is also perpendicular to the plane.

[0085] In one embodiment, tunnel barrier 1014 is made of magnesium oxide (MgO); however, other materials may be used. Free layer 1010 is a ferromagnetic metal that has the ability to change / switch its magnetization direction. Multilayers based on transition metals such as Co, Fe, and their alloys may be used to form free layer 1010. In one embodiment, free layer 1010 comprises an alloy of cobalt, iron, and boron. Reference layer 1012 may be many different types of materials, including (but not limited to) multilayers of cobalt and platinum and / or cobalt and iron alloys.

[0086] To "set" the MRAM memory cell bit value (ie, select the direction of the free layer magnetization), an electron write current 1050 is applied from conductor 1008 to conductor 1006, as Fig. 10A Depicted. To generate the electron write current 1050, the top conductor 1006 is placed at a higher voltage level than the bottom conductor 1008 due to the negative charge of the electrons. The electrons in the electron write current 1050 become spin polarized as they pass through the reference layer 1012, because the reference layer 1012 is a ferromagnetic metal. When the spin polarized electrons tunnel through the tunnel barrier 1014, the conservation of angular momentum can cause a spin transfer torque to be applied to both the free layer 1010 and the reference layer 1012, but the transfer torque is not sufficient (by design) to affect the magnetization direction of the reference layer 1012. On the contrary, if the initial magnetization orientation of the free layer 1010 is antiparallel (AP) to the reference layer 1012, then the spin transfer torque is sufficient (by design) to switch the magnetization orientation in the free layer 1010 to parallel (P) to the magnetization orientation of the reference layer 1012, which is called antiparallel to parallel (AP2P) writing. Then, before and after turning off this electron write current, the parallel magnetization will remain stable.

[0087] In contrast, if the magnetization of the free layer 1010 and the magnetization of the reference layer 1012 are initially parallel, the magnetization direction of the free layer 1010 can be switched to be antiparallel to the reference layer 1012 by applying an electron write current in the opposite direction to that in the previous case. Fig. 10B As depicted, an electron write current 1052 is applied from conductor 1006 to conductor 1008 by applying a higher voltage level on lower conductor 1008. This will write the free layer 1010 in the P state to the AP state, referred to as parallel to antiparallel (P2AP) writing. Thus, via the same STT physics, the magnetization direction of the free layer 1010 can be deterministically set to either of two stable orientations by judiciously choosing the electron write current direction (polarity).

[0088] The data ("0" or "1") in memory cell 1000 can be read by measuring the resistance of memory cell 1000. Low resistance usually represents a "0" bit, and high resistance usually represents a "1" bit, but alternative conventions sometimes occur. By applying an electronic read current (e.g., Fig. 10A For the flow shown in 1050 ("AP2P direction")), a read current can be applied across the memory cell (e.g., across the magnetic tunnel junction 1002); alternatively, an electronic read current can be applied from conductor 1006 to conductor 1008, such as Fig. 10BIn a read operation, if the electron write current is too high, this may disturb the data stored in the memory cell and change its state. For example, if the electron read current is used Fig. 10B If the P2AP direction is selected, then excessive current levels or voltage levels can switch any memory cell in the low resistance P state to the high resistance AP state. Therefore, although MRAM memory cells can be read in either direction, in various embodiments, the directional nature of the write operation can prioritize one read direction over another read direction, such as the P2AP direction, because more current is required to write a bit in that direction.

[0089] although Fig. 10A and Fig. 10B The discussion is made in the context of electron currents for read currents and write currents, but unless otherwise indicated, subsequent discussion will be made in the context of conventional currents.

[0090] Whether reading or writing 7A to 7D A selected memory cell in an array structure of, the bit line and word line corresponding to the selected memory cell are biased to apply a voltage across the selected memory cell and induce electron flow, as with respect to Fig. 10A or Fig. 10B This will also apply a voltage across the unselected memory cells of the array, which can induce current in the unselected memory cells. Although this wasteful power consumption can be mitigated to some extent by designing the memory cells to have relatively high resistance levels for both the high resistance state and the low resistance state, this will still result in increased current and power consumption and impose additional design constraints on the design of the memory cells and the array.

[0091] One approach to addressing this undesirable current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM, and FeRAM) memory cell. 7A to 7D In , a select transistor can be placed in series with each resistive memory cell element, so that element 701 is now a composite of a selector and a programmable resistor. However, the use of transistors requires the introduction of additional control lines to be able to turn on the corresponding transistor of the selected memory cell. In addition, transistors do not generally scale in the same manner as resistive memory elements, so that the use of transistor-based selectors may be a limiting factor as memory arrays move to smaller sizes.

[0092] An alternative method for the selector element is to use a threshold switch selector device in series with a programmable resistor element. The threshold switch selector has a high resistance (in a disconnected or non-conductive state) when it is biased to a voltage below its threshold voltage, and has a low resistance (in a conductive or conducting state) when it is biased to a voltage above its threshold voltage. The threshold switch selector remains on until its current drops below the holding current, or the voltage drops below the holding voltage. When this happens, the threshold switch selector returns to the disconnected state. Therefore, in order to program the memory cell at the intersection, a voltage or current sufficient to turn on the associated threshold switch selector and set or reset the memory cell is applied; and in order to read the memory cell, similarly, before the resistance state of the memory cell can be determined, the threshold switch selector must be activated by turning on. One set of examples of threshold switch selectors is the bidirectional threshold switch material of a bidirectional threshold switch (OTS).

[0093] Fig.11A and Fig. 11B Embodiments for incorporating a threshold switch selector into an MRAM memory array having a cross-point architecture are presented. Fig.11A and Fig. 11B The example shows two MRAM cells in a two-layer cross-point array, such as Fig.7D , but is shown in a side view. Fig.11A and Fig. 11B The first conductive line at the bottom, i.e., word line 11100, the first conductive line at the top, i.e., word line 2 1120, and the second conductive line in the middle, i.e., bit line 1110, are shown. In these figures, for ease of presentation, all of these lines are shown extending from left to right across the page, and through the cross-point array, they would be more accurately represented as Fig.7D , wherein the word line or first conductive line or wire extends in a direction parallel to the surface of the underlying substrate, and the bit line or second conductive line or wire extends in a second direction parallel to the surface of the substrate, the second direction being substantially orthogonal to the first direction. The MRAM memory cell is also shown in simplified form, showing only the reference layer, the free layer and the intermediate tunnel barrier, but in actual implementation, it will generally include the above description of Fig. 9 The additional structure.

[0094] An MRAM cell 1102 including a free layer 1101, a tunnel barrier 1103, and a reference layer 1105 is formed above a threshold switch selector 1109, wherein the series combination of the MRAM device 1102 and the threshold switch selector 1109 together forms a layer 1 cell between a bit line 1110 and a word line 1 1100. Except for some voltage drop across the threshold switch selector 1109, the series combination of the MRAM device 1102 and the threshold switch selector 1109 operates largely as described above with respect to Fig. 10A and Fig. 10B However, it is initially necessary to apply a voltage higher than the threshold voltage V of the threshold switch selector 1109. th The voltage is used to turn on the threshold switch selector 1109, and then the bias current or voltage needs to be maintained high enough to be higher than the holding current or holding voltage of the threshold switch selector 1109 so that it remains turned on during subsequent read or write operations.

[0095] On the second layer, an MRAM cell 1112 including a free layer 1111, a tunnel barrier 1113, and a reference layer 1115 is formed above a threshold switch selector 1119, wherein the series combination of the MRAM device 1112 and the threshold switch selector 1119 together forms a layer 2 cell between the bit line 1110 and the word line 2 1120. The layer 2 cell will operate like the layer 1 cell, but the lower conductor now corresponds to the bit line 1110, and the upper conductor is now the word line, i.e., word line 2 1120.

[0096] exist Fig.11A In the embodiment of the present invention, the threshold switch selector 1109 / 1119 is formed below the MRAM device 1102 / 1112, but in an alternative embodiment, the threshold switch selector can be formed above the MRAM device for one or both layers. Fig. 10A and Fig. 10B As discussed, MRAM memory cells have directionality. Fig.11A In the embodiment, MRAM devices 1102 and 1112 have the same orientation, with free layers 1101 / 1111 above reference layers 1105 / 1115 (relative to a substrate not shown). Forming these layers between conductive lines having the same structure can have many advantages, especially for processing, because each of the two layers, and subsequent layers in embodiments having more layers, can be formed according to the same processing sequence.

[0097] Fig. 11B Shown with Fig.11A An alternative embodiment is similarly arranged, except that in the layer 2 unit, the positions of the reference layer and the free layer are reversed. More specifically, as Fig.11AAs shown, between word line 1 1150 and bit line 1160 , layer unit 1 includes an MRAM structure 1152 having a free layer 1151 formed over a tunnel barrier 1153 , which in turn is formed over a reference layer 1155 , wherein the MRAM structure 1152 is formed over a threshold switch selector 1159 . Fig. 11B The second layer of the embodiment of the present invention also has an MRAM device 1162 formed above the threshold switch selector 1169 between the bit line 1160 and the word line 2 1170, but with respect to Fig.11A , the MRAM device 1162 is inverted such that the reference layer 1161 is now formed above the tunnel barrier 1163 and the free layer 1165 is now formed below the tunnel barrier 1163 .

[0098] Although Fig. 11B The embodiment of the invention requires a different processing sequence for forming these layers, but in some embodiments, it can have advantages. In particular, the directionality of the MRAM structure can make Fig. 11B The embodiment of is attractive because when writing or reading in the same direction (relative to the reference layer and the free layer), the bit line will be biased the same amount for both the lower layer and the upper layer, and both word lines will also be biased the same amount. For example, if both the layer 1 memory cell and the layer 2 memory cell are sensed in the P2AP direction (relative to the reference layer and the free layer), the bit line layer 1160 will be biased, such as in the P2AP direction, the bit line 1160 is biased low (e.g., 0V) for both the upper cell and the lower cell, and both word line 1 1150 and word line 2 1170 are biased to a higher voltage level. Similarly, with respect to writing, to write the high resistance AP state, bit line 1160 is biased low (e.g., 0V) for both the upper cell and the lower cell, and word line 1 1150 and word line 2 1170 are both biased to a higher voltage level; and to write the low resistance P state, bit line 1160 is biased to a high voltage level, and word line 1 1150 and word line 2 1170 are both biased to a low voltage level. In contrast, for Fig.11A In an embodiment of the present invention, the bit lines and word lines will need to have their bias levels reversed in order to perform any of these operations on a higher level relative to a lower level.

[0099] Reading data from or writing data to an MRAM memory cell involves passing current through the memory cell. In embodiments where the threshold switch selector is placed in series with the MRAM device, the threshold switch selector needs to be turned on by applying a sufficient voltage across the series combination of the threshold switch selector and the MRAM device before current can pass through the MRAM device. Fig.12 and Fig.13This activation of the threshold switch selector is considered in more detail in the context of a read operation.

[0100] Fig.12 and Fig.13 are used in read operations respectively Fig.11A and Fig. 11B One embodiment of a set of waveforms of current and voltage of layer 1 unit, wherein Fig.12 and Fig.13 The time axes of are aligned and on the same scale. In this embodiment for a read operation, the read is performed in the P2AP direction, where word line 1 1100 / 1150 is biased high and bit line 1110 / 1160 is set low (e.g., 0V), so that the (conventional) current flows upward, first through the reference layer 1105 / 1155, and then through the free layer 1101 / 1151. (In terms of electron current, the electron flow will be opposite to the conventional current as shown in FIG. Fig. 10B .

[0101] exist Fig.12 and Fig.13 In an embodiment, a forced current method is used, in which the memory is read from the reference layer side with a read current I from a current source in the driver circuit system for the line 读取 Drive. Fig.12 As shown by the solid line 1201, the current increases to I 读取 value and maintains that value for the duration of the current read operation. This current will move the line that supplies current to the selected memory cell, such as Fig.11A / B and also supports any leakage in the path. Fig.13 As shown at 1251 in FIG. 1 , when the threshold switch selector is in the off state, the voltage across the parallel combination of the threshold switch selector and the resistive MRAM element ramps up. Once the voltage across the threshold switch selector reaches the threshold voltage V of the threshold switch selector at 1253 阈值 , the threshold switch selector will turn on and switch to the low resistance state.

[0102] Once the threshold switch selector is in the on state, I 读取 Current will flow through the selected memory cell. Fig.12 The dashed line 1203 shows that when the threshold switch selector is turned on at 1253, it reroutes the current through the memory cell, jumping from zero to I 读取 When the current level is kept fixed at I 读取When the voltage across the memory cell will drop to a level that depends on the series resistance of the MRAM device and the on-state resistance of the threshold switch selector. For a binary implementation, the memory cell will have a high resistance antiparallel state and a low resistance parallel state. The resulting voltage across the series connected MRAM device and the threshold switch selector and the series decoding transistor is responsive to the I of the high resistance state (HRS) and the low resistance state (LRS). 读取 The current is directed to 1 of the N word lines and 1 of the N bit lines, which are shown as 1255 and 1253, respectively. The resulting voltage difference can then be measured by a sense amplifier to determine the data state stored in the memory cell. Although the discussion here is conducted in the context of an MRAM-based memory cell placed in series with a threshold switch selector, the reading technique can be similarly applied to other programmable resistive memory cells, such as PCM, FeRAM, or ReRAM devices.

[0103] Fig.13 The voltage is shown applied at 1251 to ramp up until it reaches V at 1253 阈值 , and then drops to the high resistance state level (HRS) at 1255 or the low resistance state (LRS) at 1253. In a real device, there will be some delay when the voltage spike at 1253 drops to 1255 or 1253 due to resistance and capacitance. This is caused by Fig.14 Example display for low resistance state.

[0104] Fig.14 An example of the voltage across an MRAM device when a threshold switch selector switches from an off state to an on state is shown. Fig.13 , Fig.14 shows the voltage V across the MRAM device only MRAM ,and Fig.13 Represents the voltage across the series combination of the threshold switch selector and the MRAM device. Initially, before the threshold switch selector is turned on, the voltage across the MRAM device will be zero as the applied voltage ramps up to the Vthreshold voltage. Once the threshold switch selector is turned on, current begins to flow through the MRAM device and the voltage across the MRAM device will spike to the Vthreshold level minus the reduced voltage Vhold across the threshold switch selector. Therefore, V MRAM will jump from 0V to ΔV = (Vthreshold - Vhold), after which it will decay the voltage drop across the MRAM device in the low resistance state in response to the applied IRead, V MRAM (LRS).

[0105] The VMRAM voltage drops to near V MRAMThe rate at which the (LRS) level is reduced depends on the spike from the “snapback voltage” ΔV (which is the difference between (Vthreshold - Vhold)) and V MRAM The size of the (LRS), and the rate at which charge can flow out of the device, depends on the internal resistance of the MRAM and the selector when the selector is turned on, the RC characteristics of the memory cell and the lines between which the memory cell is connected (e.g., the word line from the word line driver to the memory cell and the bit line from the bit line driver to the memory cell). For lower capacitance and lower resistance, dissipation is faster. This behavior has some practical implications for the operation of the memory cell.

[0106] The first effect is that both the low resistance state and the high resistance state will decay, e.g. Fig.14 As shown, Fig.14 The low resistance state is shown. The high resistance state will show similar behavior, but with a higher asymptotic state Vfinal determined by the path resistance × Iread. In order to distinguish between the two states, they need to be separated by enough margin that a sensing operation cannot be performed until enough time has passed so that the two states have well-defined and distinguishable voltage levels.

[0107] Another effect is that the spike may disturb the data stored in the memory cell. Fig. 10A and Fig. 10B As discussed, the state of an MRAM memory can be changed by passing a current through the memory cell such that if the voltage across the memory cell and / or the current through the memory cell is high enough for a long enough time, it will change from a parallel state to an anti-parallel state (P2AP write), depending on the direction of the current flow, as shown in FIG. Fig. 10B As shown, or the antiparallel state is changed to a parallel state (AP2P write), as Fig. 10A For example, Fig.12 and Fig.13 The reading process is described as being performed in the P2AP direction such that Fig.14 The disturbance caused by the waveform of can switch the low resistance state memory cell to the high resistance state before the data state can be stored.

[0108] Fig.15 An example of the current Icell through the MRAM device when the threshold switch selector switches from the off state to the on state is shown (the current graph corresponds to Fig.14 Voltage curve of ). Fig.12 , Fig.14 shows the current through the MRAM device only, while Fig.12represents the current requested from the driver (e.g., the current through the series combination of the word line, bit line, threshold switch selector, and MRAM device). Initially, before the threshold switch selector turns on, as the applied voltage ramps up to V 阈值 Voltage, the current through the MRAM device will be zero (or close to zero). The word line and / or bit line to the memory cell may be charged during this time. Once the threshold switch selector is turned on, a relatively high current (which may be referred to as "snapback current" or "Isnapback") flows through the MRAM device as the parasitic capacitors formed between the word lines and / or bit lines discharge. The discharge rate may depend on many factors, including the resistance and capacitance of the word lines and / or bit lines connected to the memory cell.

[0109] Fig.15 Two curves are shown corresponding to different snapback currents experienced by different memory cells in the same memory array. The first curve 1562 shows a first snapback current I snapback1, while the second curve 1560 shows a second snapback current I snapback2 that is less than I snapback1. Moreover, the first curve 1562 shows a slower decay time (t1) than the decay time (t2) of the second curve 1562. The snapback current and the corresponding snapback current decay time can vary between memory cells in the same array, which can have certain consequences. For example, a higher snapback current and a longer current decay time (e.g., the first curve 1562) can result in more interference and more errors (e.g., a higher bit error rate or "BER") than a memory cell with a lower snapback current and a shorter decay time (e.g., the second curve 1560).

[0110] The snapback current and decay time may be affected by various factors, including the size of the lines connecting the memory cells to the corresponding drivers. For example, a line (e.g., a word line and / or a bit line) has a series resistance that depends on its size (e.g., may increase proportionally with length). A line (e.g., a word line and / or a bit line) also has a certain capacitance that may increase with length (e.g., a parasitic capacitor formed with adjacent lines). Word line drivers and bit line drivers may be connected to different memory cells in an array by lines of different lengths (e.g., some memory cells are closer to word line drivers and / or bit line drivers (near cells) than other memory cells (distant cells)). The different geometries of such lines may affect the snapback current and snapback current decay time of different memory cells in the array, and may therefore affect error rates.

[0111] Fig.16An example of a memory structure 602 and corresponding word line drivers 660 and bit line drivers 650 is shown (the word line drivers 660 and bit line drivers 650 may be located on a memory die having the memory structure 602 or on a separate die connected to the memory die containing the memory structure 602). Two bit lines BL0 and BLn and two word lines WL0 and WLn are shown with a first memory cell 1670 and a second memory cell 1672 (additional lines and memory cells are omitted for clarity). The first memory cell 1670 (near memory cell) is relatively close to both the word line driver 660 and the bit line driver 650. The first memory cell 1670 is connected to the bit line driver 650 through BLn with an effective bit line length of BLmin, and is connected to the word line driver 660 through WL0 with an effective word line length of WLmin. This gives a combined electrical distance of BLmin+WLmin (combination of effective word line and bit line lengths). The second memory cell 1672 (far memory cell) is relatively far from both the word line driver 660 and the bit line driver 650. The second memory cell 1672 is connected to the bit line driver 650 via BL0 with an effective bit line length of BLmax, and to the word line driver 660 via WLn with an effective word line length of WLmax. This gives a combined electrical distance of BLmax+WLmax (a combination of the effective word line and bit line lengths). Due to the different electrical distances and their associated resistances and capacitances, the first memory cell 1670 and the second memory cell 1672 may have different snapback currents Isb and different snapback current decay times (e.g., the first memory cell 1670 may have a higher snapback current and a longer snapback current decay time as the first curve 1562, compared to the second memory cell 1672, which may have characteristics as the second curve 1560). Due to these differences and / or for any other reason, the data read from the first memory cell 1670 and the second memory cell 1672 may have different error rates (e.g., the data from the first memory cell 1670 may have a higher BER than the data from the second memory cell 1672). While certain examples may relate to mitigating snapback-related effects, aspects of the present technique are not limited to such applications, and the present technique may be applied to mitigate other effects (eg, effects that may produce errors that are not uniform across a die).

[0112] The first memory cell 1670 and the second memory cell 1672 represent situations where the memory cells of the memory structure 602 are at either end of a range of possible electrical distances from the bit line drivers and the word line drivers. Other memory cells may have electrical distances somewhere within the range with corresponding snapback currents and snapback current decay times between those of the first memory cell 1670 and the second memory cell 1672, which may result in error rates between those of the first memory cell 1670 and the second memory cell 1672. The effect of the snapback current on some or all of the memory cells may be at least partially predictable based on the electrical distances of the memory cells (e.g., based on the respective distances to the word line drivers and the bit line drivers).

[0113] In some memory systems, data from different arrays (e.g., on different memory dies) can be read in parallel and combined for ECC decoding. This parallel operation can provide high throughput and allow ECC codewords to be distributed across multiple arrays.

[0114] Fig.17A 17 shows an example of an arrangement including five media (Medium 1-Medium 5) connected to a memory controller 1780, which includes an ECC engine 1782. For example, each of the media 1-5 may be a memory package 104 (e.g., such as a memory package 104) connected to the controller. Figure 1 As shown), memory die 292 (as Figure 4 ) or an integrated memory component 600 (e.g., as FIG. 6A to FIG. 6B ). Fig.17A In the example of FIG. 1 , medium 1-5 is connected to memory controller 1780 via communication channels (e.g., channels of memory bus 294) including address communication channel 1784 and data communication channel 1786. Address communication channel 1784 is shared by medium 1-5 (a common communication channel), while data communication channel 1786 is a dedicated communication channel, with each medium having one data communication channel (e.g., x bits wide, where x can be any suitable number, such as 16, 32, 64, 128, or more).

[0115] In an example of a read operation, the memory controller 1780 sends a read address to the medium 1-5 via the address communication channel 1784, thereby specifying one (or more) addresses (target addresses) to be read. Since the address communication channel 1784 is common to the medium 1-5, each medium in the medium 1-5 receives the same address. The medium 1-5 can read the data in response to the read command and send the data to the ECC engine 1782 (e.g., ECC engine 226 / 256) in the memory controller 1780 via the data communication channel 1786. In this example, each medium sends x bits at a time. The medium 1-5 can read and send data in parallel, so that the ECC engine 1782 receives 5x bits of data in parallel (e.g., 4x bits of user data and x bits of ECC data). The ECC engine 1782 can perform ECC correction on the received 5x bits together (e.g., the ECC engine 1782 can be configured to have a codeword size of 5x bits). In other examples, different amounts of data may be sent from different numbers of mediums (eg, more or less than 5), and the ECC engine 1782 may be configured to encode / decode using codewords of appropriate size.

[0116] In the example of a write operation, the memory controller 1780 sends a read address to the media 1-5 via the address communication channel 1784, thereby specifying the address (or addresses) to be written. The ECC engine 1782 may generate a 5x-bit ECC codeword (e.g., may receive 4x-bits of user data and generate a 5x-bit codeword), and may send x bits to each of the media 1-5 via the data communication channel 1786. In response, the media 1-5 may each write the corresponding x bits.

[0117] FIG. 17B to FIG. 17D An exemplary structure of a medium 1788 (eg, any of mediums 1 - 5 ) is shown. Fig. 17B A medium 1788 is shown including K memory banks (1-K, where K may be any suitable number, such as 8, 16, 32, 64, or more).

[0118] Fig. 17C A memory bank 1790 (eg, Fig. 17B 1-K) of any memory bank, the memory bank includes x active modules, including exemplary module 1792 (shaded). The modules are configured to read in parallel and perform data transfer in parallel, so that x bits can be read and sent in parallel from the modules of the selected memory bank.

[0119] Fig.17D As shown in the previous 7A to 17DThe arrangement shown in FIG. 17 shows an exemplary structure of a module 1792 including n bit lines (two groups of n / 2 bit lines "n / 2 BL") and n word lines (two groups of n / 2 bit lines each having "n / 2 WL"). Fig.16 In this example, the number of bit lines and word lines is equal (n bit lines and n word lines), but in other examples, these numbers may be different. Module 1792 also includes a driver circuit 1794 (e.g., word line driver circuit 660 and / or bit line driver circuit 650), which is shown in this example as being located in the middle of module 1792, with portions of the memory array located on either side. In some cases, the driver circuit may be located below the memory array. In some cases, the driver circuit is located in multiple locations (e.g., some driver circuits are located below the memory array, and some driver circuits are located between portions of the memory array or in the peripheral area of ​​the array). The metal connections between the driver circuit and the array components (e.g., word lines and bit lines) may extend horizontally and / or vertically. In some cases, the driver circuit is located on a die separate from the memory die (e.g., in an integrated memory component). The present technology is not limited to the driver circuit at any particular location. Some logic circuits associated with the driver circuit may be located together with the driver circuit (e.g., module 1792 may include some logic circuits to control the driver circuit 1794).

[0120] Fig.18A The following diagram shows the relationship between the number of media (e.g., Fig.17A The first example of a read operation of media 1-5 of FIG. 17 is shown. The read command may specify a selected memory bank 1790 and a selected memory cell (e.g., an intersection of a selected word line and a selected bit line). In each medium, the specified memory cell of each module of the selected memory bank 1790 is read in parallel. Fig.18A In the example of FIG. 1 , the designated memory cell is shown in the lower right corner (shaded) of each module 0-x in the selected storage body 1790 of each of the media 1-N. This location may correspond to Fig.16 The location of the first memory cells 1670 (close to the memory cells) is shown such that data read from these memory cells may have a relatively high error rate. Fig.18A In the example of , the read data bits 1894 (x bits from each of media 1-N) may be sent in parallel to an ECC circuit (e.g., ECC engine 1782) where they are decoded together as a unit (ECC codeword), which may have a relatively high error rate and therefore a relatively high UE probability.

[0121] Fig.18B Shown for Fig.18AAnother example of a read operation of N media. In this example, the read command specifies different memory cells (different intersections of word lines and bit lines). In each medium, the specified memory cells of each module of the selected memory body 1790 are read in parallel. Fig.18B In the example of FIG. 1 , the designated memory cell is shown in the upper left corner (shaded) of each module 0-x in the selected storage bank 1790 of each of the media 1-N. This location may correspond to Fig.16 The second memory cells 1672 (far memory cells) are positioned so that data read from these memory cells may have a relatively low error rate. Fig.18B In the example of , the read data bits 1896 (x bits from each of media 1-N) can be sent in parallel to an ECC circuit (e.g., ECC engine 1782) where they are decoded together as a unit (ECC codeword), which may have a relatively low error rate and therefore a relatively low UE probability.

[0122] Aspects of the present technology are directed to accessing data in an MRAM structure such that the error rate (e.g., BER) and probability of UE in any portion of the data read together and ECC decoded together are managed to mitigate ECC non-uniformity (e.g., Fig.18A For example, data to be ECC decoded as a unit may be stored and subsequently read from different corresponding locations in different media and / or different locations in different modules of the media and / or originally inconsistent locations.

[0123] Fig.19 An example of a read operation is shown in which the control circuitry of each of the media 1-N (e.g., the system control logic 560 / 659) applies a different offset to the read address received via the address communication channel 1784 to generate a corresponding offset address (where the number of media N may be any suitable number, e.g., 2, 4, 8, 16, or more). For example, medium 1 may apply a first offset (offset 1) that causes the memory cell at the bottom right of the memory module 1-x of the selected memory bank 1790 to be read (similar to Fig.18A ) to obtain data 1902 (each module 1-x is read in parallel at the same corresponding position). Medium N may apply an Nth offset (Offset N) that causes the top left memory cell of the memory module 1-x of the selected memory bank 1790 to be read (similar to Fig.18B) to obtain data 1904. Medium 2 to Medium N-1 may apply other offsets to cause memory cells at intermediate locations to be read to obtain additional data (e.g., offset 2 in Medium 2 to obtain data 1906). The separate address offsets used in each medium may include at least one of a word line offset and / or a bit line offset that causes modules of different media to be read at different locations (in this example, modules of selected memory banks in any given medium are read at a common offset address). Data from all media 1-N (including data 1902, 1904, and 1906) may be read in parallel and may be sent in parallel to an ECC circuit where the data is decoded. Because the data comes from different corresponding locations in different media, the combined data may have an intermediate error rate (e.g., in Fig.18A and Fig.18B The error rates for different codewords may be relatively uniform (e.g., as in FIG. 18A to FIG. 18B Compared with reading all data of the codeword from the same position in all media as in , the probability of the UE is relatively low.

[0124] Although Fig.19 An example of a read operation is shown, but a write operation may use the same offset so that the codewords generated by the ECC encoding are spread over different locations in different media. For example, data 1902, 1904, 1906 and any additional portions of data from media 3 to N-1 may be part of an ECC codeword written in parallel at the locations shown.

[0125] Fig.19 The scheme may be implemented by providing a control circuit with an offset register in each medium, which offset register records the corresponding individual address offset, where different media have different address offsets (e.g., each medium 1-N has a different address offset value stored in the register of the corresponding control circuit). The offset address value may be selected based on the number of media in the module and the number of memory cells (e.g., the number of cells may be divided by the number of media so that the offset causes the memory cells of different media to be accessed at locations equally spaced from each other). A memory controller (e.g., controller 102) may determine how many media (e.g., memory dies) are present in the system and may configure the offset register of each die to evenly spread out the addresses (e.g., so that increasing the number of dies will reduce the offset in proportion to the inverse of the number of dies). For example, Fig.19A medium 1 having a control circuit 1910 including an offset register (e.g., register 561) storing offset 1, a medium 2 having a control circuit 1912 including an offset register storing offset 2, and a medium N having a control circuit 1914 including an offset register storing offset N are shown. The address offsets may be set during configuration of the memory system in a one-time operation or may be reconfigured during the operating life of the memory system. The control circuits of the mediums 1-N (including control circuits 1910, 1912, and 1914) may be configured to: receive read addresses in parallel from a memory controller (e.g., via a common address communication channel 1784); apply corresponding individual address offsets to the read addresses to generate corresponding offset addresses; read portions of data (e.g., data 1902, 1906, ..., 1904) from the corresponding offset addresses; and send the data read from the offset addresses to the memory controller to perform error correction code (ECC) decoding of the data portions.

[0126] Fig. 20 Another read operation is shown, where data is stored and read from an offset address to provide an ECC codeword including data from a range of locations. Fig. 20 In the example of , an offset is applied and a corresponding offset address is generated by the memory controller 1780. In this example, no offset is applied to media 1 to media N, and an offset register as in the previous example may not be included. Each medium receives a different offset address from the memory controller 1780. For example, medium 1 receives offset address 1, medium 2 receives offset address 2, and medium N receives offset address N. In this example, a dedicated communication channel 2020 is used to provide a different offset address to each medium so that data is read from the corresponding offset address (one address communication channel for each medium so that different offset addresses can be sent in parallel). The data from different corresponding locations is then sent to the ECC engine to be decoded as a unit as before.

[0127] In another example, instead of dedicated communication channel 2020, a common address communication channel (e.g., address communication channel 1784) may be used to send (e.g., serially send) different addresses to different media (e.g., control circuits in each medium may parse commands such as read commands or write commands to determine whether they are the destinations for the command).

[0128] Fig.21 Another read operation is shown, where data is stored and read from an offset address to provide an ECC codeword including data from a range of locations. Fig.21In the example of , an offset is applied module by module within the selected memory bank of each medium. For example, in medium 1, modules 0-x of the selected memory bank 1790 are accessed at different positions indicated by the offset stored in register 2130. The memory cell at the bottom right of module 0 is read in parallel with the memory cell at the top left of module x and the middle memory cells in modules 1 to N-1. The data 2132 read from these memory cells comes from memory cells at different positions relative to the word line driver and the bit line driver, and may have an error rate that is an average of the error rates at different positions within the module. Similarly, in each of the media from medium 2 to medium N, the data in the selected memory bank 1790 is read from different positions in different modules, and may have an error rate that is an average of the error rates at different positions within the module. Data 2132 from medium 1, data 2134 from medium 2 to data 2136 from medium N can be read in parallel and can be sent in parallel to the ECC engine for decoding together.

[0129] Since data is read from a certain range of positions in each medium, the data from each medium may have a similar error rate. Each medium can apply a group of similar offsets so that the read mode can be the same for all media. Each medium includes a group of registers 2130, which store the offsets applied when writing and reading data. In some cases where different bits are sampled in each module, registers 2130 may be unnecessary. In one example, different offsets are applied to each module. In another example, modules are grouped into groups with different offsets (for example, x modules can be grouped into four groups, each group of x / 4 modules, wherein each group has a corresponding offset, and there are four offsets in registers 2130). In some cases, the offsets of different media can be different (for example, the aspect of module-by-module offset can be combined with medium-by-medium offset).

[0130] Fig. 22 An example of a method according to aspects of the present technology is shown. The method includes: sending a read address to a plurality of memory dies (2240); applying a plurality of address offsets to the read address to generate a plurality of corresponding offset addresses in the plurality of memory dies, the plurality of corresponding offset addresses including at least a first offset address in a first memory die and a second offset address in a second memory die (2242). The method also includes: reading a portion of data from the corresponding offset addresses of the memory dies, including reading a first portion of the data from the first offset address and reading a second portion of the data from the second offset address (2244); and decoding the portion of the data including the first portion and the second portion together for all memory dies in the plurality of memory dies (2246).

[0131] Fig. 22 The method can be implemented in various ways according to various aspects of the present technology. Fig.23 An exemplary implementation is shown, which includes: sending a read address to a plurality of memory dies including N memory dies, each memory die including a corresponding array, the read address being received in parallel by the plurality of memory dies via a common communication channel between a memory controller and the plurality of memory dies (2350) (e.g., Fig.19 or Fig.21 N media of the memory die receive the same read address via address communication channel 1784); and applying N different address offsets to the read address so that portions of the data are read from different corresponding locations in each memory die (2352) (e.g., as Figure 19 to Figure 20 Data in 1902, 1904 and 1906 or Fig.21 The method further includes: reading a portion of the data from the corresponding offset addresses of the memory dies, including reading a first portion of the data (e.g., data 1902) from a first offset address and reading a second portion of the data (e.g., data 1904) from a second offset address (2354); sending portions of the data from the plurality of memory dies in parallel through a plurality of communication channels between the plurality of memory dies and the memory controller (2356) (e.g., Fig.17A a data communication channel 1786 between the medium 1-5 and the memory controller 1780); and decoding (2358) portions of the data including the first portion and the second portion of all memory dies in the plurality of memory dies together (e.g., the ECC engine 1782 decodes portions of the data including data 1902 and 1904 together into codewords).

[0132] The offset (e.g., a separate die-specific offset, a module-specific offset, or other offset) may be used for all memory accesses, including read accesses (e.g., as Fig. 22 or Fig.23 Although the above examples are described with respect to read operations and subsequent ECC decoding of the data read using an offset, write operations may also use an offset such that the data to be written is ECC encoded and then decoded according to the offset (e.g., Figures 19 to 21 The offset of the example) is written at a different location. Fig.24 An example of a method of using an offset address when writing is shown (for example, Fig. 22 Or write the data which is then read as shown in 23). Fig.24 The method may be implemented in any suitable memory system, including, for example, 17A to 17D A storage system with multiple media as shown in the example.

[0133] Fig.24 An example of a method is shown, the method comprising: Figures 19 to 21 receiving a write address and write data (2460); applying a corresponding individual address offset (e.g., offset 1-N) to the write address by each memory die (e.g., each of the media 1-N) to generate a corresponding offset address (2462); and writing the write data (2464) at the corresponding offset address in the plurality of memory dies (e.g., writing the data at the same offset address that can be used later when reading the data, such as Figure 19 to Figure 20 Data in 1902, 1904 and 1906 or Fig.21 (as shown in data 2132, 2134 and 2136).

[0134] According to a first set of aspects, an apparatus includes a plurality of control circuits configured to be individually connected to arrays, each of which includes a plurality of non-volatile memory cells. Each non-volatile memory cell includes a programmable resistance element. Each control circuit is configured with an individual address offset. The plurality of control circuits are configured to: receive a read address in parallel from a memory controller; apply the respective individual address offset to the read address to generate a respective offset address; read a portion of data from the respective offset address; and send the data read from the offset address to the memory controller to perform error correction code (ECC) decoding of the portion of the data.

[0135] The plurality of control circuits may include at least a first control circuit configured to be connected to a first array and a second control circuit configured to be connected to a second array, the first control circuit being configured with a first address offset and the second control circuit being configured with a second address offset, such that a first offset address generated by applying the first address offset is closer to at least one of a word line driver or a bit line driver than a second offset address generated by applying the second address offset. The first control circuit and the first array may be located on a first die, and the second control circuit and the second array may be located on a second die. The first control circuit may be located on a first control die configured to be bonded to a first memory die containing the first array, and the second control circuit may be located on a second control die configured to be bonded to a second memory die containing the second array. The plurality of control circuits may include N control circuits, each of the N control circuits being connected to a respective array, the N control circuits applying N different address offsets. The N different address offsets may be configured to cause each array to be read at a different respective position relative to at least one of a word line driver or a bit line driver. The N different address offsets may be configured to cause each array to be read at different corresponding locations that are equally spaced apart from each other. Each array may include multiple memory banks, each memory bank may include multiple modules configured to be read in parallel, and the individual address offset may include at least one of a word line offset or a bit line offset that causes each module of the memory bank indicated by the read command to be read at a common offset address. Each array may include multiple memory banks, each memory bank may include multiple modules configured to be read in parallel, and the individual address offset may cause different modules of the memory bank indicated by the read command to be read at different offset addresses. Each control circuit may include a register to store a corresponding individual address offset.

[0136] In another set of aspects, a method includes: sending a read address to a plurality of memory die; applying a plurality of address offsets to the read address to generate a plurality of corresponding offset addresses in the plurality of memory die, the plurality of corresponding offset addresses including at least a first offset address in a first memory die and a second offset address in a second memory die; reading a portion of data from the corresponding offset addresses of the memory die, including reading a first portion of the data from the first offset address and reading a second portion of the data from the second offset address; and decoding the portion of the data including the first portion and the second portion together for all memory dies in the plurality of memory dies.

[0137] The plurality of memory dies may include N memory dies, each memory die including a corresponding array, the N memory dies applying N different address offsets so that portions of the data are read from different corresponding locations in each memory die. The read address may be received in parallel by the plurality of memory dies through a common communication channel between a memory controller and the plurality of memory dies. Portions of the data from the plurality of memory dies may be sent in parallel through a plurality of communication channels between the plurality of memory dies and the memory controller. The method may also include: receiving a write address and write data by the plurality of memory dies; applying the corresponding individual address offset to the write address by each memory die to generate a corresponding offset address; and writing the write data at the corresponding offset address in the plurality of memory dies. The method may also include selecting the corresponding individual address offset based on the number of memory dies and the location of the word line driver and the bit line driver relative to the address in the die. Applying the corresponding individual address offset to the read address to generate a plurality of corresponding offset addresses in the plurality of memory dies may include applying different address offsets in a first memory die to read different modules of the first memory die in parallel.

[0138] In another set of aspects, a system includes: an error correction code (ECC) circuit; a first array, the first array including a plurality of nonvolatile memory cells, each of which includes a programmable resistance element; a device for applying a first address offset to a read command and a write command from the memory controller directed to a target address to obtain a first offset address, reading data from the first offset address in the first array, and sending the data from the first offset address in the first array to the ECC circuit for ECC decoding; a second array, the second array including a plurality of nonvolatile memory cells, each of which includes a programmable resistance element; and a device for applying a second address offset to a read command and a write command from the memory controller directed to the target address to obtain a second offset address, reading data from the second offset address in the second array, and sending the data from the second offset address in the second array to the ECC circuit for ECC decoding using the data from the first offset address in the first array.

[0139] The first offset address may be located at a first distance from a wordline driver and / or a bitline driver of the first array, the second offset address may be located at a second distance from a wordline driver and / or a bitline driver of the second array, and the first distance may be less than the second distance. The first array and the means for applying the first address offset may be located in a first medium, the second array and the means for applying the second address offset may be located in a second medium, and the ECC circuit may be located in a memory controller die connected to the first medium, the second medium, and an additional medium.

[0140] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0141] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0142] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0143] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0144] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0145] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A device, comprising: a plurality of control circuits configured to be individually connected to arrays, the arrays each comprising a plurality of non-volatile memory cells, each non-volatile memory cell comprising a programmable resistance element, each control circuit being configured with an individual address offset, the plurality of control circuits being configured to: receiving read addresses in parallel from a memory controller; applying the corresponding individual address offset to the read address to generate a corresponding offset address; Reading a portion of data from the corresponding offset address; as well as The data read from the offset address is sent to the memory controller to perform error correction code (ECC) decoding of a portion of the data.

2. The apparatus of claim 1 , wherein the plurality of control circuits include at least a first control circuit configured to be connected to the first array and a second control circuit configured to be connected to the second array, the first control circuit being configured with a first address offset, and the second control circuit being configured with a second address offset, such that a first offset address generated by applying the first address offset is closer to at least one of a word line driver or a bit line driver than a second offset address generated by applying the second address offset.

3. The apparatus of claim 2, wherein the first control circuit and the first array are located on a first die, and the second control circuit and the second array are located on a second die.

4. The apparatus of claim 2, wherein the first control circuit is located on a first control die configured to be bonded to a first memory die containing the first array, and the second control circuit is located on a second control die configured to be bonded to a second memory die containing the second array.

5. The apparatus of claim 1, wherein the plurality of control circuits comprises N control circuits, each of the N control circuits being connected to a corresponding array, the N control circuits applying N different address offsets.

6. The apparatus of claim 5, wherein the N different address offsets are configured to cause each array to be read at a different respective location relative to at least one of a word line driver or a bit line driver.

7. The apparatus of claim 6, wherein the N different address offsets are configured to cause each array to be read at different respective locations that are equally spaced from one another.

8. The apparatus of claim 1 , wherein each array comprises a plurality of memory banks, each memory bank comprises a plurality of modules configured to be read in parallel, and the individual address offsets comprise at least one of a word line offset or a bit line offset, the word line offset or the bit line offset causing each module of the memory bank indicated by the read command to be read at a common offset address.

9. The apparatus of claim 1, wherein each array comprises a plurality of memory banks, each memory bank comprises a plurality of blocks configured to be read in parallel, and the separate address offsets cause different blocks of the memory bank indicated by the read command to be read at different offset addresses.

10. The apparatus of claim 1, wherein each control circuit comprises a register to store a corresponding individual address offset.

11. A method comprising: sending a read address to a plurality of memory dies; applying a plurality of address offsets to the read address to generate a plurality of corresponding offset addresses in the plurality of memory dies, the plurality of corresponding offset addresses comprising at least a first offset address in a first memory die and a second offset address in a second memory die; reading a portion of data from a corresponding offset address of the memory die, including reading a first portion of data from the first offset address and reading a second portion of data from the second offset address; as well as Portions of the data including the first portion and the second portion are decoded together for all memory dies in the plurality of memory dies.

12. The method of claim 11, wherein the plurality of memory dies comprises N memory dies, each memory die comprising a corresponding array, the N memory dies applying N different address offsets such that portions of the data are read from different corresponding locations in each memory die.

13. The method of claim 11, wherein the read addresses are received in parallel by the plurality of memory dies via a common communication channel between a memory controller and the plurality of memory dies.

14. The method of claim 13, wherein portions of the data from the plurality of memory dies are sent in parallel over a plurality of communication channels between the plurality of memory dies and the memory controller.

15. The method according to claim 11, further comprising: receiving, by the plurality of memory dies, write addresses and write data; applying, by each memory die, the respective individual address offset to the write address to generate a respective offset address; as well as The write data is written at the corresponding offset addresses in the plurality of memory dies.

16. The method of claim 11, further comprising selecting the respective individual address offsets based on a number of memory die and locations of word line drivers and bit line drivers relative to addresses in the die.

17. The method of claim 16, wherein applying respective individual address offsets to the read addresses to generate a plurality of respective offset addresses in the plurality of memory dies comprises applying different address offsets in a first memory die to read different modules of the first memory die in parallel.

18. A system, comprising: Error correction code (ECC) circuit; a first array comprising a plurality of nonvolatile memory cells, each nonvolatile memory cell comprising a programmable resistance element; means for applying a first address offset to a read command and a write command from the memory controller directed to a target address to obtain a first offset address, reading data from the first offset address in the first array, and sending the data from the first offset address in the first array to the ECC circuit for ECC decoding; a second array comprising a plurality of nonvolatile memory cells, each nonvolatile memory cell comprising a programmable resistance element; as well as Means for applying a second address offset to read commands and write commands from the memory controller directed to the target address to obtain a second offset address, reading data from the second offset address in the second array, and sending the data from the second offset address in the second array to the ECC circuit for ECC decoding using the data from the first offset address in the first array.

19. The system of claim 18, wherein the first offset address is located at a first distance from the word line drivers and / or bit line drivers of the first array, the second offset address is located at a second distance from the word line drivers and / or bit line drivers of the second array, and the first distance is less than the second distance.

20. The system of claim 18, wherein the first array and the means for applying the first address offset are located in a first medium, the second array and the means for applying the second address offset are located in a second medium, and the ECC circuit is located in a memory controller die connected to the first medium, the second medium, and an additional medium.

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