Methods to reduce the height of the Schottky trench bottom step

Abstract

This invention provides a method for reducing the height of the bottom step of a Schottky trench. A substrate is provided, an N-type epitaxial layer is formed on the substrate, a plurality of first trench gates are formed in the N-type epitaxial layer, an etch stop layer is formed to cover the N-type epitaxial layer and the first trench gates, and an interlayer dielectric layer covering the etch stop layer is formed. A trench serving as a Schottky junction window is formed in the interlayer dielectric layer. The method includes the following steps: photolithography defines the Schottky trench formation region; a first dry etching is performed to form a first opening; wet etching is performed to remove all the interlayer dielectric layer remaining below the bottom surface of the first opening to the etch stop layer; a second dry etching is performed to open the exposed etch stop layer, forming a second opening as a Schottky trench, making the top of the exposed Schottky trench more flat. This invention results in a flatter Schottky barrier metal layer at the undercut notch location, leading to a significantly improved final morphology.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for reducing the height of the bottom step of a Schottky trench. Background Technology

[0002] Schottky diodes have advantages such as low forward voltage drop and high switching frequency, and are widely used in power device fields such as switching power supplies and drive circuits.

[0003] However, traditional Schottky diodes have large reverse leakage current, which makes the device prone to soft breakdown and reduces the breakdown voltage. To solve this problem, the industry has developed TMBS devices.

[0004] like Figure 1 The diagram shown is a schematic of the structure of a conventional TMBS device. An N-type epitaxial layer 202 is formed on the surface of an N-type semiconductor substrate 201. A trench gate structure is formed in the N-type epitaxial layer 202, including trenches, a gate dielectric layer 204 formed on the inner surface of the trenches, and a polysilicon gate 203 filled in the trenches. The trench gate structure is a MOS structure.

[0005] A Schottky barrier metal layer covers the surface of the N-type epitaxial layer 202 outside the trench gate structure, i.e., outside the trench. The Schottky barrier metal layer includes a Ti layer 205 and a TiN layer 206. The Schottky barrier metal layer and the N-type epitaxial layer 202 form a Schottky contact.

[0006] A front metal layer 208 needs to be formed on top of the Schottky barrier metal layer. The front metal layer 208 leads out the anode of the TMBS device. The location of the anode region is defined by the passivation layer 207.

[0007] A back metal layer 209 is formed on the back side of an N-type semiconductor substrate 201, and a cathode is led out from the back metal layer 209.

[0008] TMBS device working principle: Under normal bias, the Schottky junction turns on with a small turn-on voltage, retaining the forward conduction characteristics of the Schottky diode; under reverse bias, the MOS structure depletes the N-type epitaxial layer 202 between the trenches, reducing the surface electric field, thereby reducing leakage current and increasing the device breakdown voltage.

[0009] TMBS devices are typically integrated into power devices such as power MOSFETs, such as Figure 2 The diagram shown is a circuit diagram of an existing power device that integrates a TMBS device. Figure 2 In this configuration, the power device comprises a parallel structure consisting of multiple MOSFET units connected in parallel, and a TMBS device. The TMBS device employs... Figure 1 The structure shown.

[0010] The gates (G) of each MOSFET unit are connected together, the sources (S) are connected together, and the drains (D) are connected together. In the TMBS device, the anode is connected to the source (S), and the cathode is connected to the drain (D).

[0011] In shielded gate trench (SGT) power devices, the trench gate structure also includes an SGT structure. The SGT process flow for integrated Schottky diodes involves inserting a Schottky process loop between the contact hole (CT) process loop and the barrier metal in conventional products. The overall process flow is as follows:

[0012] Trench->Poly->body->IMP->Source->IMP->CT->Schottky(PH+ETCH+IMP)->barrier->WEB->TM->PV / PI.

[0013] In this context, Trench represents the gate trench formation process, Poly represents the polysilicon gate formation process, Body IMP represents body ion implantation, Source IMP represents source ion implantation, CT represents the contact hole opening formation process, Schottky represents the Schottky process ring, and (PH+ETCH+IMP) in Schottky represents the three sub-steps of Schottky, where PH represents the photolithographic definition of the Schottky trench, ETCH represents the etching of the Schottky trench, and IMP represents Schottky ion implantation. Barrier represents the barrier metal formation process, WEB represents the tungsten filling and etch-back process of the contact hole, TM represents the front metal layer formation process, and PV / PI represents the passivation layer and pad window formation process.

[0014] The existing etching process for Schottky trenches uses a two-step process: dry etching and wet etching. The wet process requires more than 50% over-etching, which can easily result in an excessively large undercut, leading to problems in the formation of the barrier metal layer.

[0015] The existing baseline process forms Schottky trenches at the undercut location after wet etching with relatively straight sidewalls and a step height greater than the tip of the mesa region between the gate trenches. This is detrimental to the formation of a barrier metal layer during the subsequent sputtering of Schottky metals such as Ti and TiN.

[0016] like Figure 3The image shown is an electron microscope image of a device after wet etching of the Schottky trench in the existing TMBS device manufacturing method; the step height between the undercut and plateau regions reaches 714 angstroms.

[0017] like Figure 4 The image shown is an electron microscope image of the device after the Schottky barrier metal layer formation process is completed in the existing TMBS device manufacturing method.

[0018] like Figure 5 The image shown is an electron microscope (EMS) image of a device after the metal layer of the contact holes has been etched back in a conventional TMBS device manufacturing method. Metal residue, typically tungsten, tends to form on the sides of the Schottky trenches. Figure 6 As shown in the circled area, the Schottky barrier metal layer has weak points, i.e., its thickness is reduced or it is broken. This makes it easy for tungsten puncture to occur, that is, tungsten residue directly contacts the N-type epitaxial layer. This affects the performance of the device, such as increasing the zero gate voltage drain current (IDSS) and decreasing the source-drain breakdown voltage (BVDSS), which will eventually reduce the product yield.

[0019] To address the aforementioned issues, a novel method for reducing the height of the Schottky trench bottom step is needed. Summary of the Invention

[0020] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for reducing the height of the bottom step of a Schottky trench, in order to solve the problem of the adverse effects caused by the undercut opening formed by over-etching of the interlayer dielectric layer at the bottom of the Schottky trench in the prior art.

[0021] To achieve the above and other related objectives, the present invention provides a method for reducing the height of the Schottky trench bottom step, comprising:

[0022] Step 1: Provide a substrate on which an N-type epitaxial layer is formed, and a plurality of first trench gates are formed in the N-type epitaxial layer. An etch stop layer is formed to cover the N-type epitaxial layer and the first trench gates. An interlayer dielectric layer is formed to cover the etch stop layer.

[0023] Step 2: Forming trenches as Schottky junction windows in the interlayer dielectric layer, including the following sub-steps:

[0024] Step 21: Photolithography defines the Schottky trench formation region;

[0025] Step 22: Perform the first dry etching, which removes the interlayer dielectric layer within the etching depth range and forms a first opening, with a portion of the interlayer dielectric layer remaining below the bottom surface of the first opening.

[0026] Step 23: Perform wet etching to remove all the interlayer dielectric layer remaining below the bottom surface of the first opening to the etching stop layer;

[0027] The wet etching process includes an over-etching amount to ensure that all the interlayer dielectric layer remaining below the bottom surface of the first opening is removed.

[0028] Step 24: Perform a second dry etching process to open the exposed etching stop layer, forming a second opening as a Schottky trench, making the top of the exposed Schottky trench more flat, and reducing the over-etching amount of the wet etching at the bottom edge of the first opening to form an undercut notch.

[0029] Preferably, the first trench gate exposed by the Schottky junction window in step one includes: a first gate trench, a first gate dielectric layer formed on the first gate trench, and a first gate conductive material layer filling the remainder of the first trench gate.

[0030] Preferably, the material of the etching stop layer in step one is silicon nitride.

[0031] Preferably, the thickness of the etching stop layer in step one is 50 to 70 angstroms.

[0032] Preferably, the second dry etching in step 24 uses CF4 and CHF3 as etching gases, with the gas ratio of CF4 to CHF3 being 5:9 to 7:9.

[0033] Preferably, the radio frequency power of the second dry etching in step 24 is 380 to 420W, and there is only one etching step.

[0034] Preferably, the undercut notch in step 24 has an inclined shape, and the step height of the undercut notch is less than 500 angstroms.

[0035] Preferably, the method further includes: step three, forming a Schottky barrier metal layer; making the Schottky barrier metal layer have a flat surface at the bottom of the Schottky trench; the epitaxial layer between the Schottky barrier metal layer and the first trench gate is in contact to form a Schottky diode; step four, forming a front metal layer, the front metal layer being in contact with the Schottky barrier metal layer and serving as the anode of the Schottky diode.

[0036] Preferably, the Schottky barrier metal layer in step three comprises a Ti layer and a TiN layer stacked sequentially.

[0037] Preferably, a trench gate power device is also formed on the substrate.

[0038] Preferably, in step one, a P-type well and a plurality of second trench gates are formed in the trench gate power device forming region;

[0039] The second trench gate includes a second gate trench, a second gate dielectric layer, and a second gate conductive material layer;

[0040] The second gate trench is formed in the first epitaxial layer and each second gate trench extends longitudinally through the P-type well. The second gate dielectric layer covers the inner surface of the second gate trench, and the second gate conductive material layer fills the second gate trench in which the second gate dielectric layer is formed.

[0041] The N+ doped source region is formed on the surface of the P-type well and the source region and the sidewalls of the second trench gate are self-aligned.

[0042] Preferably, before step three, before step two, or after step two, the method further includes: photolithography defining the formation area of ​​the contact hole; etching to form a contact hole opening that passes through the interlayer dielectric layer and the etch stop layer, with corresponding contact hole openings formed on the top of the second gate conductive material layer and the top of the source region, respectively; after step three and before step four, the method further includes: depositing a first metal layer, which completely fills the contact hole opening and forms the contact hole; etching back the first metal layer to remove all of the first metal layer on the surface of the interlayer dielectric layer outside the contact hole opening, leaving metal residue on the side of the Schottky trench, and at the undercut notch on the side of the Schottky trench, the flat structure of the Schottky barrier metal layer prevents the metal residue from causing metal puncture; in step four, after the front metal layer is patterned, a source and a gate are also formed simultaneously, the top of the second gate conductive material layer is connected to the gate through the corresponding contact hole, and the top of the source region is connected to the source through the corresponding contact hole; the source and the anode are shared.

[0043] Preferably, the material of the first metal layer includes tungsten.

[0044] Preferably, the trench gate power device includes a trench gate power device with an SGT; the second trench gate further includes an SGT structure, the SGT structure including a shielding conductive material layer, a shielding dielectric layer, and an inter-gate dielectric layer; in each of the second gate trenches, each of the shielding dielectric layers is located on the inner surface of the second gate trench at the bottom of the second gate dielectric layer; the shielding conductive material layer and the second gate trench are isolated by the shielding dielectric layer; the shielding conductive material layer and the second gate conductive material layer are isolated by the inter-gate dielectric layer.

[0045] Preferably, after the front-side process is completed, the following back-side process is further included: thinning the substrate; forming an N+ doped drain region; the substrate is N+ doped, and the thinned semiconductor substrate acts as the drain region; or, performing N+ back-side ion implantation on the thinned substrate to form the drain region; forming a back-side metal layer, which forms the drain of the trench gate power device and simultaneously serves as the cathode of the Schottky diode.

[0046] Preferably, in step two, after step 24 is completed, step 25 is further included: performing Schottky ion implantation.

[0047] As described above, the method for reducing the height of the Schottky trench bottom step of the present invention has the following beneficial effects:

[0048] The Schottky barrier metal layer at the bottom notch position of the present invention is formed more flatly, and the final morphology is significantly improved; the present invention significantly improves the convergence of IDSS leakage current and effectively reduces the probability of low yield in actual production. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the structure of an existing TMBS device;

[0050] Figure 2 This is a circuit diagram of an existing power device that integrates a TMBS device;

[0051] Figure 3 These are electron microscope images of devices after wet etching of Schottky trenches in existing TMBS device manufacturing methods;

[0052] Figure 4 These are electron microscope images of the device after the Schottky barrier metal layer formation process is completed in the existing TMBS device manufacturing method;

[0053] Figure 5 These are electron microscope images of devices after the metal layer of the contact holes has been etched back in the existing TMBS device manufacturing method.

[0054] Figure 6 These are electron microscope images of tungsten punctures in existing TMBS devices;

[0055] Figure 7 The diagram shown is a schematic representation of the process flow of the present invention.

[0056] Figure 8 The diagram shows a photolithographic definition of the Schottky trench formation region according to the present invention.

[0057] Figure 9 The diagram shown illustrates the formation of the first opening according to the present invention.

[0058] Figure 10The diagram shows the device structure after wet etching according to the present invention.

[0059] Figure 11 This is a schematic diagram of the first metal layer being etched back according to the present invention;

[0060] Figure 12 This is an electron microscope image of a TMBS device after the metal layer of the contact holes has been etched back during the manufacturing process. Detailed Implementation

[0061] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] Please see Figure 7 The present invention provides a method for reducing the height of the bottom step of a Schottky trench, comprising:

[0063] Step 1: Provide a substrate 101, on which an N-type epitaxial layer 102 is formed, and a plurality of first trench gates are formed in the N-type epitaxial layer 102. An etch stop layer 110 is formed to cover the N-type epitaxial layer 102 and the first trench gates, and an interlayer dielectric layer 111 covering the etch stop layer 110 is formed.

[0064] In some embodiments, the first trench gate exposed by the Schottky junction window in step one includes: a first gate trench, a first gate dielectric layer 103 formed on the first gate trench, and a first gate conductive material layer 104 filling the remaining first trench gate.

[0065] In some embodiments, the material of the etch stop layer 110 in step one is silicon nitride.

[0066] In some embodiments, the thickness of the etch stop layer 110 in step one is 50 to 70 angstroms.

[0067] Step 2: Forming trenches as Schottky junction windows in the interlayer dielectric layer 111, including the following sub-steps:

[0068] Step 21: Photolithography defines the Schottky trench formation region, forming a shape like... Figure 8 The structure shown; specifically, a photoresist layer 113 is formed on the interlayer dielectric layer 111, and then photolithography is used to open the photoresist layer 113 to define the Schottky trench formation region;

[0069] Step 22: Perform the first dry etching. The first dry etching removes the interlayer dielectric layer 111 within the etching depth range and forms the first opening. A portion of the interlayer dielectric layer 111 remains below the bottom surface of the first opening, forming a structure as shown in the image. Figure 9 The structure shown;

[0070] Step 23: Perform wet etching to remove all the interlayer dielectric layer 111 remaining below the bottom surface of the first opening onto the etching stop layer 110;

[0071] The wet etching process has an over-etching amount to ensure that all the interlayer dielectric layer 111 remaining below the bottom surface of the first opening is removed.

[0072] Step 24: Perform a second dry etching process to open the exposed etch stop layer 110, forming a second opening as a Schottky trench, forming as shown in the image. Figure 10 The structure shown, because the wet etching process stops at the etching stop layer 110 at the bottom of the first opening and only forms an undercut notch at the bottom of the sidewall of the second opening, can make the top of the exposed Schottky trench more flat and reduce the over-etching amount of the wet etching, thus reducing the undercut notch formed at the bottom edge of the first opening. Adding a dry etching step with a smaller etching amount after the wet etching significantly reduces the undercut notch caused by the wet etching amount. The step height of the undercut notch can be controlled below 500 angstroms and the angle is relatively inclined, which is beneficial for the subsequent formation of the Schottky barrier metal layer 114.

[0073] In some embodiments, the second dry etching in step 24 uses CF4 and CHF3 as etching gases, with the gas ratio of CF4 to CHF3 being 5:9 to 7:9, for example, the gas ratio of CF4 to CHF3 being 5:9, 6:9 or 7:9.

[0074] In some embodiments, the radio frequency power of the second dry etching in step 24 is 380 to 420 W, and there is only one etching step, such as 380 W, 400 W, or 420 W. A high proportion of CF4 gas can reduce the polymer in the etching reaction, which is beneficial for morphology control. The radio frequency power of 380 to 420 W and the single etching step can effectively control the etching amount.

[0075] In some embodiments, step two, after step 24 is completed, further includes: step 25, performing Schottky ion implantation.

[0076] In some embodiments, the method further includes: step three, forming a Schottky barrier metal layer 114; making the Schottky barrier metal layer 114 have a flat surface at the bottom of the Schottky trench; the epitaxial layer 102 between the Schottky barrier metal layer 114 and the first trench gate is in contact to form a Schottky diode; step four, forming a front metal layer, the front metal layer being in contact with the Schottky barrier metal layer 114 and serving as the anode of the Schottky diode.

[0077] In some embodiments, the Schottky barrier metal layer 114 in step three includes a Ti layer and a TiN layer stacked sequentially.

[0078] In some embodiments, a trench gate power device is also formed on the substrate 101.

[0079] In some embodiments, in step one, a P-type well and a plurality of second trench gates are formed in the trench gate power device forming region.

[0080] The second trench gate includes a second gate trench, a second gate dielectric layer 109, and a second gate conductive material layer 108.

[0081] The second gate trench is formed in the first epitaxial layer 102 and each second gate trench extends longitudinally through the P-type well. The second gate dielectric layer 109 covers the inner surface of the second gate trench, and the second gate conductive material layer 108 fills the second gate trench in which the second gate dielectric layer 109 is formed.

[0082] The N+ doped source region 112 is formed on the surface of the P-type well and the sidewalls of the source region 112 and the second trench gate are self-aligned.

[0083] In some embodiments, before step three, before step two, or after step two, the method further includes: photolithography defining the formation region of the contact hole; etching to form a contact hole opening through the interlayer dielectric layer 111 and the etch stop layer 110, with corresponding contact hole openings formed on the top of the second gate conductive material layer 108 and the top of the source region 112, respectively; after step three and before step four, the method further includes: depositing a first metal layer 115, the first metal layer 115 completely filling the contact hole opening and forming a contact hole; etching back the first metal layer 115 to completely remove the first metal layer 115 from the surface of the interlayer dielectric layer 111 outside the contact hole opening, leaving metal residue 115a on the side of the Schottky trench, forming a... Figure 11 The structure shown has a flat structure of Schottky barrier metal layer 114 at the undercut notch on the side of the Schottky trench to prevent metal residue from causing metal puncture; in step four, after the front metal layer is patterned, the source and gate are also formed simultaneously, the top of the second gate conductive material layer 108 is connected to the gate through the corresponding contact hole, and the top of the source region 112 is connected to the source through the corresponding contact hole; the source and anode are shared.

[0084] In some embodiments, the material of the first metal layer 115 includes tungsten.

[0085] In some embodiments, the trench gate power device includes a trench gate power device having an SGT; the second trench gate further includes an SGT structure, the SGT structure including a shielding conductive material layer 106, a shielding dielectric layer 105, and an inter-gate dielectric layer 107; in each second gate trench, each shielding dielectric layer 105 is located on the inner surface of the second gate trench at the bottom of the second gate dielectric layer 109; the shielding conductive material layer 106 and the second gate trench are isolated by the shielding dielectric layer 105; the shielding conductive material layer 106 and the second gate conductive material layer 108 are isolated by the inter-gate dielectric layer 107.

[0086] In some embodiments, after the front-side process is completed, the following back-side process is further included: thinning the substrate 101; forming an N+ doped drain region; the substrate 101 is N+ doped, and the thinned semiconductor substrate 101 acts as the drain region; or, performing N+ back-side ion implantation on the thinned substrate 101 to form the drain region; forming a back-side metal layer, which forms the drain of the trench gate power device and simultaneously serves as the cathode of the Schottky diode.

[0087] Please see Figure 12 In this invention, the Schottky barrier metal layer 114 at the bottom notch location is relatively flat, and the final morphology is better than expected. Figure 5 The existing technology morphology shown is significantly improved; the present invention significantly improves the convergence of IDSS leakage current and effectively reduces the probability of low yield in actual production.

[0088] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0089] In summary, the Schottky barrier metal layer at the undercut notch of this invention is formed more smoothly, resulting in a significantly improved final morphology. This invention also significantly improves the convergence of IDSS leakage current and effectively reduces the probability of low yields in actual production. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for reducing the height of the bottom step of a Schottky trench, characterized in that, At least including: Step 1: Provide a substrate on which an N-type epitaxial layer is formed, and a plurality of first trench gates are formed in the N-type epitaxial layer. An etch stop layer is formed to cover the N-type epitaxial layer and the first trench gates. An interlayer dielectric layer is formed to cover the etch stop layer. Step 2: Forming trenches as Schottky junction windows in the interlayer dielectric layer, including the following sub-steps: Step 21: Photolithography defines the Schottky trench formation region; Step 22: Perform the first dry etching, which removes the interlayer dielectric layer within the etching depth range and forms a first opening, with a portion of the interlayer dielectric layer remaining below the bottom surface of the first opening. Step 23: Perform wet etching to remove all the interlayer dielectric layer remaining below the bottom surface of the first opening to the etching stop layer; The wet etching process includes an over-etching amount to ensure that all the interlayer dielectric layer remaining below the bottom surface of the first opening is removed. Step 24: Perform a second dry etching process to open the exposed etching stop layer, forming a second opening as a Schottky trench. This flattens the top of the exposed Schottky trench and reduces the over-etching amount of the wet etching by creating an undercut notch at the bottom edge of the Schottky trench. The second dry etching process uses CF4 and CHF3 as etching gases, with a CF4 to CHF3 gas ratio of 5:9 to 7:

9. The radio frequency power of the second dry etching process is 380 to 420 W, and it involves only one etching step.

2. The method for reducing the height of the Schottky trench bottom step according to claim 1, characterized in that: The first trench gate at the Schottky junction window in step one includes: a first gate trench, a first gate dielectric layer formed on the first gate trench, and a first gate conductive material layer filling the remainder of the first trench gate.

3. The method for reducing the height of the Schottky trench bottom step according to claim 1, characterized in that: The material of the etching stop layer in step one is silicon nitride.

4. The method for reducing the height of the Schottky trench bottom step according to claim 1, characterized in that: The thickness of the etching stop layer in step one is 50 to 70 angstroms.

5. The method for reducing the height of the Schottky trench bottom step according to claim 1, characterized in that: The undercut notch in step 24 has an inclined shape, and the step height of the undercut notch is less than 500 angstroms.

6. The method for reducing the height of the Schottky trench bottom step according to claim 1, characterized in that, It also includes: Step 3, forming a Schottky barrier metal layer; making the Schottky barrier metal layer have a flat surface at the bottom of the Schottky trench; the N-type epitaxial layer between the Schottky barrier metal layer and the first trench gate is in contact to form a Schottky diode; Step 4, forming a front metal layer, the front metal layer is in contact with the Schottky barrier metal layer and serves as the anode of the Schottky diode.

7. The method for reducing the height of the Schottky trench bottom step according to claim 6, characterized in that: The Schottky barrier metal layer in step three comprises a Ti layer and a TiN layer stacked sequentially.

8. The method for reducing the height of the Schottky trench bottom step according to claim 6, characterized in that: Trench gate power devices are also formed on the substrate.

9. The method for reducing the height of the Schottky trench bottom step according to claim 8, characterized in that: In step one, a P-type well and multiple second trench gates are formed in the trench gate power device forming region; The second trench gate includes a second gate trench, a second gate dielectric layer, and a second gate conductive material layer; The second gate trench is formed in the N-type epitaxial layer and each second gate trench extends longitudinally through the P-type well. The second gate dielectric layer covers the inner surface of the second gate trench, and the second gate conductive material layer fills the second gate trench in which the second gate dielectric layer is formed. An N+ doped source region is formed on the surface of the P-type well, and the source region and the sidewalls of the second trench gate are self-aligned.

10. The method for reducing the height of the Schottky trench bottom step according to claim 9, characterized in that: Before step three, before step two, or after step two, the process includes: photolithography defining the formation area of ​​the contact hole; etching to form a contact hole opening that passes through the interlayer dielectric layer and the etch stop layer, with corresponding contact hole openings formed on the top of the second gate conductive material layer and the top of the source region, respectively; after step three and before step four, the process includes: depositing a first metal layer that completely fills the contact hole opening and forms the contact hole; etching back the first metal layer to remove all of the first metal layer on the surface of the interlayer dielectric layer outside the contact hole opening, leaving metal residue on the side of the Schottky trench; at the undercut notch on the side of the Schottky trench, the flat structure of the Schottky barrier metal layer prevents the metal residue from causing metal puncture; in step four, after the front metal layer is patterned, a source and a gate are also formed simultaneously, the top of the second gate conductive material layer is connected to the gate through the corresponding contact hole, and the top of the source region is connected to the source through the corresponding contact hole; the source and the anode are shared.

11. The method for reducing the height of the Schottky trench bottom step according to claim 10, characterized in that: The material of the first metal layer includes tungsten.

12. The method for reducing the height of the Schottky trench bottom step according to claim 9, characterized in that: The trench gate power device includes a trench gate power device with an SGT; the second trench gate further includes an SGT structure, the SGT structure including a shielding conductive material layer, a shielding dielectric layer and an inter-gate dielectric layer; in each of the second gate trenches, each of the shielding dielectric layers is located on the inner surface of the second gate trench at the bottom of the second gate dielectric layer; the shielding conductive material layer and the second gate trench are isolated by the shielding dielectric layer; The shielding conductive material layer and the second gate conductive material layer are isolated by the inter-gate dielectric layer.

13. The method for reducing the height of the Schottky trench bottom step according to claim 8, characterized in that: After the front-side process is completed, the following back-side process is also included: thinning the substrate; forming an N+ doped drain region; the substrate is N+ doped, and the thinned substrate serves as the drain region; Alternatively, the thinned substrate can be subjected to N+ backside ion implantation to form the drain region; A back metal layer is formed, which constitutes the drain of the trench gate power device and simultaneously serves as the cathode of the Schottky diode.

14. The method for reducing the height of the Schottky trench bottom step as described in claim 1, characterized in that: Step 2, after step 24 is completed, also includes: Step 25, performing Schottky ion implantation.

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