Semiconductor device

Abstract

There is provided a semiconductor device including a lower wiring structure, an upper interlayer insulating film on the lower wiring structure and including an upper wiring trench, and an upper wiring structure in the upper wiring trench. The upper wiring structure includes an upper barrier structure and an upper fill film on the upper barrier structure. The upper blocking structure includes a sidewall portion extending along a sidewall of the upper wiring trench and a bottom portion extending along a bottom surface of the upper wiring trench. The upper barrier structure includes an upper barrier film and an upper liner film between the upper barrier film and the upper fill film. A sidewall portion of the upper barrier structure includes a two-dimensional material (2D material), and a bottom surface of the upper barrier structure is free of the two-dimensional material.

Description

[0001] This application claims priority to and all rights arising from Korean Patent Application No. 10-2023-0075672 filed in the Korean Intellectual Property Office on June 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a wiring line formed in a BEOL (back-end of line) process and a method for manufacturing the same. Background Art

[0003] With the rapid progress of semiconductor element scaling due to the development of electronic technology, there is a demand for higher integration and lower power consumption of semiconductor chips. In order to cope with the demand for higher integration and lower power consumption of semiconductor chips, the feature size of semiconductor devices continues to decrease.

[0004] As feature sizes decrease, various studies are being conducted on stable connection methods between wirings. Summary of the invention

[0005] Aspects of the present disclosure provide a semiconductor device capable of improving element performance and reliability.

[0006] Aspects of the present disclosure provide a method for manufacturing a semiconductor device capable of improving element performance and reliability.

[0007] According to one aspect of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a lower wiring structure; an upper interlayer insulating film, on the lower wiring structure and including an upper wiring groove, the upper wiring groove being located in the upper interlayer insulating film; and an upper wiring structure, in the upper wiring groove and including an upper barrier structure and an upper filling film on the upper barrier structure. The upper barrier structure comprises a sidewall portion extending along the sidewall of the upper wiring groove and a bottom portion extending along the bottom surface of the upper wiring groove. The upper barrier structure comprises an upper barrier film and an upper liner film between the upper barrier film and the upper filling film. The sidewall portion of the upper barrier structure comprises a two-dimensional material (2D material), and the bottom portion of the upper barrier structure is free of the two-dimensional material.

[0008] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a lower wiring structure; an upper interlayer insulating film, on the lower wiring structure and comprising an upper wiring groove, the upper wiring groove being located in the upper interlayer insulating film. The upper wiring structure is in the upper wiring groove and comprises an upper barrier film and an upper filling film on the upper barrier film. The upper barrier film extends along the sidewall of the upper wiring groove and does not extend along the interface between the upper wiring structure and the lower wiring structure. The upper barrier film comprises a two-dimensional material (2D material).

[0009] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a lower wiring structure; and an upper wiring structure, on the lower wiring structure and comprising an upper barrier film, a first upper liner film and an upper filling film. The first upper liner film is between the upper barrier film and the upper filling film. The first upper liner film comprises a first portion in contact with the lower wiring structure and a second portion extending away from the lower wiring structure. The upper barrier film extends along the second portion of the first upper liner film, and the first portion of the first upper liner film has no upper barrier film thereon. The upper barrier film comprises tantalum sulfide, and the first upper liner film comprises tantalum nitride.

[0010] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a lower wiring structure; forming an upper interlayer insulating film including an upper wiring groove on the lower wiring structure, wherein the upper wiring groove exposes the lower wiring structure; forming a selective inhibition film on the lower wiring structure exposed by the upper wiring groove; in response to forming the selective inhibition film on the lower wiring structure, forming an upper barrier film along the sidewalls of the upper wiring groove, wherein the upper barrier film comprises a two-dimensional material and is not formed along the bottom surface of the upper wiring groove; removing the selective inhibition film after forming the upper barrier film; after removing the selective inhibition film, forming an upper liner film on the upper barrier film along the sidewalls and bottom surface of the upper wiring groove; and forming an upper filling film in the upper wiring groove and on the upper liner film.

[0011] However, aspects of the present disclosure are not limited to the aspects specifically described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 are example layout diagrams for explaining semiconductor devices according to some embodiments.

[0013] Figure 2 It is along Figure 1 Example cross-sectional view taken by AA.

[0014] Figure 3 It is along Figure 1 Example cross-sectional view of BB taken.

[0015] Figure 4 yes Figure 2 An enlarged view of part P.

[0016] Figure 5 It is used to explain Figure 4 FIG. 1 is a diagram of the shape of the first upper liner film.

[0017] Figure 6 , Figure 7 and Figure 8 is a diagram for explaining a semiconductor device according to some embodiments.

[0018] Fig. 9 is a diagram for explaining a semiconductor device according to some embodiments.

[0019] Fig.10 and Fig.11 is a diagram for explaining a semiconductor device according to some embodiments.

[0020] Fig.12 and Fig.13 are diagrams for explaining semiconductor devices according to some embodiments.

[0021] Fig.14 , Fig.15 , Fig.16 and Fig.17 is a diagram for explaining a semiconductor device according to some embodiments.

[0022] Fig.18 is a diagram for explaining a semiconductor device according to some embodiments.

[0023] Fig.19 is a diagram for explaining a semiconductor device according to some embodiments.

[0024] Fig. 20 , Fig.21 and Fig. 22 is a diagram for explaining a semiconductor device according to some embodiments.

[0025] Fig.23 is a diagram for explaining a semiconductor device according to some embodiments.

[0026] Fig.24 , Fig.25 and Fig.26 are diagrams for explaining semiconductor devices according to some embodiments.

[0027] Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 and Fig.32is a diagram for describing intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0028] Although the terms such as first and second are used in this specification to describe various elements or components, it is self-evident that these elements or components are not limited by these terms. These terms are only used to distinguish a single element or component from other elements or components. Therefore, the first element or first component mentioned below can be the second element or second component within the technical idea of ​​the present disclosure. That is, the terms "first", "second", etc. can be used only here to distinguish a component, layer, direction, etc. from another component, layer, direction, etc. When the terms "include", "include" and / or their variations are used here, it is explained that there are stated elements, but the presence of additional elements is not excluded. The term "and / or" includes any combination and all combinations of one or more of the related listed items. Similarly, the phrase "at least one (kind / person) of A, B and C" refers to any combination and all combinations of one or more (kind / person) of A, B and C, and should not be interpreted as meaning "at least one (kind / person) of A, at least one (kind / person) of B and at least one (kind / person) of C".

[0029] Although the drawings of semiconductor devices according to some example embodiments illustrate fin transistors (FinFETs) including a channel region in a fin pattern shape, transistors including nanowires or nanosheets, MBCFETs TM (Multi-bridge channel field effect transistor) or vertical transistor (vertical FET), but the present disclosure is not limited thereto. The semiconductor device according to some embodiments may include a tunneling transistor (tunneling FET) or a three-dimensional (3D) transistor. The semiconductor device according to some embodiments may include a planar transistor. In addition, the technical ideas of the present disclosure can be applied to transistors based on two-dimensional materials (FETs based on 2D materials) and their heterostructures.

[0030] In addition, the semiconductor device according to some embodiments may also include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS), and the like.

[0031] Figure 1 are example layout diagrams for explaining semiconductor devices according to some embodiments. Figure 2 It is along Figure 1 Example cross-sectional view taken by AA. Figure 3 It is along Figure 1 Example cross-sectional view of BB taken.

[0032] Figure 4 yes Figure 2 An enlarged view of part P. Figure 5 It is used to explain Figure 4 FIG. 1 is a diagram of the shape of the first upper liner film.

[0033] Reference Figures 1 to 5 , a semiconductor device according to some embodiments may include a first lower wiring structure 110 and a first upper wiring structure 210 .

[0034] The first lower wiring structure 110 may be disposed inside the first interlayer insulating film 150. The first lower wiring structure 110 may extend, for example, in the first direction D1.

[0035] The first lower wiring structure 110 may have a linear shape or a line shape extending in a first direction D1. For example, the first direction D1 may be a longitudinal (longitudinal) direction of the first lower wiring structure 110, and the second direction D2 may be a width direction of the first lower wiring structure 110. Here, the first direction D1 intersects with the second direction D2 and the third direction D3. The second direction D2 intersects with the third direction D3.

[0036] The first interlayer insulating film 150 may cover the source / drain of a transistor formed in a FEOL (Front End of Line) process. Alternatively, the first interlayer insulating film 150 may be an interlayer insulating film formed in a BEOL (Back End of Line) process.

[0037] In other words, as an example, the first lower wiring structure 110 may be a contact or contact wiring formed in a MOL (middle of the line) process. As another example, the first lower wiring structure 110 may be a connection wiring formed in a BEOL (back end of the line) process.

[0038] The first interlayer insulating film 150 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The low dielectric constant material may be, for example, silicon oxide having a suitably high amount of carbon and hydrogen, and may be a material such as SiCOH. On the other hand, since carbon is included in the insulating material, the dielectric constant of the insulating material may be reduced. However, in order to further reduce the dielectric constant of the insulating material, the insulating material may include a hole such as a cavity filled with a gas or air in the insulating material.

[0039] Low dielectric constant materials may include, but are not limited to, for example, tetraethyl fluoride orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), dibenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tonen SilaZe, Dongran Siloxane), FSG (fluorinated silicate glass), nanofoams such as polypropylene oxide and polyimide, CDO (carbon-doped silicon oxide), OSG (organosilicate glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof.

[0040] For example, if the first lower wiring structure 110 is a connection wiring formed in a BEOL process, the first lower wiring structure 110 may be disposed at a first metal level. The first interlayer insulating film 150 may include a first lower wiring trench 110t extending longitudinally (lengthwise) in a first direction D1.

[0041] The first lower wiring structure 110 may be disposed inside the first lower wiring trench 110t. The first lower wiring structure 110 fills the first lower wiring trench 110t.

[0042] The first lower wiring structure 110 may include a lower barrier film 111 and a lower filling film 112. The lower barrier film 111 may extend along sidewalls and a bottom surface of the first lower wiring trench 110t.

[0043] The lower filling film 112 may be disposed on the lower barrier film 111. The lower filling film 112 may fill the remaining portion of the first lower wiring trench 110t. As may be used herein, the term "surrounding" or "covering" or "filling" may not require completely surrounding or completely covering or completely filling the described element or layer, but may, for example, refer to partially surrounding or partially covering or partially filling the described element or layer, such as having a gap or other space throughout.

[0044] The lower barrier film 111 may include a conductive material. The lower barrier film 111 may include, for example, tantalum (Ta), tantalum nitride (TaN), tantalum nitride doped with ruthenium (Ru) (TaN:Ru), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), tungsten carbonitride (WCN), ruthenium (Ru), cobalt (Co), ruthenium cobalt (RuCo) alloy, zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh) and at least one of a two-dimensional material (2D material). The lower barrier film 111 is shown as a single-layer film, but is not limited thereto. In contrast to the example shown, the lower barrier film 111 may include a plurality of conductive films.

[0045] The lower filling film 112 includes a conductive material and may include, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), rhodium (Rh), iridium (Ir), RuAl, NiAl, NbB 2 、MoB 2 , TaB 2 、V 2 At least one of AlC and CrAlC.

[0046] The upper face or upper surface 110US of the first lower wiring structure may be defined by the lower barrier film 111 and the lower filling film 112. In contrast to the illustrated example, the first lower wiring structure 110 may have a single film structure. Although not shown, a via pattern connecting a conductive pattern disposed below the first lower wiring structure 110 may also be included.

[0047] The first lower wiring structure 110 may be formed using, for example, a damascene method. Figure 2 The width of the first lower wiring structure 110 in the second direction D2 is shown as being constant, but the present disclosure is not limited thereto. Compared to the illustrated example, the width of the first lower wiring structure 110 in the second direction D2 may decrease as it moves away from the upper surface of the first interlayer insulating film 150 .

[0048] The first etch stopper film 155 may be disposed on the first lower wiring structure 110 and the first interlayer insulating film 150. The second interlayer insulating film 160 may be disposed on the first etch stopper film 155. The first etch stopper film 155 may be disposed between the first interlayer insulating film 150 and the second interlayer insulating film 160.

[0049] The second interlayer insulating film 160 may include a first upper wiring trench 210t. The first upper wiring trench 210t may pass through the first etch stop film 155. The first upper wiring trench 210t may expose a portion of the first lower wiring structure 110. The term "exposed" may be used to describe the relationship between elements and / or certain intermediate processes when manufacturing a complete semiconductor device, but is not intended to necessarily require that a specific region, layer, structure, or other element in the completed device be exposed.

[0050] The first upper wiring trench 210t may include an upper via trench 210V_t and a first upper wiring trench 210L_t. For example, the first upper wiring trench 210L_t may extend longitudinally in the second direction D2. The first upper wiring trench 210L_t may extend up to the upper side of the second interlayer insulating film 160. The upper via trench 210V_t may be formed on the bottom surface or bottom surface of the first upper wiring trench 210L_t.

[0051] For example, the bottom surface of the first upper wiring trench 210 t may be the bottom surface of the upper via trench 210V_t. The bottom surface of the first upper wiring trench 210 t may be defined by the first lower wiring structure 110 .

[0052] The sidewalls of the first upper wiring trench 210t may include the sidewalls and bottom surface of the first upper wiring trench 210L_t and the sidewalls of the upper via trench 210V_t. The sidewalls and bottom surface of the first upper wiring trench 210L_t may be defined by the second interlayer insulating film 160. The sidewalls of the upper via trench 210V_t may be defined by the second interlayer insulating film 160 and the first etching stop film 155.

[0053] The second interlayer insulating film 160 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0054] The first etch stopper film 155 may include a material having an etch selectivity with respect to the second interlayer insulating film 160. The first etch stopper film 155 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxycarbide (AlOC), and combinations thereof.

[0055] Although the first etch stopper film 155 is shown as a single film, this is only for convenience of explanation and the embodiment is not limited thereto. Needless to say, in contrast to the illustrated example, the first etch stopper film 155 may include a plurality of insulating films sequentially stacked on the first interlayer insulating film 150 .

[0056] The first upper wiring structure 210 may be disposed inside the first upper wiring trench 210 t . The first upper wiring structure 210 may fill the first upper wiring trench 210 t . The first upper wiring structure 210 may be disposed in the second interlayer insulating film 160 .

[0057] The first upper wiring structure 210 is disposed on the first lower wiring structure 110. The first upper wiring structure 210 is connected to the first lower wiring structure 110. The first upper wiring structure 210 is in contact with the first lower wiring structure 110 along an interface (eg, 110US).

[0058] The first upper wiring structure 210 may include a first upper wiring 210L and an upper via 210V. The upper via 210V connects the first upper wiring 210L and the first lower wiring structure 110. The term "connected" or variations thereof may be used herein to refer to a physical and / or electrical connection. The upper via 210V may be in contact with the first lower wiring structure 110. As used herein, when a component or layer is referred to as being "directly" on or "directly" connected or "directly" in contact, there are no intervening components or intervening layers.

[0059] For example, upper surface 110US of the first lower wiring structure may include a first region contacting the first upper wiring structure 210 and a second region not contacting the first upper wiring structure 210. The upper via 210V contacts the first region of upper surface 110US of the first lower wiring structure.

[0060] The first upper wiring structure 210 fills the upper via trench 210V_t and the first upper wiring trench 210L_t. The first upper wiring 210L is disposed in the first upper wiring trench 210L_t. The upper via 210V is disposed in the upper via trench 210V_t.

[0061] If the first lower wiring structure 110 is a connection wiring formed in a BEOL process, the first upper wiring 210L may be disposed at a second metal level different from the first metal level. The first upper wiring 210L is disposed in a second metal level higher than the first metal level. If the first lower wiring structure 110 is a conductive contact formed in an MOL process, the first upper wiring 210L may be disposed at the lowest metal level among the metal levels formed in the BEOL process.

[0062] The first upper wiring structure 210 includes a first upper barrier structure 211ST and a first upper filling film 213. The first upper filling film 213 is disposed on the first upper barrier structure 211ST. The first upper barrier structure 211ST includes a first upper barrier film 211 and a first upper liner film 212. Although not shown, the first upper wiring structure 210 may include an upper cover film extending along an upper surface of the first upper filling film 213.

[0063] The first upper barrier structure 211ST may extend along the sidewall and bottom surface of the first upper wiring trench 210t. The first upper barrier structure 211ST may include a sidewall portion 211ST_S and a bottom portion 211ST_B.

[0064] The sidewall portion 211ST_S of the first upper barrier structure extends along the sidewall and bottom surface of the first upper wiring trench 210L_t and the sidewall of the upper via trench 210V_t. The bottom portion 211ST_B of the first upper barrier structure extends along the bottom surface of the upper via trench 210V_t.

[0065] The first upper barrier film 211 extends along the sidewall of the first upper wiring trench 210t. The first upper barrier film 211 does not extend along the bottom surface of the first upper wiring trench 210t. The first upper barrier film 211 contacts the second interlayer insulating film 160. The first upper barrier film 211 may not cover the first lower wiring structure 110 exposed by the upper via trench 210V_t.

[0066] The first upper barrier film 211 extends along the sidewalls and bottom surface of the first upper wiring trench 210L_t and the sidewalls of the upper via trench 210V_t. The first upper barrier film 211 may not extend to the first lower wiring structure 110, which defines the bottom surface of the first upper wiring trench 210t.

[0067] In the semiconductor device according to some embodiments, the first upper barrier film 211 does not extend to the upper surface 110US of the first lower wiring structure 110. That is, a portion or all of the interface (e.g., 110US) between the first lower wiring structure 110 and the first upper wiring structure 210 may be free of the first upper barrier film 211. The first upper barrier film 211 may extend along a portion of the sidewall of the upper via trench 210V_t. The first upper barrier film 211 may not be in direct contact with the first lower wiring structure 110. For example, the first upper barrier film 211 may not extend along at least a portion of the interface between the first lower wiring structure 110 and the first upper wiring structure 210.

[0068] The first upper barrier film 211 includes a conductive material, and may include, for example, a two-dimensional material. For example, the first upper barrier film 211 may be formed of a two-dimensional material. The two-dimensional material (2D material) may include a 2D allotrope or a 2D compound, and may include, for example, but not limited to, at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide. That is, since the above-mentioned 2D materials are listed only by way of example, the 2D materials that may be included in the semiconductor device of the present disclosure are not limited to the above-mentioned materials.

[0069] In the semiconductor device according to some embodiments, the first upper barrier film 211 may include tantalum sulfide as a two-dimensional material. As an example, the first upper barrier film 211 may be formed of tantalum sulfide as a two-dimensional material. As another example, the first upper barrier film 211 may be in a state where tantalum sulfide as a two-dimensional material is doped with ruthenium (Ru).

[0070] The first upper liner film 212 is disposed on the first upper barrier film 211. The first upper liner film 212 is disposed between the first upper barrier film 211 and the first upper filling film 213. For example, the first upper liner film 212 may be in contact with the first upper barrier film 211.

[0071] The first upper liner film 212 extends along the sidewalls and bottom surface of the first upper wiring trench 210t. The first upper liner film 212 extends along the sidewalls and bottom surface of the first upper wiring trench 210L_t and the sidewalls and bottom surface of the upper via trench 210V_t.

[0072] First upper liner film 212 contacts first lower wiring structure 110 . First upper liner film 212 contacts upper surface 110US of first lower wiring structure 110 . First upper liner film 212 extends along upper surface 110US of first lower wiring structure 110 .

[0073] Since first upper barrier film 211 is not in contact with first lower wiring structure 110, a portion of first upper liner film 212 may be inserted between upper surface 110US of the first lower wiring structure and the lowest portion of first upper barrier film 211, for example, along interface 110US. Figure 4 , first upper barrier film 211 may be located on first upper liner film 212 such that first upper liner film 212 separates first upper barrier film 211 from upper surface 110US of first lower wiring structure 110, and separates first upper barrier film 211 from first upper filling film 213. In contrast to the illustrated example, first upper liner film 212 may not be inserted between upper surface 110US of the first lower wiring structure and the lowest portion of first upper barrier film 211, or may not extend between upper surface 110US of the first lower wiring structure and the lowest portion of first upper barrier film 211.

[0074] The first upper liner film 212 may contact the first etch stopper film 155 defining the sidewalls of the first upper wire trench 210t. In contrast to the illustrated example, the first upper liner film 212 may not contact the first etch stopper film 155 defining the sidewalls of the first upper wire trench 210t.

[0075] The first upper liner film 212 may include a conductive material and may include at least one of tantalum (Ta), tantalum nitride (TaN), tantalum nitride doped with ruthenium (Ru) (TaN:Ru), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), tungsten carbonitride (WCN), ruthenium (Ru), cobalt (Co), ruthenium cobalt (RuCo) alloy, zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir) and rhodium (Rh).

[0076] As an example, the first upper liner film 212 may include a metal nitride. The first upper liner film 212 may include, for example, one of tantalum nitride (TaN) and tantalum nitride doped with ruthenium (Ru) (TaN:Ru).

[0077] As another example, the first upper liner film 212 may include one of cobalt (Co) and ruthenium cobalt (RuCo). Here, "ruthenium cobalt" may be a metal formed purely of ruthenium and cobalt, or may be a metal containing impurities introduced during the process of forming the first upper liner film 212. Here, "ruthenium cobalt" may be in the form of an alloy made of ruthenium and cobalt, or may be in the form of cobalt (Co) doped with ruthenium (Ru).

[0078] For example, the thickness t21 of the first upper liner film 212 at the sidewall of the upper via trench 210V_t may be the same as the thickness t1 of the first upper liner film 212 at the upper surface 110US of the first lower wiring structure. The thickness t21 of the first upper liner film 212 at the sidewall of the upper via trench 210V_t may be the same as the thickness t22 of the first upper liner film 212 at the bottom surface of the first upper wiring trench 210L_t.

[0079] exist Figure 2 and Figure 4 In the embodiment, the sidewall portion 211ST_S of the first upper barrier structure 211ST may include the first upper barrier film 211 and the first upper liner film 212. The bottom portion 211ST_B of the first upper barrier structure 211ST includes the first upper liner film 212 but does not include the first upper barrier film 211.

[0080] The sidewall portion 211ST_S of the first upper barrier structure 211ST includes a two-dimensional material. The bottom portion 211ST_B of the first upper barrier structure 211ST (eg, the bottom portion 211ST_B along the interface 110US) does not include a two-dimensional material.

[0081] exist Figure 2 , Figure 4 and Figure 5In the embodiment, the first upper liner film 212 may include a first portion 212_P1 in contact with the first lower wiring structure 110 and a second portion 212_P2 not in contact with the first lower wiring structure 110. In the semiconductor device according to some embodiments, the first portion 212_P1 of the first upper liner film may extend along the bottom surface of the first upper wiring trench 210t. The second portion 212_P2 of the first upper liner film may extend along the sidewall of the first upper wiring trench 210t.

[0082] The first upper barrier film 211 does not extend along the first portion 212_P1 of the first upper liner film. The first upper barrier film 211 is not disposed along a boundary or interface between the first portion 212_P1 of the first upper liner film and the first lower wiring structure 110. The first upper barrier film 211 may extend along the second portion 212_P2 of the first upper liner film.

[0083] The first upper filling film 213 is disposed on the first upper liner film 212. The first upper filling film 213 may be in contact with the first upper liner film 212. The first upper filling film 213 may fill the remaining portion of the first upper wiring trench 210t.

[0084] The first upper liner film 212 is disposed between the first upper filling film 213 and the first lower wiring structure 110. The first upper filling film 213 may not contact the first lower wiring structure 110.

[0085] The first upper filling film 213 includes a conductive material and may include, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), rhodium (Rh), iridium (Ir), RuAl, NiAl, NbB 2 、MoB 2 , TaB 2 、V 2 At least one of AlC and CrAlC.

[0086] When the first upper barrier film 211 is formed of a two-dimensional material, the thickness of the first upper barrier film 211 can be thinned. Even if the thickness of the first upper barrier film 211 is thin, the first upper barrier film 211 can effectively reduce or prevent the diffusion of materials included in the first upper filling film 213 and the like. Since the volume of the first upper barrier film 211 in the first upper wiring trench 210t is reduced, sufficient space for forming the first upper filling film 213 can be secured. Therefore, the resistance value of the first upper wiring structure 210 can be reduced.

[0087] Furthermore, since the resistance of the two-dimensional material is low in the in-plane direction, the first upper barrier film 211 may help reduce the resistance of the first upper wiring structure 210 .

[0088] However, the resistance of the two-dimensional material in the out-of-plane direction may be high. For example, the out-of-plane direction of the two-dimensional material may be the third direction D3 along which the first lower wiring structure 110 and the first upper wiring structure 210 contact each other. The first upper barrier film 211 formed of the two-dimensional material is not disposed at a boundary portion or interface where the first lower wiring structure 110 and the first upper wiring structure 210 contact each other. That is, the resistance between the first lower wiring structure 110 and the first upper wiring structure 210 may be reduced. Therefore, the reliability and performance of the semiconductor device may be improved or enhanced.

[0089] When the first upper filling film 213 and the lower filling film 112 are in contact with each other, the electromigration (EM) characteristics may be degraded. However, since the first upper liner film 212 is disposed between the first upper filling film 213 and the first lower wiring structure 110, the first upper filling film 213 and the lower filling film 112 are not in contact with each other. That is, the electromigration characteristics between the first lower wiring structure 110 and the first upper wiring structure 210 are not degraded. Therefore, the reliability and performance of the semiconductor device can be improved or enhanced.

[0090] Although the first lower wiring structure 110 is shown as having a different conductive film stack structure from the first upper wiring structure 210 , the embodiment is not limited thereto. In contrast to the illustrated example, the first lower wiring structure 110 may have the same conductive film stack structure as the first upper wiring structure 210 .

[0091] Figures 6 to 8 is a diagram for explaining a semiconductor device according to some embodiments. For ease of explanation, the explanation will focus on the use of Figures 1 to 5 The explanations are different.

[0092] For reference, Figure 7 and Figure 8 yes Figure 6 An enlarged view of part P.

[0093] Reference Figures 6 to 8 In the semiconductor device according to some embodiments, the first upper liner film 212 may include a plurality of conductive films.

[0094] The first upper liner film 212 may include a first upper sub-liner film 212A and a second upper sub-liner film 212B. The first upper sub-liner film 212A may be disposed between the first upper barrier film 211 and the second upper sub-liner film 212B. The second upper sub-liner film 212B may be disposed between the first upper filling film 213 and the first upper sub-liner film 212A.

[0095] The first upper sub liner film 212A may be in contact with the first upper barrier film 211 . The second upper sub liner film 212B may be in contact with the first upper filling film 213 .

[0096] The first sub-liner film 212A may include a metal nitride. The first sub-liner film 212A may include, for example, one of tantalum nitride (TaN) and tantalum nitride doped with ruthenium (Ru) (TaN:Ru). The second sub-liner film 212B may include one of cobalt (Co) and ruthenium cobalt (RuCo).

[0097] exist Figure 7 In the embodiment, the first upper sub-liner film 212A and the second upper sub-liner film 212B may extend along the sidewall and the bottom surface of the first upper wiring trench 210t, respectively. The first upper sub-liner film 212A may contact the upper surface 110US of the first lower wiring structure, and the second upper sub-liner film 212B may not contact the upper surface 110US of the first lower wiring structure.

[0098] The sidewall portion 211ST_S of the first upper barrier structure may include the first upper barrier film 211 , the first and second sub-liner films 212A and 212B. The bottom portion 211ST_B of the first upper barrier structure includes the first and second sub-liner films 212A and 212B, but does not include the first upper barrier film 211 .

[0099] Since first upper barrier film 211 does not contact first lower wiring structure 110, a portion of first upper sub liner film 212A may be inserted between upper surface 110US of the first lower wiring structure and the lowest portion of first upper barrier film 211. In contrast to the illustrated example, first upper sub liner film 212A may not be inserted between upper surface 110US of the first lower wiring structure and the lowest portion of first upper barrier film 211.

[0100] The first upper sub liner film 212A may contact the first etch stopper film 155 defining the sidewalls of the first upper wire trench 210t. In contrast to the illustrated example, the first upper sub liner film 212A may not contact the first etch stopper film 155 defining the sidewalls of the first upper wire trench 210t.

[0101] exist Figure 8 In the embodiment of the present invention, the second upper sub-liner film 212B may extend along the sidewalls and bottom surface of the first upper wiring trench 210t. The first upper sub-liner film 212A may extend along the sidewalls of the first upper wiring trench 210t. The first upper sub-liner film 212A may not extend along the bottom surface of the first upper wiring trench 210t (or may extend along less than the entire bottom surface of the first upper wiring trench 210t). The first upper sub-liner film 212A may contact the upper surface 110US of the first lower wiring structure 110, for example, at the edge portion of the upper surface 110US of the first lower wiring structure 110. The second upper sub-liner film 212B may contact the upper surface 110US of the first lower wiring structure 110, for example, at the center portion of the upper surface 110US of the first lower wiring structure 110.

[0102] The sidewall portion 211ST_S of the first upper barrier structure may include the first upper barrier film 211, the first sub-liner film 212A and the second sub-liner film 212B. The bottom portion 211ST_B of the first upper barrier structure includes the second sub-liner film 212B but does not include the first upper barrier film 211 and the first sub-liner film 212A.

[0103] In contrast to the illustrated example, the first upper sub liner film 212A may not contact the upper face 110US of the first lower wiring structure. The first upper sub liner film 212A may not contact the first etch stopper film 155 defining the sidewalls of the first upper wiring trench 210t.

[0104] In contrast to the illustrated example, the second upper sub liner film 212B may be interposed between the upper face 110US of the first lower wiring structure and the lowest portion of the first upper barrier film 211 .

[0105] Fig. 9 is a diagram for explaining a semiconductor device according to some embodiments. Fig.10 and Fig.11 is a diagram for explaining a semiconductor device according to some embodiments. Fig.12 and Fig.13 are diagrams for explaining semiconductor devices according to some embodiments. For ease of explanation, the explanation will focus on the use of Figures 1 to 5 The explanations are different.

[0106] For reference, Fig.11 yes Fig.10 An enlarged view of part P.

[0107] Reference Fig. 9 In the semiconductor device according to some embodiments, a thickness t21 of the first upper liner film 212 on the sidewall of the upper via trench 210V_t is smaller than a thickness t1 of the first upper liner film 212 on the upper surface 110US of the first lower wiring structure.

[0108] A thickness t21 of the first upper liner film 212 at the sidewall of the upper via trench 210V_t is smaller than a thickness t22 of the first upper liner film 212 at the bottom surface of the first upper wiring trench 210L_t.

[0109] Reference Fig.10 and Fig.11 In the semiconductor device according to some embodiments, the first upper barrier film 211 may extend up to the first lower wiring structure 110 defining the bottom surface of the first upper wiring trench 210t, that is, at least partially extend along the interface between the first lower wiring structure 110 and the first upper wiring structure 210.

[0110] The first upper barrier film 211 may be in contact with the first lower wiring structure 110, for example, at an edge portion of the first lower wiring structure 110. The first upper barrier film 211 may extend up to an upper face 110US of the first lower wiring structure.

[0111] The first upper barrier film 211 does not include a portion extending along the upper face 110US of the first lower wiring structure. For example, the first upper barrier film 211 on the sidewall of the upper via trench 210V_t may have an "I" shape instead of an "L" shape.

[0112] Reference Fig.12 and Fig.13 In the semiconductor device according to some embodiments, the first lower wiring structure 110 may further include a lower cover film 113 extending along an upper surface of the lower fill film 112 .

[0113] The lower covering film 113 may extend along the upper face of the lower filling film 112. The lower covering film 113 may not cover the upper face of the lower barrier film 111. In contrast to the illustrated example, the lower covering film 113 may cover the upper face of the lower barrier film 111.

[0114] The lower cover film 113 includes a conductive material, and may include, for example, a metal. The lower cover film 113 may include, for example, cobalt (Co).

[0115] exist Fig.12 , lower cover film 113 may be removed from a portion of first lower wiring structure 110 connected to first upper wiring structure 210, or may not be additionally present on a portion of first lower wiring structure 110 connected to first upper wiring structure 210. First upper wiring structure 210 may be in direct contact with exposed lower filling film 112. Upper surface 110US of the first lower wiring structure may be defined by lower filling film 112 and lower cover film 113.

[0116] exist Fig.13 , lower cover film 113 is not removed from a portion of first lower wiring structure 110 connected to first upper wiring structure 210. First upper wiring structure 210 may be in contact with lower cover film 113. Lower filling film 112 may not be in direct contact with first upper wiring structure 210. Upper face 110US of the first lower wiring structure may be defined by lower cover film 113.

[0117] Figures 14 to 17 is a diagram for explaining a semiconductor device according to some embodiments. For reference, Fig.14 is an example layout diagram for describing a semiconductor device according to some embodiments. Fig.15 It is along Fig.14 Example cross-sectional view taken by CC. Fig.16 It is along Fig.14Example cross-sectional view taken from DD. Fig.17 yes Fig.15 A magnified view of part Q.

[0118] Reference Figures 14 to 17 , a semiconductor device according to some embodiments may include a second lower wiring structure 120 and a second upper wiring structure 220 .

[0119] The second lower wiring structure 120 may be disposed inside the first interlayer insulating film 150. The second lower wiring structure 120 may have a contact shape.

[0120] As an example, the second lower wiring structure 120 may be a contact formed in an MOL process. As another example, the second lower wiring structure 120 may be a via included in a connection wiring formed in a BEOL process.

[0121] The first interlayer insulating film 150 may include a second lower wiring trench 120t. The second lower wiring structure 120 may be disposed inside the second lower wiring trench 120t. The second lower wiring structure 120 fills the second lower wiring trench 120t.

[0122] The second lower wiring structure 120 may have a single conductive film structure. The second lower wiring structure 120 may include a metal that can be selectively grown on a conductive material. The second lower wiring structure 120 may include, for example but not limited to, one of titanium (Ti), tungsten (W), molybdenum (Mo), ruthenium (Ru) and cobalt (Co). In contrast to the example shown, the second lower wiring structure 120 may have a plurality of conductive film structures including a lower barrier film and a lower filling film like the first lower wiring structure 110.

[0123] The second interlayer insulating film 160 may include a second upper wiring trench 220t. The second upper wiring trench 220t may pass through the first etch stopper film 155. The second upper wiring trench 220t may expose the second lower wiring structure 120.

[0124] The second upper wiring groove 220t includes a second upper wiring groove 220L_t. The second upper wiring groove 220L_t may extend in one direction, for example, in the second direction D2. The second upper wiring groove 220t does not include the second upper wiring groove ( Figure 2 and Figure 3 The upper via groove 210V_t of 210t).

[0125] The sidewalls of the second upper wiring trench 220t may be the sidewalls of the second upper wiring trench 220L_t, and the bottom surface of the second upper wiring trench 220t may be the bottom surface of the second upper wiring trench 220L_t. The sidewalls of the second upper wiring trench 220L_t may be defined by the second interlayer insulating film 160 and the first etch stop film 155. The bottom surface of the second upper wiring trench 220L_t may be defined by the second lower wiring structure 120 and the first interlayer insulating film 150.

[0126] Second upper wiring structure 220 may be disposed inside second upper wiring trench 220t. Second upper wiring structure 220 is disposed on second lower wiring structure 120. Second upper wiring structure 220 is connected to second lower wiring structure 120. Second upper wiring structure 220 contacts second lower wiring structure 120 and first interlayer insulating film 150.

[0127] The second upper wiring structure 220 includes a second upper wiring 220L. The second upper wiring structure 220 does not include the second upper wiring structure ( Figures 1 to 3 The upper via 210V in 210).

[0128] The second upper wiring 220L is disposed inside the second upper wiring trench 220L_t. The second upper wiring 220L contacts the second lower wiring structure 120. The second upper wiring 220L may be directly connected to the second lower wiring structure 120.

[0129] The second upper wiring structure 220 includes a second upper barrier structure 221ST and a second upper filling film 223. The second upper filling film 223 is disposed on the second upper barrier structure 221ST.

[0130] The second upper barrier structure 221ST includes a second upper barrier film 221 and a second upper liner film 222. The second upper barrier structure 221ST may extend along the sidewall and bottom surface of the second upper wiring trench 220t.

[0131] The second upper barrier film 221 extends along the sidewall of the second upper wiring trench 220t. The second upper barrier film 221 extends along a portion or a part of the bottom surface of the second upper wiring trench 220t. The second upper barrier film 221 does not extend along a portion of the bottom surface of the second upper wiring trench 220t defined by the second lower wiring structure 120. The second upper barrier film 221 does not extend along the upper surface 120US of the second lower wiring structure 120. That is, a portion or all of the interface (e.g., 120US) between the second lower wiring structure 120 and the second upper wiring structure 220 is free of the second upper barrier film 221.

[0132] The second upper barrier film 221 is in contact with the second interlayer insulating film 160. The second upper barrier film 221 is in contact with the first interlayer insulating film 150 defining the bottom surface of the second upper wiring trench 220t.

[0133] The second upper barrier film 221 may not be in contact with the second lower wiring structure 120. The second upper barrier film 221 may not be in contact with the upper surface 120US of the second lower wiring structure. In contrast to the illustrated example, the second upper barrier film 221 may be in contact with the upper surface 120US of the second lower wiring structure at a boundary portion between the second lower wiring structure 120 and the first interlayer insulating film 150. In this case, the second upper barrier film 221 does not include a portion extending along the upper surface 120US of the second lower wiring structure 120 (e.g., does not extend along the central portion of the interface 120US of the second lower wiring structure 120).

[0134] The description of the materials included in the second upper barrier film 221 may be the same as that included in the first upper barrier film ( Figures 2 to 4 The materials are the same as described in 211).

[0135] The second upper liner film 222 is disposed on the second upper barrier film 221. The second upper liner film 222 is disposed between the second upper barrier film 221 and the second upper filling film 223. For example, the second upper liner film 222 may contact the second upper barrier film 221. The second upper liner film 222 extends along the sidewall and bottom surface of the second upper wiring trench 220t.

[0136] Second upper liner film 222 contacts second lower wiring structure 120. Second upper liner film 222 contacts upper surface 120US of the second lower wiring structure. Second upper liner film 222 extends along upper surface 120US of the second lower wiring structure.

[0137] The description of the materials included in the second upper liner film 222 may be the same as that included in the second upper liner film ( Figures 2 to 4 The second upper liner film 222 may include the following materials: Figures 6 to 8 Multiple conductive films described in.

[0138] The second upper barrier structure 221ST disposed on the sidewall of the second upper wiring trench 220t includes a two-dimensional material. A portion of the second upper barrier structure 221ST disposed on the bottom surface of the second upper wiring trench 220t does not include (ie, is free of) the two-dimensional material.

[0139] exist Fig.15 and Fig.17In the present invention, the second upper liner film 222 may include a first portion 222_P1 (e.g., a central portion) in contact with the second lower wiring structure 120 and a second portion 222_P2 (e.g., an edge portion) not in contact with the second lower wiring structure 120. In the semiconductor device according to some embodiments, the first portion 222_P1 of the second upper liner film may extend along a portion of the bottom surface of the second upper wiring trench 220t. The second portion 222_P2 of the second upper liner film may extend along the remaining portion of the bottom surface of the second upper wiring trench 220t and the sidewall of the second upper wiring trench 220t.

[0140] The second upper barrier film 221 does not extend along the first portion 222_P1 of the second upper liner film. The second upper barrier film 221 is not disposed along a boundary or interface between the first portion 222_P1 of the second upper liner film and the second lower wiring structure 120. The second upper barrier film 221 may extend along the second portion 222_P2 of the second upper liner film.

[0141] The second upper filling film 223 is disposed on the second upper liner film 222. The second upper filling film 223 may be in contact with the second upper liner film 222. The second upper filling film 223 may fill the remaining portion of the second upper wiring trench 220t.

[0142] The second upper liner film 222 is disposed between the second upper filling film 223 and the second lower wiring structure 120. The second upper filling film 223 may not be in direct contact with the second lower wiring structure 120.

[0143] The description of the materials included in the second upper filling film 223 may be the same as that included in the first upper filling film ( Figures 2 to 4 The same as the description of the materials in 213).

[0144] Fig.18 is a diagram for explaining a semiconductor device according to some embodiments.

[0145] For reference, Fig.18 The structure taken along the first gate electrode GE is exemplarily shown. Fig.18 In the embodiment, the first gate electrode GE may be Figures 1 to 17 The first fin pattern AF1 extends in the first direction D1 described in the embodiment, or may extend in the second direction D2. When the first gate electrode GE extends in the second direction D2, the first fin pattern AF1 extends in the first direction D1 and intersects with the first gate electrode GE.

[0146] Reference Fig.18 , a semiconductor device according to some embodiments may include a transistor TR disposed between a substrate 10 and a first lower wiring structure 110 .

[0147] The substrate 10 may be a silicon substrate or a silicon on insulator (SOI). In contrast, the substrate 10 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0148] The transistor TR may include a first fin pattern AF1 , a first gate electrode GE on the first fin pattern AF1 , and a first gate insulating film GI between the first fin pattern AF1 and the first gate electrode GE.

[0149] Although not shown, the transistor TR may include source / drain patterns disposed on both sides or opposite sides of the first gate electrode GE.

[0150] The first fin pattern AF1 may protrude from the substrate 10. The first fin pattern AF1 may extend longitudinally in one direction. The first fin pattern AF1 may be a part of the substrate 10 and may include an epitaxial layer grown from the substrate 10. The first fin pattern AF1 may include, for example, silicon or germanium as an elemental semiconductor material. In addition, the first fin pattern AF1 may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0151] The IV-IV compound semiconductor may include, for example, a binary compound or a ternary compound containing two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with a group IV element. The III-V compound semiconductor may be, for example, at least one of a binary compound, a ternary compound, and a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as group V elements.

[0152] The field insulating film 15 may be formed on the substrate 10. The field insulating film 15 may be formed on a portion of a sidewall of the first fin pattern AF1. The first fin pattern AF1 may protrude above an upper surface of the field insulating film 15. The field insulating film 15 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0153] The first gate electrode GE may be disposed on the first fin pattern AF1. The first gate electrode GE may extend in another direction intersecting with one direction in which the first fin pattern AF1 extends. The first gate electrode GE may intersect with the first fin pattern AF1.

[0154] The first gate electrode GE may include, for example, at least one of metal, conductive metal nitride, conductive metal carbonitride, conductive metal carbide, metal silicide, a doped semiconductor material, conductive metal oxynitride, and conductive metal oxide.

[0155] The first gate insulating film GI may be disposed between the first gate electrode GE and the first fin pattern AF1 and between the first gate electrode GE and the field insulating film 15. The first gate insulating film GI may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, at least one of boron nitride, metal oxide, and metal silicon oxide.

[0156] The semiconductor device according to some embodiments may include an NC (Negative Capacitance) FET using a negative capacitor.For example, the first gate insulating film GI may include a ferroelectric material film having a ferroelectric property and a paraelectric material film having a paraelectric property.

[0157] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is reduced from the capacitance of each of the individual capacitors. On the other hand, if the capacitance of at least one of the two or more capacitors connected in series has a negative value, the total capacitance may be greater than the absolute value of each of the individual capacitors while having a positive value.

[0158] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series can be increased. By using the increased total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than 60mV / decade at room temperature.

[0159] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0160] The ferroelectric material film may be doped with a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on what type of ferroelectric material is included in the ferroelectric material film.

[0161] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0162] When the dopant is aluminum (Al), the ferroelectric material film may include 3 at% (atomic %) to 8 at% of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0163] When the dopant is silicon (Si), the ferroelectric material film may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50at% to 80at% zirconium.

[0164] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example but not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0165] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film has ferroelectric properties, while the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0166] The ferroelectric material film may have a thickness that provides ferroelectric properties. The thickness of the ferroelectric material film may be, for example but not limited to, 0.5 nm to 10 nm. Since the critical thickness that exhibits ferroelectric properties may vary for various ferroelectric materials, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0167] As an example, the first gate insulating film GI may include a single ferroelectric material film. As another example, the first gate insulating film GI may include a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film GI may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0168] The gate capping pattern GE_CAP may be disposed on the first gate electrode GE. In contrast to the illustrated example, in some embodiments, the gate capping pattern GE_CAP may not be disposed on the first gate electrode GE.

[0169] The first lower wiring structure 110 may be disposed on the first gate electrode GE. Although the first lower wiring structure 110 is shown as not connected to the first gate electrode GE, the embodiment is not limited thereto. One of the first lower wiring structures 110 may be connected to the first gate electrode GE. The first upper wiring structure 210 is disposed on the first lower wiring structure 110.

[0170] Description and Use of the First Lower Wiring Structure 110 and the First Upper Wiring Structure 210 Figures 1 to 13 The contents described are basically the same, so these descriptions will not be provided below.

[0171] Compared to Fig.18 The example shown in Figures 14 to 17 The described second lower wiring structure 120 and the second upper wiring structure 220 may be disposed on the substrate 10 instead of the first lower wiring structure 110 and the first upper wiring structure 210 .

[0172] Fig.19 is a diagram for explaining a semiconductor device according to some embodiments. For ease of explanation, the explanation will focus on the use of Fig.18 The explanations are different.

[0173] Reference Fig.19 In the semiconductor device according to some embodiments, the transistor TR may include a nanosheet NS, a first gate electrode GE wrapped around or extending around the nanosheet NS, and a first gate insulating film GI between the nanosheet NS and the first gate electrode GE.

[0174] The nanosheet NS may be disposed on the lower fin pattern BAF. The nanosheet NS may be disposed in the third direction ( Figure 2 The transistor TR is shown as including three nanosheets NS spaced apart in the third direction D3, but is not limited thereto. Needless to say, the number of nanosheets NS disposed on the lower fin pattern BAF in the third direction D3 may be greater than three or less than three.

[0175] The lower fin pattern BAF and the nanosheet NS may both include, for example, silicon or germanium as an elemental semiconductor material. The lower fin pattern BAF and the nanosheet NS may both include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The lower fin pattern BAF and the nanosheet NS may include the same material or may include materials different from each other.

[0176] Figure 20 to Figure 22 is a diagram for explaining a semiconductor device according to some embodiments. For reference, Fig. 20 is a plan view for explaining a semiconductor device according to some embodiments. Fig.21 It is along Fig. 20 A cross-sectional view taken along lines EE and FF. Fig. 22 It is along Fig. 20 A cross-sectional view taken from GG.

[0177] Reference Figure 20 to Figure 22 , the logic cell LC may be disposed on the substrate 10. The logic cell LC may refer to a logic element (eg, an inverter, a flip-flop, etc.) that performs a specific function. The logic cell LC may include vertical transistors (vertical FETs) that form the logic element and wiring that connects the vertical transistors.

[0178] The logic cell LC on the substrate 10 may include a first active region RX1 and a second active region RX2. For example, the first active region RX1 may be a PMOSFET (P-type metal oxide semiconductor field effect transistor) region, and the second active region RX2 may be an NMOSFET (N-type metal oxide semiconductor field effect transistor) region. The first active region RX1 and the second active region RX2 may be defined by a trench T_CH formed in an upper portion of the substrate 10. The first active region RX1 and the second active region RX2 may be spaced apart from each other in the first direction D1.

[0179] The first lower epitaxial pattern SPO1 may be disposed on the first active region RX1, and the second lower epitaxial pattern SPO2 may be disposed on the second active region RX2. From a planar perspective, the first lower epitaxial pattern SPO1 may overlap with the first active region RX1, and the second lower epitaxial pattern SPO2 may overlap with the second active region RX2. The first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 may be epitaxial patterns formed by a selective epitaxial growth process. The first lower epitaxial pattern SPO1 may be disposed in a first recessed region RS1 of the substrate 10, and the second lower epitaxial pattern SPO2 may be disposed in a second recessed region RS2 of the substrate 10.

[0180] The first active pattern AP1 may be disposed on the first active region RX1, and the second active pattern AP2 may be disposed on the second active region RX2. Each of the first active pattern AP1 and the second active pattern AP2 may have a shape of a fin protruding vertically. From a planar perspective, each of the first active pattern AP1 and the second active pattern AP2 may have a strip shape extending in the first direction D1. The first active pattern AP1 may be arranged and spaced apart along the second direction D2, and the second active pattern AP2 may be arranged and spaced apart along the second direction D2.

[0181] Each first active pattern AP1 may include a first channel pattern CHP1 vertically protruding from the first lower epitaxial pattern SPO1 and a first upper epitaxial pattern DOP1 on the first channel pattern CHP1. Each second active pattern AP2 may include a second channel pattern CHP2 vertically protruding from the second lower epitaxial pattern SPO2 and a second upper epitaxial pattern DOP2 on the second channel pattern CHP2.

[0182] An element isolation film ST may be disposed on the substrate 10 to fill the trench T_CH. The element isolation film ST may cover upper surfaces of the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2. The first active pattern AP1 and the second active pattern AP2 may protrude vertically above the element isolation film ST.

[0183] A plurality of second gate electrodes 420 extending parallel to each other in the first direction D1 may be disposed on the element isolation film ST. The second gate electrodes 420 may be arranged and spaced apart along the second direction D2. The second gate electrode 420 may surround the first channel pattern CHP1 of the first active pattern AP1, and may surround the second channel pattern CHP2 of the second active pattern AP2. For example, the first channel pattern CHP1 of the first active pattern AP1 may have first to fourth side walls SW1 to SW4. The first side wall SW1 and the second side wall SW2 may be opposite to each other in the second direction D2, and the third side wall SW3 and the fourth side wall SW4 may be opposite to each other in the first direction D1. The second gate electrode 420 may be disposed on the first to fourth side walls SW1 to SW4. In other words, the second gate electrode 420 may surround the first to fourth side walls SW1 to SW4.

[0184] The second gate insulating film 430 may be interposed between the second gate electrode 420 and each of the first and second channel patterns CHP1 and CHP2. The second gate insulating film 430 may cover the bottom surface of the second gate electrode 420 and the inner sidewalls of the second gate electrode 420. For example, the second gate insulating film 430 may directly cover the first to fourth sidewalls SW1 to SW4 of the first active pattern AP1.

[0185] The first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 may protrude vertically above the second gate electrode 420. The upper surface of the second gate electrode 420 may be lower than the bottom surface of each of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. In other words, each of the first active pattern AP1 and the second active pattern AP2 may have a structure protruding vertically from the substrate 10 and penetrating the second gate electrode 420.

[0186] The semiconductor device according to the present embodiment may include a vertical transistor in which carriers move in a third direction D3. For example, when a voltage is applied to the second gate electrode 420 and the transistor turns "on", the carriers may move from the lower epitaxial patterns SPO1 and SPO2 to the upper epitaxial patterns DOP1 and DOP2 through the channel patterns CHP1 and CHP2. In the semiconductor device according to some embodiments, the second gate electrode 420 may completely surround the sidewalls SW1 to SW4 of the channel patterns CHP1 and CHP2. The transistor according to the present disclosure may be a three-dimensional vertical field effect transistor (e.g., VFET) having a ring gate structure. Since the gate surrounds the channel, the semiconductor device according to the disclosure may have excellent electrical properties.

[0187] The spacer 440 covering the second gate electrode 420 and the first and second active patterns AP1 and AP2 may be disposed on the element isolation film ST. The spacer 440 may include a silicon nitride film or a silicon oxynitride film. The spacer 440 may include a lower spacer 440LS, an upper spacer 440US, and a gate spacer 440GS between the lower spacer 440LS and the upper spacer 440US.

[0188] The lower spacer 440LS may directly cover the upper surface of the element isolation film ST. The second gate electrode 420 may be spaced apart from the element isolation film ST by the lower spacer 440LS in the third direction D3. The gate spacer 440GS may cover the upper surface and the outer sidewall of each of the second gate electrodes 420. The upper spacer 440US may cover the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. However, the upper spacer 440US does not cover the upper surface of the first upper epitaxial pattern DOP1 and the upper surface of the second upper epitaxial pattern DOP2, and may expose the upper surface of the first upper epitaxial pattern DOP1 and the upper surface of the second upper epitaxial pattern DOP2.

[0189] The first portion 190BP of the first lower interlayer insulating film 190 may be disposed on the spacer 440. An upper surface of the first portion 190BP of the first lower interlayer insulating film 190 may be substantially coplanar with an upper surface of the first upper epitaxial pattern DOP1 and an upper surface of the second upper epitaxial pattern DOP2. The second portion 190UP of the first lower interlayer insulating film 190 and the first interlayer insulating film 150 and the second interlayer insulating film 160 may be sequentially stacked on the first portion 190BP of the first lower interlayer insulating film 190. The first portion 190BP and the second portion 190UP may be included in the first lower interlayer insulating film 190. The second portion 190UP of the first lower interlayer insulating film 190 may cover an upper surface of the first upper epitaxial pattern DOP1 and an upper surface of the second upper epitaxial pattern DOP2.

[0190] At least one first source / drain contact 470 may be provided, the at least one first source / drain contact 470 penetrating the second portion 190UP of the first lower interlayer insulating film and connected to the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. At least one second source / drain contact 570 may be provided, the at least one second source / drain contact 570 sequentially penetrating the first lower interlayer insulating film 190, the lower spacer 440LS and the element isolation film ST and connected to the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2. A gate contact 480 may be provided, the gate contact 480 sequentially penetrating the second portion 190UP of the first lower interlayer insulating film, the first portion 190BP of the first lower interlayer insulating film and the gate spacer 440GS and connected to the second gate electrode 420.

[0191] The second etch stopper film 156 may be additionally disposed between the second portion 190UP of the first lower interlayer insulating film and the first interlayer insulating film 150. The first etch stopper film 155 may be disposed between the first interlayer insulating film 150 and the second interlayer insulating film 160.

[0192] The first lower wiring structure 110 may be disposed in the first interlayer insulating film 150. The first lower wiring structure 110 may include a lower via 110V and a lower wiring 110L. The description of the lower via 110V and the lower wiring 110L may be similar to the description of the upper via 210V and the first upper wiring 210L. However, the film structure of the first lower wiring structure 110 may be different from or the same as the film structure of the first upper wiring structure 210.

[0193] The first lower wiring structure 110 may be connected to the first source / drain contact 470, the second source / drain contact 570, and the gate contact 480. The first upper wiring structure 210 may be disposed in the second interlayer insulating film 160.

[0194] In contrast to the illustrated example, an additional wiring structure similar to the first upper wiring structure 210 may be further disposed, for example, between the first source / drain contact 470 and the first lower wiring structure 110 .

[0195] The detailed description of the first upper wiring structure 210 can be compared with the Figures 1 to 13 The content described is basically the same. Fig.21 and Fig. 22 As shown in FIG. 1 , the second lower wiring structure 120 and the second upper wiring structure 220 can be used as shown in FIG. Figures 14 to 17 The ground is arranged on the substrate 10 .

[0196] Fig.23 is a diagram for explaining a semiconductor device according to some embodiments.

[0197] Reference Fig.23 , a semiconductor device according to some embodiments may include a first source / drain pattern SD1, a second source / drain pattern SD2, a third source / drain contact CA1, a fourth source / drain contact CA2, a first contact connection via VPR1, a second contact connection via VPR2, and back wiring structures 250 and 260.

[0198] The second fin pattern AF2 and the third fin pattern AF3 may protrude from the substrate 10. For example, the second fin pattern AF2 and the third fin pattern AF3 may protrude from the upper side of the substrate 10. The second fin pattern AF2 and the third fin pattern AF3 may be spaced apart from each other. Each of the second fin pattern AF2 and the third fin pattern AF3 may include at least one of an elemental semiconductor such as silicon or germanium, a group IV-IV compound semiconductor, and a group III-V compound semiconductor.

[0199] The field insulating film 15 may be disposed on sidewalls of the second fin pattern AF2 and the third fin pattern AF3 . The field insulating film 15 may separate the second fin pattern AF2 and the third fin pattern AF3 .

[0200] A first source / drain pattern SD1 , a second source / drain pattern SD2 , a third source / drain contact CA1 , and a fourth source / drain contact CA2 may be disposed on an upper surface of the substrate 10 .

[0201] The first source / drain pattern SD1 may be disposed on the second fin pattern AF2. The first source / drain pattern SD1 may be connected to the second fin pattern AF2.

[0202] The second source / drain pattern SD2 may be disposed on the third fin pattern AF3. The second source / drain pattern SD2 may be connected to the third fin pattern AF3. The second source / drain pattern SD2 is separated from the first source / drain pattern SD1. The second source / drain pattern SD2 is not connected to the first source / drain pattern SD1.

[0203] Although not shown, as an example, the first source / drain pattern SD1 and the second source / drain pattern SD2 may be connected to a first electrode having a first electrode and a second electrode. Fig.18 As another example, the first source / drain pattern SD1 and the second source / drain pattern SD2 may be connected to the same Fig.19 The nanosheet NS shown in FIG. 1 has a channel region of the same shape. In this case, the second fin pattern AF2 and the third fin pattern AF3 may both be similar to Fig.19 The lower fin pattern shown in BAF is similar.

[0204] The first source / drain pattern SD1 and the second source / drain pattern SD2 include a semiconductor material. The first source / drain pattern SD1 and the second source / drain pattern SD2 may be semiconductor patterns formed through an epitaxial growth process.

[0205] The third source / drain contact CA1 may be disposed on the first source / drain pattern SD1. The third source / drain contact CA1 is connected to the first source / drain pattern SD1. For example, the third source / drain contact CA1 is electrically connected to the first source / drain pattern SD1.

[0206] The fourth source / drain contact CA2 may be disposed on the second source / drain pattern SD2. The fourth source / drain contact CA2 is connected to the second source / drain pattern SD2. For example, the fourth source / drain contact CA2 is electrically connected to the second source / drain pattern SD2. The third source / drain contact CA1 and the fourth source / drain contact CA2 are separated from each other.

[0207] The second lower interlayer insulating film 170 may be disposed on the field insulating film 15. The second lower interlayer insulating film 170 may be disposed around the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain contact CA1, and the fourth source / drain contact CA2. The second lower interlayer insulating film 170 separates the third source / drain contact CA1 from the fourth source / drain contact CA2.

[0208] The back wiring structures 250 and 260 may be disposed on the lower face of the substrate 10. The lower face of the substrate 10 is aligned with the upper face of the substrate 10 in the third direction ( Figure 2The back wiring structures 250 and 260 may include a first back wiring structure 250 and a second back wiring structure 260.

[0209] The first back wiring structure 250 may be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, the first back wiring structure 250 may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0210] The second back wiring structure 260 may be disposed on the first back wiring structure 250. The second back wiring structure 260 may be connected to the first back wiring structure 250.

[0211] Although a plurality of back wiring structures disposed at a plurality of metal levels are shown as being disposed on the lower surface of the substrate 10, this is only for ease of explanation, and the embodiment is not limited thereto. In contrast to the illustrated example, only a back wiring structure disposed at one metal level may be disposed on the lower surface of the substrate 10. That is, only the first back wiring structure 250 may be disposed on the lower surface of the substrate 10.

[0212] Although the first back wiring structure 250 and the second back wiring structure 260 are both shown as an integral structure in which wiring and vias are integrated, the embodiment is not limited thereto. In contrast to the illustrated example, at least one of the first back wiring structure 250 and the second back wiring structure 260 may have a structure in which a boundary between wiring and vias is divided.

[0213] The first back wiring structure 250 is shown to include wirings and vias, but is not limited thereto. In contrast to the illustrated example, the back wiring structure 250 may include only a portion corresponding to the wirings.

[0214] The back wiring insulating film 290 is disposed on the lower surface of the substrate 10. The back wiring structures 250 and 260 are disposed in the back wiring insulating film 290.

[0215] The first contact connection via VPR1 may be disposed between the third source / drain contact CA1 and the first back wiring structure 250. The first contact connection via VPR1 electrically connects the third source / drain contact CA1 and the first back wiring structure 250. The first contact connection via VPR1 passes through the field insulating film 15 and the substrate 10 and may be connected to the first back wiring structure 250.

[0216] The second contact connection via VPR2 may be disposed between the fourth source / drain contact CA2 and the first back wiring structure 250. The second contact connection via VPR2 electrically connects the fourth source / drain contact CA2 and the first back wiring structure 250. The second contact connection via VPR2 passes through the field insulating film 15 and the substrate 10 and may be connected to the first back wiring structure 250.

[0217] Taking the third source / drain contact CA1 and the first contact connection via VPR1 as an example, although the third source / drain contact CA1 is shown as covering the entire top of the first contact connection via VPR1, this is only for ease of explanation, and the embodiment is not limited thereto. In contrast to the example shown, as an example, the third source / drain contact CA1 may cover a portion of the top of the first contact connection via VPR1. In this case, the remaining portion of the top of the first contact connection via VPR1 may be coplanar with the top of the third source / drain contact CA1. As another example, the entire top of the first contact connection via VPR1 may be coplanar with the top of the third source / drain contact CA1. In this case, the third source / drain contact CA1 and the first contact connection via VPR1 may be connected by a via connection pattern, which contacts the top of the third source / drain contact CA1 and the top of the first contact connection via VPR1.

[0218] In contrast to the illustrated example, the first contact connection via VPR1 and the second contact connection via VPR2 may include a connection via portion and a buried conductive pattern portion. The connection via portion may be connected to the third source / drain contact CA1 and the fourth source / drain contact CA2. The buried conductive pattern portion may be connected to the back wiring structures 250 and 260.

[0219] The connecting via portion may be provided in the second lower interlayer insulating film 170 and the field insulating film 15. The buried conductive pattern portion may be provided in the substrate 10. As an example, the buried conductive pattern portion may have a linear shape extending longitudinally in one direction. As another example, the buried conductive pattern portion may be formed like Fig.15 and Fig.16 The second lower wiring structure 120 has a contact shape as well.

[0220] The third source / drain contact CA1, the fourth source / drain contact CA2, the first contact connection via VPR1, the second contact connection via VPR2 and the back wiring structures 250 and 260 may all include, for example, at least one of a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride and a conductive metal oxide.

[0221] Although the third source / drain contact CA1, the fourth source / drain contact CA2, the first contact connection via VPR1, the second contact connection via VPR2, the first back wiring structure 250 and the second back wiring structure 260 are shown as Fig.15 and Fig.16The second lower wiring structure 120 has a single conductive film structure, but the embodiment is not limited thereto. At least one of the third source / drain contact CA1, the fourth source / drain contact CA2, the first contact connection via VPR1, the second contact connection via VPR2, the first back wiring structure 250 and the second back wiring structure 260 may have a plurality of conductive film structures including a barrier film and a filling film.

[0222] The first lower wiring structure 110 may be disposed on the upper surface of the substrate 10. The first lower wiring structure 110 may be disposed on the third source / drain contact CA1 and the fourth source / drain contact CA2. Although the first lower wiring structure 110 is shown as not connected to the third source / drain contact CA1 and the fourth source / drain contact CA2, the embodiment is not limited thereto. The first upper wiring structure 210 is disposed on the first lower wiring structure 110.

[0223] In contrast to the example shown, if using Figures 14 to 17 The explained second lower wiring structure 120 and the second upper wiring structure 220 may be disposed on an upper surface of the substrate 10 .

[0224] Furthermore, in contrast to the illustrated example, at least one of the first back wiring structure 250 and the second back wiring structure 260 may include a barrier film formed of a two-dimensional material like the first upper wiring structure 210 .

[0225] In contrast to the example shown, Fig.23 The semiconductor device shown in FIG. 1 may not include the substrate 10. During the manufacturing process, the substrate 10 may be removed using a grinding process or the like.

[0226] Figure 24 to Figure 26 are diagrams for explaining semiconductor devices according to some embodiments. For ease of explanation, the explanation will focus on the use of Fig.23 The explanations are different.

[0227] Reference Fig.24 In the semiconductor device according to some embodiments, the second upper wiring structure 220 and the second lower wiring structure 120 may connect the third source / drain contact CA1 and the first contact connection via VPR1 .

[0228] The second upper wiring structure 220 and the second lower wiring structure 120 may connect the fourth source / drain contact CA2 and the second contact connection via VPR2 .

[0229] The third source / drain contact CA1 and the first contact connection via VPR1 may be electrically connected through a second upper wiring structure 220 including a barrier film formed of a two-dimensional material. The fourth source / drain contact CA2 and the second contact connection via VPR2 may be electrically connected through a second upper wiring structure 220 including a barrier film formed of a two-dimensional material.

[0230] The second lower wiring structure 120 may be disposed between the second upper wiring structure 220 and the third source / drain contact CA1. The second lower wiring structure 120 may be disposed between the second upper wiring structure 220 and the fourth source / drain contact CA2.

[0231] A portion of the first contact connection via VPR1 and a portion of the second contact connection via VPR2 may be disposed in the first interlayer insulating film 150. The first contact connection via VPR1 and the second contact connection via VPR2 may make contact with the second upper wiring structure 220, respectively.

[0232] In contrast to the illustrated example, the second lower wiring structure 120 may also be disposed between the first contact connection via VPR1 and the second upper wiring structure 220. The second lower wiring structure 120 may also be disposed between the second contact connection via VPR2 and the second upper wiring structure 220.

[0233] Description and use of the second lower wiring structure 120 and the second upper wiring structure 220 Figures 14 to 17 The content described is essentially the same.

[0234] Reference Fig.25 In the semiconductor device according to some embodiments, the first lower wiring structure 110 may connect the third source / drain contact CA1 and the first contact connection via VPR1 .

[0235] The first lower wiring structure 110 may connect the fourth source / drain contact CA2 and the second contact connection via VPR2 .

[0236] The first lower wiring structure 110 may include a lower via 110V and a lower wiring 110L. The lower via 110V may be disposed between the lower wiring 110L and the third source / drain contact CA1. The lower via 110V may be disposed between the lower wiring 110L and the fourth source / drain contact CA2.

[0237] The first contact connection via VPR1 and the second contact connection via VPR2 may both contact the lower wiring 110L. In contrast to the illustrated example, the lower via 110V may also be disposed between the first contact connection via VPR1 and the lower wiring 110L. The lower via 110V may also be disposed between the second contact connection via VPR2 and the lower wiring 110L.

[0238] The first upper wiring structure 210 may be disposed on the first lower wiring structure 110 .

[0239] Although the lower via 110V and the lower wiring 110L are shown as having different structures, the embodiment is not limited thereto. The first lower wiring structure 110 may include the lower via 110V and the lower wiring 110L formed as an integral structure. As an example, the first lower wiring structure 110 formed as an integral structure may include a barrier film formed of a two-dimensional material like the first upper wiring structure 210. As another example, the first lower wiring structure 110 formed as an integral structure may not include a barrier film formed of a two-dimensional material.

[0240] Reference Fig.26 In the semiconductor device according to some embodiments, the third source / drain contact CA1 and the fourth source / drain contact CA2 may both be connected to the first back wiring structure 250 .

[0241] The third source / drain contact CA1 and the fourth source / drain contact CA2 may each include a contact portion connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 and a contact portion extending in the third direction ( Figure 2 The via portion of the third source / drain contact CA1 and the via portion of the fourth source / drain contact CA2 may penetrate the field insulating film 15. For example, the via portion of the third source / drain contact CA1 and the via portion of the fourth source / drain contact CA2 may penetrate the substrate 10.

[0242] In contrast to the illustrated example, additional buried conductive patterns may be disposed between the third source / drain contact CA1 and the first back wiring structure 250 and between the fourth source / drain contact CA2 and the first back wiring structure 250. For example, additional buried conductive patterns may be disposed inside the substrate 10.

[0243] The second upper wiring structure 220 may be disposed on the third source / drain contact CA1 and the fourth source / drain contact CA2 . The third source / drain contact CA1 and the fourth source / drain contact CA2 may both be in contact with the second upper wiring structure 220 .

[0244] Figures 27 to 32 is a diagram for describing intermediate steps of a method for manufacturing a semiconductor device according to some embodiments.

[0245] For reference, Fig. 27 and Figure 29 to Figure 32 It is along Figure 1 AA cross-sectional view. Fig.28 It is along Figure 1 A cross-sectional view of BB.

[0246] Reference Fig. 27 and Fig.28 , a first lower wiring structure 110 is formed in the first interlayer insulating film 150 .

[0247] A first lower wiring trench 110t is formed in the first interlayer insulating film 150. A first lower wiring structure 110 is formed in the first lower wiring trench 110t. The first lower wiring structure 110 may include a lower barrier film 111 and a lower filling film 112.

[0248] Subsequently, a first etch stopper film 155 may be formed on the first interlayer insulating film 150 and the first lower wiring structure 110 .

[0249] A second interlayer insulating film 160 may be formed on the first etch stopper film 155. The second interlayer insulating film 160 may include a first upper wiring trench 210t. The first upper wiring trench 210t may include an upper via trench 210V_t and a first upper wiring trench 210L_t.

[0250] The first upper wiring trench 210t may penetrate the first etch stopper film 155. The first upper wiring trench 210t may expose a portion of the first lower wiring structure 110.

[0251] Reference Fig.29 A selective inhibition film 180 is formed on the first lower wiring structure 110 exposed by the first upper wiring trench 210t.

[0252] The selective inhibiting film 180 may be formed on a conductive material. The selective inhibiting film 180 is not formed on an insulating material.

[0253] The selective inhibition film 180 includes an organic material. The selective inhibition film 180 may prevent a conductive material from being deposited on a surface on which the selective inhibition film 180 is formed.

[0254] Reference Fig.30 In a state where the selective inhibition film 180 is formed, a pre-upper barrier film 211P is formed along the sidewall of the first upper wiring trench 210 t . The pre-upper barrier film 211P is formed along the upper surface of the second interlayer insulating film 160 .

[0255] The pre-upper barrier film 211P is not formed on the first lower wiring structure 110 formed with the selective inhibition film 180. The pre-upper barrier film 211P may not be formed along the bottom surface of the first upper wiring trench 210t.

[0256] Reference Fig.30 and Fig.31 , the selective inhibition film 180 may be removed to expose the first lower wiring structure 110 .

[0257] The selective suppression film 180 may be removed by, for example, plasma treatment, but is not limited thereto.

[0258] Subsequently, a pre-liner film 212P may be formed on the pre-blocking film 211P. The pre-liner film 212P may be formed along the sidewalls of the first upper wiring trench 210t and the bottom surface of the first upper wiring trench 210t. The pre-liner film 212P is formed along the upper surface of the second interlayer insulating film 160.

[0259] Reference Fig.32 , a pre-fill film 213P may be formed on the pre-liner film 212P.

[0260] The pre-upper-fill film 213P may fill the first upper wiring trench 210 t . The pre-upper-fill film 213P may cover the upper surface of the second interlayer insulating film 160 .

[0261] Then, refer to Figure 2 , the pre-upper barrier film 211P, the pre-upper liner film 212P, and the pre-upper fill film 213P on the upper surface of the second interlayer insulating film 160 may be removed. Thus, the first upper wiring structure 210 may be formed in the first upper wiring trench 210t.

[0262] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be implemented in various different forms. It will be understood by those of ordinary skill in the technical field to which the present disclosure belongs that the present disclosure can be implemented in other specific forms without changing the inventive concept of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive but illustrative in all aspects.

Claims

1. A semiconductor device, the semiconductor device include: Lower wiring structure; an upper interlayer insulating film on the lower wiring structure and including an upper wiring trench, the upper wiring trench being located in the upper interlayer insulating film; as well as an upper wiring structure in the upper wiring trench and including an upper barrier structure and an upper filling film on the upper barrier structure, The upper barrier structure includes a sidewall portion extending along a sidewall of the upper wiring trench and a bottom portion extending along a bottom surface of the upper wiring trench. wherein the sidewall portion of the upper barrier structure comprises a two-dimensional material, and There is no two-dimensional material at the bottom portion of the upper barrier structure.

2. The semiconductor device according to claim 1, in, The upper barrier structure includes an upper barrier film and an upper liner film between the upper barrier film and the upper filling film, wherein the upper barrier film is in contact with the upper interlayer insulating film and includes a two-dimensional material.

3. The semiconductor device according to claim 2, in, The upper liner film includes tantalum nitride and / or tantalum nitride doped with ruthenium.

4. The semiconductor device according to claim 2, in, The upper film includes cobalt and / or ruthenium cobalt.

5. The semiconductor device according to claim 2, in, The upper liner film includes a first sub-upper liner film and a second sub-upper liner film between the first sub-upper liner film and the upper filling film.

6. The semiconductor device according to claim 5, in, The first upper sub liner film and the second upper sub liner film each extend along the sidewall and the bottom surface of the upper wiring trench.

7. The semiconductor device according to claim 5, in, The first sub-liner film includes tantalum nitride and / or tantalum nitride doped with ruthenium, and The second upper sub-liner film includes cobalt and / or ruthenium cobalt.

8. The semiconductor device according to claim 1, in, The upper barrier structure includes an upper barrier film and an upper liner film between the upper barrier film and the upper filling film. wherein the upper barrier film has no direct contact with the lower wiring structure, and The upper liner film contacts the upper filling film and the lower wiring structure along an interface between the lower wiring structure and the upper wiring structure.

9. The semiconductor device according to claim 1, in, The upper barrier structure includes an upper barrier film and an upper liner film between the upper barrier film and the upper filling film. wherein the upper barrier film contacts the lower wiring structure at an edge portion of an interface between the lower wiring structure and the upper wiring structure, and There is no upper barrier film at a central portion of an interface between the lower wiring structure and the upper wiring structure.

10. The semiconductor device according to claim 1, in, Two-dimensional materials include tantalum sulfide.

11. A semiconductor device, the semiconductor device include: Lower wiring structure; an upper interlayer insulating film on the lower wiring structure and including an upper wiring trench, the upper wiring trench being located in the upper interlayer insulating film; as well as an upper wiring structure in the upper wiring trench and including an upper barrier film and an upper filling film on the upper barrier film, wherein the upper barrier film extends along the sidewall of the upper wiring trench and does not extend along at least a portion of an interface between the upper wiring structure and the lower wiring structure, and The upper barrier film includes a two-dimensional material.

12. The semiconductor device according to claim 11, further comprising: include: The upper liner film is between the upper barrier film and the upper filling film. The upper liner film extends along the sidewalls and the bottom surface of the upper wiring trench.

13. The semiconductor device according to claim 12, in, The upper liner film includes tantalum nitride, tantalum nitride doped with ruthenium, cobalt and / or ruthenium cobalt.

14. The semiconductor device according to claim 12, in, The upper liner film includes a plurality of conductive films.

15. The semiconductor device according to claim 11, in, The upper filling film is not in direct contact with the lower wiring structure.

16. The semiconductor device according to claim 11, in, The upper barrier film includes tantalum sulfide.

17. A semiconductor device, the semiconductor device include: Lower wiring structure; as well as an upper wiring structure, on the lower wiring structure and comprising an upper barrier film, a first upper liner film and an upper filling film, The first upper liner film is between the upper barrier film and the upper filling film. The first upper liner film includes a first portion in contact with the lower wiring structure and a second portion extending away from the lower wiring structure. wherein the upper barrier film extends along the second portion of the first upper liner film and does not extend along the first portion of the first upper liner film, wherein the upper barrier film comprises tantalum sulfide, and The first upper liner film includes tantalum nitride or tantalum nitride doped with ruthenium.

18. The semiconductor device according to claim 17, further comprising: include: The second upper liner film is between the first upper liner film and the upper filling film. Wherein, the second upper liner film includes cobalt or ruthenium cobalt.

19. The semiconductor device according to claim 17, in, The upper wiring structure includes an upper wiring and an upper via, and The upper via electrically connects the upper wiring and the lower wiring structure.

20. The semiconductor device according to claim 17, in, The upper wiring structure includes an upper wiring extending longitudinally in one direction, and A portion of the upper wiring is directly on the lower wiring structure.

Images