Two-terminal integrated circuit device for electrostatic discharge protection

Abstract

The two-terminal IC device may be used for ESD protection. The IC device may include a deep N-well between a P-type substrate and a well group including a first P-well, a second P-well, and an N-well. Another well may be present between the second P-well and the N-well. A P-type semiconductor structure may be formed in the P-well. Two N-type semiconductor structures may be formed in the N-well and the second P-well, respectively. A contact of the P-type semiconductor structure may be electrically coupled to a contact of the N-type semiconductor structure in the second P-well. The two contacts may constitute a first terminal of the IC device. A contact of the N-type semiconductor structure in the N-well may constitute a second terminal of the IC device. The first P-well may have a larger size but a lower dopant concentration than the second P-well or N-well.

Description

Technical Field

[0001] A field effect transistor (FET), such as a metal oxide semiconductor (MOS) FET (MOSFET), is typically a three-terminal device including a source, a drain, and a gate terminal, and uses an electric field to control the current flowing through the device. A FET typically includes a semiconductor channel material, a source region and a drain region provided in the channel material, and a gate stack (also referred to as a "gate"), the gate stack including at least a gate electrode material and may also include a gate dielectric material, the gate stack being provided on a portion of the channel material between the source region and the drain region. Recently, FETs with non-planar architectures, such as FinFETs (sometimes also referred to as "wrap around gate transistors" or "tri-gate transistors") and nanosheet or nanoribbon FETs (sometimes also referred to as "all-around gate transistors"), have been widely explored as alternatives to planar structure transistors. Background Art

[0002] The embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For ease of description, similar reference numerals denote similar structural elements. In the figures of the accompanying drawings, the embodiments are illustrated by way of example and not limitation.

[0003] Figure 1 An example integrated circuit (IC) device for electrostatic discharge (ESD) protection according to some embodiments of the present disclosure is described.

[0004] Figure 2 A circuit diagram of an IC device having two terminals according to some embodiments of the present disclosure is illustrated.

[0005] Figure 3 Voltage-current curves of an IC device having two terminals according to some embodiments of the present disclosure are illustrated.

[0006] Figure 4 is a top view of an IC device having two terminals according to some embodiments of the present disclosure.

[0007] Figures 5A-5I A process for forming a two-terminal IC device according to some embodiments of the present disclosure is described.

[0008] Figure 6A-6B is a top view of a wafer and die that may facilitate one or more two-terminal IC devices for ESD protection according to some embodiments of the present disclosure.

[0009] Figure 7is a side cross-sectional view of an example IC package that may include one or more two-terminal IC devices for ESD protection according to some embodiments of the present disclosure.

[0010] Figure 8 is a cross-sectional side view of an IC device assembly that may include components having one or more two-terminal IC devices for ESD protection according to some embodiments of the present disclosure.

[0011] Fig. 9 is a block diagram of an example computing device that may include one or more components having one or more two-terminal IC devices according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0013] Many IC devices, such as MOS devices, are often susceptible to gate oxide breakdown and may fail prematurely during an ESD event. Many currently available ESD protection solutions are circuit-based. An example is an SCR (silicon controlled rectifier) ​​triggered ESD solution. An SCR with an external trigger circuit system can be used in conjunction with a diode for ESD protection. For fail-safe protection, a large area diode is often used in conjunction with an SCR for ESD protection. An intrinsic SCR can have a very high snapback voltage, for example, the breakdown voltage of the NW / PW junction, which is typically greater than the oxide and junction breakdown voltage of the victim. Therefore, a thick gate transistor can be used as a trigger for the SCR to induce conduction at a much lower voltage. However, many SCRs have a high inherent overshoot and a lower holding voltage, which can result in a large voltage accumulation on the victim device and the risk of permanent conduction during transients at the pad node.

[0014] Another example is a standalone grounded gate NMOS (GGMOS) solution. During an ESD event, the high current / voltage at the drain of the GGNMOS causes it to recover quickly when the bipolar junction transistor (BJT) turns on, and the device begins to shunt the ESD current to ground, thereby protecting the core circuit / buffer from ESD stress. However, GGNMOS devices may be susceptible to gate oxide breakdown and fail prematurely during ESD events. This is due to high voltage ESD spikes at the drain, which can cause gate oxide leakage and / or breakdown at the drain / oxide corner area. Adding a series ballast resistor at the drain node helps to evenly distribute the ESD current across all legs of the device to achieve higher ESD protection. A standalone GGMOS can be used with the gate and source connected to the ground node and the drain connected to an exposed pin / pad.

[0015] Embodiments of the present disclosure may improve at least some of the above challenges and problems by providing a two-terminal IC device for ESD protection.The two-terminal IC device may be based on a FET with a non-planar architecture and may be used as an ESD clamp for devices susceptible to ESD events.

[0016] In various embodiments of the present disclosure, a two-terminal IC device may include a deep N-well stacked between a substrate and a well group. The substrate may be a P-type substrate, based on which a deep N-well and a well group may be formed. The well group may include a first P-well, a second P-well, and an N-well, wherein a semiconductor structure may be formed. For example, a P-type semiconductor structure may be formed in a first P-well, a first N-type semiconductor structure may be formed in a second P-well, and a second N-type semiconductor structure may be formed in an N-well. The P-type semiconductor structure, the first N-type semiconductor structure, or the second N-type semiconductor structure may include one or more fins, nanoribbons, or other types of non-planar structures. The contact of the P-type semiconductor structure may be electrically coupled to a contact in the first N-type semiconductor structure. For example, a conductive structure may be electrically coupled to both the P-type semiconductor structure and the first N-type semiconductor structure. This may be one of the two terminals of the IC device. The terminal may be electrically coupled to a ground plane. The contact of the second N-type semiconductor structure may constitute another terminal of the IC device, which may be electrically coupled to a power plane. The IC device may also include a gate (e.g., a metal gate, a polysilicon gate, etc.) on some or all of the wells. The gates may be separated from each other by an electrical insulator. The gate may be a floating gate.

[0017] The size and dopant concentration of the wells in the two-terminal IC device can be controlled to optimize key fast recovery characteristics of the two-terminal IC device, such as breakdown voltage, trigger voltage, holding voltage, etc. In some embodiments, the second P-well can be between the first P-well and the N-well. The IC device can also include another well separating the second P-well from the N-well. The size of the first P-well can be larger than the corresponding size of the second P-well. The distance between the edge of the first P-well and the edge of the P-type semiconductor structure can be larger than the distance between the edge of the second P-well and the edge of the first N-type semiconductor structure. The second P-well can be doped higher than the first P-well. The second P-well can also be doped higher than the well between the second P-well and the N-well.

[0018] The present disclosure provides a solution for adjusting the fast recovery characteristics of an ESD protection device by adjusting the doping at a specific concentration and material, without the need for additional circuitry, to meet the requirements of the parent circuit. The solution can avoid false triggering during conventional DC operation and prevent the victim device in the parent circuit from breaking down before it is too late to turn on the ESD protection. The two-terminal IC device can be used for ESD protection requirements of various circuits and topologies, such as open drain circuits, buck circuits, etc.

[0019] It should be noted that in some arrangements, the term "nanoribbon" has been used to describe an elongated semiconductor structure having a substantially rectangular cross-section (e.g., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term "nanowire" has been used to describe a similar structure, but having a substantially circular or square transverse cross-section. In the following, the single term "nanoribbon" is used to describe the elongated semiconductor structure regardless of the shape of the transverse cross-section. Thus, as used herein, the term "nanoribbon" is used to encompass an elongated semiconductor structure having a substantially rectangular transverse cross-section (possibly with rounded corners), an elongated semiconductor structure having a substantially square transverse cross-section (possibly with rounded corners), an elongated semiconductor structure having a substantially circular or elliptical / oval transverse cross-section, and an elongated semiconductor structure having any polygonal transverse cross-section.

[0020] In the following, some descriptions may refer to a particular source or drain (S / D) region or contact being a source region / contact or a drain region / contact. However, unless otherwise specified, it is not important which region / contact of a transistor or diode is considered to be a source region / contact and which region / contact is considered to be a drain region / contact, as it is common in the FET field that the designation of source and drain is generally interchangeable. Therefore, the descriptions of some illustrative embodiments of source and drain regions / contacts provided herein apply to embodiments in which the designation of source and drain regions / contacts may be reversed.

[0021] As used herein, the term "metal layer" may refer to a layer above a substrate that includes conductive interconnect structures for providing electrical connections between different IC components. The metal layers described herein may also be referred to as "interconnect layers" to clearly indicate that these layers include conductive interconnect structures that may be, but need not be, metal.

[0022] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0023] In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly used by those skilled in the art to convey the essence of their operation to others skilled in the art. For example, the term "connected" means a direct electrical or magnetic connection between connected things without any intermediate device, while the term "coupled" means a direct electrical or magnetic connection between connected things, or an indirect connection through one or more passive or active intermediate devices. The term "circuit" means one or more passive and / or active components that are arranged to cooperate with each other to provide the desired function. If used, the terms "oxide", "carbide", "nitride", etc. refer to compounds containing oxygen, carbon, nitrogen, etc., respectively, the term "high-k dielectric" refers to a material having a higher dielectric constant (k) than silicon oxide, and the term "low-k dielectric" refers to a material having a lower k than silicon oxide. The terms "substantially", "close", "approximately", "close to", and "about" generally refer to within + / -10% of the target value, such as within + / -5% or within + / -2%, based on the context of the specific value described herein or known in the art. Similarly, terms indicating the orientation of elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally refer to within + / -8% of the target value, e.g., within + / -5% of the target value or within + / -2% of the target value, based on the context of the specific value described herein or known in the art. In addition, the term "or" refers to an inclusive "or" rather than an exclusive "or."

[0024] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with both layers, or may have one or more intervening layers. In contrast, a first layer "above" a second layer is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0025] For purposes of this disclosure, the phrase "A and / or B" or the phrase "A or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" or the phrase "A, B, or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used with reference to a measurement range, the term "between" includes the ends of the measurement range. As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0026] The specification may use the phrases "in one embodiment" or "in multiple embodiments," each of which may refer to one or more identical or different embodiments. In addition, as used with respect to embodiments of the present disclosure, the terms "including," "comprising," and "having," etc. are synonymous. The present disclosure may use perspective-based descriptions, such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects only indicates that reference is made to different instances of similar objects, and is not intended to imply that the objects described must be in a given order in time, space, ranking, or in any other way.

[0027] In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be taken in a limiting sense. For convenience, if there are sets of figures designated with different letters, e.g. Figure 7 A-7B, then the set may be referred to here without a letter, e.g. as " Figure 7 ”

[0028] Some schematic illustrations of example structures of various devices and components described herein may be shown in the accompanying drawings with exact right angles and straight lines, but it should be understood that when any structure described herein is examined using, for example, a scanning electron microscope (SEM) image or a transmission electron microscope (TEM) image, such schematic illustrations may not reflect actual process limitations that may cause features to appear less than "ideal." In such images of real structures, possible processing defects may also be visible, such as imperfectly straight edges of material, tapered vias or other openings, unintentional rounding of corners or thickness variations of different material layers, occasional spiral, edge or combined dislocations within a crystal region, and / or occasional dislocation defects of single atoms or clusters of atoms. Other defects that are not listed here but are common in the field of device manufacturing may exist. Examining the layout and mask data of portions of the device using, for example, an optical microscope, TEM or SEM and reverse engineering them to reconstruct the circuit, and / or examining a cross-section of the device using, for example, physical failure analysis (PFA) to detect the shape and position of the various device elements described herein will allow the presence of a two-terminal IC device as described herein to be determined.

[0029] The various operations may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations are necessarily dependent on the order. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0030] Various IC devices with two terminals as described herein may be implemented in or associated with one or more components associated with the IC, or / and may be implemented between various such components. In various embodiments, the components associated with the IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. The components associated with the IC may include those components mounted on the IC or those components connected to the IC. The IC may be analog or digital and may be used in a variety of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be used as part of a chipset for performing one or more related functions in a computer.

[0031] Figure 1An example IC device 100 for ESD protection according to some embodiments of the present disclosure is illustrated. The IC device 100 includes a support structure 110, an electrical insulator 115, a deep N-well 120, a P-well 130, another P-well 140, a well 150, an N-well 160, a semiconductor structure 135, another semiconductor structure 145, yet another semiconductor structure 165, a conductive structure 170, another conductive structure 180, and a plurality of gate electrodes 190 (individually referred to as "gate electrodes 190"). In other embodiments, the IC device 100 may include different, fewer, or more components.

[0032] The support structure 110 may be any suitable structure, such as a substrate, a die, a wafer, or a chip, based on which a semiconductor structure (e.g., deep N-well 120, P-well 130, P-well 140, well 150, N-well 160, etc.) may be constructed. The support structure 110 may be, for example, a Fig. 6A The wafer 2000 may be a die or included in a die, such as discussed below. Figure 6B The singled die 2002 of FIG. 1 is a semiconductor substrate composed of a semiconductor material system, including, for example, an N-type or P-type material system. In some embodiments, the support structure 110 includes a doped semiconductor material, such as a semiconductor material with a P-type dopant. The support structure 110 may be a P-type substrate.

[0033] In some embodiments, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or silicon-on-insulator substructures. In other embodiments, the semiconductor substrate may be formed using alternative materials, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-V, II-VI, or IV materials. In some embodiments, the substrate may be amorphous. In some embodiments, the support structure may be a printed circuit board (PCB) substrate.

[0034] Although some examples of materials that can be used to form support structure 110 are described herein, any material that can be used as a basis on which an IC can be built falls within the spirit and scope of the present disclosure. In various embodiments, support structure 110 may include any such substrate, possibly with some layers and / or devices already formed thereon, which are not specifically shown in this figure. As used herein, the term "support" does not necessarily mean that it provides mechanical support for the IC devices / structures (e.g., transistors, capacitors, interconnects, etc.) built thereon. For example, some other structures (e.g., a carrier substrate or a packaging substrate) can provide such mechanical support, and support structure 110 can provide material "support" because, for example, the IC devices / structures described herein are built based on the semiconductor material of support structure 110. However, in some embodiments, support structure 110 can provide mechanical support.

[0035] Deep N well 120 separates support structure 110 from P well 130, P well 140, well 150, and N well 160. Deep N well 120 may include one or more N-doped semiconductor materials. In some embodiments, deep N well 120 may be formed based on a substrate including support structure 110, for example, by doping a portion of the substrate located on top of support structure 110. The dopant concentration (e.g., the concentration of N-type dopants in deep N well 120) may be in the range of approximately 5×10 17 atoms / cm 3 To approximately 1.7×10 18 atoms / cm 3 within the range.

[0036] The P-well 130 is above a portion of the deep N-well 120. The P-well 140 may be a P-doped semiconductor region including one or more semiconductor materials and one or more P-type dopants. In some embodiments, the P-well 130 may be formed based on a substrate including the support structure 110, for example, by doping a portion of the substrate on top of the support structure 110 or on top of the deep N-well 120. The P-well 130 includes one or more P-doped semiconductor materials. The dopant concentration (e.g., the concentration of the P-type dopant in the P-well 130) may be in the range of approximately 5×10 16 atoms / cm 3 To approximately 5×10 17 atoms / cm 3 In some embodiments, the P-well 140 may be doped by multiple doping steps with different energies. For example, the first doping may be at 15-30k, the second doping may be at 35-50k, and the third doping may be at 50-70k. The dopant may be a P-type dopant, such as boron or other P-type dopants.

[0037] The P-well 140 is above another portion of the deep N-well 120. The P-well 140 may be a P-doped semiconductor region including one or more semiconductor materials and one or more P-type dopants. The dopant concentration (e.g., the concentration of the P-type dopant in the P-well 140 may be in the range of approximately 1.5×10 18 atoms / cm 3 to approximately 3.5×10 18 atoms / cm 3 In some embodiments, the lengths and doping concentrations of the two P-wells 130 and 140 can be selected to adjust the trigger voltage Vt1 of the IC device 100 by adjusting the Rb resistance. In some embodiments, the size of the P-well 140 along the Y axis (denoted by Figure 1 The P-well 140 in FIG. 1 is smaller than the corresponding size of the P-well 130 (indicated by the dashed arrow in FIG. 140 ). Figure 1 140 is indicated by a dashed arrow in the P-well 130 in FIG. 140 . The size of the P-well 130 may be in a range from approximately 300 nanometers (nm) to approximately 900 nm. The size of the P-well 140 may be smaller than the size of the P-well 130 by up to approximately 200 nm.

[0038] In some embodiments, the P-well 140 may be formed based on a substrate including the support structure 110, for example, by doping a portion of the substrate on top of the support structure 110 or on top of the deep N-well 120 and immediately adjacent to the P-well 130. In some embodiments, the dopant concentration of the P-well 140 may be higher than the dopant concentration of the P-well 130. In an embodiment, the dopant concentration of the P-well 140 may be approximately at least 2.5 times the dopant concentration of the P-well 130. For example, the dopant concentration of the P-well 140 may be approximately 2.5 to 6 times the dopant concentration of the P-well 130.

[0039] Well 150 may be a P-well, an N-well, or an intrinsic well without additional implantation. In some embodiments, well 150 may be formed based on a substrate including support structure 110, for example, by doping a portion of the substrate on top of support structure 110 or on top of deep N-well 120 and immediately adjacent to P-well 140. Well 150 may separate P-wells 130 and 140 from N-well 160. In some embodiments, well 150 may have a lower dopant concentration than that of P-well 140. For example, the dopant concentration of well 150 may be approximately half of the dopant concentration of P-well 140, or even lower. In an embodiment, the dopant concentration of well 150 may be approximately 0 to 0.5 times the dopant concentration of P-well 140, or even lower.

[0040] N-well 160 is an N-doped semiconductor region that includes one or more semiconductor materials and one or more N-type dopants. In some embodiments, N-well 160 can be formed based on a substrate including support structure 110, for example, by doping a portion of the substrate on top of support structure 110 or on top of deep N-well 120 and immediately adjacent to well 150. In some embodiments, N-well 160 can have a dopant concentration that is the same as or substantially similar to that of P-well 140.

[0041] A portion of P-well 130, P-well 140, well 150, or N-well 160 may be surrounded by electrical insulator 115. Electrical insulator 115 may include a dielectric material, a hysteresis material, etc. Example dielectric materials include oxides (e.g., silicon-based oxides, metal oxides, etc.), high-k dielectrics, etc. Example hysteresis materials include ferroelectric materials, antiferroelectric materials, etc.

[0042] The semiconductor structure 135 is at least partially in the P-well 130. The semiconductor structure 135 may be a P-type semiconductor structure. In some embodiments, the semiconductor structure 135 includes one or more semiconductor materials and one or more P-type dopants. The semiconductor structure 145 is at least partially in the P-well 140. The semiconductor structure 145 may be a P-type semiconductor structure. In some embodiments, the semiconductor structure 145 includes one or more semiconductor materials and one or more P-type dopants. The semiconductor structure 165 is at least partially in the N-well 160. The semiconductor structure 165 may be a P-type semiconductor structure. In some embodiments, the semiconductor structure 165 includes one or more semiconductor materials and one or more P-type dopants. The semiconductor structures 135, 145, or 165 may be formed by an epitaxial deposition process and a subsequent doping process.

[0043] Conductive structure 170 has a first portion (e.g., a vertical segment on the left) above semiconductor structure 135, a second portion (e.g., a vertical segment on the right) above semiconductor structure 145, and a third portion (e.g., a horizontal portion) connected to the first portion and the second portion. With conductive structure 170, semiconductor structure 135 and semiconductor structure 145 can be at the same electrical potential. Conductive structure 170 can constitute a terminal of IC device 100. In some embodiments, conductive structure 170 is electrically coupled to a power plane or a ground plane associated with IC device 100. In an embodiment, conductive structure 170 is electrically coupled to VSS.

[0044] Conductive structure 180 is above semiconductor structure 165 and may constitute another terminal of IC device 100. Conductive structure 180 may be separated from conductive structure 170 by electrical insulator 115 or one or more other electrical insulators. In some embodiments, conductive structure 170 is electrically coupled to a power plane or a ground plane associated with IC device 100. In an embodiment, conductive structure 170 is electrically coupled to a power plane.

[0045] The gate electrode 190 is above the P-well 130, the P-well 140, and the N-well 160. The gate electrode 190 may extend in a direction perpendicular to the plane of the support structure 110. The semiconductor structures 135, 145, and 165 are each between a pair of gate electrodes 190. Figure 1 Six gate electrodes 190 are shown, but IC device 100 may include a different number of gate electrodes 190. Gate electrodes 190 are conductive and separated from each other by electrical insulator 115 or one or more other electrical insulators. Gate electrodes 190 may include metal, polycrystalline silicon (polysilicon), or the like.

[0046] Figure 2 1 illustrates a circuit diagram of an IC device 200 having two terminals 201 and 202 according to some embodiments of the present disclosure. Embodiments of the IC device 200 may be Figure 1 The IC device 100 in FIG. Figure 2 As shown, IC device 200 includes support structure 210, electrical insulator 215, layer 220, P well 230, another P well 240, well 250, N well 260, and contacts 270, 275, and 280. In other embodiments, IC device 200 may include different, fewer, or more components.

[0047] The support structure 210 may be a P-type substrate. Figure 1 The electrical insulator 215 may include a dielectric material, a hysteresis material, etc. The electrical insulator 215 may be an embodiment of the electrical insulator 115. The layer 220 may include a deep N well. The layer 220 may be Figure 1 An embodiment of the deep N well 120 in FIG.

[0048] P-well 230, P-well 240, well 250, and N-well 260 are above layer 220. P-well 240 is between P-well 230 and well 250. Well 250 is between P-well 240 and N-well 260. P-well 230 may be an embodiment of P-well 130. P-well 240 may be an embodiment of P-well 140. Well 250 may be an embodiment of well 150. N-well 260 may be an embodiment of N-well 160.

[0049] Contacts 270, 275, and 280 may each include an electrical conductor, such as a metal, etc. Contact 270 is above P-well 230. Contact 275 is above P-well 240. Contacts 270 and 275 are both coupled to terminal 201 of IC device 200. Contact 280 is above N-well 260 and is coupled to another terminal 202 of IC device 200. Terminal 201 and terminal 202 may be at different electrical potentials.

[0050] IC device 200 may constitute a BJT, such as an NPN BJT. P-well 230 (optionally including one or more semiconductor structures in P-well 230) may be a base. In addition, P-well 240 (optionally including one or more semiconductor structures in P-well 240) may be an emitter, and N-well 260 (optionally including one or more semiconductor structures in N-well 260) may also be a collector. The BJT has a base resistor 211 and a collector resistor 212. Base resistor 211 may be adjusted by doping of P-well 130 or P-well 140 or spacing of the emitter. Collector resistor 212 may be adjusted by doping of layer 220 and a conduction path to the collector. Figure 3 Certain aspects of the performance characteristics of the IC device are described.

[0051] Figure 3 The voltage-current curve of an IC device with two terminals according to some embodiments of the present disclosure is illustrated. The IC device can be used for ESD protection. The IC device can be Figure 1 IC device 100 or Figure 2 An embodiment of the IC device 200 in FIG. Figure 3 The voltage-current curve in indicates the performance characteristics of the IC device. The voltage-current curve shows the breakdown voltage (BV), trigger voltage (Vt1), and holding voltage (Vh). These voltages can be adjusted using dopant adjustments and device architecture / design to meet the requirements of the parent circuit to avoid false triggering of the IC device during normal DC operation. In addition, the IC device will not turn on too late to prevent the victim device in the circuit from crashing.

[0052] During ESD operation, the N-well / P-well breaks down at a voltage, i.e., a breakdown voltage (BV), and an avalanche current flows. The breakdown voltage can be adjusted by spacing or doping of the P-well 140, the well 150, or the N-well 160. The emitter-base voltage can increase until the BJT trigger voltage, i.e., the trigger voltage (Vt1). The trigger voltage can be adjusted by a base resistor Rb, such as base resistor 211. The device then quickly returns to a low resistance mode and reaches a holding voltage (Vh), which can be independently adjusted by adjusting the gain of the base. The IC device can absorb sufficient peak current (It2). The collector resistor (Rc), such as collector resistor 212, can be adjusted by doping a deeper N-well and a conduction path to the collector. The IC can be self-sufficient and does not require an additional resistor on the base for faster triggering, or a ballast resistor on the collector to evenly conduct current to maintain a higher peak current (It2).

[0053] Figure 4 is a top view of an IC device 400 having two terminals according to some embodiments of the present disclosure. The IC device 400 may be Figure 1 IC device 100 or Figure 2 An embodiment of the IC device 200 in FIG. Figure 4 As shown, IC device 400 includes base region 401, emitter region 402, collector region 403, well 450, support structure 410, and deep N-well 420. In other embodiments, IC device 200 may include different, fewer, or more components.

[0054] The support structure 410 may be a P-type substrate. Figure 1 The deep N well 420 is above the support structure 410. The deep N well 420 may be Figure 1 The base region 401 , the emitter region 402 , and the collector region 403 are above the deep N well 120 .

[0055] The base region 401 includes a well 430, a semiconductor structure 435 (individually referred to as "semiconductor structure 435"), and two gates 490 (individually referred to as "gate 490"). The well 430 may be above a portion of the deep N-well 420. In some embodiments, the well 430 may surround at least a portion of each semiconductor structure 435. The well 430 may include one or more doped semiconductor materials. In some embodiments, the well 430 is a P-well. The semiconductor structure 435 may be a structure formed by epitaxy. The semiconductor structure 435 may include one or more P-type doped semiconductor materials. In some embodiments, the dopant concentration in the semiconductor structure 435 is higher than the dopant concentration in the well 430. The semiconductor structure 435 may be Figure 1 4. Each gate 490 intersects the semiconductor structure 435. The gate 490 can be a floating gate. In some embodiments, the gate 490 is not coupled to a power plane or a ground plane.

[0056] The emitter region 402 includes a well 440, a semiconductor structure 445 (individually referred to as "semiconductor structure 445"), and two gates 490 (individually referred to as "gate 490"). The well 440 may be above a portion of the deep N-well 420. In some embodiments, the well 440 may surround at least a portion of each semiconductor structure 445. The well 440 may include one or more doped semiconductor materials. In some embodiments, the well 440 is a P-well. The semiconductor structure 445 may be a structure formed by epitaxy. The semiconductor structure 445 may include one or more N-type doped semiconductor materials. The semiconductor structure 445 may be Figure 1 4. Each gate 490 intersects the semiconductor structure 445. The gate 490 can be a floating gate. In some embodiments, the gate 490 is not coupled to any power plane or ground plane.

[0057] The collector region 403 includes a well 460, a semiconductor structure 465 (individually referred to as "semiconductor structure 465"), and two gates 490 (individually referred to as "gate 490"). The well 460 may be above a portion of the deep N-well 420. In some embodiments, the well 460 may surround at least a portion of each semiconductor structure 465. The well 460 may include one or more doped semiconductor materials. In some embodiments, the well 460 is an N-well. The semiconductor structure 465 may be a structure formed by epitaxy. The semiconductor structure 465 may include one or more N-type doped semiconductor materials. In some embodiments, the dopant concentration in the semiconductor structure 465 is higher than the dopant concentration in the well 460. The semiconductor structure 465 may be Figure 1 4. Each gate 490 intersects the semiconductor structure 465. The gate 490 can be a floating gate. In some embodiments, the gate 490 is not coupled to any power plane or ground plane.

[0058] Well 450 is between emitter region 402 and collector region 403. Well 450 may separate well 440 from well 460, for example in embodiments where well 440 and well 460 have opposite doping types. Well 450 may be over a portion of deep N well 420.

[0059] The spacing or doping / energy of the wells in the IC device 400 can affect the performance of the IC device 400 for ESD protection. For example, the doping / energy of the well 430 and the spacing 411 (indicated by the dashed arrow) between the edge of the well 430 and the edge of the semiconductor structure 435 can be related to the trigger voltage (Vt1) of the IC device 400. In addition, the spacing 412 (indicated by the dashed arrow) between the edge of the well 440 and the edge of the semiconductor structure 445 can be related to the ratio of the holding voltage (Vh) to the trigger voltage (Vt1) of the IC device 400. The doping / energy of the well 440 or the width 413 of the well 440 can be related to the trigger voltage (Vt1) and the holding voltage (Vh). The width 414 of the well 450 along the Y axis can be related to the breakdown voltage (BV) of the IC device 400. The width 415 of the well 460 along the Y axis can be related to the ratio of the resistance (Ron) to the peak current (It2) of the IC device 400. Therefore, by adjusting the spacing or doping / energy of the wells, the ESD protection performance of IC device 400 can be optimized. Spacing 411 can be in the range of from about 300 nm to about 900 nm. Spacing 412 or width 414 can be in the range of from about 100 nm to about 350 nm.

[0060] Figures 5A-5I A process for forming a two-terminal IC device 500 according to some embodiments of the present disclosure is described. Fig.5I The IC device 500 is shown in FIG. The IC device 500 may be Figure 1 The IC device 100, Figure 2 IC device 200 or Figure 4 In some embodiments, Figures 5A-5I Each of the diagrams may represent a step in a process of forming IC device 500. In other embodiments, the diagrams may represent more than one step or a portion of a step in a process. Figures 5A-5I The sequence of FIG. 1 may not represent the order in which the components of IC device 500 are formed. For example, a component shown in a figure may be formed before a component shown in a previous figure. Figures 5A-5I This process is described, but other processes for forming a two-terminal IC device may be used instead. For example, in combination with Figures 5A-5I Some of the steps described may be changed, eliminated, or combined.

[0061] exist Figure 5AIn the embodiment, a support structure 501 is provided. The support structure 501 can be a semiconductor substrate composed of a semiconductor material system. In some embodiments, the support structure 501 can be a P-type substrate. In some embodiments, the semiconductor substrate can be a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure. In other embodiments, an alternative material can be used to form the semiconductor substrate, which can be combined with silicon or not combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-V, II-VI, or IV materials. In some embodiments, the substrate can be amorphous. An electrical insulator 515 is also provided. The electrical insulator 515 can be at least partially surrounded by the support structure 501.

[0062] exist Figure 5B In the embodiment, a deep N well 520 is formed in the support structure 501. The deep N well 520 may be formed by diffusing or implanting an N-type dopant into a region (eg, a region between the region 502 and the region 510) in the support structure 501. The region 510 may be Figure 1 The supporting structure 110, Figure 2 The support structure 210 or Figure 4 An embodiment of the support structure 410 in FIG.

[0063] exist Figure 5C In the embodiment, a P-well 504 is formed by doping a portion of the region 502, that is, the region 502 excluding the region 503. The P-well 504 may be doped by diffusing or implanting a P-type dopant into a portion of the region 502. Figure 5D 504 and 530. In some embodiments, the dopant concentration in P-well 540 may be approximately 2.5 to 6 times the dopant concentration in P-well 504 or 530. The dopant concentration in P-well 530 may be the same or substantially similar to the dopant concentration in P-well 504. P-well 530 may be an embodiment of P-well 130, 230, or 430. P-well 540 may be an embodiment of P-well 140, 240, or 440. The doping used to form P-well 504 and P-well 540 may be adjusted to optimize the performance of IC device 500 for ESD protection.

[0064] exist Figure 5E 5, a well 550 is formed by doping a portion of the region 503, that is, the region 503 excluding the region 505. The well 550 can adjust the breakdown voltage of the IC device 500. The doping can be N-type doping or P-type doping. The well 550 can be an embodiment of the well 150, 250, or 450.

[0065] exist Fig. 5F 540, an N-well 560 is formed by doping region 505. N-well 560 may be formed by diffusing or implanting an N-type dopant into N-well 560. The dopant concentration in N-well 560 may be substantially the same as the dopant concentration in P-well 540, but higher than the dopant concentration in well 550. In some embodiments, the dopant concentration in N-well 560 may be at least twice the dopant concentration in well 550.

[0066] exist Figure 5G , semiconductor structures 535, 545, and 565 are formed. In some embodiments, semiconductor structure 535 is at least partially inside P-well 530. Semiconductor structure 535 may be a P-type semiconductor structure. Semiconductor structure 535 may be formed by an epitaxial deposition process, which may be followed by a P-type doping process. Semiconductor structure 535 may include a P-type dopant, such as boron or other P-type dopants. Semiconductor structure 535 may be Figure 1 The semiconductor structure 135 or Figure 4 An embodiment of the semiconductor structure 435 in FIG.

[0067] The semiconductor structure 545 is at least partially inside the P-well 540. The semiconductor structure 545 may be an N-type semiconductor structure. The semiconductor structure 545 may be formed by an epitaxial deposition process, which may be followed by an N-type doping process. The semiconductor structure 545 may be Figure 1 The semiconductor structure 145 or Figure 4 An embodiment of the semiconductor structure 445 in FIG.

[0068] The semiconductor structure 565 is at least partially inside the N-well 560. The semiconductor structure 565 may be an N-type semiconductor structure. The semiconductor structure 565 may be formed by an epitaxial deposition process, which may be followed by an N-type doping process. The semiconductor structure 565 may be Figure 1 The semiconductor structure 165 or Figure 4 4. The semiconductor structure 545 or 565 may include an N-type dopant, such as arsenic, phosphorus, or other N-type dopant. The dopant concentration of the semiconductor structure 535, 545, or 565 may be in the range of approximately 1×10 21 atoms / cm 3 To approximately 1×10 22 atoms / cm 3 The dopant concentration of N well 560 may be in the range of approximately 1.5×10 18 atoms / cm 3 to approximately 3.5×10 18 atoms / cm 3 within the range.

[0069] exist Figure 5H In the embodiment of the present invention, a gate 590 (referred to individually as "gate 590") is formed. A portion of gate 590 is in well or electrical insulator 515. Gate 590 may include metal, polysilicon, or other types of conductive materials. Figure 5H Six gates 590 are shown, but a different number of gates 590 may be formed. In addition, the positions of the gates 590 may be different from their positions in FIG. Figure 5H The gate 590 may be floating. In some embodiments, the gate 590 may not affect the performance of the IC device 500 for ESD protection.

[0070] exist Fig.5I , two conductive structures 570 and 580 are formed. Conductive structure 570 is connected to semiconductor structure 535 and semiconductor structure 545 so that the P+ base and the N+ epitaxial portion of the emitter are shorted together. In some embodiments, conductive structure 570 is grounded. For example, the conductive structure is coupled to VSS. Conductive structure 580 is connected to semiconductor structure 565. In some embodiments, conductive structure 580 is coupled to a power plane so that the N+ epitaxial portion of the collector is connected to power.

[0071] Figure 6A-6B 2 is a top view of wafer 2000 and die 2002, which may facilitate one or more two-terminal IC devices for ESD protection according to some embodiments of the present disclosure. In some embodiments, die 2002 may be included in an IC package according to some embodiments of the present disclosure. For example, any die 2002 may be used as Figure 7Any die 2256 in the IC package 2200 shown. Wafer 2000 can be composed of semiconductor materials and can include one or more die 2002 having IC devices formed on the surface of wafer 2000. Each die 2002 can be a repeating unit of a semiconductor product including any suitable IC (e.g., an IC including two terminals as described herein). After the fabrication of the semiconductor product is completed (e.g., after the fabrication of a two-terminal IC device as described herein), wafer 2000 can undergo a singulation process, in which the individual dies 2002 are separated from each other to provide discrete "chips" of the semiconductor product. In particular, the two-terminal IC devices as disclosed herein can take the form of wafer 2000 (e.g., not singulated) or the form of die 2002 (e.g., singulated). Die 2002 can include one or more diodes, one or more transistors, and optionally supporting circuitry to route electrical signals to III-N diodes, III-N transistors, and any other IC components with N-doped wells and capping layers. In some embodiments, wafer 2000 or die 2002 may implement an ESD protection device, an RF front-end device, a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple of these devices may be combined on a single die 2002.

[0072] Figure 7 is a side cross-sectional view of an example IC package 2200 that may include one or more two-terminal IC devices for ESD protection according to some embodiments of the present disclosure. In some embodiments, IC package 2200 may be a system in package (SiP).

[0073] like Figure 7 As shown, IC package 2200 may include package substrate 2252. Package substrate 2252 may be formed of a dielectric material (e.g., ceramic, glass, a combination of organic and inorganic materials, a built-up film, an epoxy film with filler particles therein, etc., and may have embedded portions with different materials), and may have conductive pathways extending through the dielectric material between face 2272 and face 2274, or between different locations on face 2272, and / or between different locations on face 2274.

[0074] The packaging substrate 2252 may include conductive contacts 2263, which are coupled to the conductive paths 2264 through the packaging substrate 2252, thereby allowing the circuit system within the die 2256 and / or the insert 2257 to be electrically coupled to various conductive contacts in the conductive contacts 2264 (or to other devices included in the packaging substrate 2252, not shown).

[0075] The IC package 2200 may include an interposer 2257 coupled to a package substrate 225 via conductive contacts 2261 of the interposer 2257 , first level interconnects 2265 , and conductive contacts 2263 of the package substrate 2252 . Figure 7 The first level interconnect 2265 illustrated in FIG. 2 is a solder bump, but any suitable first level interconnect 2265 may be used. In some embodiments, interposer 2257 may not be included in IC package 2200; instead, die 2256 may be directly coupled to conductive contact 2263 at face 2272 via first level interconnect 2265.

[0076] IC package 2200 may include one or more dies 2256 coupled to interposer 2257 via conductive contacts 2254 of die 2256, first level interconnects 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled to conductive pathways (not shown) through interposer 2257, thereby allowing circuitry within die 2256 to be electrically coupled to various conductive contacts in conductive contacts 2261 (or to other devices included in interposer 2257, not shown). Figure 7 The first level interconnect 2258 illustrated in the figure is a solder bump, but any suitable first level interconnect 2258 may be used. As used herein, a "conductive contact" may refer to a portion of an electrical material (e.g., a metal) that serves as an interface between different components; a conductive contact may be recessed in a surface of a component, flush with a surface of a component, or extend away from a surface of a component, and may take any suitable form (e.g., a conductive pad or a socket).

[0077] In some embodiments, an underfill material 2266 can be disposed around the first level interconnect 2265 between the package substrate 2252 and the interposer 2257, and a mold compound 2268 can be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 can be the same as the mold compound 2268. An example material that can be used for the underfill material 2266 and the mold compound 2268 is an epoxy molding material, as appropriate. The second level interconnect 2270 can be coupled to the conductive contact 2264. Figure 7 The second level interconnect 2270 illustrated in FIG. 2 is a solder ball (e.g., for a ball grid array arrangement), but any suitable second level interconnect 2270 may be used (e.g., a pin in a land grid array arrangement or a land in a land grid array arrangement). The second level interconnect 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference to Figure 8 discussed.

[0078] The die 2256 may take the form of any embodiment of the die 2002 discussed herein, and may facilitate any embodiment of a two-terminal IC device. In embodiments where the IC package 2200 includes multiple die 2256, the IC package 2200 may be referred to as a multi-chip package. Importantly, even in such embodiments of an MCP implementation of the IC package 2200, one or more two-terminal IC devices may be provided in a single chip in accordance with any embodiment described herein. The die 2256 may include circuitry for performing any desired function. For example, one or more of the die 2256 may be an ESD protection die including one or more two-terminal IC devices described herein, one or more of the die 2256 may be a logic die (e.g., a silicon-based die), one or more of the die 2256 may be a memory die (e.g., a high-bandwidth memory), etc. In some embodiments, any of the die 2256 may include one or more two-terminal IC devices, for example, as discussed above; in some embodiments, at least some of the die 2256 may not include any III-N diodes with an N-doped well and cap layer.

[0079] Figure 7 The IC package 2200 illustrated in the figure may be a flip chip package, however other package architectures may be used. For example, the IC package 2200 may be a ball grid array (BGA) package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although in Figure 7 Two dies 2256 are illustrated in the IC package 2200 of FIG. 2 , but the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors, disposed on the first side 2272 or the second side 2274 of the package substrate 2252, or disposed on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0080] Figure 8is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more two-terminal IC devices for ESD protection according to some embodiments of the present disclosure. IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (e.g., which may be a motherboard). IC device assembly 2300 includes components disposed on a first side 2340 of circuit board 2302 and an opposing second side 2342 of circuit board 2302; typically, the components may be disposed on one or both of sides 2340 and 2342. In particular, any suitable component of the components of IC device assembly 2300 may include any of the IC devices having two terminals according to any embodiments disclosed herein; for example, any of the IC packages discussed below with reference to IC device assembly 2300 may take the form described above with reference to FIG. Figure 7 Any of the embodiments of IC package 2200 discussed (eg, may include one or more two-terminal IC devices in / on die 2256 ).

[0081] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally in conjunction with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB substrate.

[0082] Figure 8 The IC device assembly 2300 illustrated in FIG. 2 includes a package-on-interposer structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling component 2316. The coupling component 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and can include solder balls (e.g., Figure 8 as shown), male and female portions of a socket, adhesive, bottom fill material and / or any other suitable electrical and / or mechanical coupling structure.

[0083] The package-on-interposer structure 2336 may include an IC package 2320 coupled to the interposer 2304 via a coupling component 2318. The coupling component 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 2316. The IC package 2320 may be or include, for example, a die ( Figure 6B 2002), IC devices (e.g., Figure 1-2 IC device) or any other suitable component. In particular, IC package 2320 may include one or more two-terminal IC devices as described herein. Figure 8A single IC package 2320 is shown in FIG, but multiple IC packages can be coupled to interposer 2304; indeed, additional interposers can be coupled to interposer 2304. Interposer 2304 can provide an intermediate substrate for bridging circuit board 2302 and IC package 2320. Typically, interposer 2304 can extend connections to a wider spacing, or reroute connections to different connections. For example, interposer 2304 can couple IC package 2320 (e.g., a die) to a BGA of coupling component 2316 for coupling to circuit board 2302. Figure 8 In the illustrated embodiment, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304; in other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0084] The insert 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or a polymer material such as polyimide. In some embodiments, the insert 2304 may be formed of an alternative rigid or flexible material, which may include the same materials as those used for the semiconductor substrate described above, such as silicon, germanium, and other III-V and IV materials. The insert 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSV 2306. The insert 2304 may also include embedded devices 2314, including passive and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD protection devices, and memory devices. More complex devices, such as other RF (radio frequency) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the insert 2304. In some embodiments, an IC device with two terminals as described herein may also be implemented in / on the insert 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.

[0085] IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0086] Figure 8The illustrated IC device assembly 2300 includes a package-on-package structure 2334 coupled to the second side 2342 of the circuit board 2302 via a coupling component 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together via a coupling component 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any of the embodiments of the coupling components 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any of the embodiments of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0087] Fig. 9 2400 may include one or more components having one or more two-terminal IC devices according to some embodiments of the present disclosure. For example, according to some embodiments of the present disclosure, any suitable component among the components of computing device 2400 may include a die including one or more two-terminal IC devices (e.g., Figure 6B Any component of computing device 2400 may include one or more two-terminal IC devices (e.g., the above combined Figure 1-4 and 5A-5I) and / or IC packages (e.g., Figure 7 Any component of computing device 2400 may include an IC device component (e.g., Figure 8 IC device component 2300).

[0088] Fig. 9 A number of components included in computing device 2400 are illustrated, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC (system on chip) die.

[0089] In addition, in various embodiments, the computing device 2400 may not include Fig. 92400, but the computing device 2400 may include interface circuitry for coupling to one or more of the components. For example, the computing device 2400 may not include the display device 2406, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include the audio input device 2418 or the audio output device 2408, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which the audio input device 2408 or the audio output device 2408 may be coupled.

[0090] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include, for example, eDRAM and / or spin transfer torque magnetic random access memory (STT-MRAM).

[0091] In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communications for transmitting data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0092] The communication chip 2412 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment)), Long Term Evolution (LTE) project and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the conformance and interoperability tests of the IEEE 802.16 standard. The communication chip 2412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication chip 2412 may operate according to other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0093] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 may include multiple communication chips. For example, the first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, while the second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 2412 may be dedicated to wireless communications, while the second communication chip 2412 may be dedicated to wired communications.

[0094] In various embodiments, an IC device with two terminals as described herein may be particularly advantageous for use as part of an ESD circuit to protect a power amplifier, a low noise amplifier, a filter (including filter banks and arrays of filters), a switch, or other active components. In some embodiments, an IC device with two terminals as described herein may be used in a PMIC, for example as a rectifier diode for high current. In some embodiments, an IC device with two terminals as described herein may be used in an audio device and / or various input / output devices.

[0095] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).

[0096] Computing device 2400 may include display device 2406 (or corresponding interface circuitry as discussed above). Display device 2406 may include any visual indicator such as, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0097] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry as discussed above). Audio output device 2408 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earbuds.

[0098] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry as discussed above). The audio input device 2418 may include any device that generates a signal representative of sound, such as, for example, a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0099] Computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry as discussed above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0100] Computing device 2400 may include another output device 2410 (or corresponding interface circuitry as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0101] The computing device 2400 may include another input device 2420 (or corresponding interface circuitry as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0102] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0103] The following paragraphs provide various examples of the embodiments disclosed herein.

[0104] Example 1 provides an IC device, which includes: a layer including a first doped semiconductor material having a first doping type; a first region above the layer, the first region including a second doped material having a second doping type opposite to the first doping type; a second region above the layer, the second region including a third doped semiconductor material having the second doping type; a first structure including a fourth doped semiconductor material having the second doping type, the first structure being at least partially surrounded by the first region; a second structure including a fifth doped semiconductor material having the first doping type, the second structure being at least partially surrounded by the second region; and a conductive structure including a first portion above the first structure and a second portion above the second structure.

[0105] Example 2 provides an IC device according to Example 1, further including: a third region above the layer, the third region including a sixth doped semiconductor material having the first doping type; and a third structure including a seventh doped semiconductor material having the first doping type, the third structure being at least partially surrounded by the third region, wherein the second region is between the first region and the third region.

[0106] Example 3 provides the IC device of Example 2, further comprising: an additional conductive structure over the third structure, wherein the additional conductive structure is separated from the conductive structure by an electrical insulator.

[0107] Example 4 provides the IC device of Example 3, wherein the additional conductive structure is electrically coupled to a power plane, and the conductive structure is electrically coupled to a ground plane.

[0108] Example 5 provides an IC device according to any of the preceding examples, wherein a dopant concentration in the second region is at least 2.5 times higher than a dopant concentration in the first region.

[0109] Example 6 provides an IC device according to any of the preceding examples, wherein the first region or the second region is above the layer in a first direction, and a size of the first region in a second direction perpendicular to the first direction is larger than a size of the second region in the second direction.

[0110] Example 7 provides an IC device according to any of the preceding examples, further comprising: a third region above the layer, the third region comprising a sixth doped semiconductor material having the first doping type, wherein the dopant concentration in the third region is not greater than half the dopant concentration in the second region, and the second region is between the first region and the third region.

[0111] Example 8 provides an IC device, which includes: a base segment, including a first P-well and a P-type semiconductor structure; an emitter segment, including a second P-well and a first N-type semiconductor structure; a collector segment, including an N-well and a second N-type semiconductor structure; an N-well above at least one of the base segment, the emitter segment, and the collector segment; a first contact portion, electrically coupled to the P-type semiconductor structure and the first N-type semiconductor structure; and a second contact portion, electrically coupled to the second N-type semiconductor structure.

[0112] Example 9 provides an IC device according to Example 8, wherein a distance from an edge of the P-type semiconductor structure to an edge of the first P-well in a direction is greater than a distance from an edge of the first N-type semiconductor structure to an edge of the second P-well.

[0113] Example 10 provides the IC device according to Example 8 or 9, further comprising: a P-doped substrate above the N-well, wherein the N-well is between at least one of the base segment, the emitter segment, and the collector segment and the P-doped substrate.

[0114] Example 11 provides the IC device of any of Examples 8-10, wherein the base region further includes a gate, and at least a portion of the gate is above the P-type semiconductor structure.

[0115] Example 12 provides the IC device of any of Examples 8-11, wherein the P-type semiconductor structure, the first N-type semiconductor structure, or the second N-type semiconductor structure comprises a fin or a nanoribbon.

[0116] Example 13 provides the IC device of any of Examples 8-12, further comprising: an electrical insulator between the first P-well and the second P-well.

[0117] Example 14 provides the IC device of any of Examples 8-13, wherein a dopant concentration in the first P-well is lower than a dopant concentration in the second P-well or the N-well.

[0118] Example 15 provides a method for forming an IC device, comprising: forming an N-well in a substrate, the N-well being between a first portion of the substrate and a second portion of the substrate in a first direction; forming a first P-well in the first portion of the substrate by doping a first portion of the first portion of the substrate; forming a second P-well in the first portion of the substrate by doping a second portion of the first portion of the substrate; forming an N-well in the first portion of the substrate by doping a third portion of the first portion of the substrate, wherein the second portion is between the first portion and the third portion in a second direction perpendicular to the first direction; forming a first semiconductor structure in the first P-well; forming a second semiconductor structure in the second P-well; and forming a third semiconductor structure in the N-well.

[0119] Example 16 provides the method according to Example 15, further comprising: forming a conductive structure, a first portion of the conductive structure being above the first semiconductor structure, and a second portion of the conductive structure being above the second semiconductor structure.

[0120] Example 17 provides the method according to Example 15 or 16, further comprising: forming a conductive structure over the third semiconductor structure.

[0121] Example 18 provides a method according to any one of Examples 15-17, further comprising: forming a well in the first portion of the substrate by doping a fourth portion of the first portion of the substrate, wherein the fourth portion is between the second portion and the third portion in the second direction.

[0122] Example 19 provides the method according to Example 18, wherein forming the well includes: forming the N well after forming the well.

[0123] Example 20 provides the method according to any one of Examples 15-19, further comprising: after forming the N-well, forming a gate over the first semiconductor structure, the second semiconductor structure, or the third semiconductor structure in the second direction.

[0124] Example 21 provides an IC package, comprising an IC device according to any of Examples 1-14; and another IC component coupled to the device.

[0125] Example 22 provides the IC package of Example 21, wherein the another IC component includes one of a package substrate, an interposer, or another IC die.

[0126] Example 23 provides an IC package according to Example 21 or 22, wherein the IC device according to any of Examples 1-14 may include at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communication device, or a portion thereof.

[0127] Example 24 provides an electronic device, comprising: a carrier substrate; and one or more of the IC device according to any of Examples 1-14 and the IC package according to any of Examples 21-23, coupled to the carrier substrate.

[0128] Example 25 provides the electronic device of Example 24, wherein the carrier substrate is a motherboard.

[0129] Example 26 provides the electronic device of Example 24, wherein the carrier substrate is a PCB.

[0130] Example 27 provides an electronic device according to any one of Examples 24-26, wherein the electronic device is a wearable electronic device or a handheld electronic device.

[0131] Example 28 provides an electronic device according to any one of Examples 24-27, wherein the electronic device further includes an antenna and one or more communication chips.

[0132] Example 29 provides the electronic device of any of Examples 24-28, wherein the electronic device is an RF transceiver.

[0133] Example 30 provides an electronic device according to any of Examples 24-28, wherein the electronic device is one of a switch, a power amplifier, a low noise amplifier, a filter, a filter bank, a duplexer, an upconverter or a downconverter of an RF communication device (e.g., an RF transceiver).

[0134] Example 31 provides an electronic device according to any of Examples 24-30, wherein the electronic device is a computing device.

[0135] Example 32 provides an electronic device according to any of Examples 24-31, wherein the electronic device is included in a base station of a wireless communication system.

[0136] Example 33 provides an electronic device according to any one of Examples 24-31, wherein the electronic device is included in a user equipment device of a wireless communication system.

[0137] Example 34 provides the method according to any of Examples 15-20, further comprising a process for forming the IC device according to any of Claims 1-14.

[0138] Example 35 provides the method of any of Examples 15-20, further comprising a process for forming an IC package of any of Claims 21-23.

[0139] Example 36 provides the method according to any of Examples 15-20, further comprising a process for forming an electronic device according to any of Claims 24-33.

[0140] The above description of the embodiments of the disclosure, including the contents described in the abstract, is not intended to be exhaustive or limit the disclosure to the precise form disclosed. Although specific embodiments and examples of the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure as will be appreciated by those skilled in the relevant art. These modifications may be made to the disclosure in accordance with the above detailed description.

Claims

1. An integrated circuit (IC) device comprising: a layer comprising a first doped semiconductor material having a first doping type; a first region above the layer, the first region comprising a second doping material having a second doping type opposite to the first doping type; a second region above the layer, the second region comprising a third doped semiconductor material having the second doping type; a first structure comprising a fourth doped semiconductor material having the second doping type, the first structure being at least partially surrounded by the first region; a second structure comprising a fifth doped semiconductor material having the first doping type, the second structure being at least partially surrounded by the second region; as well as A conductive structure includes a first portion over the first structure and a second portion over the second structure.

2. The IC device according to claim 1, further comprising: a third region above the layer, the third region comprising a sixth doped semiconductor material having the first doping type, The second area is between the first area and the third area.

3. The IC device according to claim 2, further comprising: A third structure includes a seventh doped semiconductor material having the first doping type, wherein the third structure is at least partially surrounded by the third region.

4. The IC device according to claim 2 or 3, further comprising: an additional conductive structure on top of the third structure, Wherein, the additional conductive structure is separated from the conductive structure by an electrical insulator.

5. The IC device according to claim 4, wherein: The additional conductive structure is electrically coupled to the power plane.

6. The IC device according to claim 5, wherein: The conductive structure is electrically coupled to a ground plane.

7. The IC device according to any one of claims 1 to 3, wherein: The dopant concentration in the second region is at least 2.5 times higher than the dopant concentration in the first region.

8. The IC device according to any one of claims 1 to 3, wherein: The first region or the second region is above the layer in a first direction, and a size of the first region in a second direction perpendicular to the first direction is larger than a size of the second region in the second direction.

9. The IC device according to any one of claims 1 to 3, further comprising: a third region above the layer, the third region comprising a sixth doped semiconductor material having the first doping type, The dopant concentration in the third region is not greater than half of the dopant concentration in the second region, and the second region is between the first region and the third region.

10. An integrated circuit (IC) device comprising: A base section including a first P-well and a P-type semiconductor structure; An emitter section including a second P-well and a first N-type semiconductor structure; A collector section including an N-well and a second N-type semiconductor structure; an N-well over at least one of the base section, the emitter section, and the collector section; a first contact portion electrically coupled to the P-type semiconductor structure and the first N-type semiconductor structure; as well as The second contact portion is electrically coupled to the second N-type semiconductor structure.

11. The IC device according to claim 10, wherein: In one direction, a distance from an edge of the P-type semiconductor structure to an edge of the first P-well is greater than a distance from an edge of the first N-type semiconductor structure to an edge of the second P-well.

12. The IC device according to claim 10 or 11, further comprising: A P-doped substrate above the N-well, The N-well is between at least one of the base section, the emitter section and the collector section and the P-doped substrate.

13. The IC device according to claim 10 or 11, wherein: The base region further includes a gate, and at least a portion of the gate is above the P-type semiconductor structure.

14. The IC device according to claim 10 or 11, wherein: The P-type semiconductor structure includes a fin or a nanoribbon.

15. The IC device according to claim 10 or 11, wherein: The first N-type semiconductor structure includes a fin or a nanoribbon.

16. The IC device according to claim 10 or 11, wherein: The second N-type semiconductor structure includes a fin or a nanoribbon.

17. The IC device of claim 10, further comprising: An electrical insulator between the first P-well and the second P-well.

18. The IC device according to claim 10 or 11, wherein: The dopant concentration in the first P-well is lower than the dopant concentration in the second P-well or the N-well.

19. A method for forming an integrated circuit (IC) device, comprising: forming an N-well in a substrate, the N-well being between a first portion of the substrate and a second portion of the substrate in a first direction; forming a first P-well in the first portion of the substrate by doping a first portion of the first portion of the substrate; forming a second P-well in the first portion of the substrate by doping a second portion of the first portion of the substrate; forming an N well in the first portion of the substrate by doping a third portion of the first portion of the substrate, wherein the second portion is between the first portion and the third portion in a second direction perpendicular to the first direction; forming a first semiconductor structure in the first P-well; forming a second semiconductor structure in the second P-well; and A third semiconductor structure is formed in the N-well.

20. The method according to claim 19, further comprising: A conductive structure is formed, wherein a first portion of the conductive structure is above the first semiconductor structure.

21. The method according to claim 20, wherein: The second portion of the conductive structure is over the second semiconductor structure.

22. The method according to any one of claims 19 to 21, further comprising: A conductive structure is formed on the third semiconductor structure.

23. The method according to any one of claims 19 to 21, further comprising: A well is formed in the first portion of the substrate by doping a fourth portion of the first portion of the substrate, wherein the fourth portion is between the second portion and the third portion in the second direction.

24. The method according to claim 23, wherein: Forming the well includes: The well is formed before forming the N well.

25. The method according to any one of claims 19 to 21, further comprising: After forming the N well, a gate is formed on the first semiconductor structure, the second semiconductor structure, or the third semiconductor structure in the second direction.

Images