Trench gate IGBT structure and semiconductor device

Abstract

The present invention provides a trench gate IGBT structure and a semiconductor device, wherein the trench gate IGBT structure comprises: a first trench gate extending from the substrate surface to the N-drift region; a first P-type doped region, the P-type base region and the N-drift region each arranged on one side of the first trench gate, wherein a plug is arranged in the first P-type doped region for grounding; a second trench gate arranged in the first P-type doped region, electrically connected to the first trench gate, and the length of the second trench gate is less than the length of the first trench gate; an N-type floating buried layer arranged in the first P-type doped region below the second trench gate, wherein one end of the N-type floating buried layer is spaced apart from the first trench gate. The present invention can simultaneously optimize the on-state voltage drop and off-state loss of the trench gate IGBT structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench gate IGBT structure and a semiconductor device. Background Art

[0002] IGBT devices are a representative type of three-terminal devices in power semiconductor devices, including gate, emitter and collector. They establish a bipolar current conduction mechanism and a MOSFET gate current control mechanism in the same semiconductor region. When the IGBT device is turned on, the emitter emits electrons and the collector emits holes, where electrons and holes participate in the conductance regulation; when the IGBT device is turned off, electrons can be quickly withdrawn from the channel, while holes can only disappear by recombination, and the speed is relatively slow (tailing phenomenon).

[0003] In order to pursue the optimal IGBT device characteristics, reduce the power loss of IGBT devices, and expand their safe operating area, the technical development route of IGBT devices is, for example: its gate structure gradually develops from a planar gate structure to a trench gate structure; its vertical structure gradually develops from a punch-through type to a non-punch-through type, and then to a field-stop type.

[0004] However, these technologies have limited improvements on devices or are just a compromise method that sacrifices one thing for another, and it is difficult to take both into account. Take Vcesat (on-state voltage drop) and switching loss as an example. There is an obvious seesaw relationship between the two, and the compromise relationship between Vcesat and switching loss is difficult to balance. Summary of the invention

[0005] The object of the present invention is to provide a trench gate IGBT structure and a semiconductor device, which are used to simultaneously optimize the on-state voltage drop and the off-state loss of the trench gate IGBT structure.

[0006] In order to solve the above technical problems, the present invention provides a trench gate IGBT structure, comprising a substrate and a P+ collector region, an N-drift region, a P-type base region and an N+ emitter region arranged in the substrate and arranged in sequence from bottom to top;

[0007] A first trench gate extending from the substrate surface into the N-drift region;

[0008] A first P-type doping region, the P-type base region and an N-drift region each disposed on one side of the first trench gate, wherein a plug is disposed in the first P-type doping region for grounding;

[0009] a second trench gate, disposed in the first P-type doping region and electrically connected to the first trench gate, wherein the length of the second trench gate is smaller than the length of the first trench gate;

[0010] An N-type floating buried layer is disposed in the first P-type doped region below the second trench gate, and one end of the N-type floating buried layer is spaced apart from the first trench gate.

[0011] Optionally, both the first trench gate and the second trench gate extend downward from the substrate surface, and the length of the second trench gate is 1 / 3 to 2 / 3 of the length of the first trench gate.

[0012] Optionally, the first P-type doped region extends downward from the substrate surface, the depth of the first P-type doped region is 0.5~1.1 of the length of the first trench gate, and the depth of the first P-type doped region is greater than the depth of the N-type floating buried layer.

[0013] Optionally, the first P-type doped region, the second trench gate and the N-type floating buried layer constitute a P-channel depletion-type transistor structure, and the first P-type doped region between the N-type floating buried layer and the first trench gate serves as a channel region of the P-channel depletion-type transistor structure.

[0014] Optionally, the plug is disposed in a first P-type doping region on a side of the second trench gate away from the channel region, and a depth of the plug is less than a depth of the second trench gate.

[0015] Optionally, the other end of the N-type floating buried layer away from the channel region extends to separate the plug from the first P-type doped region under the N-type floating buried layer.

[0016] Optionally, a second P-type doping region is respectively provided in the N-drift region below the first trench gate and the second trench gate, the doping concentration of the second P-type doping region is greater than the doping concentration of the first P-type doping region, the two second P-type doping regions have the same doping concentration and junction depth, and one of the second P-type doping regions is close to the bottom of the first trench gate.

[0017] Optionally, an N-type buffer layer or an N-type field stop layer is further provided between the P+ collector region and the N-drift region.

[0018] Based on another aspect of the present invention, a semiconductor device is also provided, including a plurality of cells, wherein the cells include two first trench gates, wherein an N-drift region, a P-type base region and an N+ emitter region are sequentially arranged in the substrate outside the two first trench gates from bottom to top, and a first P-type doped region, an N-type floating buried layer and a second trench gate are arranged in the substrate inside the two first trench gates from bottom to top, wherein the first trench gate and the second trench gate are electrically connected, wherein a first end of the N-type floating buried layer is spaced apart from one of the first trench gates, and a second end of the N-type floating buried layer is connected to a side wall of another first trench gate, and a plug is arranged in the first P-type doped region above the second end of the N-type floating buried layer for grounding.

[0019] Based on another aspect of the present invention, a semiconductor device is also provided, including a plurality of cells, wherein the cells include two first trench gates, wherein an N-drift region, a P-type base region and an N+ emitter region are sequentially arranged in the substrate outside the two first trench gates from bottom to top, and a first P-type doped region, an N-type floating buried layer and two second trench gates are arranged in the substrate inside the two first trench gates from bottom to top, wherein the first trench gate and the second trench gate are electrically connected, and the two ends of the N-type floating buried layer are respectively spaced apart from the side walls of the two first trench gates, and a plug is provided in the first P-type doped region between the two second trench gates for grounding.

[0020] In summary, the trench gate IGBT structure of the present invention includes a substrate and a P+ collector region, an N-drift region, a P-type base region, an N+ emitter region, a first trench gate, a first P-type doped region, a second trench gate, an N-type floating buried layer and a plug arranged in the substrate. The first trench gate extends from the surface of the substrate to the N-drift region; the first P-type doped region, the P-type base region and the N-drift region each arranged on one side of the first trench gate, and a plug is arranged in the first P-type doped region for grounding; the second trench gate is arranged in the first P-type doped region, electrically connected to the first trench gate, and the length of the second trench gate is less than the length of the first trench gate; the N-type floating buried layer is arranged in the first P-type doped region below the second trench gate, one end of the N-type floating buried layer is arranged at a distance from the first trench gate, and the doping concentration of the N-type floating buried layer is greater than the doping concentration of the first P-type doped region. In the present invention, the first P-type doping region, the second trench gate and the N-type floating buried layer constitute a P-channel depletion transistor structure, wherein the second trench gate serves as the control end of the P-channel depletion transistor structure, is electrically connected to the first trench gate and is always at the same potential, the first P-type doping region between the N-type floating buried layer and the first trench gate serves as a channel, the first P-type doping regions on the upper and lower sides of the N-type floating buried layer serve as the two ends of the P-channel depletion transistor structure, and the plug connects one end of the first P-type doping region above the N-type floating buried layer (i.e., the upper end of the P-channel depletion transistor structure) and is grounded. When the IGBT structure is in the forward conduction stage, the second trench gate is in an inversion state, so that the channel of the P-channel depletion transistor structure is pinched off, and the holes in the first P-type doping region flow and accumulate toward the region away from the N-type floating buried layer, that is, the holes discharged by the second trench gate accumulate toward the bottom of the P-type base region, thereby increasing the conductivity modulation effect and reducing Vcesat (on-state voltage drop), which is used to reduce the power loss during conduction. Moreover, compared with two parallel long trench gates (similar to two parallel first trench gates), the second trench gate is similar to a small capacitor in parallel between the first trench gate and the P+ collector region when turned off (the depth of the second trench gate is relatively small), which can reduce the input capacitance, and thereby reduce the power loss and turn-on time when turned on. When the IGBT structure is in the off stage, the second trench gate makes the P-channel depletion-type transistor structure in a normally open state, and the holes accumulated in the P-type base region and its surroundings can be quickly transferred upward from the bottom of the first P-type doped region by the P-channel depletion-type transistor structure and quickly extracted using a plug, reducing the off-end current (tail current) and reducing the power loss and turn-off time when turned off. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0022] Figure 1 is a schematic structural diagram of a trench gate IGBT device used as a reference in the related art;

[0023] Figure 2 A schematic structural diagram of a trench gate IGBT structure provided by an embodiment of the present invention;

[0024] Figure 3a A schematic diagram of a trench gate IGBT structure when it is turned on according to an embodiment of the present invention;

[0025] Figure 3b A schematic diagram of a trench gate IGBT structure when turned off according to an embodiment of the present invention;

[0026] Figure 4a A schematic diagram of an IGBT cell provided by an embodiment of the present invention;

[0027] Figure 4b A schematic diagram of another IGBT cell provided according to an embodiment of the present invention.

[0028] Figure 1 Middle: 11'-P+ collector region; 12'-N-type buffer layer; 13'- N-drift region; 14'- P-type base region; 15'- N+ emitter region; 16'- trench gate.

[0029] Figures 2 to 4b In the figure: 10-substrate; 10a-front side; 10b-back side; 11-P+ collector region; 12-N-type buffer layer; 13-N-drift region; 14-P-type base region; 15-N+ emitter region; 16-first trench gate; 16a-first trench; 17-isolation dielectric layer; 21-first P-type doped region; 22-N-type floating buried layer; 22a-first end; 22b-second end; 23-second trench gate; 23a-second trench; 24-second P-type doped region; 25-channel region; 26-plug. DETAILED DESCRIPTION

[0030] As described in the background technology, Figure 1 Schematic diagram of the structure of a trench gate IGBT device in the related art. Figure 1As shown, the trench gate IGBT device includes a P+ collector region 11', an N-type buffer layer 12', an N-drift region 13', a P-type base region 14', an N+ emitter region 15' and a trench gate 16' arranged in sequence from bottom to top, and the trench gate 16' passes through the P-type base region 14' and extends into the N-drift region 13'. The trench gate IGBT device uses the above-mentioned trench gate 16' for switch control. When the trench gate IGBT device is turned on, holes enter from the P+ collector region 11' (electrons enter from the N+ emitter region 15') to participate in conductivity modulation. The more holes there are in the N-drift region 13', the more conducive it is to reduce Vcesat; when the trench gate IGBT device is turned off, holes are extracted from the N+ emitter region 15', and the extraction speed will affect the turn-off time and turn-off loss. Therefore, in the above-mentioned trench gate IGBT device, in order to reduce Vcesat, the hole concentration at turn-on needs to be increased, and in order to reduce the time for extracting holes at turn-off (and turn-off loss), the hole concentration at turn-on needs to be reduced. In other words, the Vcesat and turn-off loss of the above-mentioned trench gate IGBT device present a "seesaw" relationship, and the two can only be balanced by a compromise method of giving up one while losing the other, and it is difficult to optimize them at the same time.

[0031] To this end, the present invention provides a trench gate IGBT structure, and simultaneously optimizes the Vcesat and turn-off loss of the trench gate IGBT device to improve the performance of the trench gate IGBT device.

[0032] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0033] It should be understood that when an element or layer is referred to as "on...", "connected to" other elements or layers, it can be directly on other elements or layers, connected to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on...", "directly connected to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be expressed as a second element, component, region, layer or part. Spatial relationship terms such as "under...", "below", "below", "above...", "above", "above", etc., can be used here for the convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the devices in use and operation. For example, if the device in the accompanying drawings is turned over, then, the elements or features described as "under...", "below", "below" will be oriented to be "on" other elements or features. The device can be oriented in other ways (rotated 90 degrees or other orientations) and the spatial descriptors used here are interpreted accordingly. The purpose of the terms used here is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used here, the singular forms of "one", "one" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "including" is used to determine the existence of features, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, steps, operations, elements, parts and / or groups. When used here, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] An embodiment of the present invention provides a trench gate IGBT structure.

[0035] Figure 2 A schematic structural diagram of a trench gate IGBT structure provided in one embodiment of the present invention.

[0036] like Figure 2 As shown, the trench gate IGBT structure provided in this embodiment includes a substrate 10 and a P+ collector region 11, an N-drift region 13, a P-type base region 14, an N+ emitter region 15, a first trench gate 16, a first P-type doped region 21, a second trench gate 23, an N-type floating buried layer 22 and a plug 26 arranged in the substrate 10.

[0037] In this embodiment, the material of the substrate 10 can be any semiconductor material suitable for forming an IGBT device, such as silicon, silicon carbide, gallium nitride, etc. Figure 2 The substrate 10 may include a front side 10a and a back side 10b opposite to each other. From the back side 10b to the front side 10a (i.e., from bottom to top), the P+ collector region 11, the N-type buffer layer 12, and the N-drift region 13 of the IGBT device may be arranged in sequence. The N-type buffer layer 12 may also be an N-type field stop structure (N-type field stop layer) in other examples. The doping concentration of the N-type buffer layer 12 or the N-type field stop layer is greater than the doping concentration of the N-drift region 13. A first trench gate 16 is arranged in the N-drift region 13 near the front side 10a of the substrate 10, and is used to control the on and off of the trench gate IGBT device. The first trench gate 16 is arranged in the first trench 16a on the front side 10a of the substrate 10, and includes a gate dielectric layer covering the inner wall of the first trench 16a and a gate conductive layer covering the gate dielectric layer and filling the first trench 16a.

[0038] Please continue to refer to Figure 2 , a P-type base region 14 and an N+ emitter region 15 may be provided in the N-drift region 13 on one side of the first trench gate 16, the N+ emitter region 15 is provided in the P-type base region 14 and is located on the surface of the front side 10a of the substrate 10, and the P-type base region 14 may extend from the surface of the substrate 10 to a partial depth of the first trench gate 16, for example, 1 / 2 of the depth of the first trench gate 16. Of course, a contact hole may also be provided in the N+ emitter region 15 on the front side 10a of the substrate 10 for electrical extraction.

[0039] Please continue to refer to Figure 2 A first P-type doped region 21, an N-type floating buried layer 22, a second trench gate 23 and a plug 26 may be provided in the N-drift region 13 on the other side of the first trench gate 16 (i.e., the side away from the P-type base region 14). The first P-type doped region 21 extends from the front side 10a of the substrate 10 to a partial depth of the first trench gate 16, and its depth may be flush with the bottom of the first trench gate 16, or slightly (downward) exceed the bottom of the first trench gate 16. The N-type floating buried layer 22 and the second trench gate 23 are both provided in the first P-type doped region 21, and the second trench gate 23 is located above the N-type floating buried layer 22, and the depth (length) of the second trench gate 23 is less than the depth (length) of the first trench gate 16.

[0040] Specifically, a second trench 23a is provided in the first P-type doping region 21 on the front side 10a of the substrate 10, and the second trench 23a extends from the front side 10a of the substrate 10 to a partial depth of the first trench gate 16. The second trench gate 23 is provided in the second trench 23a, and includes a gate dielectric layer covering the inner wall of the second trench 23a and a gate conductive layer covering the gate dielectric layer and filling the second trench 23a. An isolation dielectric layer 17 is provided on the front side 10a of the substrate 10, and conductive through holes are respectively provided in the isolation dielectric layer 17 for electrically leading out the first trench gate 16 and the second trench gate 23. The first trench gate 16 and the second trench gate 23 are electrically connected by using the interconnection structure above the conductive through hole so that the first trench gate 16 and the second trench gate 23 are always at the same potential. In a preferred example, the depth (length) of the second trench 23a (the second trench gate 23) can be 1 / 3 to 2 / 3 of the length of the first trench gate 16.

[0041] Please continue to refer to Figure 2 , the first P-type doping region 21 extends downward from the surface of the substrate 10, and its doping concentration may be greater than the doping concentration of the N-drift region 13, and is used to provide hole carriers to the IGBT device. The doping concentration of the N-type floating buried layer 22 is greater than the doping concentration of the first P-type doping region 21. The N-type floating buried layer 22 may be, for example, heavily doped with N-type, and its top does not contact the bottom of the second trench 23a, that is, it is separated by a certain distance. Both ends of the N-type floating buried layer 22 in the horizontal direction each exceed the two ends (i.e., both sides) of the second trench gate 23 in the horizontal direction, that is, the second trench 23a is projected into the N-type floating buried layer 22. The N-type floating buried layer 22 may include a first end 22a close to the first trench 16a and a second end 22b away from the first trench 16a, a first interval is maintained between the first end 22a and the sidewall of the first trench 16a, and the second end 22b extends in another direction to the first P-type doping region 21 that separates the upper and lower sides thereof. The plug 26 is disposed in the first P-type doping region 21 on one side of the second trench gate 23 and is grounded through the isolation dielectric layer 17. The depth of the plug 26 in the first P-type doping region 21 is less than the depth of the second trench 23a. In other words, the plug 26 is used to electrically lead out the first P-type doping region 21 above the N-type floating buried layer 22 and is grounded. In some examples, the source of the trench gate IGBT device, that is, the N+ emitter region 15 is also grounded, that is, the plug 26 is set at the same potential as the N+ emitter region 15.

[0042] It should be noted that, in this embodiment, the first P-type doped region 21, the second trench gate 23 and the N-type floating buried layer 22 constitute a P-channel depletion-type transistor structure (that is, a P-channel depletion-type MOS tube structure), the second trench gate 23 serves as a control end of the P-channel depletion-type transistor structure, and is electrically connected to the first trench gate 16 and always has the same potential, the first P-type doped region 21 between the N-type floating buried layer 22 (for example, the first end 22a) and the first trench gate 16 serves as a channel (that is, a channel region 25), and the second trench gate 23 serves as a control end of the P-channel depletion-type transistor structure, and is electrically connected to the first trench gate 16 and always has the same potential, and the first P-type doped region 21 between the N-type floating buried layer 22 (for example, the first end 22a) and the first trench gate 16 serves as a channel (that is, a channel region 25). The first P-type doped regions 21 on the upper and lower sides of the layer 22 serve as the two ends (source and drain ends) of the P-channel depletion-type transistor structure, and the plug 26 is connected to one end of the first P-type doped region 21 above the N-type floating buried layer 22 (i.e., the end above the P-channel depletion-type transistor structure) and is grounded, so that the second trench gate 23 is used in conjunction with the N-type floating buried layer 22 to control the channel region 25 to achieve the movement and distribution of hole carriers in the first P-type doped region 21 and its vicinity, thereby simultaneously optimizing the on-state voltage drop and turn-off loss of the trench gate IGBT structure.

[0043] Figure 3a Schematic diagram of the trench gate IGBT structure of this embodiment when it is turned on. Figure 3a As shown, when the first trench gate 16 and the second trench gate 23 are connected to a positive voltage greater than the threshold voltage, the IGBT structure is in the forward conduction stage, that is, electrons and holes are respectively input from the N+ emitter region 15 and the P+ collector region 11. At this time, the second trench gate 23 is in an inversion state, so that the channel region 25 of the P-channel depletion-type transistor structure is pinched off, and the holes in the first P-type doped region 21 flow to and accumulate in the region away from the N-type floating buried layer 22, that is, the holes discharged by the second trench gate 23 accumulate at the bottom of the P-type base region 14, thereby increasing the conductivity modulation effect and reducing Vcesat (on-state voltage drop), which is used to reduce power loss during conduction. Moreover, compared to two parallel long trench gates (similar to two parallel first trench gates 16), the second trench gate 23 is similar to a small capacitor connected in parallel between the first trench gate 16 and the P+ collector region 11 when turned off (the depth of the second trench gate 23 is relatively small). This embodiment can have a relatively smaller input capacitance, thereby reducing power loss and turn-on time during turn-on.

[0044] Figure 3b Schematic diagram of the trench gate IGBT structure of this embodiment when it is turned off (just turned off), as shown Figure 3bAs shown, when the first trench gate 16 and the second trench gate 23 are connected to a voltage less than the threshold voltage (ground or negative voltage), the IGBT structure is in the off stage. At this time, the second trench gate 23 makes the P-channel depletion transistor structure in a normally open state, and the holes accumulated in the P-type base region 14 and its surroundings can be quickly transferred upward from the bottom of the first P-type doping region 21 by the P-channel depletion transistor structure, and quickly extracted and discharged by the plug 26, reducing the off-end current (tail current), reducing the power loss and turn-off time during shutdown. Compared with the extraction or recombination of excess hole carriers along the N-drift region 13, the hole carriers can be extracted along the channel region 25 of the P-channel depletion transistor structure, which not only adds an additional extraction channel, but also can be used to realize the multiple extraction of hole carriers in the P-channel depletion MOS tube structure, which is more conducive to improving the extraction rate.

[0045] From the above-mentioned role of the P-channel depletion-type transistor structure in the trench gate IGBT structure, it can be understood how to set the first P-type doping region 21, the second trench gate 23 and the N-type floating buried layer 22 so that the three are matched to achieve the above-mentioned role. In this embodiment, the depth of the first P-type doping region 21 is 0.5-1.1 of the length of the first trench gate 16, and the first interval between the N-type floating buried layer 22 and the sidewall of the first trench 16a needs to match the doping concentration of the first P-type doping region 21 and the N-type floating buried layer 22, so as to use the voltage of the first trench gate 16 and the second trench gate 23 to control the switch of the channel region 25. In a preferred example, the second end 22b of the N-type floating buried layer 22 extends to the edge of the first P-type doping region 21, and the plug 26 is located in the first P-type doping region 21 near the second end 22b, so that the area between the second trench gate 23 and the N-type floating buried layer 22 is also used as a part of the channel region 25, which is conducive to the second trench gate 23 controlling the switch of the channel region 25 and isolating the plug from the first P-type doping region under the N-type floating buried layer. Of course, in some examples, it is also feasible that the plug 26 is located in the first P-type doping region 21 near the first end 22b.

[0046] For further information, please refer to Figure 2A second P-type doping region 24 may be provided in each of the N-drift regions 13 below the first trench gate 16 and the second trench gate 23. The doping concentration of the second P-type doping region 24 is greater than the doping concentration of the first P-type doping region 21, and is used to prevent the P-channel depletion-type transistor structure from affecting the breakdown voltage of the trench gate IGBT structure. A certain distance is reserved between the two second P-type doping regions 24, which can serve as a channel for hole carriers to enter and exit the aforementioned P-channel depletion-type transistor structure. The above-mentioned two second P-type doping regions 24 may be, for example, two heavily doped regions formed simultaneously by high-energy injection, that is, the two second P-type doping regions 24 have similar or identical doping concentrations and junction depths. The two second P-type doping regions 24 are arranged at intervals, wherein the second P-type doping region 24 located below the first trench gate 16 is close to the bottom of the first trench gate 16, and the width of the second P-type doping region 24 located below the first trench gate 16 is substantially the same as the width of the first trench 16a and is substantially aligned with the first trench 16a, and the second P-type doping region 24 located below the second trench gate 23 may also be substantially the same as the width of the second trench 23a and is substantially aligned with the second trench 23a. Of course, the length of the second P-type doping region 24 below the second trench gate 23 along the horizontal direction may also be specifically adjusted according to the breakdown voltage of the trench gate IGBT structure, and this embodiment does not limit its length.

[0047] Figure 1 This is a schematic diagram of the structure of a trench gate IGBT device used as a reference in the related art. Its basic structure is similar to the structure of the present embodiment on the side of the P-type base region of the first trench gate. It includes a P+ collector region 11', an N-type buffer layer 12', an N-drift region 13', a P-type base region 14', an N+ emitter region 15' and a trench gate 16' arranged in sequence from bottom to top. The trench gate IGBT structure of the above-mentioned related art and the trench gate IGBT structure in the present embodiment can be simulated to obtain the following electrical parameter table of Table 1 under the same settings as much as possible:

[0048]

[0049] Table 1 is a comparison of simulation parameters of the trench gate IGBT of the related art and the present invention.

[0050] As can be seen from Table 1, compared with the trench gate IGBT structure in the related art, the trench gate IGBT structure provided by the present invention can greatly optimize the on-state voltage drop, switching loss and switching time without substantially affecting (or slightly affecting) the breakdown voltage, thereby improving the performance of the trench gate IGBT structure. Specifically, relative to the trench gate IGBT structure in the related art, the trench gate IGBT structure of this embodiment reduces the on-state voltage drop Vcesat by about 18.5% while reducing the input capacitance by about 30.1%, thereby achieving a significant reduction in switching loss and switching time (not reflected in Table 1).

[0051] In addition, the present embodiment does not impose any restrictions on the specific structures in the first trench gate 16, the N-drift region 13 and the P-type base region 14, that is, other structures or settings for improving the on-state voltage drop or switching time may also be included. In one example, a super junction structure may also be provided in the N-drift region 13. In other examples, an N-type carrier layer may also be provided between the P-type base region 14 and the N-drift region 13, and its doping concentration may be slightly higher than the doping concentration of the N-drift region 13.

[0052] Another embodiment of the present invention further provides a semiconductor device. The semiconductor device provided in this embodiment may include cells, wherein at least some of the cells include the above-mentioned trench gate IGBT structure, that is, at least some of the cells are IGBT cells. In the example of this embodiment, the above-mentioned semiconductor device may be a trench gate IGBT device composed of IGBT cells. In other examples, the above-mentioned semiconductor device may include other semiconductor structures in addition to the above-mentioned IGBT cells for integrating other functional modules.

[0053] Figure 4a A schematic diagram of a cell of a trench gate IGBT device provided in this embodiment.

[0054] like Figure 4a As shown, the cell includes two first trench gates 16 arranged at intervals, and the substrate 10 outside the two first trench gates 16 is provided with a P+ collector region 11, an N-type buffer layer 12, an N-drift region 13, a P-type base region 14 and an N+ emitter region 15 from bottom to top, and the substrate 10 inside (between) the two first trench gates 16 is provided with a first P-type doping region 21, an N-type floating buried layer 22, a second trench gate 23 and a plug 26 from bottom to top. The second trench gate 23 can be, for example, provided in the first P-type doping region 21 at the middle position of the two first trench gates 16. The N-type floating buried layer 22 is disposed in the first P-type doping region 21 below the second trench gate 23. The N-type floating buried layer 22 includes a first end 22a and a second end 22b opposite to each other in the horizontal direction. The first end 22a is spaced apart from the adjacent first trench gate 16, and the second end 22b extends to contact with another first trench gate 16, so as to separate the first P-type doping regions 21 on the upper and lower sides of the N-type floating buried layer 22. The plug 26 is disposed in the first P-type doping region 21 near the second end 22b of the second trench gate 23. The two first trench gates 16 and the second trench gate 23 are electrically connected. In addition, the three second P-type doping regions 24 can also be respectively located in the N-drift region 13 below the two first trench gates 16 and one second trench gate 23.

[0055] In addition, the specific configuration of the first P-type doping region 21 , the N-type floating buried layer 22 , the second trench gate 23 and the second P-type doping region 24 in the cell may refer to the aforementioned trench gate IGBT structure.

[0056] Another embodiment of the present invention further provides a semiconductor device. The semiconductor device provided in this embodiment may include a cell, and the cell includes the aforementioned trench gate IGBT structure, that is, an IGBT cell. In the example of this embodiment, the above-mentioned semiconductor device may be a trench gate IGBT device composed of IGBT cells. In other examples, the above-mentioned semiconductor device may include other semiconductor structures in addition to the above-mentioned IGBT cell, for integrating other functional modules.

[0057] Figure 4b Schematic diagram of a cell of a trench gate IGBT device provided in this embodiment. Figure 4b As shown, the cell includes two first trench gates 16 arranged at intervals, and the substrate 10 outside the two first trench gates 16 is provided with a P+ collector region 11, an N-type buffer layer 12, an N-drift region 13, a P-type base region 14 and an N+ emitter region 15 from bottom to top, and the substrate 10 inside (between) the two first trench gates 16 is provided with a first P-type doping region 21, an N-type floating buried layer 22, two second trench gates 23 and a plug 26 from bottom to top. The two second trench gates 23 can be arranged at intervals in the first P-type doping region 21 between the two first trench gates 16. The N-type floating buried layer 22 is disposed in the first P-type doping region 21 below the two second trench gates 23. The N-type floating buried layer 22 includes a first end 22a and a second end 22b opposite to each other in the horizontal direction. The first end 22a and the second end 22b are respectively arranged to be spaced apart from the adjacent first trench gate 16, so as to separate the first P-type doping region 21 on the upper and lower sides of the N-type floating buried layer 22. The plug 26 is disposed in the first P-type doping region 21 between the two second trench gates 23. The two first trench gates 16 and the two second trench gates 23 are electrically connected. In other words, compared with the cell of the aforementioned example including a P-channel depletion transistor structure, the cell of this example includes two parallel P-channel depletion transistor structures, and the first end 22a and the second end 22b of the N-type floating buried layer 22 and the first P-type doping region 21 between the adjacent first trench gates 16 serve as the channel region 25 of the two P-channel depletion transistor structures, and the two P-channel depletion transistor structures share a plug 26. In addition, three second P-type doping regions 24 can also be spaced apart below the first trench gate 16 and the second trench gate 23, wherein the two second P-type doping regions 24 on both sides are respectively located in the N-drift region 13 below the two first trench gates 16, and the middle second P-type doping region 24 can be located below the two second trench gates 23.

[0058] In addition, the specific configurations of the first P-type doping region 21 , the N-type floating buried layer 22 , the second trench gate 23 and the second P-type doping region 24 may refer to the aforementioned embodiments.

[0059] In summary, the trench gate IGBT structure of the present invention includes a substrate and a P+ collector region, an N-drift region, a P-type base region, an N+ emitter region, a first trench gate, a first P-type doped region, a second trench gate, an N-type floating buried layer and a plug arranged in the substrate. The first trench gate extends from the surface of the substrate to the N-drift region; the first P-type doped region, the P-type base region and the N-drift region each arranged on one side of the first trench gate, and a plug is arranged in the first P-type doped region for grounding; the second trench gate is arranged in the first P-type doped region, electrically connected to the first trench gate, and the length of the second trench gate is less than the length of the first trench gate; the N-type floating buried layer is arranged in the first P-type doped region below the second trench gate, one end of the N-type floating buried layer is arranged at a distance from the first trench gate, and the doping concentration of the N-type floating buried layer is greater than the doping concentration of the first P-type doped region. In the present invention, the first P-type doping region, the second trench gate and the N-type floating buried layer constitute a P-channel depletion transistor structure, wherein the second trench gate serves as the control end of the P-channel depletion transistor structure, is electrically connected to the first trench gate and is always at the same potential, the first P-type doping region between the N-type floating buried layer and the first trench gate serves as a channel, the first P-type doping regions on the upper and lower sides of the N-type floating buried layer serve as the two ends of the P-channel depletion transistor structure, and the plug connects one end of the first P-type doping region above the N-type floating buried layer (i.e., the upper end of the P-channel depletion transistor structure) and is grounded. When the IGBT structure is in the forward conduction stage, the second trench gate is in an inversion state, so that the channel of the P-channel depletion transistor structure is pinched off, and the holes in the first P-type doping region flow and accumulate toward the region away from the N-type floating buried layer, that is, the holes discharged by the second trench gate accumulate toward the bottom of the P-type base region, thereby increasing the conductivity modulation effect and reducing Vcesat (on-state voltage drop), which is used to reduce the power loss during conduction. Moreover, compared with two parallel long trench gates (similar to two parallel first trench gates), the second trench gate is similar to a small capacitor in parallel between the first trench gate and the P+ collector region when turned off (the depth of the second trench gate is relatively small), which can reduce the input capacitance, and thereby reduce the power loss and turn-on time when turned on. When the IGBT structure is in the off stage, the second trench gate makes the P-channel depletion-type transistor structure in a normally open state, and the holes accumulated in the P-type base region and its surroundings can be quickly transferred upward from the bottom of the first P-type doped region by the P-channel depletion-type transistor structure and quickly extracted using a plug, reducing the off-end current (tail current) and reducing the power loss and turn-off time when turned off.

[0060] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A trench gate IGBT structure, characterized in that: The trench gate IGBT structure includes a substrate and a P+ collector region, an N-drift region, a P-type base region and an N+ emitter region which are arranged in the substrate and arranged in sequence from bottom to top. The trench gate IGBT structure also includes: A first trench gate extending from the substrate surface into the N-drift region; A first P-type doping region, wherein the first P-type doping region and the P-type base region are respectively arranged in an N-drift region on one side of the first trench gate, and a plug is arranged in the first P-type doping region for grounding; a second trench gate, disposed in the first P-type doping region and electrically connected to the first trench gate, wherein the length of the second trench gate is smaller than the length of the first trench gate; An N-type floating buried layer is disposed in the first P-type doped region below the second trench gate, and one end of the N-type floating buried layer is spaced apart from the first trench gate; Among them, the first P-type doped region, the second trench gate and the N-type floating buried layer constitute a P-channel depletion-type transistor structure, and the first P-type doped region between the N-type floating buried layer and the first trench gate serves as the channel region of the P-channel depletion-type transistor structure.

2. The trench gate IGBT structure according to claim 1, characterized in that: The first trench gate and the second trench gate both extend downward from the substrate surface, and the length of the second trench gate is 1 / 3 to 2 / 3 of the length of the first trench gate.

3. The trench gate IGBT structure according to claim 2, characterized in that: The first P-type doping region extends downward from the substrate surface, the depth of the first P-type doping region is 0.5-1.1 of the length of the first trench gate, and the depth of the first P-type doping region is greater than the depth of the N-type floating buried layer.

4. The trench gate IGBT structure according to claim 1, characterized in that: The plug is disposed in the first P-type doping region on a side of the second trench gate away from the channel region, and a depth of the plug is less than a depth of the second trench gate.

5. The trench gate IGBT structure according to claim 1, characterized in that: The other end of the N-type floating buried layer away from the channel region extends to separate the plug from the first P-type doped region under the N-type floating buried layer.

6. The trench gate IGBT structure according to claim 1, characterized in that: A second P-type doping region is also provided in the N-drift region below the first trench gate and the second trench gate, and the doping concentration of the second P-type doping region is greater than the doping concentration of the first P-type doping region. The two second P-type doping regions have the same doping concentration and junction depth, and one of the second P-type doping regions is close to the bottom of the first trench gate.

7. The trench gate IGBT structure according to claim 1, characterized in that: An N-type buffer layer or an N-type field stop layer is also provided between the P+ collector region and the N-drift region.

8. A semiconductor device, characterized in that: The invention comprises a plurality of cells, wherein the cell comprises two first trench gates, wherein an N-drift region, a P-type base region and an N+ emitter region are sequentially arranged in the substrate outside the two first trench gates from bottom to top, wherein a first P-type doped region, an N-type floating buried layer and a second trench gate are arranged in the substrate inside the two first trench gates from bottom to top, wherein the first trench gate and the second trench gate are electrically connected, wherein a first end of the N-type floating buried layer is spaced apart from one of the first trench gates, wherein a second end of the N-type floating buried layer is connected to a side wall of another first trench gate, wherein a plug is arranged in the first P-type doped region above the second end of the N-type floating buried layer for grounding, wherein the first P-type doped region, the second trench gate and the N-type floating buried layer constitute a P-channel depletion-type transistor structure, and the first P-type doped region between the N-type floating buried layer and the first trench gate serves as a channel region of the P-channel depletion-type transistor structure.

9. A semiconductor device, characterized in that: The invention comprises a plurality of cells, wherein the cell comprises two first trench gates, wherein an N-drift region, a P-type base region and an N+ emitter region are sequentially arranged in the substrate outside the two first trench gates from bottom to top, wherein a first P-type doped region, an N-type floating buried layer and two second trench gates are arranged in the substrate inside the two first trench gates from bottom to top, wherein the first trench gate and the second trench gate are electrically connected, wherein the two ends of the N-type floating buried layer are respectively spaced from the side walls of the two first trench gates, and a plug is arranged in the first P-type doped region between the two second trench gates for grounding, wherein the first P-type doped region, the second trench gate and the N-type floating buried layer constitute a P-channel depletion-type transistor structure, and the first P-type doped region between the N-type floating buried layer and the first trench gate serves as a channel region of the P-channel depletion-type transistor structure.

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