Semiconductor device
By using a polycrystalline silicon carbide substrate and a superjunction structure design, the bipolar degradation problem of silicon carbide superjunction IGBT devices was solved, the on-resistance was reduced, the conductivity modulation effect and device reliability were improved, and the fabrication process was simplified.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU LOONGSPEED SEMICON TECH CO LTD
- Filing Date
- 2025-05-08
- Publication Date
- 2026-06-09
Smart Images
Figure CN224343672U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device. Background Technology
[0002] An insulated-gate bipolar transistor (IGBT) is a semiconductor device that combines the advantages of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar junction transistor (BJT). A super-junction (SJ) is a charge-balancing technique that modulates the longitudinal electric field by introducing alternating P-type and N-type dopants into the semiconductor device, thereby increasing the breakdown voltage while reducing its on-resistance.
[0003] Silicon carbide superjunction IGBTs are high-performance semiconductor devices based on silicon carbide materials and utilizing superjunction structures to achieve high voltage and low conduction. They have high withstand voltage, low conduction loss and fast switching speed.
[0004] Because IGBTs are bipolar devices, when an IGBT is turned on, electrons enter from the front and holes are injected from the back. Electrons and holes recombine in the drift region to form a current. This characteristic of electrons and holes jointly participating in conduction is called "bipolar operation." When electrons and holes recombine in the drift region, they release energy. However, silicon carbide crystals contain a defect called basal plane dislocation (BPD). The recombination energy generated by electrons and holes triggers the stacking faults at the BPD to propagate outward, forming an extended defect, which is called "bipolar degradation." Bipolar degradation increases the on-resistance, leading to increased power loss. It also affects the device's electrothermal characteristics and reliability, and long-term operation can cause localized overheating or device failure. Utility Model Content
[0005] In view of the above problems, this application provides a semiconductor device to solve the problem of increased on-resistance caused by bipolar degradation in semiconductor devices in the related art.
[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:
[0007] This application provides a semiconductor device comprising: a polycrystalline silicon carbide substrate having P-type conductivity; a drift layer having N-type conductivity, the drift layer being stacked on one side of the polycrystalline silicon carbide substrate and having a superjunction structure therein; and a collector metal layer being directly stacked on the other side of the polycrystalline silicon carbide substrate opposite to the drift layer and forming an ohmic contact with the polycrystalline silicon carbide substrate.
[0008] In one embodiment of this application, the grain size of the polycrystalline silicon carbide in the polycrystalline silicon carbide substrate is 2nm-30nm.
[0009] In one embodiment of this application, the semiconductor device further includes: a buffer layer having N-type conductivity, the buffer layer being disposed between the polycrystalline silicon carbide substrate and the drift layer.
[0010] In one embodiment of this application, the materials of the drift layer and the buffer layer include single-crystal silicon carbide.
[0011] In one embodiment of this application, both the drift layer and the buffer layer are doped with N-type impurities, wherein the N-type impurities are nitrogen; the concentration of N-type impurities in the drift layer is lower than the concentration of N-type impurities in the buffer layer.
[0012] In one embodiment of this application, the concentration of N-type impurities in the drift layer is 1 x 10⁻⁶. 13 cm -3 ~1x10 14 cm -3 .
[0013] In one embodiment of this application, the polycrystalline silicon carbide substrate is doped with P-type impurities, wherein the P-type impurities include aluminum or boron; the concentration of the P-type impurities is less than 1 x 10⁻⁶. 18 cm -3 .
[0014] In one embodiment of this application, the semiconductor device further includes: a base region having P-type conductivity; the base region is stacked on the side of the drift layer away from the polycrystalline silicon carbide substrate, an emitter having N-type conductivity is disposed in the base region, the emitter and the base region form a PN junction, and the PN junction is capable of injecting minority carriers into the drift layer.
[0015] In one embodiment of this application, the superjunction structure includes at least one P-type region and at least one N-type region, which are alternately arranged in the lateral direction.
[0016] In one embodiment of this application, the material of the current collector metal layer includes NiSi.
[0017] The semiconductor device provided in this application has the following technical effects:
[0018] Replacing the monocrystalline silicon carbide substrate with a polycrystalline silicon carbide substrate and directly depositing the collector metal layer on the back side of the polycrystalline silicon carbide substrate eliminates the need for additional P-type impurity implantation on the back side. The polycrystalline silicon carbide substrate allows for the injection of a higher concentration of minority carriers into the drift layer, increasing the carrier concentration and significantly enhancing the conductivity modulation effect in the on-state, thereby reducing resistance. It also reduces the number of back-side ion implantation steps, simplifying the semiconductor device fabrication process.
[0019] Meanwhile, the polycrystalline silicon carbide in the polycrystalline silicon carbide substrate is composed of a large number of small grains, each with a randomly distributed and different crystal orientation. Defects (plane dislocations) cannot be concentrated on specific crystal planes or orientations like in single-crystal silicon carbide; instead, they are dispersed within each grain, resulting in a more dispersed defect distribution in the polycrystalline silicon carbide substrate. Furthermore, defects cannot extend across grain boundaries, thus reducing the propagation of stacking faults. Therefore, the dispersed defects in the polycrystalline silicon carbide substrate make the recombination process of electrons and holes in the drift layer more uniform, preventing energy release from concentrated at a single point and reducing the severe bipolar degradation caused by localized defect aggregation. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 A schematic diagram of the structure of a semiconductor device provided for related technologies;
[0022] Figure 2 A process flow diagram for the fabrication of semiconductor devices provided for related technologies;
[0023] Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;
[0024] Figure 4 A process flow diagram for the fabrication of semiconductor devices provided in the embodiments of this application;
[0025] Figure 5 A comparison graph showing the doping concentration versus thickness of semiconductor devices provided for related technologies and semiconductor devices provided in the embodiments of this application;
[0026] Figure 6 A comparison chart of Ic-Vc curves of semiconductor devices provided for related technologies and semiconductor devices provided in the embodiments of this application;
[0027] Figure 7 A comparison diagram of electron-hole density distribution curves of semiconductor devices provided for related technologies and semiconductor devices provided in the embodiments of this application;
[0028] Figure 8 for Figure 7 A magnified view of the rectangular area.
[0029] Figure label:
[0030] 100-Polycrystalline silicon carbide substrate;
[0031] 101 - Single-crystal silicon carbide substrate; 102 - P-type impurity layer;
[0032] 200-Buffer Layer;
[0033] 300-Drift Layer;
[0034] 301-P type area; 302-N type area;
[0035] 400 - Collector metal layer;
[0036] 500 - Emitter metal layer;
[0037] 600 - Dielectric layer;
[0038] 601 - Gate region;
[0039] 700 - Current guiding layer;
[0040] 701 - Highly doped P-type region; 702 - Emitter; 703 - Base region. Detailed Implementation
[0041] refer to Figure 1 and Figure 2 In related technologies, when fabricating silicon carbide superjunction IGBTs, after growing an N-type epitaxial layer on a single-crystal silicon carbide substrate 101, the back side of the single-crystal silicon carbide substrate 101 needs to be thinned to reduce the on-resistance and thermal resistance of the device. After thinning, P-type impurities are implanted multiple times on the back side of the single-crystal silicon carbide substrate 101 using an ion implantation process to form a P-type impurity layer 102. This makes the single-crystal silicon carbide substrate 101 heavily P-type doped, thereby generating conductivity modulation when the IGBT is turned on. Conductivity modulation can greatly reduce the on-resistance of the device drift layer 300, thereby reducing the on-voltage drop of the device.
[0042] However, the ion implantation process in related technologies can only achieve limited implantation depth and low implantation concentration; and the doping concentration gradually increases and then decreases from the surface to the interior, with a relatively low doping concentration at the junction; in other words, the superjunction IGBT structure in related technologies cannot ensure the conductivity modulation effect when the IGBT is turned on.
[0043] To address the aforementioned technical problems, embodiments of this application provide a semiconductor device that replaces a single-crystal substrate with a polycrystalline silicon carbide substrate. The polycrystalline silicon carbide substrate can inject a higher concentration of minority carriers into the drift layer, thereby increasing the carrier concentration in the drift layer and significantly enhancing the conductivity modulation effect in the conduction state, thus reducing resistance. It also makes the recombination process of electrons and holes in the drift layer more uniform, preventing the energy from being concentrated at a certain point and reducing the severe bipolar degradation phenomenon caused by the accumulation of local defects.
[0044] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0045] refer to Figure 3 The semiconductor device provided in this application includes: a polycrystalline silicon carbide substrate 100, a buffer layer 200, and a drift layer 300.
[0046] The polycrystalline silicon carbide substrate 100 has P-type conductivity, and the buffer layer 200 has N-type conductivity. The buffer layer 200 is stacked on the upper surface of the polycrystalline silicon carbide substrate 100.
[0047] The drift layer 300 has N-type conductivity. The drift layer 300 is stacked on top of the polycrystalline silicon carbide substrate 100 and disposed on the upper surface of the buffer layer 200. The drift layer 300 has at least one P-type region 301 and at least one N-type region 302 arranged alternately in the lateral direction to form a superjunction structure, so that the electric field distribution is more uniform and the on-resistance is reduced.
[0048] The buffer layer 200 can improve the lattice matching between the polycrystalline silicon carbide substrate 100 and the drift layer 300, thereby reducing lattice defects; it can also improve the flatness of the upper surface of the polycrystalline silicon carbide substrate 100, providing a good foundation for the setting of the drift layer 300.
[0049] The polycrystalline silicon carbide substrate 100 can inject a higher concentration of minority carriers into the drift layer 300, thereby increasing the carrier concentration of the drift layer 300 and significantly enhancing the conductivity modulation effect in the on state, thus reducing the resistance.
[0050] Meanwhile, since the polycrystalline silicon carbide in the polycrystalline silicon carbide substrate 100 is composed of a large number of small grains, the crystal orientation of each small grain is randomly distributed, and the crystal orientation of each small grain is different. The grains are connected by grain boundaries. Defects (base plane dislocations) cannot be concentrated in a specific crystal plane or crystal orientation like in single-crystal silicon carbide. Instead, they are dispersed in each small grain, making the defect distribution in the polycrystalline silicon carbide substrate 100 more dispersed. Moreover, defects cannot extend across grain boundaries. Defects are confined to the vicinity of grain boundaries, thereby reducing the propagation of stacking faults.
[0051] The grain structure of the polycrystalline silicon carbide substrate 100 can also disperse external stress to multiple grain boundaries, thereby avoiding dislocation multiplication caused by stress concentration.
[0052] Therefore, the dispersed defects in the polycrystalline silicon carbide substrate 100 make the recombination process of electrons and holes in the drift layer 300 more uniform, and prevent the energy from being concentrated and released at a certain point, thus reducing the severe bipolar degradation caused by the aggregation of local defects.
[0053] refer to Figure 5 , Figure 5 The curve 'a' in the figure is a graph showing the doping concentration versus thickness of semiconductor devices provided by related technologies. Figure 5 The b curve in the figure is a graph of the doping concentration versus thickness of the semiconductor device provided in the embodiments of this application.
[0054] As can be seen, the b-curve provided in this embodiment is a horizontal line, indicating that the doping concentration does not change with depth. This suggests that the P-type impurity in the semiconductor device provided in this embodiment is uniformly doped, and its doping concentration remains constant throughout the thickness of the material. In contrast, the a-curve of the superjunction IGBT structure in related technologies is a sloping line or curve, indicating that the doping concentration gradually changes with thickness.
[0055] Meanwhile, compared with the superjunction IGBT structure of related technologies, the semiconductor device provided in this application has a higher doping concentration at the junction.
[0056] In other words, the simulation results show that, compared with the superjunction IGBT structure of related technologies, the semiconductor device provided in this application has a more uniform distribution of P-type impurity ions and a higher concentration at the junction. Therefore, when minority carriers are injected into the drift layer 300, more minority carriers will be injected under the same voltage, the conductivity modulation effect will be stronger, and the resistance of the drift layer 300 will be lower.
[0057] refer to Figure 6 , Figure 6 The c-curve in the figure is the Ic-Vc curve of a semiconductor device provided by related technologies. Figure 6The d-curve in the figure is the Ic-Vc curve of the semiconductor device provided in the embodiments of this application. It can be seen that the semiconductor device provided in the embodiments of this application has a larger current.
[0058] refer to Figure 7 and Figure 8 , Figure 7 and Figure 8 The e-curve in the figure represents the electron density of the semiconductor device provided in the embodiments of this application. Figure 7 and Figure 8 The f-curve in the figure represents the electron density of the semiconductor device provided by the relevant technology. Figure 7 and Figure 8 The n-curve in the figure represents the hole density of the semiconductor device provided in the embodiments of this application. Figure 7 and Figure 8 The m-curve in the figure represents the hole density of the semiconductor device provided by the relevant technology.
[0059] It can be seen that at the end of the drift layer 300 near the buffer layer 200, the electron and hole densities are on the same order of magnitude and the difference is very small. This indicates that the polycrystalline silicon carbide substrate 100 can still provide hole injection to modulate the conductivity of the drift layer 300, thereby greatly reducing the resistance.
[0060] Continue to refer to Figure 3 The semiconductor device provided in this application embodiment also includes: collector metal layer 400.
[0061] The collector metal layer 400 is directly stacked on the lower surface of the polycrystalline silicon carbide substrate 100 and forms an ohmic contact with the polycrystalline silicon carbide substrate 100; the lower surface of the polycrystalline silicon carbide substrate 100 is away from the drift layer 300.
[0062] Direct stacking means that no other structure needs to be set between the collector metal layer 400 and the polycrystalline silicon carbide substrate 100, and the interface of the collector metal layer 400 is in direct contact with the lower surface of the polycrystalline silicon carbide substrate 100.
[0063] In silicon carbide superjunction IGBTs of related technologies, due to the wide bandgap of single-crystal silicon, a low-resistance ohmic contact can only be formed by heavy doping on the back side of the single-crystal silicon carbide substrate combined with high-temperature annealing; since there is an oxide layer on the surface of single-crystal carbon, special pretreatment is required after heavy doping on the back side of the single-crystal silicon carbide substrate to ensure ohmic contact with the metal.
[0064] Compared to silicon carbide superjunction IGBTs of related technologies, the semiconductor device provided in this application embodiment has a narrower bandgap in polycrystalline carbon, allowing the collector metal layer 400 to directly form an ohmic contact with the polycrystalline silicon carbide substrate 100, resulting in a simpler process; it also reduces the back-side ion implantation process steps, simplifying the semiconductor device fabrication process.
[0065] Meanwhile, due to the abundance of grain boundaries in polycrystalline silicon carbide, the loose atomic arrangement in these grain boundary regions provides more diffusion channels and bonding sites. When in contact with the collector metal layer 400, it promotes mechanical interlocking and chemical bonding between the metal and the polycrystalline material, resulting in stronger interfacial adhesion between the collector metal layer 400 and the polycrystalline silicon carbide substrate 100. The collector metal layer 400 can be made of NiSi.
[0066] Continue to refer to Figure 3 The semiconductor device provided in this application embodiment further includes: a base region 703 with P-type conductivity, the base region 703 being stacked on the side of the drift layer 300 away from the polycrystalline silicon carbide substrate 100, an emitter 702 with N-type conductivity being disposed in the base region 703, the emitter 702 and the base region 703 forming a PN junction, the PN junction being able to inject minority carriers into the drift layer 300.
[0067] When the semiconductor device is in the on state, the PN junction formed by the emitter 702 and the base region 703 is forward biased, which causes the base region 703 to inject minority carriers into the drift layer 300, while the emitter 702 injects electrons into the base region 703; this can significantly increase the carrier concentration of the drift layer 300, thereby achieving a conductivity modulation effect and reducing the on-state voltage drop of the device.
[0068] Continue to refer to Figure 3 The semiconductor device provided in this application embodiment further includes: an emitter metal layer 500, a dielectric layer 600, a current guiding layer 700, and a highly doped P-type region 701.
[0069] The current guiding layer 700 is disposed on the upper surface of the drift layer 300 away from the polycrystalline silicon carbide substrate 100. The current guiding layer 700 is N-type doped and is responsible for controlling the flow of current.
[0070] A highly doped P-type region 701 is disposed above the base region 703. The highly doped P-type region 701 short-circuits the emitter 702 and the base region 703 to form an ohmic contact.
[0071] A dielectric layer 600 is disposed above the current guiding layer 700, the emitter 702 and the base region 703. The dielectric layer 600 includes a gate region 601 and is used to separate the gate and the emitter 702.
[0072] The emitter metal layer 500 is disposed above the dielectric layer 600, and the emitter metal layer 500 is connected to the highly doped P-type region 701 to achieve an ohmic contact.
[0073] In this embodiment, the grain size of the polycrystalline silicon carbide in the polycrystalline silicon carbide substrate 100 is 2nm-30nm.
[0074] The size of grains affects the hardness, strength, toughness, electrical properties, and thermal conductivity of a material. Keeping the grain size within the above range can ensure that the material has good hardness and strength while optimizing electrical and thermal properties.
[0075] In this embodiment, both the drift layer 300 and the buffer layer 200 are made of single-crystal silicon carbide.
[0076] Due to the wide bandgap characteristics of single-crystal silicon carbide, the drift layer 300 made of single-crystal silicon carbide is thinner and can withstand higher voltages, resulting in a significant reduction in on-resistance.
[0077] The buffer layer 200 made of single-crystal silicon carbide can provide good lattice matching between the polycrystalline silicon carbide substrate 100 and the drift layer 300 to reduce defects caused by lattice mismatch.
[0078] In this embodiment, both the drift layer 300 and the buffer layer 200 are doped with N-type impurities, and the N-type impurities are nitrogen; the concentration of N-type impurities in the drift layer 300 is lower than the concentration of N-type impurities in the buffer layer 200.
[0079] The low doping concentration in the drift layer 300 helps to form a more uniform electric field distribution and can distribute heat more evenly, reducing the risk of local overheating and improving the thermal stability of the device.
[0080] The high doping concentration in the buffer layer 200 serves as a transition from the drift layer 300 to the polycrystalline silicon carbide substrate 100, which can reduce the resistance and defects at the interface; it can also alleviate the stress caused by different doping concentrations and improve the structural integrity and reliability of the device.
[0081] In this embodiment, the concentration of N-type impurities in the drift layer 300 is 1 x 10⁻⁶. 13 cm -3 ~1x10 14 cm -3 .
[0082] In this embodiment, the polycrystalline silicon carbide substrate 100 is doped with P-type impurities, including aluminum or boron.
[0083] Among them, the concentration of P-type impurities is less than 1x10. 18 cm -3 .
[0084] refer to Figure 4 This application also provides a method for fabricating a semiconductor device, comprising:
[0085] Step S1: An N-type epitaxial layer is grown on a polycrystalline silicon carbide substrate 100 to obtain a drift layer 300 with N-type conductivity.
[0086] Step S2: Thin the back side of the polycrystalline silicon carbide substrate 100 to reduce the on-resistance and thermal resistance of the device.
[0087] Step S3: A collector metal layer 400 is disposed on the back side of the polycrystalline silicon carbide substrate 100. The collector metal layer 400 is used to make ohmic contact with the polycrystalline silicon carbide substrate 100.
[0088] Compared with the process of preparing silicon carbide superjunction IGBTs in related technologies, the semiconductor device preparation method provided in this application reduces the back-side ion implantation process and simplifies the semiconductor device preparation process.
[0089] In summary, this application provides a semiconductor device comprising: a polycrystalline silicon carbide substrate 100, a drift layer 300, and a collector metal layer 400. The polycrystalline silicon carbide substrate 100 has P-type conductivity, and the drift layer 300 has N-type conductivity. The drift layer 300 is stacked on one side of the polycrystalline silicon carbide substrate 100. The drift layer 300 has P-pillars 301 and N-regions 302 that are laterally adjacent. The collector metal layer 400 is directly stacked on the other side of the polycrystalline silicon carbide substrate 100 away from the drift layer 300 and forms an ohmic contact with the polycrystalline silicon carbide substrate 100. The polycrystalline silicon carbide substrate 100 can inject a higher concentration of minority carriers into the drift layer 300, thereby increasing the carrier concentration of the drift layer 300 and significantly enhancing the conductivity modulation effect in the on-state, thereby reducing the resistance.
[0090] Meanwhile, the defects (basal plane dislocations) in the polycrystalline silicon carbide substrate 100 are dispersed in each small grain, making the recombination process of electrons and holes in the drift layer 300 more uniform, and preventing the energy release from being concentrated at a certain point, thus reducing the severe bipolar degradation caused by the aggregation of local defects; moreover, the defects cannot continue to extend across the grain boundaries, reducing the expansion of stacking faults.
[0091] Furthermore, the collector metal layer 400 is directly disposed on the lower surface of the polycrystalline silicon carbide substrate 100, eliminating the need to implant P-type impurities on the back side of the substrate, reducing the back side ion implantation process steps, and simplifying the semiconductor device fabrication process.
[0092] The various embodiments or embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other.
[0093] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.
[0094] Generally speaking, terms should be understood at least in part by their use in context. For example, at least in part by context, the term "one or more" as used in the text can be used to describe any feature, structure, or characteristic of the singular meaning, or a combination of features, structures, or characteristics of the plural meaning. Similarly, at least in part by context, terms such as "a" or "the" can also be understood to convey either singular or plural usage.
[0095] It should be readily understood that the terms “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “on top of something” but also “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).
[0096] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.
[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A semiconductor device, characterized in that, include: A polycrystalline silicon carbide substrate with P-type conductivity; as well as, A drift layer with N-type conductivity is stacked on one side of the polycrystalline silicon carbide substrate, and a superjunction structure is disposed within the drift layer; A collector metal layer is directly stacked on the opposite side of the polycrystalline silicon carbide substrate from the drift layer and forms an ohmic contact with the polycrystalline silicon carbide substrate.
2. The semiconductor device according to claim 1, characterized in that, The grain size of the polycrystalline silicon carbide in the polycrystalline silicon carbide substrate is 2nm-30nm.
3. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a buffer layer having N-type conductivity, the buffer layer being disposed between the polycrystalline silicon carbide substrate and the drift layer.
4. The semiconductor device according to claim 3, characterized in that, The drift layer and the buffer layer are made of monocrystalline silicon carbide.
5. The semiconductor device according to claim 3, characterized in that, Both the drift layer and the buffer layer are doped with N-type impurities, and the N-type impurities are nitrogen. The concentration of N-type impurities in the drift layer is lower than that in the buffer layer.
6. The semiconductor device according to claim 5, characterized in that, The concentration of N-type impurities in the drift layer is 1 x 10⁻⁶. 13 cm -3 ~1x10 14 cm -3 .
7. The semiconductor device according to claim 1, characterized in that, The polycrystalline silicon carbide substrate is doped with P-type impurities, including aluminum or boron. The concentration of the P-type impurity is less than 1 x 10⁻⁶. 18 cm -3 .
8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: a base region having P-type conductivity; The base region is stacked on the side of the drift layer away from the polycrystalline silicon carbide substrate. An emitter with N-type conductivity is disposed in the base region. The emitter and the base region form a PN junction. The PN junction can inject minority carriers into the drift layer.
9. The semiconductor device according to claim 1, characterized in that, The superjunction structure includes at least one P-type region and at least one N-type region, which are arranged alternately in the lateral direction.
10. The semiconductor device according to claim 1, characterized in that, The material of the current collector metal layer includes NiSi.