Novel nano wall (NWaFET) IC basic structure
The NWaFET IC structure with an embedded silicon dioxide insulating part addresses the DIBL effect and leakage current challenge, enabling channel length reduction to 5nm and improved integration.
Patent Information
- Application Number
- CN202411198895.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2024-12-13
AI Technical Summary
The challenge of achieving further reduction in channel length below 12nm in integrated circuits to sustain Moore's Law is hindered by the DIBL effect and leakage current, which existing technologies like HVTFET and NWaFET structures have not adequately addressed.
A new nano-wall (NWaFET) IC structure is optimized by embedding a silicon dioxide insulating part within the channel to suppress the DIBL effect and reduce leakage current, utilizing a combined structure of heavily doped channel and lightly doped drain regions.
The new structure effectively suppresses the DIBL effect and reduces leakage current, enabling further reduction in channel length to 5nm, enhancing integration and performance.
Smart Images
Figure CN119133239A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the fields of microelectronics and integrated circuits. Background Art
[0002] The integrated circuit industry has been developing rapidly since the 1950s. According to Moore's Law[1], the number of components on a chip doubles every six months (every 18 months after 1975), and the performance and capacity of semiconductors will show exponential growth[2]. The basis of Moore's Law is the proportional reduction of integrated circuits. However, according to the prediction of the IE EE International Roadmap for Devices and Systems (IRDS), if the channel length Lch of integrated circuits cannot exceed (be less than) 12nm[3], Moore's Law will face the dilemma of being unable to move forward.
[0003] The HVTFET (heterojunction vertical channel field effect transistor) and the new nano-wall N WaFET structure [4-6] before the present invention adopted a vertical design scheme, which greatly improved the integration of the device and suppressed the DIBL effect through a combined structure of heavily doped channel region and lightly doped drift region. The HVT and NWaFET structures further reduced Lch by adopting a channel heavy doping method. They have a shorter channel length Lch than the existing FINFET [7], GAA [8], etc., and have a higher integration.
[0004] The basic structure of a new type of nano-wall (NWaFET) IC proposed in this paper is an optimization of the traditional NWaFET structure by combining the full depletion principle based on the continuation of HVTFET and NWaFET theories. An insulating part (silicon dioxide in this case) is embedded inside the channel surface away from the channel surface to cut off the leakage current path. The DIBL effect is more effectively suppressed and the leakage current is reduced.
[0005] References
[0006] [1].MOORE GECramming More Components Onto Integrated Circuits[J].Proceedings of the IEEE,1998,86(1):82–85.
[0007] [2].Thompson S, Packan P, Bohr M.MOS scaling: transistor challenges forth e 21 stcentury. Intel Technology Journal, 1998; pp 1-18.
[0008] [3].https: / / semiwiki.com / events / 306532-ibm-at-iedm /
[0009] [4]. Liao Yongbo, Li Ping, Tang Ruifeng, et al. Structure of a new digital gate integrated circuit [P]. China, invention patent, application number: CN111048579.1.2020.
[0010] [5]. Li Ping, Tang Ruifeng, Liao Yongbo, et al. A new DRAM structure and implementation method [P]. China, invention patent, application number: CN202110252584.1.2021.
[0011] [6]. Liao Yongbo, Liu Jinming, Li Ping et al. A high-integration nano-wall integrated circuit structure [P]. China, invention patent, application number: CN202210413345.4.2022.
[0012] [7].Chenming Hu,Lee WC,Kedzierski J,et al.FinFET-a self-aligned double-gateMOSFET scalable to 20nm[J].IEEE Transactions on Electron Devices,2000,47(12):2320-2325.
[0013] [8].JPColinge,MHGao,A.Romano,H.Maes,C.Claeys.Silicon-on-insulator "gate-all-around" MOS device[C].1990IEEE SOS / SOI Technology Conference.Proceedings.Key West, FL, USA: IEEE, 1990:137-138. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 This is a three-dimensional diagram of the basic structure of a new type of nano-wall (NWaFET) IC.
[0015] Figure 2 A cross-sectional view of the basic structure of a new type of nano-wall (NWaFET) IC.
[0016] Figure 3A top view of the basic structure of a new type of nano-wall (NWaFET) IC (surrounded by gates on four sides).
[0017] Figure 4 A top view of the basic structure of a new type of nano-wall (NWaFET) IC (surrounded by gates on three sides).
[0018] Figure 5 A top view of the basic structure of a new type of nano-wall (NWaFET) IC (surrounded by gates on two sides).
[0019] Figure 6 A top view of the basic structure of a new type of nano-wall (NWaFET) IC (surrounded by a single-sided gate).
[0020] Figure 7 This is a simulation diagram of the output characteristics of a new type of nano-wall (NWaFET) IC basic structure (channel length is 5nm).
[0021] Figure 8 This is a comparison chart of the simulated transfer characteristic curves of two NWaFET structures (channel length is 5nm). DETAILED DESCRIPTION
[0022] [Example]
[0023] A new type of nano-wall (NWaFET) IC basic structure is characterized in that the device structure is based on the NWaFET basic structure, with a silicon dioxide insulating part embedded in the middle. Figure 1 The three-dimensional diagram and the cross-sectional diagram are shown as follows: the region (108, 116, 117) is a heavily doped source region N+, the region (110, 122, 140) is a lightly doped drain region N-, the region (109, 120, 119) is a heavily doped channel region P+, the region (111, 123) is a heavily doped drain region N+, the region (102, 121) is a silicon dioxide insulating portion embedded therein, from the surface of the source (106, 116, 117) to the lightly doped drain (110, 122), and the depth of the lightly doped drain (140, 122, 110) embedded therein is adjustable. The side is a gate oxide layer region (101, 104, 103, 115, 118) close to the silicon region, and the outer layer is a gate material (105, 106, 107, 113, 114). The output characteristic curve of this structure when the channel length is 5nm is shown in Figure 7 The simulation results of relevant parameters are compared with those of the traditional NWaFET structure when the channel length is 5nm. Figure 8 .
Claims
1. A new type of nano-wall (NWaFET) IC basic structure, characterized in that: The device structure is based on the basic structure of NWaFET, with a silicon dioxide insulating part embedded in the middle. As shown in the stereogram of Figure 1 and the cross-sectional view of Figure 2: the regions (108, 116, 117) are heavily doped source regions N+, the regions (110, 122, 140) are lightly doped drain regions N-, the regions (109, 120, 119) are heavily doped channel regions P+, the regions (111, 123) are heavily doped drain regions N+, the regions (102, 121) are silicon dioxide insulating portions embedded therein, from the surface of the source (108, 116, 117) to the lightly doped drain (110, 122), and the depth of the lightly doped drain (140, 122, 110) embedded therein is adjustable. The side is the gate oxide layer region (101, 104, 103, 115, 118) close to the silicon region, and the outer layer is the gate material (105, 106, 107, 113, 114).
2. A novel nano-wall (NWaFET) IC basic structure as claimed in claim 1, characterized in that: The thickness of the P-type channel semiconductor region (109, 120, 119) of the NMOS is less than 12 nm.
3. A silicon dioxide embedded NWaFET structure as claimed in claim 1, wherein the doping concentration of the P-type channel semiconductor region (109, 120, 119) of the NMOS is more than one order of magnitude higher than that of the N-drain region (110, 122, 140).
4. A novel nano-wall (NWaFET) IC basic structure as claimed in claim 1, characterized in that: The thickness of all layers ranges from 1nm to 100nm, and the doping concentration ranges from 1e14cm-3 to 1e20cm-3.
5. A novel nano-wall (NWaFET) IC basic structure as claimed in claim 1, wherein the heavily doped drain region (111, 123), the semiconductor substrate or the well (112) is single crystal silicon, the lightly doped drain region (110, 122, 140) is a narrow bandgap pseudocrystalline semiconductor material (such as SiGe pseudocrystalline), the heavily doped source region (102, 202) is single crystal Si or a narrow bandgap single crystal semiconductor material, and the heavily doped source region (111, 123) is a narrow bandgap semiconductor polycrystalline material such as polycrystalline Ge, polycrystalline SiGe, polycrystalline TWS (mercury cadmium telluride), polycrystalline InP, polycrystalline InSb, etc. or a combination of the above materials; when the channel semiconductor region (109, 120, 119), the heavily doped drain region (108, 116, 117), the semiconductor substrate or the well (112) are wide bandgap single crystal semiconductor materials (such as SiC single crystal or GaN single crystal), the lightly doped drain region (110, 122, 140) is a pseudocrystalline Si semiconductor material, the heavily doped source region (106, 116, 117) is a single crystal Si semiconductor material, and the gate (105, 106, 107, 113, 114) is composed of heavily doped polycrystalline or refractory metal silicide or refractory metal or a combination thereof.
6. A novel nano-wall (NWaFET) IC basic structure as claimed in claim 1, characterized in that: The gate electrode (105, 106, 107, 113, 114) is arranged on the entire area (138) of one side of the semiconductor region, or on a local area (138) of one side of the semiconductor region; further, the gate electrode (113, 114) is arranged on the entire area (126) of two side surfaces of the semiconductor region, or on the entire area of one side surface of the semiconductor region and on a local area (126) of the other side surface; further, the gate electrode (113, 114) is arranged on the entire area (129, 130) of three side surfaces of the semiconductor region, or on the entire area of two side surfaces of the semiconductor region and on a local area (129, 130) of the other side surface; further, the gate electrode (105, 106, 107, 113, 114) is arranged on the entire area (132, 134) of four side surfaces of the semiconductor region, or on the entire area of three side surfaces of the semiconductor region and on a local area (132, 134) of the last side surface.