Drive circuit for lasers in a transmitter and transmitter architecture

Abstract

The present invention discloses a drive circuit and transmitter architecture for a laser in a transmitter. The drive circuit may include a transcoding module, a retiming module, a pulse generation module, an asymmetric feedforward amplifier module, a first current summing module, a high-pass filtering module, a low-pass filtering module, a push-pull driver module, a pre-driver module, and a second current summing module. In the technical solution of the present invention, due to the provision of the first and second current summing modules, PAM4-type current signal conversion can be performed at the output end of the asymmetric feedforward amplifier module. The large capacitive load at the output end is shared by the summing node, so that the parasitic capacitance of the drive circuit itself is reduced when outputting a third PAM4-type current signal, avoiding the concentrated superposition of large loads at the output end of the second current summing module, thereby significantly reducing the power consumption of the drive circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated module design, and in particular to a driving circuit for a laser in a transmitter and a transmitter architecture. Background Art

[0002] like Figure 1 The figure shows a commonly used laser driver circuit in the prior art. It can compensate for the linearity of PAM4 (4-Level Pulse Amplitude Modulation) signals. Specifically, a multiplexer converts low-speed parallel data signals into high-speed serial data signals. A pulse generation circuit generates the three timing pulse waveforms necessary for equalization and divides them into high, medium, and low signal paths. A feedforward amplifier adjusts the heights of the upper, middle, and lower eyes in the PAM4 signal output eye diagram, thereby improving the signal output quality. At the output stage, each input signal passes through a pre-amplifier before entering the output driver. The signals are summed at the output node to form a PAM4 current signal used to drive the laser.

[0003] Figure 1 Although the driving circuit of the laser shown can perform linear compensation and bandwidth compensation in the process of driving the laser, the driving circuit requires greater power consumption when performing linear compensation and bandwidth compensation to improve and compensate for the deteriorated linearity caused by bandwidth limitation, laser power saturation and device relaxation effect.

[0004] Therefore, the existing technology still needs to be improved and developed. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a driving circuit and transmitter architecture for a laser in a transmitter, so as to solve the problem that the laser driving circuit in the prior art requires greater power consumption when performing linear compensation and bandwidth compensation to improve and compensate for the deteriorated linearity caused by bandwidth limitation, laser power saturation and device relaxation effect.

[0006] The technical solution adopted by the present invention to solve the technical problem is: to provide a driving circuit for a laser in a transmitter, comprising:

[0007] Transcoding module, used to convert binary code into three-way temperature code;

[0008] a retiming module connected to the transcoding module, the retiming module being configured to receive the three temperature codes and retime the three temperature codes to reduce jitter of the temperature codes converted by the transcoding module;

[0009] A pulse generation module is connected with the retiming module, and is configured to receive the three-way temperature code after retiming to generate three-way timing pulse signals for feedforward equalization.

[0010] An asymmetric feedforward amplification module is connected with the pulse generation module, and is configured to adjust the height of the three-way timing pulse signals to output a first PAM4 type current signal.

[0011] A first current summation module is connected with the asymmetric feedforward amplification module, and is configured to receive the first PAM4 type current signal output by the asymmetric feedforward amplification module and sum to output a second PAM4 type current signal.

[0012] A high-pass filter module is connected with the first current summation module.

[0013] A low-pass filter module is connected with the input end of the high-pass filter module.

[0014] A push-pull drive module is connected with the output end of the high-pass filter module, and includes a first voltage input end and a second voltage input end, wherein the first voltage input end is connected with a first power supply end, and the second voltage input end is connected with a second power supply end, and the second PAM4 type current signal is output to the push-pull drive module through the high-pass filter module.

[0015] A pre-driver module is connected with the output end of the low-pass filter module, and includes a third voltage input end and a fourth voltage input end, wherein the third voltage input end is connected with the second power supply end, and the fourth voltage input end is grounded, and the second PAM4 type current signal is output to the pre-driver module through the low-pass filter module, and the pre-driver module is configured to receive the current signal output through the low-pass filter module and adjust the linearization gain and high-frequency equalization capability to form an equalization current.

[0016] A second current summation module is connected with the output end of the pre-driver module and the output end of the push-pull drive module, and is configured to sum the current signal output by the pre-driver module and the current signal output by the push-pull drive module to output a third PAM4 type current signal to drive the laser.

[0017] Further, the asymmetric feedforward amplification module includes a high-path slice, a middle-path slice and a low-path slice connected with the pulse generation module.

[0018] The high path slice, the middle path slice and the low path slice are also connected with the first current adding module respectively.

[0019] The first current adding module comprises a first resistor, one end of the first resistor is connected with the high path slice, the middle path slice and the low path slice, and the other end of the first resistor is connected with the input end of the high pass filter module and the input end of the low pass filter module.

[0020] The second current adding module comprises a second resistor, one end of the second resistor is connected with the output end of the push-pull driving module and the output end of the pre-driving module, and the other end of the second resistor is connected with the laser.

[0021] The push-pull driving module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first inductor, a second inductor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first current source and a load matching unit.

[0022] The gate of the first transistor is connected with one end of the third resistor and one end of the first capacitor, the drain of the first transistor is connected with the first power supply end, and the source of the first transistor is connected with the drain of the third transistor.

[0023] The gate of the third transistor is connected with one end of the second capacitor and one end of the fourth resistor, and the source of the third transistor is connected with one end of the first current source.

[0024] The drain of the second transistor is connected with the first power supply end, the gate of the second transistor is connected with one end of the fifth resistor and one end of the third capacitor, and the source of the second transistor is connected with one end of the first inductor.

[0025] The drain of the fourth transistor is connected with one end of the second inductor, the gate of the fourth transistor is connected with one end of the sixth resistor and one end of the fourth capacitor, and the source of the fourth transistor is connected with the source of the third transistor.

[0026] One end of the load matching unit is connected to the connection end of the source of the first transistor and the drain of the third transistor, and the other end of the load matching unit is connected to the second power supply end.

[0027] The other end of the third resistor and the other end of the fifth resistor are connected to the first bias voltage output terminal, the other end of the fourth resistor and the other end of the sixth resistor are connected to the second bias voltage output terminal, and the other end of the first current source is connected to the second power supply terminal;

[0028] The other end of the first capacitor, the other end of the second capacitor, the other end of the third capacitor, and the other end of the fourth capacitor are connected to the output end of the high-pass filtering module;

[0029] The other end of the first inductor is connected to the other end of the second inductor, wherein one end where the first inductor is connected to the second inductor is the output end of the push-pull driving module.

[0030] A further arrangement of the present invention is that the load matching unit includes: a seventh resistor and a fifth capacitor, one end of the fifth capacitor is connected to the connection end of the source of the first transistor and the drain of the third transistor, the other end of the fifth capacitor is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the second power supply end.

[0031] In a further configuration of the present invention, the pre-driver module includes: an eighth resistor, a ninth resistor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a fifth transistor, a sixth transistor, a second current source, a third current source, and an RC network;

[0032] One end of the eighth resistor is connected to the second power supply end, the other end of the eighth resistor is connected to one end of the third inductor, the other end of the third inductor is connected to one end of the fourth inductor, the other end of the fourth inductor is connected to the drain of the fifth transistor, the gate of the fifth transistor is connected to the output end of the low-pass filter module, and the source of the fifth transistor is connected to one end of the second current source;

[0033] One end of the ninth resistor is connected to the second power supply end, the other end of the ninth resistor is connected to one end of the fifth inductor, the other end of the fifth inductor is connected to one end of the sixth inductor, the other end of the sixth inductor is connected to the drain of the sixth transistor, the gate of the sixth transistor is connected to the output end of the low-pass filter module, and the source of the sixth transistor is connected to one end of the third current source;

[0034] The other ends of the second current source and the third current source are grounded, one end of the RC network is connected to the source of the fifth transistor, and the other end of the RC network is connected to the source of the sixth transistor;

[0035] The third inductor and the fourth inductor are connected to one end of the output end of the pre-driver module.

[0036] The second power supply end is an output end of a low dropout linear regulator.

[0037] The driving circuit further comprises a parasitic inductance suppression module connected to the second current adding module and the laser.

[0038] The application further provides a transmitter architecture comprising at least a laser and a driving circuit for the laser in the transmitter as described above, and the driving circuit is connected to the laser.

[0039] The application has the following beneficial effects:

[0040] The application provides a driving circuit for a laser in a transmitter and a transmitter architecture, wherein the asymmetric amplification module can alleviate the nonlinear relaxation effect when outputting a PAM4 type current signal to the laser, and can also compensate for the bandwidth loss on the circuit transmission path, in addition, due to the balancing effect of the pre-driver module, the push-pull driving module and the asymmetric feedforward amplification module, the ringing phenomenon caused by the complex conjugate pole of the third PAM4 type current signal output by the second current adding module is improved, and the linearity of the output third PAM4 type current signal is also improved, the pre-driver module can adjust the linearization gain and high-frequency equalization capability to form an equalization current, thereby reducing the bandwidth requirement of the push-pull driving module, further, due to the provision of the first current adding module and the second current adding module, compared with the driving circuit of the laser in the prior art, the PAM4 type current signal conversion can be performed at the output end of the asymmetric feedforward amplification module, the large-capacitance load of the output end (the first current adding module and the second current adding module) is shared through the summation node, so that the parasitic capacitance of the driving circuit is reduced when outputting the third PAM4 type current signal, and the large load is avoided to be concentrated and superimposed at the output end of the second current adding module, thereby significantly reducing the power consumption of the driving circuit, and thus it can be seen that the power consumption required when the driving circuit performs linear compensation and bandwidth compensation is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative effort.

[0042] Figure 1 is a circuit structure diagram of the driving circuit in the prior art.

[0043] Figure 2 is a circuit structure diagram of the driving circuit for the laser in the transmitter of the present application.

[0044] Figure 3 is a specific circuit structure diagram of the push-pull driving module and the pre-driving module in an embodiment of the present application.

[0045] Figure 4 is an optical eye diagram of the output before the equalization is turned on in the driving circuit for the laser in the transmitter in an embodiment of the present application.

[0046] Figure 5 is an optical eye diagram of the output after the equalization is turned on in the driving circuit for the laser in the transmitter in an embodiment of the present application.

[0047] The signs in the drawings: 10, driving circuit; 101, transcoding module; 102, retiming module; 103, pulse generation module; 104, asymmetric feedforward amplification module; 105, first current addition module; 106, high-pass filter module; 107, low-pass filter module; 108, push-pull driving module; 1081, load matching unit; 109, pre-driving module; 110, second current addition module; 111, parasitic inductance suppression module; VDDH, first power supply terminal; VDDL, second power supply terminal; I1, first current source; I2, second current source; I3, third current source; I DAC fourth current source; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; L1, first inductor; L2, second inductor; L3, third inductor; L4, fourth inductor; L5, fifth inductor; L6, sixth inductor; L7, seventh inductor; L8, eighth inductor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor. DETAILED DESCRIPTION

[0048] In order to make the technical features, objectives and effects of the present application clearer, the specific embodiments of the present application will be described in detail below. In the following description, it should be understood that the directions or positional relationships indicated by "front", "back", "upper", "lower", "left", "right", "vertical", "horizontal", "vertical", "horizontal", "top", "bottom", "inner", "outer", "head", "tail" and the like are based on the directions or positional relationships shown in the drawings, constructed and operated in a specific direction, and are only for the convenience of describing the technical solutions, and cannot be understood as indicating that the devices or elements referred to must have a specific direction, thus cannot be understood as limiting the present application.

[0049] The laser driven by the current signal needs an output stage driver circuit to provide a modulation current of about milliamperes. Due to the light-emitting principle of the laser, the equivalent time constant of the laser in the charging and discharging paths is inconsistent, which shows that the rising edge is faster than the falling edge in the eye diagram test, thereby causing the eye diagram to be skewed, affecting the quality of the output optical signal. At the same time, various parasitics (including bonding wire and packaging parasitic effects) on the signal link also introduce bandwidth limitations. Therefore, a bipolar transistor circuit with high current gain is often applied to drive the laser in the transmitter.

[0050] The proliferation of data-intensive applications and the exponential growth of data traffic have placed unprecedented demands on the performance and efficiency of data centers. In response to these challenges, data center operators are constantly seeking innovative solutions to provide cost-effective and high-speed data transmission capabilities. Due to the advantages of high output power, high conversion efficiency and low manufacturing cost of lasers, transmitter technology based on laser driver circuits has been widely used in data center interconnections.

[0051] Despite these attractive advantages, it must be recognized that there are limitations to optical interconnection applications based on laser driver circuits. Typically, interfaces (including bonding wires and packaging parasitic effects) introduce signal loss and bandwidth bottlenecks in the transmitter link, thereby affecting overall system performance. Another challenge lies in the nonlinearity of devices in the driver circuit of the laser, which exhibits amplitude distortion and faster falling time than rising time (relaxation effect) in the eye diagram. Complex modulation methods (such as PAM-4) can improve bandwidth utilization efficiency under limited bandwidth and device nonlinearity, but also require greater power consumption to improve and compensate for deteriorating linearity caused by bandwidth limitations, laser power saturation phenomena and device relaxation effects. The driver circuit of the laser in the prior art can ensure the output quality of the signal, but the power consumption is high.

[0052] Based on the above problems, the present application provides a driver circuit 10 for a laser in a transmitter, as Figure 2As shown, the driving circuit 10 can include a transcode module 101, a retiming module 102, a pulse generation module 103, an asymmetric feedforward amplification module 104, a first current summing module 105, a high-pass filtering module 106, a low-pass filtering module 107, a push-pull driving module 108, a pre-driver module 109, and a second current summing module 110.

[0053] The transcode module 101 is configured to convert binary codes into three-way temperature codes. The retiming module 102 is connected to the transcode module 101 and configured to receive the three-way temperature codes and re-time the three-way temperature codes to reduce the jitter of the temperature codes converted by the transcode module 101. The pulse generation module 103 is connected to the retiming module 102 and configured to receive the re-timed three-way temperature codes and generate three-way timing pulse signals for feedforward equalization. The asymmetric feedforward amplification module 104 is connected to the pulse generation module 103 and configured to adjust the height of the three-way timing pulse signals to output a first PAM4-type current signal. The first current summing module 105 is connected to the asymmetric feedforward amplification module 104 and configured to receive the first PAM4-type current signal output by the asymmetric feedforward amplification module 104 and sum the first PAM4-type current signal to output a second PAM4-type current signal. The input end of the high-pass filtering module 106 is connected to the first current summing module 105. The input end of the low-pass filtering module 107 is connected to the input end of the high-pass filtering module 106. The input end of the push-pull driving module 108 is connected to the output end of the high-pass filtering module 106. The push-pull driving module 108 includes a first voltage input end and a second voltage input end. The first voltage input end is connected to a first power supply end VDDH, and the second voltage input end is connected to a second power supply end VDDL. The second PAM4-type current signal is output to the push-pull driving module 108 through the high-pass filtering module 106. The pre-driver module 109 includes a third voltage input end and a fourth voltage input end. The third voltage input end is connected to the second power supply end VDDL, and the fourth voltage input end is grounded. The second PAM4-type current signal is output to the pre-driver module 109 through the low-pass filtering module 107. The pre-driver module 109 is configured to receive the current signal output by the low-pass filtering module 107 and adjust the linearization gain and high-frequency equalization capability to form an equalization current. The second current summing module 110 is connected to the output end of the pre-driver module 109 and the output end of the push-pull driving module 108. The second current summing module 110 is configured to sum the current signal output by the pre-driver module 109 and the current signal output by the push-pull driving module 108 to output a third PAM4-type current signal to drive a laser.

[0054] Specifically, the data input to the transcode module 101 can be, but is not limited to, one-way data, for example, can also be two-way parallel data, wherein the data input to the transcode module 101 is output to the retiming module 102 in the form of three-way parallel temperature code, and the three-way temperature code is retimed by the retiming module 102 to reduce the jitter of the temperature code converted by the transcode module 101. The three-way temperature code retimed by the retiming module is transmitted to the pulse generation module 103, and the pulse generation module 103 forms the signal flow necessary for the feedforward equalization of the asymmetric feedforward amplification module 104 through different delays, that is, generates three-way timing pulse signals for feedforward equalization.

[0055] In the present embodiment, the asymmetric amplification module can alleviate the nonlinear relaxation effect when outputting the PAM4 type current signal to the laser, and can also compensate for the bandwidth loss on the circuit transmission path. In addition, due to the equalization effect of the pre-driver module 109, the push-pull driver module 108 and the asymmetric feedforward amplification module 104, the ringing phenomenon caused by the complex conjugate pole of the third PAM4 type current signal output by the second current summing module 110 is improved, and the linearity of the output third PAM4 type current signal is also improved. The pre-driver module 109 can adjust the linearization gain and high-frequency equalization capability to form an equalization current, thereby reducing the bandwidth requirement of the push-pull driver module 108. Further, due to the provision of the first current summing module 105 and the second current summing module 110, compared with the driving circuit of the laser in the prior art (in which PAM4 type current signal conversion is only performed at the anode of the laser), PAM4 type current signal conversion can be performed at the output end of the asymmetric feedforward amplification module 104, and the large-capacitance load at the output end (the first current summing module 105 and the second current summing module 110) is shared through the summing node, so that the parasitic capacitance of the driving circuit 10 itself is reduced when outputting the third PAM4 type current signal, avoiding the concentration of large loads at the output end of the second current summing module 110, thereby significantly reducing the power consumption of the driving circuit 10. As can be seen, when performing linear compensation and bandwidth compensation, the driving circuit 10 requires lower power consumption to solve the problem of deteriorating linearity caused by linear compensation, bandwidth compensation, laser power saturation and device relaxation effect, and finally realizes high-speed, high-extinction ratio and high light modulation amplitude of the light modulation output eye diagram.

[0056] In addition, since the push-pull driver module 108 and the pre-driver module 109 share the second power supply end VDDL, the current in the push-pull driver circuit 10 can be multiplexed in the pre-driver module 109, further reducing the power consumption of the driving circuit 10.

[0057] It should be noted that the transcode module 101 can be any transcode circuit structure in the prior art capable of converting binary code into three-way temperature code, and a person skilled in the art can determine the specific circuit structure of the transcode module 101 according to actual needs, and no further limitation is made here.

[0058] The retiming module 102 can be any retiming circuit structure in the prior art capable of retiming the temperature code and reducing the jitter of the temperature code output by the transcode module 101, and a person skilled in the art can determine the specific circuit structure of the retiming module 102 according to actual needs, and no further limitation is made here.

[0059] In some embodiments, the high-pass filter module 106 can be any high-pass filter circuit capable of filtering out low-frequency signals, and a person skilled in the art can determine the specific circuit structure of the high-pass filter module 106 according to actual needs, and no further limitation is made here.

[0060] Likewise, the low-pass filter module 107 can be any low-frequency filter circuit capable of filtering out low-frequency signals, and a person skilled in the art can determine the specific circuit structure of the low-pass filter module 107 according to actual needs, and no further limitation is made here.

[0061] In the present embodiment, the high-pass filter module 106 can filter out low-frequency signals in the second PAM4 type current signal and retain high-frequency signals, wherein the less the high-frequency signals are filtered out, the steeper the rising and falling edges in the upper eye, middle eye and lower eye of the eye diagram signal will be, and the more the high-frequency signals are, the larger the eye width of the upper eye, middle eye and lower eye in the eye diagram signal will be, wherein the low-frequency signals filtered out by the high-pass filter module 106 are further compensated by the low-pass filter module 107, the low-frequency signals affect the level height of the eye diagram signal, the more the low-frequency signals, the larger the eye height in the upper eye, middle eye and lower eye of the eye diagram signal will be, and the setting mode of the high-frequency filter module and the low-frequency filter module ensures the flexibility during compensation.

[0062] In some embodiments, as shown in Figure 2 The asymmetric feedforward amplification module 104 can include a high-path slice, a middle-path slice and a low-path slice connected with the pulse generation module 103 respectively, and the high-path slice, the middle-path slice and the low-path slice are further connected with the first current addition module 105 respectively.

[0063] Specifically, each of the three sequential pulse signals generated by the pulse generation circuit includes a preamble (EQPRE) signal, a main marker (EQMA) signal, and a postamble (EQPST) signal. The three sequential pulse signals are amplified by the asymmetric feedforward amplifier module 104. When amplifying the three sequential pulse signals, four level amplitudes are formed using high path slices, middle path slices, and low path slices. Each slice (high path slice, middle path slice, and low path slice) uses the preamble, main marker, and postamble in the sequential pulse signal to adjust the speed of the rising and falling edges during the conversion of the four level amplitudes, thereby maximizing the eye diagram signal formed by the four level amplitudes, thereby improving the signal-to-noise ratio and bit error rate performance.

[0064] In some embodiments, the first current summing module 105 may include a first resistor, one end of which is connected to the high path slice, the middle path slice, and the low path slice, and the other end of the first resistor is connected to the input end of the high-pass filtering module 106 and the input end of the low-pass filtering module 107.

[0065] In this embodiment, only one load resistor (first resistor) needs to be provided to achieve current addition, that is, the first PAM4 current signal output by the asymmetric amplification module is converted into a second PAM4 current signal through the first resistor.

[0066] In some embodiments, the second current summing module 110 may include a second resistor, one end of which is connected to the output end of the push-pull driving module 108 and the output end of the pre-driving module 109 , and one end of which is connected to the laser.

[0067] In this embodiment, similarly, only one load resistor (second resistor) is required to convert the current signal output by the push-pull driver module 108 and the current signal output by the pre-driver module 109 into a third PAM4 current signal to be output to the laser.

[0068] In some embodiments, as Figure 3 As shown, the push-pull driving module 108 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first inductor L1, a second inductor L2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first current source I1 and a load matching unit 1081.

[0069] The gate of the first transistor M1 is connected with one end of the third resistor R3 and one end of the first capacitor C1, the drain of the first transistor M1 is connected with the first power supply end VDDH, and the source of the first transistor M1 is connected with the drain of the third transistor M3; the gate of the third transistor M3 is connected with one end of the second capacitor C2 and one end of the fourth resistor R4, and the source of the third transistor M3 is connected with one end of the first current source I1; the drain of the second transistor M2 is connected with the first power supply end VDDH, the gate of the second transistor M2 is connected with one end of the fifth resistor R5 and one end of the third capacitor C3, and the source of the second transistor M2 is connected with one end of the first inductor L1; the drain of the fourth transistor M4 is connected with one end of the second inductor L2, the gate of the fourth transistor M4 is connected with one end of the sixth resistor R6 and one end of the fourth capacitor C4, and the source of the fourth transistor M4 is connected with the source of the third transistor M3; one end of the load matching unit 1081 is connected with the connection end of the source of the first transistor M1 and the drain of the third transistor M3, and the other end of the load matching unit 1081 is connected with the second power supply end VDDL; the other end of the third resistor R3 and the other end of the fifth resistor R5 are connected with the first bias voltage output end, the other end of the fourth resistor R4 and the other end of the sixth resistor R6 are connected with the second bias voltage output end, and the other end of the first current source I1 is connected with the second power supply end VDDL; the other end of the first capacitor C1, the other end of the second capacitor C2, the other end of the third capacitor C3 and the other end of the fourth capacitor C4 are connected with the output end of the high pass filter module 106; the other end of the first inductor L1 is connected with the other end of the second inductor L2, wherein the end of the first inductor L1 and the second inductor L2 is the output end of the push-pull driving module 108.

[0070] In the embodiment, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 are bias resistors respectively, the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are isolation capacitors respectively, VCM0 is the first bias voltage, and VCM1 is the second bias voltage, wherein the third resistor R3 and the first capacitor C1 are ac coupled in the conduction process of the first transistor M1, the fourth resistor R4 and the second capacitor C2 are ac coupled in the conduction process of the third transistor M3, the fifth resistor R5 and the third capacitor C3 are ac coupled in the conduction process of the second transistor M2, and the sixth resistor R6 and the fourth capacitor C4 are ac coupled in the conduction process of the fourth transistor M4.

[0071] The first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all P-MOS (P-type Metal-Oxide-Semiconductor Field Effect Transistor).

[0072] In this embodiment, the first inductor L1 and the second inductor L2 are arranged in parallel using inductor peaking technology, which can independently improve the high-frequency signal balancing capability of the push-pull driver module 108; wherein, the load matching unit 1081 can achieve load balancing among the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4.

[0073] Specifically, the load matching unit 1081 may include a seventh resistor R7 and a fifth capacitor, one end of the fifth capacitor is connected to the connection end of the source of the first transistor M1 and the drain of the third transistor M3, the other end of the fifth capacitor is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is connected to the second power supply end VDDL.

[0074] In some embodiments, as Figure 3 As shown, the pre-driver module 109 may include an eighth resistor R8, a ninth resistor R9, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a fifth transistor M5, a sixth transistor M6, a second current source I2, a third current source I3 and an RC network; one end of the eighth resistor R8 is connected to the second power supply terminal VDDL, the other end of the eighth resistor R8 is connected to one end of the third inductor L3, the other end of the third inductor L3 is connected to one end of the fourth inductor L4, the other end of the fourth inductor L4 is connected to the drain of the fifth transistor M5, the gate of the fifth transistor M5 is connected to the output end of the low-pass filter module 107, and the source of the fifth transistor M5 is connected to one end of the second current source I2; one end of the ninth resistor R9 is connected to the first inductor L3, the other end of the third inductor L3 is connected to one end of the fourth inductor L4, and the other end of the fourth inductor L4 is connected to the drain of the fifth transistor M5. The gate of the fifth transistor M5 is connected to the output end of the low-pass filter module 107, and the source of the fifth transistor M5 is connected to one end of the second current source I2; one end of the ninth resistor R9 is connected to the first inductor L3, the other end of the third inductor L3 is connected to one end of the fourth inductor L4, and the other end of the fourth inductor L4 is connected to the drain of the fifth transistor M5. The second power supply terminal VDDL is connected, the other end of the ninth resistor R9 is connected to one end of the fifth inductor L5, the other end of the fifth inductor L5 is connected to one end of the sixth inductor L6, the other end of the sixth inductor L6 is connected to the drain of the sixth transistor M6, the gate of the sixth transistor M6 is connected to the output end of the low-pass filter module 107, and the source of the sixth transistor M6 is connected to one end of the third current source I3; the other ends of the second current source I2 and the third current source I3 are grounded, one end of the RC network is connected to the source of the fifth transistor M5, and the other end of the RC network is connected to the source of the sixth transistor M6; one end of the third inductor L3 connected to the fourth inductor L4 and one end of the fifth inductor L5 connected to the sixth inductor L6 are the output ends of the pre-driver module 109.

[0075] In this embodiment, the fifth transistor M5 and the sixth transistor M6 are a pair of differential working transistors, and both the fifth transistor M5 and the sixth transistor M6 are P-MOS transistors. The RC network is a commonly used resistor-capacitor circuit and will not be described in detail here.

[0076] The third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 share the second power supply terminal VDDL, so that a stacked design structure is adopted between the push-pull driver module 108 and the pre-driver module 109. This reduces the voltage between the source and drain of the transistors (the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor) in the driver circuit 10, thereby reducing the risk of breakdown of the transistors in the driver circuit 10.

[0077] In some embodiments, the second power supply terminal VDDL is an output terminal of a low dropout regulator (LDO).

[0078] In some embodiments, as Figure 2 As shown, the driving circuit 10 further includes a parasitic inductance suppression module 111 , which is connected to the second current summing module 110 and the laser.

[0079] In a specific embodiment, if Figure 2 As shown, the parasitic inductance suppression module 111 may include a fourth current source IDAC, a seventh inductor L7 and an eighth inductor L8, wherein one end of the fourth current source IDAC is connected to the first power supply terminal VDDH, the other end of the fourth current source IDAC is connected to one end of the seventh inductor L7, the other end of the seventh inductor L7 is connected to one end of the eighth inductor L8, the other end of the eighth inductor L8 is connected to the laser, and the connection end between the seventh inductor L7 and the eighth inductor L8 is also connected to the output end of the second current summing module 110 (i.e., the other end of the second resistor).

[0080] In this embodiment, the parasitic inductance suppression module 111 can suppress the parasitic inductance generated by the driving circuit 10 at the output end of the second current summing module 110 .

[0081] like Figure 4 As shown in FIG, the optical eye diagram outputted by the driving circuit 10 for the laser in the transmitter before the equalization is turned on is shown. Figure 5 As shown, this is the optical eye diagram output by the driving circuit 10 for the laser in the transmitter after equalization is turned on. After equalization is turned on, the driving circuit 10 for the laser in the transmitter can correct the eye diagram skew and amplitude distortion of the driving laser with a higher energy efficiency ratio at the same output rate, thereby achieving high-quality transmission of the optical eye diagram signal.

[0082] In some embodiments, the present invention further provides a transmitter architecture, which at least includes the driving circuit 10 for the laser in the transmitter as described above, and the driving circuit 10 is used as the driving circuit 10 for the laser in the transmitter, and the driving circuit 10 is connected to the laser.

[0083] The driving circuit 10 in the transmitter architecture may include a transcoding module 101, a retiming module 102, a pulse generating module 103, an asymmetric feedforward amplifying module 104, a first current summing module 105, a high-pass filtering module 106, a low-pass filtering module 107, a push-pull driving module 108, a pre-driving module 109, and a second current summing module 110; wherein the transcoding module 101 is used to convert a binary code into a three-way temperature code; the retiming module 102 is connected to the transcoding module 101, and the retiming module 102 is used to receive the three-way temperature code and retime the three-way temperature code to reduce the jitter of the temperature code converted by the transcoding module 101; the pulse generating module 103 is connected to the retiming module 10 2 connection, the pulse generating module 103 is used to receive the three-way temperature code after retiming to generate three-way timing pulse signals for feedforward equalization; the asymmetric feedforward amplifying module 104 is connected to the pulse generating module 103, and the asymmetric feedforward amplifying module 104 is used to adjust the height of the three-way timing pulse signals to output a first PAM4 type current signal; the first current adding module 105 is connected to the asymmetric feedforward amplifying module 104, and the first current adding module 105 is used to receive the first PAM4 type current signal output by the asymmetric feedforward amplifying module 104 and add and output a second PAM4 type current signal; the input end of the high-pass filtering module 106 is connected to the first current adding module 105; the low-pass filtering module 106 is connected to the input end of the low-pass filtering module 106. The input end of the module 107 and the input end of the high-pass filter module 106 are connected to the first current summing module 105; the input end of the push-pull driving module 108 is connected to the output end of the high-pass filter module 106, the push-pull driving module 108 includes a first voltage input end and a second voltage input end, the first voltage input end is connected to the first power supply end VDDH, the second voltage input end is connected to the second power supply end VDDL, and the second PAM4 type current signal is output to the push-pull driving module 108 via the high-pass filter module 106; the pre-driving module 109, the input end of the pre-driving module 109 is connected to the output end of the low-pass filter module 107, and the pre-driving module 109 includes a third voltage input end and a fourth voltage input end. The first input terminal is connected to the second power supply terminal VDDL, the second voltage input terminal is grounded, and the second PAM4 current signal is output to the pre-driver module 109 via the low-pass filter module 107. The pre-driver module 109 is used to receive the current signal output by the low-pass filter module 107 and adjust the linear gain and high-frequency equalization capability to form a balanced current. The second current summing module 110 is connected to the output terminal of the pre-driver module 109 and the output terminal of the push-pull driver module 108. The second current summing module 110 is used to sum the current signal output by the pre-driver module 109 and the current signal output by the push-pull driver module 108 to output a third PAM4 current signal to drive the laser.

[0084] In the embodiment, the asymmetric amplification module can alleviate the nonlinear relaxation effect when outputting the PAM4 type current signal to the laser, and can also compensate for the bandwidth loss on the circuit transmission path. In addition, due to the equalization effect of the pre-driver module 109, the push-pull driver module 108 and the asymmetric feedforward amplification module 104, the ringing phenomenon caused by the complex conjugate pole of the third PAM4 type current signal output by the second current adding module 110 is improved, and the linearity of the output third PAM4 type current signal is also improved. The pre-driver module 109 can adjust the linearization gain and high-frequency equalization capability to form an equalization current, thereby reducing the bandwidth requirement of the push-pull driver module 108. Further, due to the arrangement of the first current adding module 105 and the second current adding module 110, compared with the prior art laser driving circuit 10 (in the prior art, the PAM4 type current signal conversion is only performed at the anode of the laser), the PAM4 type current signal conversion can be performed at the output end of the asymmetric feedforward amplification module 104, and the large-capacitance load at the output end (the first current adding module 105 and the second current adding module 110) is shared through the summation node. The parasitic capacitance of the driving circuit 10 itself is reduced when outputting the third PAM4 type current signal, avoiding the concentration of large loads at the output end of the second current adding module 110, thereby significantly reducing the power consumption of the driving circuit 10. Therefore, the driving circuit 10 requires lower power consumption when performing linear compensation and bandwidth compensation, i.e., the driving circuit 10 improves the energy efficiency of the transmitter architecture while ensuring the quality of the output signal.

[0085] Here, it should be pointed out that the description of the above transmitter architecture embodiment is similar to the description of the above driving circuit 10 for a laser in a transmitter embodiment, and has similar beneficial effects as the above driving circuit 10 for a laser in a transmitter. For technical details not disclosed in the transmitter architecture embodiment, please refer to the description of the driving circuit 10 for a laser in a transmitter embodiment of the present application.

[0086] In summary, the present application provides a driving circuit 10 for a laser in a transmitter and a transmitter architecture, which has the following beneficial effects:

[0087] The asymmetric amplification module can alleviate the nonlinear relaxation effect when outputting the PAM4 type current signal to the laser, and can also compensate the bandwidth loss on the circuit transmission path. In addition, due to the equalization effect of the pre-driver module 109, the push-pull driver module 108 and the asymmetric feedforward amplification module 104, the ringing phenomenon caused by the complex conjugate pole of the third PAM4 type current signal output by the second current adding module 110 is improved, and the linearity of the output third PAM4 type current signal is also improved. The pre-driver module 109 can adjust the linearization gain and high-frequency equalization capability to form an equalization current, thereby reducing the bandwidth requirement of the push-pull driver module 108. Further, due to the setting of the first current adding module 105 and the second current adding module 110, compared with the prior art laser driving circuit 10 (in the prior art, the PAM4 type current signal conversion is only performed at the anode of the laser), the PAM4 type current signal conversion can be performed at the output end of the asymmetric feedforward amplification module 104, and the large capacitance load of the output end (the first current adding module 105 and the second current adding module 110) is shared through the summation node, so that the parasitic capacitance of the driving circuit 10 itself is reduced when outputting the third PAM4 type current signal, avoiding the concentration of large load at the output end of the second current adding module 110, thereby significantly reducing the power consumption of the driving circuit 10. Therefore, it can be seen that the driving circuit 10 needs to reduce the power consumption when performing linear compensation and bandwidth compensation, and solve the problem of deteriorating linearity caused by linear compensation, bandwidth compensation, laser power saturation phenomenon and device relaxation effect.

[0088] It can be understood that the above embodiments only express the preferred embodiments of the present application, and the description is more specific and detailed, but it cannot be understood as a limitation on the scope of the patent of the present application; it should be pointed out that for ordinary skilled in the art, the above technical features can be freely combined without departing from the concept of the present application, and several modifications and improvements can be made, which belong to the protection scope of the present application; therefore, any equivalent transformation and modification within the scope of the claims of the present application shall belong to the scope of the claims of the present application.

Claims

1. A driving circuit for a laser in a transmitter, characterized in that: include: Transcoding module, used to convert binary code into three-way temperature code; a retiming module connected to the transcoding module, the retiming module being configured to receive the three temperature codes and retime the three temperature codes to reduce jitter of the temperature codes converted by the transcoding module; A pulse generating module connected to the retiming module, the pulse generating module is used to receive the three retimed temperature codes and generate three timing pulse signals for feedforward equalization; an asymmetric feedforward amplification module, connected to the pulse generation module, and configured to adjust the heights of the three timing pulse signals to output a first PAM4 current signal; a first current summing module, connected to the asymmetric feedforward amplification module, configured to receive the first PAM4 current signal output by the asymmetric feedforward amplification module and sum and output a second PAM4 current signal; a high-pass filtering module, wherein an input end of the high-pass filtering module is connected to the first current summing module; a low-pass filtering module, wherein an input end of the low-pass filtering module and an input end of the high-pass filtering module are connected to the first current summing module; A push-pull driving module, wherein the input end of the push-pull driving module is connected to the output end of the high-pass filtering module, the push-pull driving module includes a first voltage input end and a second voltage input end, the first voltage input end is connected to the first power supply end, the second voltage input end is connected to the second power supply end, and the second PAM4 current signal is output to the push-pull driving module via the high-pass filtering module; a pre-driver module, wherein the input end of the pre-driver module is connected to the output end of the low-pass filter module, the pre-driver module includes a third voltage input end and a fourth voltage input end, the third voltage input end is connected to the second power supply end, and the fourth voltage input end is grounded. The second PAM4 type current signal is output to the pre-driver module via the low-pass filter module, and the pre-driver module is configured to receive the current signal output by the low-pass filter module and adjust the linearization gain and high-frequency equalization capability to form a balanced current; A second current summing module is connected to the output end of the pre-driving module and the output end of the push-pull driving module. The second current summing module is used to add the current signal output by the pre-driving module and the current signal output by the push-pull driving module to output a third PAM4 current signal to drive the laser.

2. The driving circuit for a laser in a transmitter according to claim 1, characterized in that: The asymmetric feedforward amplification module includes: a high path slice, a middle path slice and a low path slice respectively connected to the pulse generation module; The high path slice, the middle path slice, and the low path slice are further connected to the first current summing module respectively.

3. The driving circuit for a laser in a transmitter according to claim 2, characterized in that: The first current summing module includes: a first resistor, one end of the first resistor is connected to the high path slice, the middle path slice and the low path slice, and the other end of the first resistor is connected to the input end of the high-pass filtering module and the input end of the low-pass filtering module.

4. The driving circuit for a laser in a transmitter according to claim 1, characterized in that: The second current summing module includes: a second resistor, one end of the second resistor is connected to the output end of the push-pull driving module and the output end of the pre-driving module, and one end of the second resistor is connected to the laser.

5. The driving circuit for a laser in a transmitter according to claim 1, characterized in that: The push-pull driving module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first inductor, a second inductor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first current source, and a load matching unit; The gate of the first transistor is connected to one end of the third resistor and one end of the first capacitor, the drain of the first transistor is connected to the first power supply end, and the source of the first transistor is connected to the drain of the third transistor; The gate of the third transistor is connected to one end of the second capacitor and one end of the fourth resistor, and the source of the third transistor is connected to one end of the first current source; The drain of the second transistor is connected to the first power supply terminal, the gate of the second transistor is connected to one end of the fifth resistor and one end of the third capacitor, and the source of the second transistor is connected to one end of the first inductor; The drain of the fourth transistor is connected to one end of the second inductor, the gate of the fourth transistor is connected to one end of the sixth resistor and one end of the fourth capacitor, and the source of the fourth transistor is connected to the source of the third transistor; One end of the load matching unit is connected to the connection end of the source of the first transistor and the drain of the third transistor, and the other end of the load matching unit is connected to the second power supply end; The other end of the third resistor and the other end of the fifth resistor are connected to the first bias voltage output terminal, the other end of the fourth resistor and the other end of the sixth resistor are connected to the second bias voltage output terminal, and the other end of the first current source is connected to the second power supply terminal; The other end of the first capacitor, the other end of the second capacitor, the other end of the third capacitor, and the other end of the fourth capacitor are connected to the output end of the high-pass filtering module; The other end of the first inductor is connected to the other end of the second inductor, wherein one end where the first inductor is connected to the second inductor is the output end of the push-pull driving module.

6. The driving circuit for a laser in a transmitter according to claim 5, characterized in that: The load matching unit includes: a seventh resistor and a fifth capacitor, one end of the fifth capacitor is connected to the connection end of the source of the first transistor and the drain of the third transistor, the other end of the fifth capacitor is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the second power supply end.

7. The driving circuit for a laser in a transmitter according to claim 5 or 6, characterized in that: The pre-driver module includes: an eighth resistor, a ninth resistor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a fifth transistor, a sixth transistor, a second current source, a third current source, and an RC network; One end of the eighth resistor is connected to the second power supply end, the other end of the eighth resistor is connected to one end of the third inductor, the other end of the third inductor is connected to one end of the fourth inductor, the other end of the fourth inductor is connected to the drain of the fifth transistor, the gate of the fifth transistor is connected to the output end of the low-pass filter module, and the source of the fifth transistor is connected to one end of the second current source; One end of the ninth resistor is connected to the second power supply end, the other end of the ninth resistor is connected to one end of the fifth inductor, the other end of the fifth inductor is connected to one end of the sixth inductor, the other end of the sixth inductor is connected to the drain of the sixth transistor, the gate of the sixth transistor is connected to the output end of the low-pass filter module, and the source of the sixth transistor is connected to one end of the third current source; The other ends of the second current source and the third current source are grounded, one end of the RC network is connected to the source of the fifth transistor, and the other end of the RC network is connected to the source of the sixth transistor; One end of the third inductor connected to the fourth inductor and one end of the fifth inductor connected to the sixth inductor serve as output ends of the pre-driver module.

8. The driving circuit for a laser in a transmitter according to claim 1, characterized in that: The second power supply end is an output end of a low voltage drop linear regulator.

9. The driving circuit for a laser in a transmitter according to claim 1, characterized in that: The driving circuit further includes a parasitic inductance suppression module, which is connected to the second current summing module and the laser.

10. A transmitter architecture, characterized in that At least: A laser and a driving circuit for a laser in a transmitter according to any one of claims 1 to 9, wherein the driving circuit is connected to the laser.

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