Driving circuit of BOOST circuit and power tube

Abstract

The invention provides a BOOST circuit and a driving circuit of a power tube, a driving control signal generation unit in the driving circuit is used for generating a first driving control signal and a second driving control signal according to an input signal and a power supply signal, and the rising edge of the first driving control signal is the same as the rising edge of the second driving control signal. The falling edge of the first driving control signal is later than the falling edge of the second driving control signal, and the second driving control signal is an inverted signal of the input signal; the slow charging driving unit is used for generating a slow charging driving signal according to the first driving control signal, the second driving control signal and the power supply signal and outputting the slow charging driving signal to the grid of the power tube; and the fast charge driving unit is used for generating a fast charge driving signal according to the first driving control signal, the second driving control signal and the power supply signal and outputting the fast charge driving signal to a grid electrode of the power tube. The problem that the performance of the BOOST circuit is badly influenced by overhigh ground burr voltage of an existing driving circuit is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a BOOST voltage-boosting circuit and a driving circuit for a power tube. Background Art

[0002] The BOOST boost circuit is a switching DC boost circuit that can convert the input voltage into a higher output voltage. Due to its high output efficiency, good stability and boost capability, the BOOST boost circuit is considered the first choice for power supply systems in automotive electronic equipment, used to convert battery voltage into a higher voltage to meet the high voltage requirements of automotive electronic equipment.

[0003] The drive circuit is an essential part of the BOOST boost circuit. However, the existing commonly used drive circuit technology also brings a negative impact, that is, the ground glitch voltage is too high. A large ground glitch voltage will not only affect the performance of the BOOST boost circuit, but also cause a latch effect in severe cases, causing permanent damage to the chip. Summary of the invention

[0004] In this regard, the present application provides a BOOST boost circuit and a power tube driving circuit to solve the problem that the high ground burr voltage of the existing driving circuit has an adverse effect on the performance of the BOOST boost circuit.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0006] The first aspect of the present application discloses a driving circuit of a power tube, comprising: a driving control signal generating unit, a slow charging driving unit and a fast charging driving unit;

[0007] The driving control signal generating unit is used to generate a first driving control signal and a second driving control signal according to an input signal and a power supply signal, wherein a rising edge of the first driving control signal is the same as a rising edge of the second driving control signal, a falling edge of the first driving control signal is later than a falling edge of the second driving control signal, and the second driving control signal is an inverted signal of the input signal;

[0008] The slow charge driving unit is used to generate a slow charge driving signal according to the first driving control signal, the second driving control signal and the power supply signal, and output the slow charge driving signal to the gate of the power tube;

[0009] The fast charge driving unit is used to generate a fast charge driving signal according to the first drive control signal, the second drive control signal and the power supply signal, and output it to the gate of the power tube.

[0010] Optionally, in the above-mentioned driving circuit of the power tube, the driving control signal generating unit includes: an inverting unit and a signal delay generating unit, the signal delay generating unit includes at least one of a first signal delay generating unit, a second signal delay generating unit, a third signal delay generating unit and a fourth signal delay generating unit, and the first signal delay generating unit, the second signal delay generating unit, the third signal delay generating unit and the fourth signal delay generating unit are cascaded in sequence;

[0011] The inverting unit is used to generate an inverted signal of the input signal;

[0012] The signal delay generating unit is used to generate the first driving control signal according to the inverted signal of the input signal and the power signal.

[0013] Optionally, in the above-mentioned driving circuit of the power tube, the inverting unit includes: a first inverter, an input end of the first inverter receives the input signal, and an output end of the first inverter outputs an inverted signal of the input signal.

[0014] Optionally, in the above-mentioned power tube driving circuit, the first signal delay generating unit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube, and a second NMOS tube;

[0015] The gate of the first NMOS tube serves as the input end of the first signal delay generating unit; the source of the first NMOS tube is respectively connected to the source of the second NMOS tube and the drain of the second NMOS tube, and the connection point is grounded; the drain of the first NMOS tube is respectively connected to the gate of the second NMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube, the gate of the fourth PMOS tube, the gate of the fifth PMOS tube and the drain of the fifth PMOS tube, and the connection point serves as the output end of the first signal delay generating unit;

[0016] The source of the first PMOS tube receives the power signal; the drain of the first PMOS tube is connected to the source of the second PMOS tube; the drain of the second PMOS tube is connected to the source of the third PMOS tube; the drain of the third PMOS tube is connected to the source of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube.

[0017] Optionally, in the above-mentioned power tube driving circuit, the second signal delay generating unit includes: a sixth PMOS tube, a seventh PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube;

[0018] The gate of the sixth PMOS tube is respectively connected to the gate of the third NMOS tube, the gate of the fourth NMOS tube, the gate of the fifth NMOS tube, the gate of the sixth NMOS tube and the gate of the seventh NMOS tube, and the connection point serves as the input end of the second signal delay generating unit;

[0019] The source of the sixth PMOS tube is respectively connected to the source of the seventh PMOS tube and the drain of the seventh PMOS tube, and the connection points receive the power signal;

[0020] The drain of the sixth PMOS tube is respectively connected to the gate of the seventh PMOS tube and the drain of the third NMOS tube, and the connection point serves as the output end of the second signal delay generating unit;

[0021] The source of the third NMOS tube is connected to the drain of the fourth NMOS tube; the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube; the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube; the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube; the source of the seventh NMOS tube is grounded.

[0022] Optionally, in the above-mentioned power tube driving circuit, the third signal delay generating unit includes: an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube and an eighth NMOS tube;

[0023] The gate of the eighth PMOS tube is respectively connected to the gate of the ninth PMOS tube, the gate of the tenth PMOS tube, the gate of the eleventh PMOS tube, the gate of the twelfth PMOS tube and the gate of the eighth NMOS tube, and the connection points serve as the input end of the third signal delay generating unit;

[0024] The source of the eighth PMOS tube receives the power signal; the drain of the eighth PMOS tube is connected to the source of the ninth PMOS tube; the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube; the drain of the tenth PMOS tube is connected to the source of the eleventh PMOS tube; the drain of the eleventh PMOS tube is connected to the source of the twelfth PMOS tube; the drain of the twelfth PMOS tube is connected to the drain of the eighth NMOS tube, and the connection point serves as the output end of the third signal delay generating unit; the source of the eighth NMOS tube is grounded.

[0025] Optionally, in the above-mentioned power tube driving circuit, the fourth signal delay generating unit includes: a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth NMOS tube and a tenth NMOS tube;

[0026] The gate of the thirteenth PMOS tube is respectively connected to the gate of the fourteenth PMOS tube, the gate of the ninth NMOS tube and the gate of the tenth NMOS tube, and the connection point serves as the input end of the fourth signal delay generating unit;

[0027] The source of the thirteenth PMOS tube receives the power signal;

[0028] The drain of the thirteenth PMOS tube is connected to the source of the fourteenth PMOS tube; the drain of the fourteenth PMOS tube is connected to the drain of the ninth NMOS tube, and the connection point serves as the output end of the fourth signal delay generating unit;

[0029] The source of the ninth NMOS tube is connected to the drain of the tenth NMOS tube; the source of the tenth NMOS tube is grounded.

[0030] Optionally, in the above-mentioned driving circuit of the power tube, the slow charge driving unit includes: a second inverter, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube and a sixteenth NMOS tube;

[0031] The input end of the second inverter serves as the first input end of the buffer charge driving unit to receive the second driving control signal; the output end of the second inverter is respectively connected to the gate of the eleventh NMOS tube, the gate of the thirteenth NMOS tube, the gate of the fourteenth NMOS tube, the gate of the fifteenth NMOS tube and the gate of the sixteenth NMOS tube;

[0032] The gate of the twelfth NMOS tube serves as the second input terminal of the buffer charge driving unit to receive the first driving control signal; the source of the twelfth NMOS tube is connected to the drain of the thirteenth NMOS tube; the source of the thirteenth NMOS tube is connected to the drain of the fourteenth NMOS tube; the source of the fourteenth NMOS tube is connected to the drain of the fifteenth NMOS tube; the source of the fifteenth NMOS tube is connected to the drain of the sixteenth NMOS tube; the source of the sixteenth NMOS tube is grounded;

[0033] The drain of the eleventh NMOS tube receives the power signal; the source of the eleventh NMOS tube is connected to the drain of the twelfth NMOS tube, and the connection point serves as the output end of the slow charge driving unit to output the slow charge driving signal.

[0034] Optionally, in the above-mentioned driving circuit of the power tube, the fast charging driving unit includes: a fifteenth PMOS tube, a sixteenth PMOS tube and a seventeenth NMOS tube;

[0035] The gate of the fifteenth PMOS tube and the gate of the seventeenth NMOS tube respectively serve as the first input terminal of the fast charge driving unit to receive the second driving control signal;

[0036] The gate of the sixteenth PMOS tube serves as the second input terminal of the fast charge driving unit to receive the first driving control signal;

[0037] The source of the fifteenth PMOS tube receives the power signal; the drain of the fifteenth PMOS tube is connected to the source of the sixteenth PMOS tube; the drain of the sixteenth PMOS tube is connected to the drain of the seventeenth NMOS tube, and the connection point serves as the output end of the fast charging drive unit to output the fast charging drive signal; the source of the seventeenth NMOS tube is grounded.

[0038] The second aspect of the present application discloses a BOOST boost circuit, comprising: an inductor, a capacitor, a resistor, a diode and a power tube;

[0039] One end of the inductor is connected to the power supply voltage input signal, and the other end of the inductor is respectively connected to the anode of the diode and the drain of the power tube; the cathode of the diode is respectively connected to one end of the resistor and one end of the capacitor, and the connection point outputs the power supply voltage output signal; the source of the power tube is respectively connected to the other end of the capacitor and the other end of the resistor, and the connection point is grounded;

[0040] The gate of the power tube is provided with a driving circuit of the power tube as disclosed in any one of the first aspects.

[0041] The present invention provides a driving circuit for a power tube, comprising: a driving control signal generating unit, a slow charging driving unit and a fast charging driving unit; the driving control signal generating unit is used to generate a first driving control signal and a second driving control signal according to an input signal and a power supply signal, the rising edge of the first driving control signal is the same as the rising edge of the second driving control signal, the falling edge of the first driving control signal is later than the falling edge of the second driving control signal, and the second driving control signal is an inverted signal of the input signal; the slow charging driving unit is used to generate a slow charging driving signal according to the first driving control signal, the second driving control signal and the power supply signal, and output it to the gate of the power tube; the fast charging driving unit is used to generate a fast charging driving signal according to the first driving control signal, the second driving control signal and the power supply signal, and output it to the gate of the power tube. Since the slow charging driving unit can avoid sudden current changes on the power tube, and the fast driving unit can control the rapid rise of the gate potential of the power tube, sufficient driving capability can be ensured while reducing the ground glitch voltage, thereby solving the problem that the high ground glitch voltage of the existing driving circuit has an adverse effect on the performance of the BOOST boost circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0043] Figure 1 A schematic diagram of an existing BOOST boost circuit provided in an embodiment of the present application;

[0044] Figure 2 A schematic diagram of an existing power tube driving circuit provided in an embodiment of the present application;

[0045] Figure 3 A schematic diagram of the structure of a power tube driving circuit provided in an embodiment of the present application;

[0046] Figure 4 A schematic diagram of the structure of a drive control signal generating unit provided in an embodiment of the present application;

[0047] Figure 5 A circuit diagram of a power tube driving circuit provided in an embodiment of the present application;

[0048] Figure 6 A timing diagram of a first driving control signal and a second driving control signal provided in an embodiment of the present application;

[0049] Figure 7A time domain waveform diagram of an input signal corresponding to a driving circuit of a power tube and a control signal of the power tube provided in an embodiment of the present application;

[0050] Figure 8 A time domain waveform comparison diagram provided in an embodiment of the present application;

[0051] Fig. 9 A schematic diagram of a BOOST boost circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] like Figure 1 As shown in the figure, in order to ensure that the output power can provide sufficient load capacity in the BOOST boost circuit, the area of ​​the power tube is usually very large, so a large current is required to drive the power tube on and off, and a simple logic signal cannot drive the power tube. The main purpose of the drive circuit is to improve the driving ability of the logic signal so that the power tube can be turned on and off faster.

[0054] In the existing BOOST boost circuits, most use a multi-stage cascade of inverters with gradually increasing sizes to drive the gate of the power tube, such as Figure 2 As shown. Figure 2 The driving method shown can provide sufficient driving capability, but due to the gradual enhancement of the inverter driving capability, the edge time of the control signal (Vout) of the power tube will be very short, that is, the flipping speed of the control signal is very fast, which will cause a sudden change in the current in the power tube. Since there is a parasitic inductance on the bonding line (chip bonding wire) between the ground inside the chip of the power tube and the ground of the PCB board, the sudden change in current will generate a glitch voltage on the parasitic inductance. Excessive glitch voltage will affect the performance of the analog circuit. In severe cases, it will cause a latch effect, causing permanent damage to the chip of the power tube.

[0055] Based on this, the present application provides a BOOST boost circuit and a power tube driving circuit to solve the problem that the high ground burr voltage of the existing driving circuit has an adverse effect on the performance of the BOOST boost circuit.

[0056] See also Figure 3 , the driving circuit of the power tube mainly includes: a driving control signal generating unit 101, a slow charging driving unit 102 and a fast charging driving unit 103;

[0057] The driving control signal generating unit 101 is used to generate a driving control signal according to an input signal ( Figure 5 Vin) and power signal ( Figure 5 AVDD in) generates a first drive control signal ( Figure 5 VCT_1 in the control signal and the second drive control signal ( Figure 5 VCT_2 in the input signal, the rising edge of the first drive control signal is the same as the rising edge of the second drive control signal, the falling edge of the first drive control signal is later than the falling edge of the second drive control signal, and the second drive control signal is an inverted signal of the input signal;

[0058] In practical applications, the power supply signal can be an analog voltage signal, which is mainly used to power transistors and triodes in the driving circuit to realize the driving function of the power tube. The input signal is generally a PWM signal.

[0059] In some embodiments, Figure 4 As shown, the driving control signal generating unit 101 mainly includes: an inverting unit 1021 and a signal delay generating unit 1022, the signal delay generating unit 1022 includes at least one of a first signal delay generating unit, a second signal delay generating unit, a third signal delay generating unit and a fourth signal delay generating unit, and the first signal delay generating unit, the second signal delay generating unit, the third signal delay generating unit and the fourth signal delay generating unit are cascaded in sequence;

[0060] The inverting unit 1021 is used to generate an inverted signal of the input signal;

[0061] Combination Figure 5 In some embodiments, the inverting unit 1021 mainly includes: a first inverter I1, an input end of the first inverter I1 receives an input signal, and an output end of the first inverter I1 outputs an inverted signal of the input signal.

[0062] It should be noted that the inverting unit 1021 is mainly used to generate an inverted signal of the input signal. In practice, the input signal can be processed by an inverter to obtain the inverted signal of the input signal; of course, it is not limited to this. The input signal can also be processed by other existing logic devices to obtain the inverted signal of the input signal. The present application does not limit the specific devices included in the inverting unit 1021, and they are all within the protection scope of the present application.

[0063] The signal delay generating unit 1022 is used to generate a first driving control signal according to an inverted signal of an input signal and a power signal.

[0064] In some embodiments, Figure 5As shown, the first signal delay generating unit may include: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first NMOS transistor NM1, and a second NMOS transistor NM2;

[0065] The gate of the first NMOS transistor NM1 serves as the input end of the first signal delay generating unit; the source of the first NMOS transistor NM1 is respectively connected to the source of the second NMOS transistor NM2 and the drain of the second NMOS transistor NM2, and the connection point is grounded; the drain of the first NMOS transistor NM1 is respectively connected to the gate of the second NMOS transistor NM2, the gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the gate of the third PMOS transistor PM3, the gate of the fourth PMOS transistor PM4, the gate of the fifth PMOS transistor PM5 and the drain of the fifth PMOS transistor PM5, and the connection point serves as the output end of the first signal delay generating unit;

[0066] The source of the first PMOS tube PM1 receives a power signal; the drain of the first PMOS tube PM1 is connected to the source of the second PMOS tube PM2; the drain of the second PMOS tube PM2 is connected to the source of the third PMOS tube PM3; the drain of the third PMOS tube PM3 is connected to the source of the fourth PMOS tube PM4; the drain of the fourth PMOS tube PM4 is connected to the source of the fifth PMOS tube PM5.

[0067] In practical applications, when only the first signal delay generating unit is set in the signal delay generating unit 1022, the input end of the first signal delay generating unit receives the inverted signal of the input signal, and the output end of the first signal delay generating unit outputs the first drive control signal; when other signal delay generating units are set in addition to the first signal delay generating unit in the signal delay generating unit 1022, the first signal delay generating unit is cascaded with the other signal delay generating units. Exemplarily, the input end of the first signal delay generating unit can receive the inverted signal of the input signal, and the output end of the first signal delay generating unit is connected to the input end of the second signal delay generating unit.

[0068] It should be noted that, by connecting a plurality of PMOS transistors in series and using the second NMOS transistor NM2 as a MOS capacitor, the falling edge of the inverted signal of the input signal is delayed to obtain the first driving control signal.

[0069] It should also be noted that the number of PMOS transistors connected in series in the first signal delay generating unit is not limited to Figure 5 The five shown in the figure can also be set according to actual needs. The present application does not specifically limit the number of PMOS tubes connected in series in the first signal delay generating unit, which are all within the protection scope of the present application.

[0070] In some embodiments, Figure 5 As shown, the second signal delay generating unit includes: a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7;

[0071] The gate of the sixth PMOS transistor PM6 is respectively connected to the gate of the third NMOS transistor NM3, the gate of the fourth NMOS transistor NM4, the gate of the fifth NMOS transistor NM5, the gate of the sixth NMOS transistor NM6 and the gate of the seventh NMOS transistor NM7, and the connection points serve as the input end of the second signal delay generating unit;

[0072] The source of the sixth PMOS transistor PM6 is connected to the source of the seventh PMOS transistor PM7 and the drain of the seventh PMOS transistor PM7 respectively, and the connection points receive a power signal;

[0073] The drain of the sixth PMOS transistor PM6 is respectively connected to the gate of the seventh PMOS transistor PM7 and the drain of the third NMOS transistor NM3, and the connection point serves as the output end of the second signal delay generating unit;

[0074] The source of the third NMOS tube NM3 is connected to the drain of the fourth NMOS tube NM4; the source of the fourth NMOS tube NM4 is connected to the drain of the fifth NMOS tube NM5; the source of the fifth NMOS tube NM5 is connected to the drain of the sixth NMOS tube NM6; the source of the sixth NMOS tube NM6 is connected to the drain of the seventh NMOS tube NM7; the source of the seventh NMOS tube NM7 is grounded.

[0075] In practical applications, when only the second signal delay generating unit is provided in the signal delay generating unit 1022, the input end of the second signal delay generating unit receives the inverted signal of the input signal, and the output end of the second signal delay generating unit outputs the first drive control signal; when other signal delay generating units are provided in addition to the second signal delay generating unit in the signal delay generating unit 1022, the second signal delay generating unit is cascaded with the other signal delay generating units. Exemplarily, the input end of the second signal delay generating unit can be connected to the output end of the first signal delay generating unit, and the output end of the second signal delay generating unit can be connected to the input end of the third signal delay generating unit.

[0076] It should be noted that, by connecting a plurality of NMOS transistors in series and using the seventh PMOS transistor PM7 as a MOS capacitor, the falling edge of the inverted signal of the input signal can be delayed.

[0077] It should also be noted that the number of NMOS transistors connected in series in the second signal delay generating unit is not limited to Figure 5 The 5 shown in the figure can also be set according to actual needs. The present application does not specifically limit the number of NMOS tubes connected in series in the second signal delay generating unit, which are all within the protection scope of the present application.

[0078] In some embodiments, Figure 5 As shown, the third signal delay generating unit includes: an eighth PMOS tube PM8, a ninth PMOS tube PM9, a tenth PMOS tube PM10, an eleventh PMOS tube PM11, a twelfth PMOS tube PM12 and an eighth NMOS tube NM8;

[0079] The gate of the eighth PMOS transistor PM8 is respectively connected to the gate of the ninth PMOS transistor PM9, the gate of the tenth PMOS transistor PM10, the gate of the eleventh PMOS transistor PM11, the gate of the twelfth PMOS transistor PM12 and the gate of the eighth NMOS transistor NM8, and the connection points serve as the input terminals of the third signal delay generating unit;

[0080] The source of the eighth PMOS tube PM8 receives a power signal; the drain of the eighth PMOS tube PM8 is connected to the source of the ninth PMOS tube PM9; the drain of the ninth PMOS tube PM9 is connected to the source of the tenth PMOS tube PM10; the drain of the tenth PMOS tube PM10 is connected to the source of the eleventh PMOS tube PM11; the drain of the eleventh PMOS tube PM11 is connected to the source of the twelfth PMOS tube PM12; the drain of the twelfth PMOS tube PM12 is connected to the drain of the eighth NMOS tube NM8, and the connection point serves as the output end of the third signal delay generating unit; the source of the eighth NMOS tube NM8 is grounded.

[0081] In practical applications, when only the third signal delay generating unit is set in the signal delay generating unit 1022, the input end of the third signal delay generating unit receives the inverted signal of the input signal, and the output end of the third signal delay generating unit outputs the first drive control signal; when other signal delay generating units are set in addition to the third signal delay generating unit in the signal delay generating unit 1022, the third signal delay generating unit is cascaded with the other signal delay generating units. Exemplarily, the input end of the third signal delay generating unit can be connected to the output end of the second signal delay generating unit, and the output end of the third signal delay generating unit outputs the first drive control signal, or connected to the input end of the fourth signal delay generating unit.

[0082] It should be noted that the falling edge of the inverted signal of the input signal can be delayed by connecting a plurality of PMOS transistors in series.

[0083] It should also be noted that the number of PMOS transistors connected in series in the third signal delay generating unit is not limited to Figure 5The 5 shown in the figure can also be set according to actual needs. The present application does not specifically limit the number of PMOS tubes connected in series in the third signal delay generating unit, which are all within the protection scope of the present application.

[0084] In some embodiments, Figure 5 As shown, the fourth signal delay generating unit may include: a thirteenth PMOS transistor PM13, a fourteenth PMOS transistor PM14, a ninth NMOS transistor NM9 and a tenth NMOS transistor NM10;

[0085] The gate of the thirteenth PMOS transistor PM13 is respectively connected to the gate of the fourteenth PMOS transistor PM14, the gate of the ninth NMOS transistor NM9 and the gate of the tenth NMOS transistor NM10, and the connection points serve as the input terminals of the fourth signal delay generating unit;

[0086] The source of the thirteenth PMOS tube PM13 receives the power signal; the drain of the thirteenth PMOS tube PM13 is connected to the source of the fourteenth PMOS tube PM14; the drain of the fourteenth PMOS tube PM14 is connected to the drain of the ninth NMOS tube NM9, and the connection point serves as the output end of the fourth signal delay generating unit;

[0087] The source of the ninth NMOS transistor NM9 is connected to the drain of the tenth NMOS transistor NM10 ; the source of the tenth NMOS transistor NM10 is grounded.

[0088] In practical applications, when only the fourth signal delay generating unit is provided in the signal delay generating unit 1022, the input end of the fourth signal delay generating unit receives the inverted signal of the input signal, and the output end of the fourth signal delay generating unit outputs the first drive control signal; when other signal delay generating units are provided in addition to the fourth signal delay generating unit in the signal delay generating unit 1022, the fourth signal delay generating unit is cascaded with the other signal delay generating units. Exemplarily, the input end of the fourth signal delay generating unit can receive the inverted signal of the input signal or be connected to the output end of the previous delay unit, and the output end of the fourth signal delay generating unit outputs the first drive control signal or is connected to the output end of the next delay unit.

[0089] It should be noted that by connecting a plurality of PMOS transistors in series and connecting a plurality of NMOS transistors in series, the falling edge of the inverted signal of the input signal can be delayed.

[0090] It should also be noted that the number of PMOS transistors and NMOS transistors connected in series in the fourth signal delay generating unit is not limited to Figure 5 The two shown can also be set according to actual needs. The present application does not specifically limit the number of PMOS tubes connected in series in the fourth signal delay generating unit, which are all within the protection scope of the present application.

[0091] Combination Figure 5 Although the structures of the first signal delay generating unit, the second signal delay generating unit, the third signal delay generating unit and the fourth signal delay generating unit are different, they can all delay the falling edge of the inverted signal of the input signal to obtain the first drive control signal. In a specific application, the delay effect of each level is as follows: the first signal delay generating unit> the second signal delay generating unit> the third signal delay generating unit> the fourth signal delay generating unit, that is, the delay effect of the first signal delay generating unit is the most significant, and then gradually decreases.

[0092] It should be noted that in a specific circuit design, you can flexibly select and match the first signal delay generating unit, the second signal delay generating unit, the third signal delay generating unit and the fourth signal delay generating unit, and you only need to ensure that the final falling edge delay time difference between the first drive control signal and the second drive control signal meets the circuit requirements.

[0093] In practical applications, the timing diagram of the first drive control signal and the second drive control signal can be as follows: Figure 6 As shown, the time difference between the falling edge of the second driving control signal and the falling edge of the first driving control signal is t2-t1.

[0094] The slow charge driving unit 102 is used to generate a slow charge driving signal according to the first driving control signal, the second driving control signal and the power supply signal, and output it to the gate of the power tube;

[0095] In practical applications, the slow charge driving unit 102 can be used to control the on and off of the transistors in itself according to the first driving control signal, the second driving control signal and the power supply signal, so as to generate a slow charge driving signal.

[0096] In some embodiments, Figure 5 As shown, the slow charge driving unit 102 may include: a second inverter I2, an eleventh NMOS tube NM11, a twelfth NMOS tube NM12, a thirteenth NMOS tube NM13, a fourteenth NMOS tube NM14, a fifteenth NMOS tube NM15 and a sixteenth NMOS tube NM16;

[0097] The input end of the second inverter I2 is used as the first input end of the buffer charge driving unit 102 to receive the second driving control signal; the output end of the second inverter I2 is respectively connected to the gate of the eleventh NMOS transistor NM11, the gate of the thirteenth NMOS transistor NM13, the gate of the fourteenth NMOS transistor NM14, the gate of the fifteenth NMOS transistor NM15 and the gate of the sixteenth NMOS transistor NM16;

[0098] The gate of the twelfth NMOS tube NM12 serves as the second input terminal of the buffer charge driving unit 102, and receives the first driving control signal; the source of the twelfth NMOS tube NM12 is connected to the drain of the thirteenth NMOS tube NM13; the source of the thirteenth NMOS tube NM13 is connected to the drain of the fourteenth NMOS tube NM14; the source of the fourteenth NMOS tube NM14 is connected to the drain of the fifteenth NMOS tube NM15; the source of the fifteenth NMOS tube NM15 is connected to the drain of the sixteenth NMOS tube NM16; the source of the sixteenth NMOS tube NM16 is grounded;

[0099] The drain of the eleventh NMOS tube NM11 receives the power signal; the source of the eleventh NMOS tube NM11 is connected to the drain of the twelfth NMOS tube NM12, and the connection point serves as the output end of the slow charge driving unit 102 to output the slow charge driving signal.

[0100] In actual applications, since there is a time difference between the falling edge of the first drive control signal and the falling edge of the second drive control signal, the eleventh NMOS tube NM11, the twelfth NMOS tube NM12, the thirteenth NMOS tube NM13, the fourteenth NMOS tube NM14, the fifteenth NMOS tube NM15 and the sixteenth NMOS tube NM16 can be turned on within the time difference period between the falling edge of the first drive control signal and the falling edge of the second drive control signal, forming an effect similar to that of resistance voltage division, and since the output end of the slow charge drive unit 102 is connected to the gate of the power tube, the gate potential of the power tube will slowly rise to an intermediate potential between the power supply signal and the ground within the time difference period between the falling edge of the first drive control signal and the falling edge of the second drive control signal, thereby avoiding sudden current changes on the power tube.

[0101] The fast charge driving unit 103 is used to generate a fast charge driving signal according to the first driving control signal, the second driving control signal and the power supply signal, and output it to the gate of the power tube.

[0102] In practical applications, the fast charge driving unit 103 can be used to control the on and off of the transistors in itself according to the first drive control signal, the second drive control signal and the power supply signal, thereby generating a fast charge driving signal.

[0103] In some embodiments, Figure 5 As shown, the fast charge driving unit 103 may include: a fifteenth PMOS tube PM15, a sixteenth PMOS tube PM16 and a seventeenth NMOS tube NM17;

[0104] The gate of the fifteenth PMOS transistor PM15 and the gate of the seventeenth NMOS transistor NM17 serve as first input terminals of the fast charge driving unit 103 to receive the second driving control signal;

[0105] The gate of the sixteenth PMOS transistor PM16 serves as the second input terminal of the fast charge driving unit 103 to receive the first driving control signal;

[0106] The source of the fifteenth PMOS tube PM15 receives a power signal; the drain of the fifteenth PMOS tube PM15 is connected to the source of the sixteenth PMOS tube PM16; the drain of the sixteenth PMOS tube PM16 is connected to the drain of the seventeenth NMOS tube NM17, and the connection point serves as the output end of the fast charging drive unit 103 to output the fast charging drive signal; the source of the seventeenth NMOS tube NM17 is grounded.

[0107] In practical applications, after the falling edge of the first drive control signal ends, the first drive control signal and the second drive control signal are both at low levels, and the fifteenth PMOS tube PM15 and the sixteenth PMOS tube PM16 are both turned on. During design, the sizes of the fifteenth PMOS tube PM15 and the sixteenth PMOS tube PM16 can be appropriately increased to provide a sufficiently large current to drive the power tube.

[0108] In summary, in the driving circuit of the power tube provided in the present application, the rising process of the gate potential of the power tube is mainly divided into two stages: the first stage is charging through the slow charging driving unit 102. During the charging process of the slow charging driving unit 102, charging is mainly carried out through the branch where the source of the eleventh NMOS tube NM11 and the drain of the twelfth NMOS tube NM12 are located, and the gate potential of the power tube rises slowly, avoiding sudden current changes on the power tube; the second stage is charging through the fast charging driving unit 103. During the fast charging driving unit 103, charging is mainly carried out through the branch where the drain of the sixteenth PMOS tube PM16 and the drain of the seventeenth NMOS tube NM17 are located, which can provide sufficient driving capability for the gate of the power tube to ensure that the gate potential of the power tube rises to a high level.

[0109] It should be noted that in the circuit design process, by properly controlling the time proportion of the two stages, it is possible to ensure that the duty cycle of the PWM signal of the BOOST boost circuit used in the power tube drive circuit meets the requirements and reduce the ground glitch voltage.

[0110] Through the working process of the above circuit, it is ensured that when the control signal output to the power tube is at a high level, the circuit can provide a sufficiently large current to drive the power tube so that its gate potential can rise to a high level to ensure the normal conduction of the power tube. At the same time, it also increases the rising edge time of the control signal of the power tube, avoiding the ground burr voltage process caused by the sudden change of the current on the power tube.

[0111] For example, Figure 5 The time domain waveform diagram of the input signal and the control signal of the power tube in the driving circuit of the power tube shown can be shown as Figure 7 It is worth noting that, through relevant simulation tools, Figure 2 The conventional power tube driving circuit and Figure 5 The driving circuit of the power tube shown in the figure is simulated and compared. Figure 2 The ground burr (pgnd1 waveform) caused by the prior art shown in the figure and the Figure 5 The time domain waveform comparison of the ground burr (pgnd2 waveform) caused by the technology proposed in this application is shown in FIG. Figure 8 As shown, it can be seen that the solution proposed in this application can effectively reduce ground burrs and improve the signal quality of analog circuits.

[0112] The driving circuit of the power tube provided in this embodiment includes: a driving control signal generating unit 101, a slow charging driving unit 102 and a fast charging driving unit 103; the driving control signal generating unit 101 is used to generate a first driving control signal and a second driving control signal according to an input signal and a power supply signal, the rising edge of the first driving control signal is the same as the rising edge of the second driving control signal, the falling edge of the first driving control signal is later than the falling edge of the second driving control signal, and the second driving control signal is an inverted signal of the input signal; the slow charging driving unit 102 is used to generate a slow charging driving signal according to the first driving control signal, the second driving control signal and the power supply signal, and output it to the gate of the power tube; the fast charging driving unit 103 is used to generate a fast charging driving signal according to the first driving control signal, the second driving control signal and the power supply signal, and output it to the gate of the power tube. Since the slow charging driving unit 102 can avoid sudden changes in current on the power tube, and the fast driving unit can control the rapid rise of the gate potential of the power tube, sufficient driving capability can be ensured while reducing the ground glitch voltage, solving the problem that the ground glitch voltage of the existing driving circuit is too high and has an adverse effect on the performance of the BOOST boost circuit.

[0113] Optionally, another embodiment of the present application further provides a BOOST boost circuit, see Fig. 9 , mainly including: inductor L11, capacitor C11, resistor R11, diode D11 and power tube;

[0114] One end of the inductor L11 is connected to the power supply voltage input signal Vddin, and the other end of the inductor L11 is respectively connected to the anode of the diode D11 and the drain of the power tube; the cathode of the diode D11 is respectively connected to one end of the resistor R11 and one end of the capacitor C11, and the connection point outputs the power supply voltage output signal Vddout; the source of the power tube is respectively connected to the other end of the capacitor C11 and the other end of the resistor R11, and the connection point is grounded;

[0115] The gate of the power tube is provided with a driving circuit of the power tube as described in any of the above embodiments.

[0116] In practical applications, the BOOST boost circuit may be a circuit in a boost converter; of course, it is not limited thereto, and may also be determined based on the application environment and user needs, all within the protection scope of this application.

[0117] It is worth noting that with the widespread use of automobiles, users are also paying more and more attention to the safety of drivers and passengers during vehicle driving. Airbags are a passive safety protection system, which, when used in conjunction with seat belts, can provide effective anti-collision protection for passengers. The inventors have found that airbags require effective power supply to achieve normal working processes. How to provide a reliable power supply for airbags has become a technical problem that needs to be solved urgently.

[0118] In this regard, the BOOST boost circuit provided in the present application can be applied to the boost converter in the airbag power system to provide a reliable power supply for the airbag power system, thereby meeting the high voltage requirements of automotive electronics.

[0119] In summary, the BOOST boost circuit provided in this embodiment can ensure that the PWM pulse signal can effectively drive the power tube to be turned on and off, while effectively reducing the ground glitch voltage, thereby ensuring the normal function of the analog circuit and the quality of the output power supply.

[0120] It should be noted that, for the relevant description of the driving circuit of the power tube, please refer to the corresponding embodiment above, and this application will not go into details; for the relevant description of the BOOST boost circuit, please refer to the prior art, and this application will not go into details either.

[0121] The features recorded in the various embodiments in this specification can be replaced or combined with each other, and the same and similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The system and system embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work. Professionals can also further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented in electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0122] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0123] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

Claims

1. A driving circuit for a power tube, characterized in that: include: A driving control signal generating unit, a slow charging driving unit and a fast charging driving unit; The driving control signal generating unit is used to generate a first driving control signal and a second driving control signal according to an input signal and a power supply signal, wherein a rising edge of the first driving control signal is the same as a rising edge of the second driving control signal, a falling edge of the first driving control signal is later than a falling edge of the second driving control signal, and the second driving control signal is an inverted signal of the input signal; The slow charge driving unit is used to generate a slow charge driving signal according to the first driving control signal, the second driving control signal and the power supply signal, and output the slow charge driving signal to the gate of the power tube; The fast charge driving unit is used to generate a fast charge driving signal according to the first drive control signal, the second drive control signal and the power supply signal, and output it to the gate of the power tube.

2. The driving circuit of the power tube according to claim 1, characterized in that: The driving control signal generating unit comprises: an inverting unit and a signal delay generating unit, the signal delay generating unit comprises at least one of a first signal delay generating unit, a second signal delay generating unit, a third signal delay generating unit and a fourth signal delay generating unit, and the first signal delay generating unit, the second signal delay generating unit, the third signal delay generating unit and the fourth signal delay generating unit are cascaded in sequence; The inverting unit is used to generate an inverted signal of the input signal; The signal delay generating unit is used to generate the first driving control signal according to the inverted signal of the input signal and the power signal.

3. The driving circuit of the power tube according to claim 2, characterized in that: The inverting unit includes: a first inverter, an input end of the first inverter receives the input signal, and an output end of the first inverter outputs an inverted signal of the input signal.

4. The driving circuit of the power tube according to claim 2, characterized in that: The first signal delay generating unit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube, and a second NMOS tube; The gate of the first NMOS tube serves as the input end of the first signal delay generating unit; the source of the first NMOS tube is respectively connected to the source of the second NMOS tube and the drain of the second NMOS tube, and the connection point is grounded; the drain of the first NMOS tube is respectively connected to the gate of the second NMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube, the gate of the fourth PMOS tube, the gate of the fifth PMOS tube and the drain of the fifth PMOS tube, and the connection point serves as the output end of the first signal delay generating unit; The source of the first PMOS tube receives the power signal; the drain of the first PMOS tube is connected to the source of the second PMOS tube; the drain of the second PMOS tube is connected to the source of the third PMOS tube; the drain of the third PMOS tube is connected to the source of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube.

5. The driving circuit of the power tube according to claim 2, characterized in that: The second signal delay generating unit includes: a sixth PMOS tube, a seventh PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube; The gate of the sixth PMOS tube is respectively connected to the gate of the third NMOS tube, the gate of the fourth NMOS tube, the gate of the fifth NMOS tube, the gate of the sixth NMOS tube and the gate of the seventh NMOS tube, and the connection point serves as the input end of the second signal delay generating unit; The source of the sixth PMOS tube is respectively connected to the source of the seventh PMOS tube and the drain of the seventh PMOS tube, and the connection points receive the power signal; The drain of the sixth PMOS tube is respectively connected to the gate of the seventh PMOS tube and the drain of the third NMOS tube, and the connection point serves as the output end of the second signal delay generating unit; The source of the third NMOS tube is connected to the drain of the fourth NMOS tube; the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube; the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube; the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube; the source of the seventh NMOS tube is grounded.

6. The driving circuit of the power tube according to claim 2, characterized in that: The third signal delay generating unit includes: an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube and an eighth NMOS tube; The gate of the eighth PMOS tube is respectively connected to the gate of the ninth PMOS tube, the gate of the tenth PMOS tube, the gate of the eleventh PMOS tube, the gate of the twelfth PMOS tube and the gate of the eighth NMOS tube, and the connection points serve as the input end of the third signal delay generating unit; The source of the eighth PMOS tube receives the power signal; the drain of the eighth PMOS tube is connected to the source of the ninth PMOS tube; the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube; the drain of the tenth PMOS tube is connected to the source of the eleventh PMOS tube; the drain of the eleventh PMOS tube is connected to the source of the twelfth PMOS tube; the drain of the twelfth PMOS tube is connected to the drain of the eighth NMOS tube, and the connection point serves as the output end of the third signal delay generating unit; the source of the eighth NMOS tube is grounded.

7. The driving circuit of the power tube according to claim 2, characterized in that: The fourth signal delay generating unit includes: a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth NMOS tube and a tenth NMOS tube; The gate of the thirteenth PMOS tube is respectively connected to the gate of the fourteenth PMOS tube, the gate of the ninth NMOS tube and the gate of the tenth NMOS tube, and the connection point serves as the input end of the fourth signal delay generating unit; The source of the thirteenth PMOS tube receives the power signal; The drain of the thirteenth PMOS tube is connected to the source of the fourteenth PMOS tube; the drain of the fourteenth PMOS tube is connected to the drain of the ninth NMOS tube, and the connection point serves as the output end of the fourth signal delay generating unit; The source of the ninth NMOS tube is connected to the drain of the tenth NMOS tube; the source of the tenth NMOS tube is grounded.

8. The driving circuit of the power tube according to claim 1, characterized in that: The slow charge driving unit comprises: a second inverter, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube and a sixteenth NMOS tube; The input end of the second inverter serves as the first input end of the buffer charge driving unit to receive the second driving control signal; the output end of the second inverter is respectively connected to the gate of the eleventh NMOS tube, the gate of the thirteenth NMOS tube, the gate of the fourteenth NMOS tube, the gate of the fifteenth NMOS tube and the gate of the sixteenth NMOS tube; The gate of the twelfth NMOS tube serves as the second input terminal of the buffer charge driving unit to receive the first driving control signal; the source of the twelfth NMOS tube is connected to the drain of the thirteenth NMOS tube; the source of the thirteenth NMOS tube is connected to the drain of the fourteenth NMOS tube; the source of the fourteenth NMOS tube is connected to the drain of the fifteenth NMOS tube; the source of the fifteenth NMOS tube is connected to the drain of the sixteenth NMOS tube; the source of the sixteenth NMOS tube is grounded; The drain of the eleventh NMOS tube receives the power signal; the source of the eleventh NMOS tube is connected to the drain of the twelfth NMOS tube, and the connection point serves as the output end of the slow charge driving unit to output the slow charge driving signal.

9. The driving circuit of the power tube according to claim 1, characterized in that: The fast charge driving unit includes: a fifteenth PMOS tube, a sixteenth PMOS tube and a seventeenth NMOS tube; The gate of the fifteenth PMOS tube and the gate of the seventeenth NMOS tube respectively serve as the first input terminal of the fast charge driving unit to receive the second driving control signal; The gate of the sixteenth PMOS tube serves as the second input terminal of the fast charge driving unit to receive the first driving control signal; The source of the fifteenth PMOS tube receives the power signal; the drain of the fifteenth PMOS tube is connected to the source of the sixteenth PMOS tube; the drain of the sixteenth PMOS tube is connected to the drain of the seventeenth NMOS tube, and the connection point serves as the output end of the fast charging drive unit to output the fast charging drive signal; the source of the seventeenth NMOS tube is grounded.

10. A BOOST boost circuit, characterized in that: include: Inductors, capacitors, resistors, diodes and power tubes; One end of the inductor is connected to the power supply voltage input signal, and the other end of the inductor is respectively connected to the anode of the diode and the drain of the power tube; the cathode of the diode is respectively connected to one end of the resistor and one end of the capacitor, and the connection point outputs the power supply voltage output signal; the source of the power tube is respectively connected to the other end of the capacitor and the other end of the resistor, and the connection point is grounded; The gate of the power tube is provided with a driving circuit of the power tube as described in any one of claims 1-9.

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