Low-power-consumption control circuit and camera equipment

Abstract

The invention provides a low-power-consumption control circuit and camera equipment, and belongs to the technical field of security equipment circuits. The low-power-consumption control circuit comprises a general control chip U6 which is suitable for controlling the low-power-consumption control circuit to realize time-sharing power supply and timing starting; the first power conversion circuit is suitable for controlling the power supply VCC3V3STB and the power supply 0V9PMUIO to supply power to the master control chip U6; the second power conversion circuit is suitable for controlling the power supply VDDARMNPU and the power supply VCC1V8 to supply power to the master control chip U6; the MOS tube control circuit is suitable for controlling the power supply VDDLOGIC and the power supply VCC3V3 to supply power to the master control chip U6; and the third power conversion circuit is suitable for controlling the power supply VCCDDR to supply power to the master control chip U6. According to the low-power-consumption control circuit provided by the invention, a time-sharing power supply and timed start mode is adopted, high-frequency information acquisition in a dormant state can be realized, the real-time performance and accuracy of the information are ensured, and meanwhile, the system power consumption is greatly reduced by adopting a hot start mode for time-sharing power supply.

Description

Technical Field

[0001] The present application belongs to the technical field of security equipment circuits, and specifically relates to a low-power control circuit and a camera device. Background Art

[0002] In some remote areas and some special application scenarios, it is impossible to set up power supply and network, and conventional network surveillance cameras cannot be used in these scenarios. Therefore, surveillance cameras are required to have battery power supply, solar charging and wireless communication functions. However, such cameras have relatively high power consumption and cannot work continuously. Once they work continuously, the solar energy cannot be charged in time, so all-day recording cannot be achieved and some key information is easily lost.

[0003] At present, the conventional practice is to use a timed start method to achieve low power consumption and ensure that the battery can be used for a long enough time. Generally, 15 days of working time is required. In this way, the equipment will not stop running even if it cannot be charged due to continuous rainy days. In addition, the system generally takes a snapshot every half an hour to obtain information. The time interval of the timed start is long, which will cause information loss and make it impossible to record all day. The integrity of the information is difficult to guarantee. In addition, the timed start is a cold start technology with a long start time, high power consumption, and is not conducive to the timely acquisition of information. Summary of the invention

[0004] In order to solve at least one technical problem existing in the background technology, the present application provides a low-power control circuit, which adopts time-sharing power supply and timed start-up to achieve high-frequency information acquisition in sleep state, thereby ensuring the real-time and accuracy of the information. At the same time, the time-sharing power supply adopts hot start to greatly reduce the system power consumption.

[0005] A second aspect of the present application provides a camera device.

[0006] The technical solution adopted in this application is:

[0007] A first aspect of the present application provides a low power consumption control circuit, including:

[0008] The master control chip U6 is suitable for controlling the low-power control circuit to realize time-sharing power supply and timed start;

[0009] A first power conversion circuit, adapted to control the power supply VCC3V3_STB and the power supply 0V9_PMUIO to supply power to the master control chip U6;

[0010] A second power conversion circuit, adapted to control the power supply VDD_ARM_NPU and the power supply VCC_1V8 to supply power to the master control chip U6;

[0011] MOS tube control circuit, suitable for controlling power supply VDD_LOGIC and power supply VCC_3V3 to supply power to the master control chip U6;

[0012] The third power conversion circuit is adapted to control the power source VCC_DDR to supply power to the master control chip U6.

[0013] According to the low-power control circuit provided by the embodiment of the first aspect of the present application, the master control chip U6 controls the entire low-power control circuit to realize time-sharing power supply and timed start-up. It can coordinate the working status of each power module and adjust the power supply strategy according to different working modes. The first power conversion circuit is responsible for outputting the two groups of power supplies VCC3V3_STB and 0V9_PMUIO to power the master control chip U6, wherein these two power supplies do not require additional control and are always in the on state to support basic system operation. The second power conversion circuit is responsible for outputting the two groups of power supplies VDD_ARM_NPU and VCC_1V8 to power the master control chip U6. The on and off of these two power supplies are determined by the control signal SOC_PWREN of the master control chip U6, realizing time-sharing power supply. The MOS tube control circuit controls the power on and off of the two groups of power supplies VDD_LOGIC and VCC_3V3 to realize the power supply to the master control chip U6. This part of the circuit allows unnecessary power supplies to be turned off in the sleep state to reduce power consumption. The third power conversion circuit is responsible for outputting the VCC_DDR power supply to supply power to the master control chip U6. Even in the sleep state, this power supply continues to supply power to support memory self-refresh and fast startup. In summary, the low-power control circuit provided by the first aspect of the present application adopts the time-sharing power supply and timed start-up method, which can achieve high-frequency information acquisition in the sleep state, ensuring the real-time and accuracy of the information. At the same time, the time-sharing power supply adopts the hot start method to greatly reduce the power consumption of the system.

[0014] According to an embodiment of the present application, the first power conversion circuit includes a first chip U1, a second chip U2, a resistor R2 and a resistor R5, the 4 pins of the first chip U1 and the second chip U2 are connected to the power supply, the 1 pin of the first chip U1 is connected to the power input circuit through the resistor R2, and the 1 pin of the second chip U2 is connected to the power input circuit through the resistor R5;

[0015] The second power conversion circuit includes a third chip U3 and a fourth chip U4, and pins 2 of the third chip U3 and the fourth chip U4 are connected to pin 34 SOC_PWREN of the master control chip U6;

[0016] The MOS tube control circuit includes a first control circuit Q1 and a second control circuit Q2_Q3, wherein the first control circuit Q1 is suitable for controlling the power supply VDD_LOGIC to supply power to the master control chip U6, and the second control circuit Q2_Q3 is suitable for controlling the power supply VCC_3V3 to supply power to the master control chip U6;

[0017] The third power conversion circuit includes a fifth chip U5 and a resistor R27 , and pin 1 of the fifth chip U5 is connected to the power input circuit through the resistor R27 .

[0018] According to an embodiment of the present application, pin 4 of the first chip U1 and the second chip U2 is a power input pin, and pin 1 of the first chip U1 and the second chip U2 is an enable pin.

[0019] According to an embodiment of the present application, pin 2 of the third chip U3 and the fourth chip U4 are enable control pins.

[0020] According to one embodiment of the present application, pin 3 of the first control circuit Q1 is connected to the power supply 0V9_PMUIO, pin 1 of the first control circuit Q1 is connected to the SOC_PWREN pin of the master control chip U6, and pin 2 of the first control circuit Q1 is connected to the power supply VDD_LOGIC.

[0021] According to an embodiment of the present application, the second control circuit Q2_Q3 includes a control circuit Q2 and a control circuit Q3, and pin 1 of the control circuit Q3 is connected to the power supply VCC_1V8.

[0022] According to one embodiment of the present application, pin 3 of the first control circuit Q1 is a power input pin, pin 1 of the first control circuit Q1 is a control pin, pin 2 of the first control circuit Q1 is an output pin, and pin 1 of the control circuit Q3 is a control pin.

[0023] According to an embodiment of the present application, when the SOC_PWREN is at a high level, the power supply VDD_LOGIC has an output, and when the SOC_PWREN is at a low level, the power supply VDD_LOGIC has no output.

[0024] According to one embodiment of the present application, pin 1 of the fifth chip U5 is a control pin.

[0025] A second aspect of the present application provides an imaging device, comprising the low power consumption control circuit in any one of the embodiments of the first aspect as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0027] Figure 1 A schematic diagram of the arrangement structure of the first chip U1 and its surroundings of the first power conversion circuit provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of the arrangement structure of the second chip U2 and its surroundings of the first power conversion circuit provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the arrangement structure of the third chip U3 and its surroundings of the second power conversion circuit provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of the arrangement structure of the fourth chip U4 and its surroundings of the second power conversion circuit provided in an embodiment of the present application;

[0031] Figure 5 A schematic diagram of the arrangement structure of the MOS tube control circuit provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of the arrangement structure of the fifth chip U5 and its surroundings of the third power conversion circuit provided in an embodiment of the present application;

[0033] Figure 7 A schematic diagram of the structure of the master control chip U6 provided in an embodiment of the present application;

[0034] Figure 8 A control logic diagram of a low power consumption control circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to more clearly illustrate the overall concept of the present application, a detailed description is given below in an illustrative manner in conjunction with the accompanying drawings.

[0036] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present application is not limited by the specific embodiments disclosed below. It should be noted that the embodiments of the present application and the features in each embodiment may be combined with each other without conflict.

[0037] In addition, in the description of the present application, it should be understood that the orientations or positional relationships indicated by the terms "top", "bottom", "inside", "outside", "axial", "radial", "circumferential", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0038] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0039] In the present application, unless otherwise clearly specified and limited, a first feature "above" or "below" a second feature may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in an appropriate manner in any one or more embodiments or examples.

[0040] like Figures 1 to 7 As shown, the first aspect of the present application provides a low-power control circuit, including a master control chip U6, which is suitable for controlling the low-power control circuit to realize time-sharing power supply and timed start; a first power conversion circuit, suitable for controlling the power supply VCC3V3_STB and the power supply 0V9_PMUIO to supply power to the master control chip U6; a second power conversion circuit, suitable for controlling the power supply VDD_ARM_NPU and the power supply VCC_1V8 to supply power to the master control chip U6; a MOS tube control circuit, suitable for controlling the power supply VDD_LOGIC and the power supply VCC_3V3 to supply power to the master control chip U6; a third power conversion circuit, suitable for controlling the power supply VCC_DDR to supply power to the master control chip U6.

[0041] The master control chip U6 is responsible for outputting control signals to control the time of time-sharing power supply, the time of scheduled start, etc. It can also run artificial intelligence detection algorithms, image acquisition programs, etc.

[0042] like Figure 8 Specifically, the control logic of the low power consumption control circuit provided in the embodiment of the present application is:

[0043] At the beginning of work, the power supply VCC3V3_STB and the power supply 0V9_PMUIO are powered on first, and then the system sets the control pin SOC_PWREN of the master control chip U6 to a high level, and other power supplies VDD_LOGIC, VDD_ARM_NPU, VCC_DDR, VCC_1V8, and VCC_3V3 start to power on. The power-on sequence is controlled by the RC circuit to ensure that the system initialization is completed and starts to work normally.

[0044] After power-on, the program is loaded and the system enters a low-power sleep state, but it does not stop working. It switches between sleep and working states. At this time, the circuit can power some circuits in time-sharing mode. The power supplies VCC3V3_STB, 0V9_PMUIO and VCC_DDR are powered to ensure basic system operation. The control pin SOC_PWEREN switches between high and low levels. When the power supply is high, the power supply VDD_LOGIC and other power supplies work, and when the power supply is low, the power supply is turned off. In this way, the system starts regularly, captures image sensor data once a second and saves it. In this process, artificial intelligence algorithms are used to determine whether an event occurs. If an event occurs, the circuit will be fully powered, and the system will record the event information completely. If there is no event, it will continue to work in a one-second one-frame time-lapse recording mode.

[0045] The low power state is a special state that is not used most of the time. Only when the battery power is lower than the threshold, the circuit will enable this state. At this time, the time-sharing power supply logic will be cancelled, and only the power supply VCC3V3_STB and the power supply 0V9_PMUIO will be retained to maintain the system's minimum power consumption. The SOC_POWER pin outputs a low level, and the other power supplies are not powered. At the same time, timed start is used to save power consumption.

[0046] According to the low-power control circuit provided by the embodiment of the first aspect of the present application, the master control chip U6 controls the entire low-power control circuit to realize time-sharing power supply and timed start-up. It can coordinate the working status of each power module and adjust the power supply strategy according to different working modes. The first power conversion circuit is responsible for outputting the two groups of power supplies VCC3V3_STB and 0V9_PMUIO to power the master control chip U6, wherein these two power supplies do not require additional control and are always in the on state to support basic system operation. The second power conversion circuit is responsible for outputting the two groups of power supplies VDD_ARM_NPU and VCC_1V8 to power the master control chip U6. The on and off of these two power supplies are determined by the control signal SOC_PWREN of the master control chip U6, realizing time-sharing power supply. The MOS tube control circuit controls the power on and off of the two groups of power supplies VDD_LOGIC and VCC_3V3 to realize the power supply to the master control chip U6. This part of the circuit allows unnecessary power supplies to be turned off in the sleep state to reduce power consumption. The third power conversion circuit is responsible for outputting the VCC_DDR power supply to supply power to the master control chip U6. Even in the sleep state, this power supply continues to supply power to support memory self-refresh and fast startup. In summary, the low-power control circuit provided by the first aspect of the present application adopts the time-sharing power supply and timed start-up method, which can achieve high-frequency information acquisition in the sleep state, ensuring the real-time and accuracy of the information. At the same time, the time-sharing power supply adopts the hot start method to greatly reduce the power consumption of the system.

[0047] like Figures 1 to 7 As shown, in some embodiments of the present application, the first power conversion circuit includes a first chip U1, a second chip U2, a resistor R2 and a resistor R5, the 4 pins of the first chip U1 and the second chip U2 are connected to the power supply, the 1 pin of the first chip U1 is connected to the power input circuit through the resistor R2, and the 1 pin of the second chip U2 is connected to the power input circuit through the resistor R5;

[0048] The second power conversion circuit includes a third chip U3 and a fourth chip U4, and pins 2 of the third chip U3 and the fourth chip U4 are connected to pin 34 SOC_PWREN of the master control chip U6;

[0049] The MOS tube control circuit includes a first control circuit Q1 and a second control circuit Q2_Q3. The first control circuit Q1 is suitable for controlling the power supply VDD_LOGIC to supply power to the master control chip U6. The second control circuit Q2_Q3 is suitable for controlling the power supply VCC_3V3 to supply power to the master control chip U6.

[0050] The third power conversion circuit includes a fifth chip U5 and a resistor R27 . Pin 1 of the fifth chip U5 is connected to the power input circuit through the resistor R27 .

[0051] Specifically, the first chip U1 and the second chip U2, as well as the peripheral resistor R2, resistor R5, capacitor and inductor together form a first power conversion circuit, which is responsible for outputting the two power groups VCC3V3_STB and 0V9_PMUIO to power the master control chip U6. The power input of the first chip U1 and the second chip U2's 4 pins comes from the battery power supply. The VCC3V3_STB power supply does not need to be controlled, so the 1st pin of the first chip U1 is connected to the power input circuit through the resistor R2, and the 0V9_PMUIO power supply does not need to be controlled either, so the 1st pin of the second chip U2 is connected to the power input circuit through the resistor R5, so that the first chip U1 and the second chip U2 can work all the time. Furthermore, the first chip U1 and the second chip U2 can use light-load high-efficiency chips, which are also very efficient under low load conditions, so that the power consumption of these two parts of the circuit can be guaranteed to be small.

[0052] The third chip U3 and the fourth chip U4 together with peripheral resistors, capacitors and inductors form a second power conversion circuit, which is responsible for outputting the two power supplies VDD_ARM_NPU and VCC_1V8 to power the master control chip U6. Pin 2 of the third chip U3 and the fourth chip U4 are enable control pins, which are connected to pin 34 SOC_PWREN of the master control chip U6. In sleep mode, they are controlled according to system needs, thereby realizing time-sharing power supply.

[0053] The two power supplies VDD_LOGIC and VCC_3V3 do not need level conversion, but need to control power on and power off. Therefore, MOS tubes are used as control circuits. The first control circuit Q1 is a MOS tube used to control the operation of VDD_LOGIC; the second control circuit Q2_Q3 is a combination circuit that controls the output of VCC_3V3 power supply. The two power supplies VDD_LOGIC and VCC_3V3 are also time-sharing power supplies and play an important role in the sleep state.

[0054] The fifth chip U5 and the peripheral resistor 27, capacitor and inductor together form a third power conversion circuit, which is responsible for outputting the VCC_DDR power supply to power the master control chip U6. Pin 1 of the fifth chip U5 is connected to the power input circuit through resistor R27. When starting to work and in sleep mode, the fifth chip U5 is not controlled by SOC_PWREN and keeps working because the master control chip U6 needs this power supply to maintain memory self-refresh and ensure data storage and fast chip startup. However, the power consumption of this power supply is extremely small and does not affect the overall level of low power consumption. In the low power state, the master control chip U6 will shut down this power supply internally to minimize power consumption and ensure battery life.

[0055] like Figure 1 to Figure 2As shown, in some embodiments of the present application, pin 4 of the first chip U1 and the second chip U2 is a power input pin, and pin 1 of the first chip U1 and the second chip U2 is an enable pin.

[0056] Pin 4 of the first chip U1 and the second chip U2 is a power input pin, which means that pin 4 is where the first chip U1 and the second chip U2 receive external power input. Usually, this is where the chip obtains voltage from the external power supply for subsequent power conversion or voltage stabilization processing.

[0057] Pin 1 of the first chip U1 and the second chip U2 is an enable pin, which is usually used to control whether the chip is working. Pin 1 as an enable pin can be used to control whether the power conversion chip outputs voltage. By controlling the state of this pin (high level or low level), the corresponding power output can be turned on or off.

[0058] Pin 1 of the first chip U1 is connected to the power input circuit through the resistor R2. The pin 1 receives an enable signal through the resistor R2 to control the working state of the first power conversion circuit.

[0059] Pin 1 of the second chip U2 is connected to the power input circuit via the resistor R5. Similarly, the pin 1 receives an enable signal via the resistor R5 to control the working state of the first power conversion circuit.

[0060] In summary, the first power conversion circuit converts the external power into two groups of power supplies, VCC3V3_STB and 0V9_PMUIO, through the first chip U1 and the second chip U2, and controls the opening and closing of the two groups of power supplies through the 1st pin (enable pin) of the first chip U1 and the second chip U2, thereby realizing the power supply management of the master control chip U6. Resistors R2 and R5 can play the role of current limiting or voltage dividing here to ensure the normal operation of the chip.

[0061] like Figure 3 to Figure 4 As shown, in some embodiments of the present application, pin 2 of the third chip U3 and the fourth chip U4 are enable control pins.

[0062] Pin 2 of the third chip U3 and the fourth chip U4 is used to control the output of the two power supplies VDD_ARM_NPU and VCC_1V8. Specifically, this pin can be used to control the on and off of the two power supplies. These two pins are connected to the 34-pin SOC_PWREN of the master control chip U6, so the power output of the third chip U3 and the fourth chip U4 is affected by the control signal of SOC_PWREN.

[0063] In general, the second power conversion circuit converts the external power into two groups of power supplies, VDD_ARM_NPU and VCC_1V8, through the third chip U3 and the fourth chip U4, and controls the opening and closing of these two groups of power supplies through the 2 pins (enable control pins) of the third chip U3 and the fourth chip U4, thereby realizing the power supply management of the master control chip U6. This design allows the opening and closing of these two groups of power supplies to be controlled according to system needs in the sleep state, thereby realizing time-sharing power supply.

[0064] like Figure 5 As shown, in some embodiments of the present application, pin 3 of the first control circuit Q1 is connected to the power supply 0V9_PMUIO, pin 1 of the first control circuit Q1 is connected to the SOC_PWREN pin of the master control chip U6, and pin 2 of the first control circuit Q1 is connected to the power supply VDD_LOGIC.

[0065] The pin 3 of the first control circuit Q1 is connected to the power supply 0V9_PMUIO, and obtains the power input from 0V9_PMUIO. The power supply 0V9_PMUIO here can be a stable power supply voltage, which is used to provide the working voltage for the first control circuit Q1.

[0066] Pin 1 of the first control circuit Q1 is connected to the SOC_PWREN pin of the master control chip U6. The SOC_PWREN pin is used to control the opening and closing of the first control circuit Q1. That is, when SOC_PWREN is at a high level, the first control circuit Q1 is turned on; when SOC_PWREN is at a low level, the first control circuit Q1 is turned off.

[0067] Pin 2 of the first control circuit Q1 is connected to the power supply VDD_LOGIC. When the first control circuit Q1 is turned on, the VDD_LOGIC power supply is activated to provide the required voltage for the system.

[0068] In general, the first control circuit Q1 in the MOS tube control circuit controls the power supply VDD_LOGIC to be turned on and off through the control signal SOC_PWREN, thereby realizing the power supply management of the master control chip U6. This design allows the VDD_LOGIC to be turned on and off according to system needs in the sleep state, thereby realizing time-sharing power supply.

[0069] like Figure 5 As shown, in some embodiments of the present application, the second control circuit Q2_Q3 includes a control circuit Q2 and a control circuit Q3, and pin 1 of the control circuit Q3 is connected to a power source VCC_1V8.

[0070] Pin 1 of the control circuit Q3 is connected to the power supply VCC_1V8, and pin 1 obtains the control signal from VCC_1V8. Here, VCC_1V8 is controlled by SOC_PWREN, so the control signal of the control signal Q3 is actually indirectly controlled by SOC_PWREN.

[0071] Combined with the previous description, we can further understand the working principle of the MOS tube control circuit:

[0072] The MOS tube control circuit includes a first control circuit Q1 and a second control circuit Q2_Q3. The first control circuit Q1 is used to control the operation of VDD_LOGIC, and its pin 1 is connected to the SOC_PWREN terminal pin of the master control chip U6, and its pin 2 is connected to the power supply VDD_LOGIC.

[0073] The second control circuit Q2_Q3 is used to control the operation of VCC_3V3, wherein pin 1 of the control circuit Q3 is connected to the power supply VCC_1V8, and is used to control the output of the VCC_3V3 power supply.

[0074] In summary, the second control circuit Q2_Q3 in the MOS tube control circuit controls the on and off of VCC_3V3 through the control signal VCC_1V8 (indirectly controlled by SOC_PWREN), thereby realizing the power supply management of the master control chip U6. This design allows the on and off of VCC_3V3 to be controlled according to system needs in the sleep state, thereby realizing time-sharing power supply.

[0075] like Figure 5 As shown, in some embodiments of the present application, pin 3 of the first control circuit Q1 is the power input pin, pin 1 of the first control circuit Q1 is the control pin, pin 2 of the first control circuit Q1 is the output pin, and pin 1 of the control circuit Q3 is the control pin.

[0076] Pin 3 of the first control circuit Q1 is connected to the power supply 0V9_PMUIO as an input pin, and the first control circuit Q1 obtains power input from 0V9_PMUIO. Pin 1 is used as a control pin, connected to the control signal SOC_PWREN output by the master control chip U6, and the conduction or cutoff of the first control circuit Q1 is controlled by the signal of SOC_PWREN.

[0077] Pin 2 of the first control circuit Q1 is used as an output pin to output the power supply VDD_LOGIC. When SOC_PWREN is at a high level, VDD_LOGIC has an output; when SOC_PWREN is at a low level, VDD_LOGIC has no output.

[0078] Pin 1 of the control circuit Q3 is used as a control pin and is connected to the power supply VCC_1V8 to control the output of the VCC_3V3 power supply. The power supply of VCC_1V8 is controlled by SOC_PWREN, so that the power supply sequence of VCC_1V8 and VCC_3V3 can be guaranteed.

[0079] In some embodiments of the present application, when SOC_PWREN is at a high level, the power supply VDD_LOGIC has an output, and when SOC_PWREN is at a low level, the power supply VDD_LOGIC has no output.

[0080] When SOC_PWREN is at a high level, pin 1 (control pin) of the first control circuit Q1 receives a high level signal, causing the first control circuit Q1 to be turned on, thereby causing the power supply VDD_LOGIC to have an output.

[0081] When SOC_PWREN is at a low level, pin 1 (control pin) of the first control circuit Q1 receives a low level signal, causing the first control circuit Q1 to be turned off, so that the power supply VDD_LOGIC has no output.

[0082] like Figure 6 As shown, in some embodiments of the present application, pin 1 of the fifth chip U5 is a control pin.

[0083] Pin 1 of the fifth chip U5 is used to control the output of the VCC_DDR power supply. Specifically, this pin can control the on and off of the VCC_DDR power supply.

[0084] Combined with the previous information, we can further understand the working principle of the third power conversion circuit:

[0085] The third power conversion circuit includes a fifth chip U5 and related resistors, capacitors and inductors. Pin 1 of the fifth chip U5 is used as a control pin and is connected to the input power supply through a resistor R27. Pin 1 of the fifth chip U5 is responsible for controlling the output of the VCC_DDR power supply group. Since the VCC_DDR power supply group is always in the on state when starting to work and in the sleep state, pin 1 of the fifth chip U5 is not directly controlled by SOC_PWREN.

[0086] In summary, the third power conversion circuit converts the external power supply into the VCC_DDR power supply through the U5 chip, and controls the opening and closing of this power supply through the 1st pin (control pin) of U5, thereby realizing the power supply management of the master control chip U6. This design allows the VCC_DDR power supply to be maintained in the sleep state to support memory self-refresh, ensure data storage and fast startup of the chip.

[0087] A second aspect of the present application provides an imaging device, comprising the low power consumption control circuit in any one of the embodiments of the first aspect.

[0088] The camera equipment can be a surveillance camera, a drone camera, a thermal imaging camera, etc.

[0089] According to the camera device provided by the embodiment of the second aspect of the present application, due to the use of the low-power control circuit in any of the above embodiments, the control circuit is started regularly in the sleep state to achieve information acquisition once every 1 second, ensuring the real-time and integrity of the information. The hot start method is adopted to reduce the startup time and power consumption, and improve the timeliness of information acquisition. When the battery power is lower than the threshold, the circuit automatically enters the low-power mode and only retains the necessary power supply to save power consumption to the greatest extent.

[0090] This low-power control circuit is particularly suitable for battery-powered surveillance cameras, especially in remote areas or special environments where stable power supply cannot be accessed.

[0091] By integrating the above-mentioned low-power control circuit, this camera device can significantly reduce power consumption while ensuring the monitoring effect. It is particularly suitable for monitoring scenarios that need to work for a long time and cannot be connected to the power grid.

[0092] Anything not described in this application can be achieved by adopting or drawing on existing technologies.

[0093] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0094] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A low power consumption control circuit, characterized in that: include: The master control chip U6 is suitable for controlling the low-power control circuit to realize time-sharing power supply and timed start; A first power conversion circuit, adapted to control the power supply VCC3V3_STB and the power supply 0V9_PMUIO to supply power to the master control chip U6; A second power conversion circuit, adapted to control the power supply VDD_ARM_NPU and the power supply VCC_1V8 to supply power to the master control chip U6; MOS tube control circuit, suitable for controlling power supply VDD_LOGIC and power supply VCC_3V3 to supply power to the master control chip U6; The third power conversion circuit is adapted to control the power source VCC_DDR to supply power to the master control chip U6.

2. The low power consumption control circuit according to claim 1, characterized in that: The first power conversion circuit includes a first chip U1, a second chip U2, a resistor R2 and a resistor R5, wherein the 4 pins of the first chip U1 and the second chip U2 are connected to a power supply, the 1 pin of the first chip U1 is connected to a power input circuit through the resistor R2, and the 1 pin of the second chip U2 is connected to a power input circuit through the resistor R5; The second power conversion circuit includes a third chip U3 and a fourth chip U4, and pins 2 of the third chip U3 and the fourth chip U4 are connected to pin 34 SOC_PWREN of the master control chip U6; The MOS tube control circuit includes a first control circuit Q1 and a second control circuit Q2_Q3, wherein the first control circuit Q1 is suitable for controlling the power supply VDD_LOGIC to supply power to the master control chip U6, and the second control circuit Q2_Q3 is suitable for controlling the power supply VCC_3V3 to supply power to the master control chip U6; The third power conversion circuit includes a fifth chip U5 and a resistor R27 , and pin 1 of the fifth chip U5 is connected to the power input circuit through the resistor R27 .

3. The low power consumption control circuit according to claim 2, characterized in that: Pin 4 of the first chip U1 and the second chip U2 is a power input pin, and pin 1 of the first chip U1 and the second chip U2 is an enable pin.

4. The low power consumption control circuit according to claim 2, characterized in that: Pin 2 of the third chip U3 and the fourth chip U4 are enable control pins.

5. The low power consumption control circuit according to claim 2, characterized in that: Pin 3 of the first control circuit Q1 is connected to the power supply 0V9_PMUIO, pin 1 of the first control circuit Q1 is connected to the SOC_PWREN terminal pin of the master control chip U6, and pin 2 of the first control circuit Q1 is connected to the power supply VDD_LOGIC.

6. The low power consumption control circuit according to claim 5, characterized in that: The second control circuit Q2_Q3 includes a control circuit Q2 and a control circuit Q3, and a pin 1 of the control circuit Q3 is connected to the power source VCC_1V8.

7. The low power consumption control circuit according to claim 6, characterized in that: Pin 3 of the first control circuit Q1 is a power input pin, pin 1 of the first control circuit Q1 is a control pin, pin 2 of the first control circuit Q1 is an output pin, and pin 1 of the control circuit Q3 is a control pin.

8. The low power consumption control circuit according to any one of claims 5 to 7, characterized in that: When the SOC_PWREN is at a high level, the power supply VDD_LOGIC has an output, and when the SOC_PWREN is at a low level, the power supply VDD_LOGIC has no output.

9. The low power consumption control circuit according to claim 2, characterized in that: Pin 1 of the fifth chip U5 is a control pin.

10. A camera device, characterized in that: The method comprises the low power consumption control circuit as claimed in any one of claims 1 to 9.

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