Data processing method and device of filter, electronic equipment and medium

Abstract

The embodiment of the invention provides a data processing method and device of a filter, electronic equipment and a medium. The method comprises the steps of obtaining input data; searching a target output bit width corresponding to the input data in a pre-stored lookup table according to a pre-configured filtering parameter; according to the target output bit width, carrying out integration processing on the input data by adopting a cascade integrator to obtain integrated data; according to the target output bit width, an extractor is adopted to extract and sample the integrated data to obtain sampling data; according to the target output bit width, a cascade differentiator is adopted to carry out differential processing on the sampling data to obtain filtered data corresponding to the input data, and the bit width adaptive control unit is additionally arranged in the embodiment of the invention to realize bit width selection and effective data bit control under different extraction rates and stages; the generation of burrs in the filtering process can be effectively avoided.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and in particular to a filter data processing method, device, electronic device and medium. Background Art

[0002] In digital signal processing, CIC filter is the best FIR filter, which uses the integration and comb filter cascade method. CIC filter consists of one or more pairs of integration-comb filters. In the extraction CIC, the input signal is successively integrated, downsampled, and comb filters with the same number of integration links. In the existing integration, extraction and differentiation process, a fixed bit width is used for processing, and the bit width cannot be dynamically configured according to the actual situation, thereby improving the accuracy of signal filtering. Summary of the invention

[0003] Some embodiments of the present application aim to provide a data processing method, device, electronic device and medium of a filter. According to the technical scheme of the embodiments of the present application, input data is obtained; according to the pre-configured filtering parameters, a target output bit width corresponding to the input data is searched in a pre-stored lookup table, wherein the pre-stored lookup table at least includes the corresponding relationship between the input data bit width, the decimation rate, the filter differential delay, the filter order and the data peak value under the output bit width; the filtering parameters at least include the decimation rate and the filter order; according to the target output bit width, a cascade integrator is used to integrate the input data to obtain integrated data; according to the target output bit width, a decimator is used to extract and sample the integrated data to obtain sampled data; according to the target output bit width, a cascade differentiator is used to differentiate the sampled data to obtain filtered data corresponding to the input data. In the embodiments of the present application, a bit width adaptive control unit is added to realize bit width selection and control of effective data bits under different decimation rates and orders, which can effectively avoid the generation of burrs in the filtering process.

[0004] In a first aspect, some embodiments of the present application provide a filter data processing method, including:

[0005] Get input data;

[0006] According to the pre-configured filtering parameters, searching for the target output bit width corresponding to the input data in a pre-stored lookup table, wherein the pre-stored lookup table at least includes the corresponding relationship between the input data bit width, the decimation rate, the filter differential delay, the filter order and the data peak value under the output bit width; the filtering parameters at least include the decimation rate and the filter order;

[0007] According to the target output bit width, integrating the input data using a cascade integrator to obtain integrated data;

[0008] According to the target output bit width, using a decimator to sample the integrated data to obtain sampled data;

[0009] According to the target output bit width, a cascade differentiator is used to perform differentiation processing on the sampled data to obtain filtered data corresponding to the input data.

[0010] Some embodiments of the present application achieve bit width selection and control of effective data bits at different extraction rates and levels by adding a bit width adaptive control unit, which can effectively avoid the generation of glitches in the filtering process.

[0011] Optionally, the pre-stored lookup table is obtained in the following manner:

[0012] Calculate the logarithmic value based on the decimation rate and the filter differential delay;

[0013] Calculating a first product according to the logarithmic value and the filter order;

[0014] Calculating an initial output bit width according to the first product and the input data bit width;

[0015] The initial output bit width is rounded up to obtain an output bit width; the output bit width is used to process the integrator, the decimator, the differentiator and the limiting output unit respectively;

[0016] Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table;

[0017] The first data peak value under the output bit width is calculated according to the sampling rate and the number of filter stages.

[0018] Some embodiments of the present application implement adaptive adjustment of bit width at different extraction rates and filtering of data during calculation by means of a lookup table and a shift register.

[0019] Optionally, the integrating the input data using a cascade integrator according to the target output bit width to obtain integrated data includes:

[0020] Using a shift operation, performing a shift operation on the target output bit width to obtain a second data peak value; the second data peak value is greater than the first data peak value;

[0021] When the input data is valid data, perform first-order integration on the input data to obtain data after first-order integration;

[0022] Calculating the input data and the data after the first-order integration to perform an addition operation to obtain a first addition result;

[0023] Performing a bitwise AND logic operation on the first addition result and the second data peak value to obtain first-level integration valid data;

[0024] Performing a secondary integration operation on the primary integrated data to obtain secondary integrated data;

[0025] Calculating a second addition result of the data after the secondary integration and the data after the primary integration;

[0026] Performing a bitwise AND logic operation on the second addition result and the second data peak value to obtain secondary integration valid data;

[0027] Performing a third-level integration operation on the data after the second-level integration to obtain third-level integrated data;

[0028] Calculating a third addition result of the data after the third-level integration and the data after the second-level integration;

[0029] Performing a bitwise AND logic operation on the third addition result and the second data peak value to obtain three-level integration valid data;

[0030] Circularly performing N-level integration operations on the data after the N-1-level integration to obtain N-level integrated data;

[0031] Calculate the Nth addition result of the data after the N-level integration and the data after the N-1-level integration;

[0032] Performing a bitwise AND logic operation on the Nth addition result and the second data peak value to obtain N-level integration valid data;

[0033] The N-level integrated valid data is determined as the integrated data, wherein N is the number of filter levels and N is a natural number greater than 1.

[0034] Some embodiments of the present application implement integration operations on input bit streams through cascaded integrators, which are implemented internally through adders and can dynamically adjust the bit width of the integrated effective data.

[0035] Optionally, the step of sampling the integrated data using a decimator according to the target output bit width to obtain sampled data includes:

[0036] Get the internal counter value;

[0037] When the internal counter value is the same as the preset extraction rate, setting the extraction data valid flag signal to a valid preset value;

[0038] When the valid preset value is detected, a bitwise AND logic process is performed on the N-level integration result and the second data peak value to obtain the sampled data.

[0039] In some embodiments of the present application, the extractor extracts and samples the integrated data and stores the sampling results in a register, and can dynamically adjust the bit width of the extracted valid data.

[0040] Optionally, the step of performing differentiation processing on the sampled data using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data includes:

[0041] Performing a delay process on the sampled data to obtain first sampled data;

[0042] Calculating a difference between the sampled data and the first sampled data to obtain a first difference;

[0043] Performing bitwise AND logic processing on the first difference and the second data peak value to obtain primary differential data;

[0044] Performing secondary delay processing on the first sampled data to obtain second sampled data;

[0045] Calculating a difference between the first-order differential data and the second sampling data to obtain a second difference;

[0046] Performing bitwise AND logic processing on the second difference and the second data peak value to obtain secondary differential data;

[0047] Performing N-1th sampling data delay processing N times to obtain Nth sampling data;

[0048] Calculate the difference between the N-1 level differential data and the Nth sampling data to obtain an Nth difference;

[0049] The Nth difference value and the second data peak value are subjected to bitwise AND logic processing to obtain N-level differential data, wherein N is the number of filter levels and N is a natural number greater than 1.

[0050] In some embodiments of the present application, a cascade differentiator implements differential operations on the extracted data, which is implemented internally through a subtractor and can dynamically adjust the bit width of the differential effective data.

[0051] Optionally, the method further comprises:

[0052] Performing a limiting process on the differentiated data according to the first data peak value under the bit width to obtain data after the limiting process;

[0053] The data after the amplitude limiting process is determined as the filtered data.

[0054] In some embodiments of the present application, after performing limiting processing on the data during the integration, extraction and differentiation operations, the differentiated data is obtained, and then the first data peak value is used to perform limiting processing on the differentiated data to obtain the final filtered target data, which can also effectively avoid glitches in the operation process.

[0055] In a second aspect, some embodiments of the present application provide a filter data processing device, including:

[0056] An acquisition module, used to obtain input data;

[0057] A search module, configured to search a target output bit width corresponding to the input data in a pre-stored lookup table according to pre-configured filtering parameters, wherein the pre-stored lookup table at least includes a corresponding relationship between input data bit width, decimation rate, filter differential delay, filter order, and data peak value under output bit width; and the filtering parameters at least include the decimation rate and the filter order;

[0058] An integration module, used for integrating the input data using a cascade integrator according to the target output bit width to obtain integrated data;

[0059] An extraction module, configured to extract samples from the integrated data using a decimator according to the target output bit width to obtain sampled data;

[0060] The differentiation module is used to perform differentiation processing on the sampled data by using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data.

[0061] Some embodiments of the present application achieve bit width selection and control of effective data bits at different extraction rates and levels by adding a bit width adaptive control unit, which can effectively avoid the generation of glitches in the filtering process.

[0062] Optionally, the pre-stored lookup table is obtained in the following manner:

[0063] Calculate the logarithmic value based on the decimation rate and the filter differential delay;

[0064] Calculating a first product according to the logarithmic value and the filter order;

[0065] Calculating an initial output bit width according to the first product and the input data bit width;

[0066] The initial output bit width is rounded up to obtain an output bit width; the output bit width is used to process the integrator, the decimator, the differentiator and the limiting output unit respectively;

[0067] Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table;

[0068] The first data peak value under the output bit width is calculated according to the sampling rate and the number of filter stages.

[0069] Some embodiments of the present application implement adaptive adjustment of bit width at different extraction rates and filtering of data during calculation by means of a lookup table and a shift register.

[0070] Optionally, the integration module is used to:

[0071] Using a shift operation, performing a shift operation on the target output bit width to obtain a bit width peak value and a second data peak value;

[0072] When the input data is valid data, perform first-order integration on the input data to obtain data after first-order integration;

[0073] Calculating the input data and the data after the first-order integration to perform an addition operation to obtain a first addition result;

[0074] Performing a bitwise AND logic operation on the first addition result and the second data peak value to obtain first-level integration valid data;

[0075] Performing a secondary integration operation on the primary integrated data to obtain secondary integrated data;

[0076] Calculating a second addition result of the data after the secondary integration and the data after the primary integration;

[0077] Performing a bitwise AND logic operation on the second addition result and the second data peak value to obtain secondary integration valid data;

[0078] Performing a third-level integration operation on the data after the second-level integration to obtain third-level integrated data;

[0079] Calculating a third addition result of the data after the third-level integration and the data after the second-level integration;

[0080] Performing a bitwise AND logic operation on the third addition result and the second data peak value to obtain three-level integration valid data;

[0081] Circularly performing N-level integration operations on the data after the N-1-level integration to obtain N-level integrated data;

[0082] Calculate the Nth addition result of the data after the N-level integration and the data after the N-1-level integration;

[0083] Performing a bitwise AND logic operation on the Nth addition result and the second data peak value to obtain N-level integration valid data;

[0084] The N-level integrated valid data is determined as the integrated data, wherein N is the number of filter levels and N is a natural number greater than 1.

[0085] Some embodiments of the present application implement integration operations on input bit streams through cascaded integrators, which are implemented internally through adders and can dynamically adjust the bit width of the integrated effective data.

[0086] Optionally, the extraction module is used to:

[0087] Get the internal counter value;

[0088] When the internal counter value is the same as the preset extraction rate, setting the extraction data valid flag signal to a valid preset value;

[0089] When the valid preset value is detected, a bitwise AND logic process is performed on the N-level integration result and the second data peak value to obtain the sampled data.

[0090] In some embodiments of the present application, the extractor extracts and samples the integrated data and stores the sampling results in a register, and can dynamically adjust the bit width of the extracted valid data.

[0091] Optionally, the differentiation module is used to:

[0092] Performing a delay process on the sampled data to obtain first sampled data;

[0093] Calculating a difference between the sampled data and the first sampled data to obtain a first difference;

[0094] Performing bitwise AND logic processing on the first difference and the second data peak value to obtain primary differential data;

[0095] Performing secondary delay processing on the first sampled data to obtain second sampled data;

[0096] Calculating a difference between the first-order differential data and the second sampling data to obtain a second difference;

[0097] Performing bitwise AND logic processing on the second difference and the second data peak value to obtain secondary differential data;

[0098] Performing N-1th sampling data delay processing N times to obtain Nth sampling data;

[0099] Calculate the difference between the N-1 level differential data and the Nth sampling data to obtain an Nth difference;

[0100] The Nth difference value and the second data peak value are subjected to bitwise AND logic processing to obtain N-level differential data, wherein N is the number of filter levels and N is a natural number greater than 1.

[0101] In some embodiments of the present application, a cascade differentiator implements differential operations on the extracted data, which is implemented internally through a subtractor and can dynamically adjust the bit width of the differential effective data.

[0102] Optionally, the differentiation module is used to:

[0103] Performing a limiting process on the differentiated data according to the first data peak value under the bit width to obtain data after the limiting process;

[0104] The data after the amplitude limiting process is determined as the filtered data.

[0105] In some embodiments of the present application, after performing limiting processing on the data during the integration, extraction and differentiation operations, the differentiated data is obtained, and then the first data peak value is used to perform limiting processing on the differentiated data to obtain the final filtered target data, which can also effectively avoid glitches in the operation process.

[0106] In a third aspect, some embodiments of the present application provide an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, the filter data processing method as described in any embodiment of the first aspect can be implemented.

[0107] In a fourth aspect, some embodiments of the present application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the filter data processing method as described in any embodiment of the first aspect.

[0108] In a fifth aspect, some embodiments of the present application provide a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, it can implement the data processing method of the filter as described in any embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] In order to more clearly illustrate the technical solutions of some embodiments of the present application, the drawings required for use in some embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0110] Figure 1 A flowchart of a filter data processing method provided in an embodiment of the present application;

[0111] Figure 2 A flowchart of another filter data processing method provided in an embodiment of the present application;

[0112] Figure 3 This is a simulation diagram of data without using a lookup table filter;

[0113] Figure 4 A simulation diagram of filtering data under a lookup table provided in an embodiment of the present application;

[0114] Figure 5 A schematic diagram of the peak value of filtered data provided in an embodiment of the present application;

[0115] Figure 6 A schematic diagram of the structure of a data processing device for a filter provided in an embodiment of the present application;

[0116] Figure 7 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0117] The technical solutions in some embodiments of the present application will be described below in conjunction with the drawings in some embodiments of the present application.

[0118] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0119] In digital signal processing, CIC filter is the best FIR filter, which uses the cascade method of integration and comb filter. CIC filter consists of one or more pairs of integration-comb filters. In the extraction CIC, the input signal is successively integrated, downsampled, and comb filters with the same number of integration links. In the existing integration, extraction and differentiation processes, a fixed bit width is used for processing, and the bit width cannot be dynamically configured according to actual conditions, thereby improving the accuracy of signal filtering. In view of this, some embodiments of the present application provide a data processing method for a filter, the method comprising obtaining input data; searching a pre-stored lookup table for a target output bit width corresponding to the input data according to pre-configured filtering parameters, wherein the pre-stored lookup table at least includes a corresponding relationship between the input data bit width, the extraction rate, the filter differential delay, the filter order and the output bit width; the filtering parameters at least include the extraction rate and the filter order, according to the target output bit width, using a cascade integrator to integrate the input data to obtain integrated data; according to the target output bit width, using an extractor to extract and sample the integrated data to obtain sampled data; according to the target output bit width, using a cascade differentiator to differentiate the sampled data to obtain filtered data corresponding to the input data, and in the embodiments of the present application, adding a bit width adaptive control unit to realize bit width selection and control of effective data bits under different extraction rates and orders can effectively avoid the generation of burrs in the filtering process.

[0120] like Figure 1 As shown, an embodiment of the present application provides a filter data processing method, the method comprising:

[0121] S101, obtaining input data;

[0122] Specifically, the input data is bit stream data;

[0123] The terminal device obtains input data to be filtered, that is, bit stream data to be filtered.

[0124] S102, according to the pre-configured filtering parameters, searching the target output bit width corresponding to the input data in the pre-stored lookup table, wherein the pre-stored lookup table at least includes the corresponding relationship between the input data bit width, the decimation rate, the filter differential delay, the filter order and the data peak value under the output bit width; the filtering parameters at least include the decimation rate and the filter order;

[0125] A lookup table is pre-stored on the terminal device, and the lookup table at least includes the corresponding relationship between the input data bit width, the sampling rate, the filter differential delay, the filter order, the output bit width and the data peak value under the output bit width; after obtaining the bit rate data, the terminal device obtains the bit width of the bit stream data, that is, the input data bit width, wherein the bit width is the amount of data that can be transmitted by the memory or the video memory at one time, and then searches for the target output bit width corresponding to the input data according to the pre-configured filtering parameters and the pre-stored lookup table.

[0126] The decimation rate and filter order in the filtering parameters in the embodiment of the present application can be set according to user needs and are not specifically limited here.

[0127] S103, integrating the input data using a cascade integrator according to the target output bit width to obtain integrated data;

[0128] Specifically, the terminal device configures the extraction rate and filter stage number of the integrator, decimator and differentiator in the multi-stage CIC filter according to the target output bit width, and then filters the input data. The target output bit width is used to limit the cascaded integrator, decimator and cascaded differentiator, respectively, wherein the cascaded integrator integrates the input data to obtain integrated data.

[0129] Among them, the multi-stage CIC filter includes at least multiple integrators, one extractor and multiple differentiators, and multiple refers to two or more. In this application, the number of integrators and the number of differentiators are not specifically limited.

[0130] S104, according to the target output bit width, using a decimator to sample the integrated data to obtain sampled data;

[0131] Specifically, the terminal device uses a decimator to sample the integrated data according to the target output bit width to obtain sampled data.

[0132] S105 . According to the target output bit width, a cascade differentiator is used to perform differentiation processing on the sampled data to obtain filtered data corresponding to the input data.

[0133] The embodiment of the present application is aimed at the input bit stream data, and can realize the dynamic adjustment of the bit width during the filtering process. If the bit width of the input data is changed, the further processing of the bit width can be realized by modifying the lookup table, that is, it can be used for optimizing the bit width and limiting the data under the dynamic adjustment of the extraction rate and the filter level.

[0134] Some embodiments of the present application achieve bit width selection and control of effective data bits at different extraction rates and levels by adding a bit width adaptive control unit, which can effectively avoid the generation of glitches in the filtering process.

[0135] Another embodiment of the present application further supplements the data processing method of the filter provided in the above embodiment.

[0136] Optionally, the pre-stored lookup table is obtained by:

[0137] Calculate the logarithmic value based on the decimation rate and the filter differential delay;

[0138] Calculate the first product based on the logarithmic value and the filter order;

[0139] Calculate an initial output bit width according to the first product and the input data bit width;

[0140] The initial output bit width is rounded up to obtain an output bit width; the output bit width is used to process the integrator, the extractor, the differentiator and the limiting output unit respectively;

[0141] Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table;

[0142] The first data peak value under the output bit width is calculated according to the sampling rate and the number of filter stages.

[0143] The lookup table is actually implemented through multiple if conditional statements, and the corresponding bit width value is matched according to the input sampling rate OSR and the number of filter stages N.

[0144] Specifically, the bit width of the intermediate signal of the integration, extraction and differentiation units is:

[0145] Bout = Bin + N * log2DM;

[0146] Where Bin is the input data bit width, D is the decimation rate (OSR), M is the filter differential delay, and N is the number of filter stages.

[0147] The bit width adaptive control unit realizes the adaptive adjustment of the bit width at different extraction rates and the filtering of the data in the calculation process through the lookup table and shift register. In the design of multi-stage CIC filter, compared with the system function of $clog2 rounding up, more accurate bit width calculation can be achieved, which can effectively avoid glitches in the filtering process.

[0148] In the embodiment of the present application, the automatic matching of the bit width is realized in the form of a lookup table, specifically:

[0149] In the bit width calculation formula Bout=Bin+N*log2DM, $log2 is a system function that rounds up. When the value of DM is not an integer power of 2, the value calculated by $log2DM is not actually an integer. Aligning and rounding up, and then performing N times the product operation is the traditional way to calculate the bit width, so the difference in the bit width obtained will be magnified.

[0150] In the embodiment of the present application, firstly, $log2DM is not rounded during the calculation process, and the value of the formula Bout=Bin+N*log2DM is directly calculated, and then Bout is rounded at the end. After the value of the decimation rate is configured, the value of the bit width r_width_tmp is directly output in the form of a lookup table. The error between the bit width obtained in this way and the bit width of the data in the actual filtering process will be very small. The bit width value is counted in excel.

[0151] Some embodiments of the present application implement adaptive adjustment of bit width at different extraction rates and filtering of data during calculation by means of a lookup table and a shift register.

[0152] Optionally, according to the target output bit width, a cascade integrator is used to perform integration processing on the input data to obtain integrated data, including:

[0153] The target output bit width is shifted by a shift operation to obtain a second data peak value; wherein the second data peak value is obtained by performing a bitwise AND logic operation on the integral value and the value of the bit width being all 1 in each level of integration operation.

[0154] When the input data is valid data, perform first-order integration on the input data to obtain data after first-order integration;

[0155] Calculating the input data and the data after the first-order integration to perform an addition operation to obtain a first addition result;

[0156] Performing a bitwise AND logic operation on the first addition result and the second data peak value to obtain first-level integration valid data;

[0157] Performing a secondary integration operation on the primary integrated data to obtain secondary integrated data;

[0158] Calculating a second addition result of the data after the secondary integration and the data after the primary integration;

[0159] Performing a bitwise AND logic operation on the second addition result and the second data peak value to obtain secondary integration valid data;

[0160] Performing a third-level integration operation on the data after the second-level integration to obtain third-level integrated data;

[0161] Calculate the third addition result of the data after the third-level integration and the data after the second-level integration;

[0162] Perform a bitwise AND logical operation on the third addition result and the second data peak value to obtain the valid data of the third-level integration;

[0163] Loop to perform the N-level integration operation on the data after the (N - 1)-level integration to obtain the data after the N-level integration;

[0164] Calculate the Nth addition result of the data after the N-level integration and the data after the (N - 1)-level integration;

[0165] Perform a bitwise AND logical operation on the Nth addition result and the second data peak value to obtain the valid data of the N-level integration;

[0166] Determine the valid data of the N-level integration as the integrated data, where N is the number of filter levels and N is a natural number greater than 1.

[0167] Specifically, first perform a left shift operation on the bit width value obtained in the bit width adaptive unit, that is, the target output bit width r_width_tmp, (1 << r_width_tmp) - 1'b1, to obtain the maximum value at this bit width, that is, the second data peak value w_valid_data.

[0168] Secondly, during the integration operation, perform an AND logical process on the accumulated value, the data r_integ_data after the first-level integration, and w_valid_data each time, and finally obtain the integrated result.

[0169] For example, in the 3-level integration operation:

[0170] (1) First-level integration: When the input data valid signal i_sd_valid is detected, perform an addition operation on the r_integ_data1 data and the original data w_sd_data, and at the same time perform a bitwise AND logical process on the result of the addition operation and w_valid_data, and finally save the result in the first-level integration result r_integ_data1 register. At the same time, generate a valid signal r_integ_valid1 of the first-level integration result.

[0171] (2) Second-level integration: When the data valid signal r_integ_valid1 is detected, the data r_integ_data2 and the first-level integration data r_integ_data1 are added, and the result of the addition operation is bitwise ANDed with w_valid_data, and the result is finally saved in the second-level integration result r_integ_data2 register. At the same time, the valid signal r_integ_valid2 of the second-level integration result is generated.

[0172] (3) Third-level integration: When the data valid signal r_integ_valid2 is detected, the r_integ_data3 data and the secondary integration data r_integ_data2 are added, and the result of the addition operation is bitwise ANDed with w_valid_data. Finally, the result is saved in the third-level integration result r_integ_data3 register, and the valid signal r_integ_valid3 of the third-level integration result is generated.

[0173] The above is an integration process of three integrators, and there can also be N integrators, which is not specifically limited in the embodiments of the present application.

[0174] Some embodiments of the present application implement integration operations on input bit streams through cascaded integrators, which are implemented internally through adders and can dynamically adjust the bit width of the integrated effective data.

[0175] Optionally, according to the target output bit width, using a decimator to sample the integrated data to obtain sampled data, including:

[0176] Get the internal counter value;

[0177] When the internal counter value is the same as the preset extraction rate, setting the extraction data valid flag signal to a valid preset value;

[0178] When the valid preset value is detected, a bitwise AND logic process is performed on the N-level integration result and the second data peak value to obtain the sampled data.

[0179] During each extraction process, the extracted value and the value with a bit width of all 1 are used for bitwise AND logic to obtain the final extracted value.

[0180] In some embodiments of the present application, the extractor extracts and samples the integrated data and stores the sampling results in a register, and can dynamically adjust the bit width of the extracted valid data.

[0181] Specifically, during the extraction operation, firstly, the internal counter is used to count according to the configured OSR value. When the count value is equal to the OSR configuration value, the flag signal r_osr_valid indicating that the extracted data is valid is set, and the counter is cleared at the same time.

[0182] Secondly, when the data valid signal r_osr_valid is detected, the r_integ_data3 data and w_valid_data are processed bitwise and logically, and the result is finally saved in the extraction register r_decim_data. At the same time, the valid signal r_decim_valid of the extraction result is generated.

[0183] Optionally, according to the target output bit width, a cascade differentiator is used to perform differentiation processing on the sampled data to obtain filtered data corresponding to the input data, including:

[0184] Performing a delay process on the sampled data to obtain first sampled data;

[0185] Calculating a difference between the sampled data and the first sampled data to obtain a first difference;

[0186] Performing bitwise AND logic processing on the first difference and the second data peak value to obtain primary differential data;

[0187] Performing secondary delay processing on the first sampled data to obtain second sampled data;

[0188] Calculating a difference between the first-order differential data and the second sampling data to obtain a second difference;

[0189] Performing bitwise AND logic processing on the second difference and the second data peak value to obtain secondary differential data;

[0190] Performing N-1th sampling data delay processing N times to obtain Nth sampling data;

[0191] Calculate the difference between the N-1 level differential data and the Nth sampling data to obtain an Nth difference;

[0192] The Nth difference value and the second data peak value are subjected to bitwise AND logic processing to obtain N-level differential data, wherein N is the number of filter levels and N is a natural number greater than 1.

[0193] Specifically, during the differential operation, each cumulative difference r_diff_data and w_valid_data are subjected to AND logic processing to obtain a differentiated result.

[0194] For example, in a three-level differential operation: in each level of differential operation, the differential value and the value with a bit width of all 1 are used to perform bitwise AND logic.

[0195] (4) First-level differentiation: When the data valid signal r_decim_valid is detected, r_decim_data is first delayed to obtain r_decim_data_r, and r_decim_data and r_decim_data_r are subtracted. The result of the subtraction operation is bitwise ANDed with w_valid_data, and the result is finally saved in the first-level differentiation result r_diff_data1 register. At the same time, the valid signal r_diff_valid1 of the first-level differentiation result is generated.

[0196] (5) Second level differentiation: When the data valid signal r_diff_valid1 is detected, r_diff_data1 is first delayed to obtain r_diff_data1_r, and r_diff_data1 and r_diff_data1_r are subtracted. The result of the subtraction operation is bitwise ANDed with w_valid_data, and the result is finally saved in the second level differentiation result r_diff_data2 register. At the same time, the valid signal r_diff_valid2 of the second level differentiation result is generated.

[0197] (6) Third-level differentiation: When the data valid signal r_diff_valid2 is detected, r_diff_data2 is first delayed to obtain r_diff_data2_r, and r_diff_data2 and r_diff_data2_r are subtracted. The result of the subtraction operation is bitwise ANDed with w_valid_data, and the result is finally saved in the third-level differentiation result register r_diff_data3. At the same time, the valid signal r_diff_valid3 of the third-level differentiation result is generated.

[0198] In some embodiments of the present application, the extractor implements sampling of the integrated data and stores the sampling results in a register, and can dynamically adjust the bit width of the extracted valid data. The cascade differentiator implements the differential operation of the extracted data, which is implemented internally through a subtractor, and can dynamically adjust the bit width of the differential valid data.

[0199] Optionally, the method further comprises:

[0200] Performing a limiting process on the differentiated data according to the first data peak value under the bit width to obtain data after the limiting process;

[0201] The data after the amplitude limiting process is determined as the filtered data.

[0202] The maximum value w_valid_data under the corresponding bit width is obtained by shift operation, and its calculation formula is: w_valid_data=(1< <r_width_tmp)-1'b1。

[0203] And use w_valid_data to limit the data during the integration, extraction and differentiation operations, which can effectively avoid glitches in the operation process.

[0204] According to the configured decimation rate OSR and the number of filter stages N, the peak value r_sinc_peak_data under the configuration is obtained. If the result after differentiation is greater than the peak value, the result of the peak value is output; if the result after differentiation is less than the peak value, the value of the current differentiation result is output.

[0205] The peak value of the filtered data is calculated by looking up the table, such as Figure 5 As shown in the figure, the peak data is used for limiting processing to further effectively filter out the burrs.

[0206] In some embodiments of the present application, after performing limiting processing on the data during the integration, extraction and differentiation operations, the differentiated data is obtained, and then the first data peak value is used to perform limiting processing on the differentiated data to obtain the final filtered target data, which can also effectively avoid glitches in the operation process.

[0207] like Figure 2 As shown, the embodiment of the present application provides a multi-stage CIC filter device based on a configurable decimation rate, including a bit width adaptive control unit, a cascade integrator unit, an extractor unit, a cascade differentiator unit, and a limiting output unit, wherein:

[0208] The bit width adaptive control realizes the bit width selection and control of effective data bits under different extraction rates and levels. It is mainly used to improve the accuracy of data and is implemented internally through a lookup table and a shift register.

[0209] The cascade integrator implements the integration operation on the input bit stream, which is realized internally by an adder and can dynamically adjust the bit width of the integrated effective data.

[0210] The extractor extracts and samples the integrated data and stores the sampling results in the register. The bit width of the extracted valid data can be dynamically adjusted.

[0211] The cascade differentiator realizes the differential operation of the extracted data, which is realized internally by a subtractor and can dynamically adjust the bit width of the differential effective data.

[0212] The limiting output realizes the limiting processing of data, which is mainly used to filter out burrs and improve the accuracy of data.

[0213] Exemplarily, for a 3-stage filter N=3, the input unsigned data bit stream Bin=1, the filter differential delay M=1, when it is configured with OSR=9, the first data peak of the filter is w_sinc_peak_data=16'h03e8.

[0214] Change the value of the decimation rate during the filtering process. When OSR=9 is configured, according to the formula Bout=Bin+N*log2DM, if $clog2 is rounded up, Bout=13 can be obtained. The following simulation waveform is obtained, such as Figure 3 As shown: i_osr = 8'h9, the calculated bit width r_width_tmp = 5'hd, the filtered data o_sinc_data is 16'hdeec for the first extraction after switching the extraction rate OSR, 16'hc0a0 for the second extraction, 16'h79e8 for the third extraction, and the filtered data is not stable until the fourth extraction at 16'h03e8. Three glitches are generated during the filtering process, such as Figure 3 shown.

[0215] Through the bit width adaptive control unit, the bit width r_width_tmp = 5'ha can be obtained. The following simulation waveform is obtained, such as Figure 4 As shown in the figure, the filtered data o_sinc_data is 16'h02ec at the first extraction after switching OSR, 16'h00a0 at the second extraction, 16'h01e8 at the third extraction, and 16'h03e8 at the fourth extraction. No burrs are generated during the filtering process, which can improve the accuracy of the filtered data.

[0216] Compared with the prior art, the embodiment of the present application implements a multi-stage CIC filter with a dynamically configurable decimation rate and realizes automatic adjustment of the bit width at different decimation rates, which can reduce the cumulative error in the data processing process and ensure the accuracy of the filtered data.

[0217] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any combination without conflict, and this application is not limited thereto.

[0218] Another embodiment of the present application provides a filter data processing device, which is used to execute the filter data processing method provided by the above embodiment.

[0219] like Figure 6 , which is a schematic diagram of the structure of the data processing device of the filter provided in the embodiment of the present application. The data processing device of the filter includes an acquisition module 601, a search module 602, an integration module 603, an extraction module 604 and a differentiation module 605, wherein:

[0220] The acquisition module 601 is used to acquire input data;

[0221] The search module 602 is used to search for a target output bit width corresponding to the input data in a pre-stored lookup table according to pre-configured filtering parameters, wherein the pre-stored lookup table at least includes a corresponding relationship between the input data bit width, the decimation rate, the filter differential delay, the filter order, and the data peak value under the output bit width; the filtering parameters at least include the decimation rate and the filter order;

[0222] The integration module 603 is used to integrate the input data using a cascade integrator according to the target output bit width to obtain integrated data;

[0223] The extraction module 604 is used to extract and sample the integrated data using a decimator according to the target output bit width to obtain sampled data;

[0224] The differentiation module 605 is used to perform differentiation processing on the sampled data using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data.

[0225] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0226] Some embodiments of the present application achieve bit width selection and control of effective data bits at different extraction rates and levels by adding a bit width adaptive control unit, which can effectively avoid the generation of glitches in the filtering process.

[0227] Another embodiment of the present application further supplements the data processing device of the filter provided in the above embodiment.

[0228] Optionally, the pre-stored lookup table is obtained by:

[0229] Calculate the logarithmic value based on the decimation rate and the filter differential delay;

[0230] Calculate the first product based on the logarithmic value and the filter order;

[0231] Calculate an initial output bit width according to the first product and the input data bit width;

[0232] The initial output bit width is rounded up to obtain an output bit width; the output bit width is used to process the integrator, the extractor, the differentiator and the limiting output unit respectively;

[0233] Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table;

[0234] The first data peak value under the output bit width is calculated according to the sampling rate and the number of filter stages.

[0235] Some embodiments of the present application implement adaptive adjustment of bit width at different extraction rates and filtering of data during calculation by means of a lookup table and a shift register.

[0236] Optionally, the integration module is used to:

[0237] Using a shift operation, performing a shift operation on the target output bit width to obtain a second data peak value;

[0238] When the input data is valid data, perform first-order integration on the input data to obtain data after first-order integration;

[0239] Calculating the input data and the data after the first-order integration to perform an addition operation to obtain a first addition result;

[0240] Performing a bitwise AND logic operation on the first addition result and the second data peak value to obtain first-level integration valid data;

[0241] Performing a secondary integration operation on the primary integrated data to obtain secondary integrated data;

[0242] Calculating a second addition result of the data after the secondary integration and the data after the primary integration;

[0243] Performing a bitwise AND logic operation on the second addition result and the second data peak value to obtain secondary integration valid data;

[0244] Performing a third-level integration operation on the data after the second-level integration to obtain third-level integrated data;

[0245] Calculating a third addition result of the data after the third-level integration and the data after the second-level integration;

[0246] Performing a bitwise AND logic operation on the third addition result and the second data peak value to obtain three-level integration valid data;

[0247] Circularly performing N-level integration operations on the data after the N-1-level integration to obtain N-level integrated data;

[0248] Calculate the Nth addition result of the data after the N-level integration and the data after the N-1-level integration;

[0249] Performing a bitwise AND logic operation on the Nth addition result and the second data peak value to obtain N-level integration valid data;

[0250] The N-level integrated valid data is determined as the integrated data, wherein N is the number of filter levels and N is a natural number greater than 1.

[0251] Some embodiments of the present application implement integration operations on input bit streams through cascaded integrators, which are implemented internally through adders and can dynamically adjust the bit width of the integrated effective data.

[0252] Optionally, the extraction module is used to:

[0253] Get the internal counter value;

[0254] When the internal counter value is the same as the preset extraction rate, setting the extraction data valid flag signal to a valid preset value;

[0255] When the valid preset value is detected, a bitwise AND logic process is performed on the N-level integration result and the second data peak value to obtain the sampled data.

[0256] In some embodiments of the present application, the extractor extracts and samples the integrated data and stores the sampling results in a register, and can dynamically adjust the bit width of the extracted valid data.

[0257] Optionally, the differentiation module is used to:

[0258] Performing a delay process on the sampled data to obtain first sampled data;

[0259] Calculating a difference between the sampled data and the first sampled data to obtain a first difference;

[0260] Performing bitwise AND logic processing on the first difference and the second data peak value to obtain primary differential data;

[0261] Performing secondary delay processing on the first sampled data to obtain second sampled data;

[0262] Calculating a difference between the first-order differential data and the second sampling data to obtain a second difference;

[0263] Performing bitwise AND logic processing on the second difference and the second data peak value to obtain secondary differential data;

[0264] Performing N-1th sampling data delay processing N times to obtain Nth sampling data;

[0265] Calculate the difference between the N-1 level differential data and the Nth sampling data to obtain an Nth difference;

[0266] The Nth difference value and the second data peak value are subjected to bitwise AND logic processing to obtain N-level differential data, wherein N is the number of filter levels and N is a natural number greater than 1.

[0267] In some embodiments of the present application, a cascade differentiator implements differential operations on the extracted data, which is implemented internally through a subtractor and can dynamically adjust the bit width of the differential effective data.

[0268] Optionally, the differentiation module is used to:

[0269] Performing a limiting process on the differentiated data according to the first data peak value under the bit width to obtain data after the limiting process;

[0270] The data after the amplitude limiting process is determined as the filtered data.

[0271] In some embodiments of the present application, after performing limiting processing on the data during the integration, extraction and differentiation operations, the differentiated data is obtained, and then the first data peak value is used to perform limiting processing on the differentiated data to obtain the final filtered target data, which can also effectively avoid glitches in the operation process.

[0272] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0273] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any manner without conflict, and this application is not limited thereto.

[0274] The embodiments of the present application further provide a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the operation of the method corresponding to any embodiment of the filter data processing method provided in the above embodiments can be implemented.

[0275] An embodiment of the present application further provides a computer program product, which includes a computer program, wherein when the computer program is executed by a processor, it can implement the operations corresponding to the method of any embodiment of the filter data processing method provided in the above embodiments.

[0276] like Figure 7As shown, some embodiments of the present application provide an electronic device 700, which includes: a memory 710, a processor 720, and a computer program stored in the memory 710 and executable on the processor 720, wherein the processor 720 can implement any embodiment of the method of data processing of the filter as described above when reading the program from the memory 710 through a bus 730 and executing the program.

[0277] Processor 720 can process digital signals and can include various computing structures, such as complex instruction set computer structure, reduced instruction set computer structure, or a structure that implements a combination of multiple instruction sets. In some examples, processor 720 can be a microprocessor.

[0278] The memory 710 may be used to store instructions executed by the processor 720 or data related to the execution of instructions. These instructions and / or data may include codes for implementing some or all functions of one or more modules described in the embodiments of the present application. The processor 720 of the disclosed embodiment may be used to execute instructions in the memory 710 to implement the method shown above. The memory 710 includes a dynamic random access memory, a static random access memory, a flash memory, an optical memory, or other memory known to those skilled in the art.

[0279] The above are only embodiments of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0280] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0281] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Claims

1. A filter data processing method, characterized in that: The method comprises: Get input data; According to the pre-configured filtering parameters, searching for the target output bit width corresponding to the input data in a pre-stored lookup table, wherein the pre-stored lookup table at least includes the corresponding relationship between the input data bit width, the decimation rate, the filter differential delay, the filter order and the data peak value under the output bit width; the filtering parameters at least include the decimation rate and the filter order; According to the target output bit width, integrating the input data using a cascade integrator to obtain integrated data; According to the target output bit width, using a decimator to sample the integrated data to obtain sampled data; According to the target output bit width, a cascade differentiator is used to perform differentiation processing on the sampled data to obtain filtered data corresponding to the input data.

2. The filter data processing method according to claim 1, characterized in that: The pre-stored lookup table is obtained in the following manner: Calculate the logarithmic value based on the decimation rate and the filter differential delay; Calculating a first product according to the logarithmic value and the filter order; Calculating an initial output bit width according to the first product and the input data bit width; The initial output bit width is rounded up to obtain an output bit width; the output bit width is used to process the integrator, the decimator, the differentiator and the limiting output unit respectively; Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table; The first data peak value under the output bit width is calculated according to the sampling rate and the number of filter stages.

3. The filter data processing method according to claim 1, characterized in that: The step of integrating the input data using a cascade integrator according to the target output bit width to obtain integrated data comprises: Using a shift operation, performing a shift operation on the target output bit width to obtain a second data peak value under the target output bit width; the second data peak value is greater than the first data peak value; When the input data is valid data, perform first-order integration on the input data to obtain data after first-order integration; Calculating the input data and the data after the first-order integration to perform an addition operation to obtain a first addition result; Performing a bitwise AND logic operation on the first addition result and the second data peak value to obtain first-level integration valid data; Performing a secondary integration operation on the primary integrated data to obtain secondary integrated data; Calculating a second addition result of the data after the secondary integration and the data after the primary integration; Performing a bitwise AND logic operation on the second addition result and the second data peak value to obtain secondary integration valid data; Performing a third-level integration operation on the data after the second-level integration to obtain third-level integrated data; Calculating a third addition result of the data after the third-level integration and the data after the second-level integration; Performing a bitwise AND logic operation on the third addition result and the second data peak value to obtain three-level integration valid data; Circularly performing N-level integration operations on the data after the N-1-level integration to obtain N-level integrated data; Calculate the Nth addition result of the data after the N-level integration and the data after the N-1-level integration; Performing a bitwise AND logic operation on the Nth addition result and the second data peak value to obtain N-level integration valid data; The N-level integrated valid data is determined as the integrated data, wherein N is the number of filter levels and N is a natural number greater than 1.

4. The filter data processing method according to claim 3, characterized in that: The method of sampling the integrated data using a decimator according to the target output bit width to obtain sampled data includes: Get the internal counter value; When the internal counter value is the same as the preset extraction rate, setting the extraction data valid flag signal to a valid preset value; When the valid preset value is detected, a bitwise AND logic process is performed on the N-level integration result and the second data peak value to obtain the sampled data.

5. The filter data processing method according to claim 4, characterized in that: The method of performing differentiation processing on the sampled data by using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data includes: Performing a delay process on the sampled data to obtain first sampled data; Calculating a difference between the sampled data and the first sampled data to obtain a first difference; Performing bitwise AND logic processing on the first difference and the second data peak value to obtain primary differential data; Performing secondary delay processing on the first sampled data to obtain second sampled data; Calculating a difference between the first-order differential data and the second sampling data to obtain a second difference; Performing bitwise AND logic processing on the second difference and the second data peak value to obtain secondary differential data; Performing N-1th sampling data delay processing N times to obtain Nth sampling data; Calculate the difference between the N-1 level differential data and the Nth sampling data to obtain an Nth difference; The Nth difference value and the second data peak value are subjected to bitwise AND logic processing to obtain N-level differential data, wherein N is the number of filter levels and N is a natural number greater than 1.

6. The filter data processing method according to claim 5, characterized in that: The method further comprises: Performing a limiting process on the differentiated data according to the first data peak value under the bit width to obtain data after the limiting process; The data after the amplitude limiting process is determined as the filtered data.

7. A filter data processing device, characterized in that: The device comprises: An acquisition module, used to obtain input data; A search module, configured to search a target output bit width corresponding to the input data in a pre-stored lookup table according to pre-configured filtering parameters, wherein the pre-stored lookup table at least includes a corresponding relationship between input data bit width, decimation rate, filter differential delay, filter order, and data peak value under output bit width; and the filtering parameters at least include the decimation rate and the filter order; An integration module, used for integrating the input data using a cascade integrator according to the target output bit width to obtain integrated data; An extraction module, configured to extract samples from the integrated data using a decimator according to the target output bit width to obtain sampled data; The differentiation module is used to perform differentiation processing on the sampled data by using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data.

8. The filter data processing device according to claim 7, characterized in that: The pre-stored lookup table is obtained in the following manner: Calculate the logarithmic value based on the decimation rate and the filter differential delay; Calculating a first product according to the logarithmic value and the filter order; Calculating an initial output bit width according to the first product and the input data bit width; The initial output bit width is rounded up to obtain an output bit width; the output bit width is used to process the integrator, the decimator, the differentiator and the limiting output unit respectively; Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table; The first data peak value under the output bit width is calculated according to the sampling rate and the number of filter stages.

9. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor can implement the filter data processing method according to any one of claims 1 to 6 when executing the program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the program, when executed by a processor, can implement the filter data processing method described in any one of claims 1 to 6.

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