An optical receiver

Abstract

The present disclosure provides an optical receiver. The optical receiver includes: a main path, an auxiliary path, and a mode selection module. The main path includes a first gain adjustment module and a second gain adjustment module. The auxiliary path is coupled to the main path. The input end of the mode selection module is coupled to the auxiliary path, and the output end of the mode selection module is coupled to the main path. The main path transmits a preamble code in a photocurrent signal to the auxiliary path in a first data transmission phase, and the main path transmits and outputs valid data in the photocurrent signal in a second data transmission phase. In the first data transmission phase, the mode selection module outputs a first control signal and a second control signal according to the preamble code. The first gain adjustment module switches the gain mode according to the first control signal. Different gain modes correspond to different gain ranges of the first gain adjustment module. The second gain adjustment module performs gain adjustment within the gain range corresponding to the gain mode of the first gain adjustment module according to the second control signal.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of optical communications, and in particular to an optical receiver. Background Art

[0002] With the widespread adoption of 5G communications, big data, cloud computing, and AI technologies, the demand for internet access for individual user data is increasing exponentially. As the last mile of internet access, passive optical networks (PONs) provide robust bandwidth access capabilities. Currently, PON technology is evolving toward higher-speed PON standards. Uplink high-speed burst mode optical receivers are a crucial component of higher-speed PON systems. Summary of the Invention

[0003] In view of this, an embodiment of the present disclosure provides an optical receiver.

[0004] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0005] An embodiment of the present disclosure provides an optical receiver, comprising:

[0006] A main path, the main path comprising a first gain adjustment module and a second gain adjustment module;

[0007] an auxiliary path coupled to the main path;

[0008] a mode selection module, wherein an input terminal of the mode selection module is coupled to the auxiliary path, and an output terminal of the mode selection module is coupled to the main path;

[0009] In which, the main path is used to receive a photocurrent signal, and the main path transmits the preamble code in the photocurrent signal to the auxiliary path in the first data transmission stage, and the main path transmits and outputs the valid data in the photocurrent signal in the second data transmission stage; in the first data transmission stage, the mode selection module outputs a first control signal and a second control signal according to the preamble code; the first gain adjustment module switches the gain mode according to the first control signal; different gain modes correspond to different gain ranges of the first gain adjustment module; the second gain adjustment module performs gain adjustment within the gain range corresponding to the gain mode of the first gain adjustment module according to the second control signal.

[0010] In some embodiments, the first gain adjustment module includes a transimpedance amplifier and a first continuous-time linear equalizer connected in series; wherein the transimpedance amplifier is located at the input end of the main path.

[0011] In some embodiments, the transimpedance amplifier includes a first switch and a plurality of feedback resistors, and the first continuous-time linear equalizer includes a second switch and a plurality of inductors;

[0012] The first switch is used to switch the number of feedback resistors connected in the transimpedance amplifier to adjust the total resistance of the connected feedback resistors; the second switch is used to switch the number of inductors connected in the first continuous-time linear equalizer to adjust the total inductance of the connected inductors; different total resistances of the feedback resistors and total inductances of the inductors correspond to different gain modes.

[0013] In some embodiments, the transimpedance amplifier further includes a third switch and a plurality of first amplifiers, and the first continuous-time linear equalizer further includes a fourth switch and a plurality of second amplifiers;

[0014] The third switch is used to switch the number of accesses of the first amplifier in the transimpedance amplifier to adjust the bandwidth of the transimpedance amplifier; the fourth switch is used to switch the number of accesses of the second amplifier in the first continuous-time linear equalizer to adjust the bandwidth of the first continuous-time linear equalizer.

[0015] In some embodiments, the auxiliary path includes a second continuous time linear equalizer, and the response frequency band of the second continuous time linear equalizer is higher than the response frequency band of the first continuous time linear equalizer.

[0016] In some embodiments, the mode selection module includes a peak extraction module and a selection module; the input end of the peak extraction module is coupled to the output end of the auxiliary path, and the output end of the peak extraction module is coupled to the input end of the selection module and the main path respectively; the output end of the selection module is coupled to the main path;

[0017] The peak extraction module is used to output the second control signal according to the preamble code, and the selection module is used to output the first control signal according to the second control signal.

[0018] In some embodiments, the first gain adjustment module outputs an offset signal carrying offset information;

[0019] The optical receiver further includes:

[0020] An offset elimination module, wherein the input end of the offset elimination module is coupled to the output end of the first gain adjustment module, and the output end of the offset elimination module is coupled to the input end of the first gain adjustment module; the offset elimination module outputs an offset elimination signal according to the offset signal, and the offset elimination signal is used to eliminate the offset information in the offset signal.

[0021] In some embodiments, the offset cancellation module includes a sample-and-hold capacitor;

[0022] In the first data transmission phase, the offset cancellation module is used to output the offset cancellation signal according to the offset signal, and load the offset cancellation signal to the sampling and holding capacitor;

[0023] In the second data transmission phase, the offset cancellation module is configured to output the offset cancellation signal through the sampling and holding capacitor.

[0024] In some embodiments, the main path further includes a buffer located at an output end of the main path.

[0025] In some embodiments, the second gain adjustment module includes a variable gain amplifier.

[0026] An embodiment of the present disclosure provides an optical receiver. The optical receiver includes: a main path, the main path including a first gain adjustment module and a second gain adjustment module; an auxiliary path, the auxiliary path coupled to the main path; a mode selection module, the input end of the mode selection module coupled to the auxiliary path, and the output end of the mode selection module coupled to the main path; wherein the main path is used to receive a photocurrent signal, the main path transmits a preamble in the photocurrent signal to the auxiliary path in a first data transmission phase, and the main path transmits and outputs valid data in the photocurrent signal in a second data transmission phase; in the first data transmission phase, the mode selection module outputs a first control signal and a second control signal according to the preamble; the first gain adjustment module switches the gain mode according to the first control signal; different gain modes correspond to different gain ranges of the first gain adjustment module; the second gain adjustment module performs gain adjustment within the gain range corresponding to the gain mode of the first gain adjustment module according to the second control signal. In the embodiment of the present disclosure, in the first data transmission phase, the mode selection module outputs a first control signal and a second control signal according to the preamble. Among them, the first gain adjustment module switches the gain mode according to the first control signal, and the second gain adjustment module performs gain adjustment within the gain range corresponding to the gain mode of the first gain adjustment module according to the second control signal, thereby achieving continuous adjustment of the gain within the main path response frequency band within a high dynamic range. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A design framework diagram of an optical receiver provided in an embodiment of the present disclosure;

[0028] Figure 2 A design framework diagram of another optical receiver provided in an embodiment of the present disclosure;

[0029] Figure 3 A schematic diagram of achieving frequency response of a high dynamic range optical receiver provided by an embodiment of the present disclosure;

[0030] Figure 4 A circuit diagram of an optical receiver provided in an embodiment of the present disclosure;

[0031] Figure 5 Response spectrum diagram corresponding to the main channel and auxiliary channel provided in the embodiment of the present disclosure;

[0032] Figure 6 is a partial architecture diagram of a peak extraction module in an embodiment of the present disclosure;

[0033] Figure 7 This is a response spectrum diagram of the auxiliary channel output point under the 50G PON standard provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0035] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0036] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0037] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0038] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0041] In optical communication technology, light is used to carry information to be transmitted. This information is then transmitted through optical transmission equipment such as optical fibers or optical waveguides to information processing equipment such as computers. Because optical signals are passive when transmitted through optical fibers or optical waveguides, they enable low-cost, low-loss information transmission. Typically, a photodetector receives an optical signal from an external device and converts it into a photocurrent signal. An optical receiver receives the photocurrent signal output by the photodetector, performs balanced amplification on it, and outputs two differential signals.

[0042] Figure 1 A design framework diagram of an optical receiver provided in an embodiment of the present disclosure.

[0043] The present disclosure provides an optical receiver, such as Figure 1 As shown, the optical receiver 100 includes: a main path 101, which includes a first gain adjustment module 108 and a second gain adjustment module 109; an auxiliary path 102, which is coupled to the main path 101; a mode selection module 103, wherein the input end of the mode selection module 103 is coupled to the auxiliary path 102, and the output end of the mode selection module 103 is coupled to the main path 101; wherein the main path 101 is used to receive a photocurrent signal, and the main path 101 transmits a preamble in the photocurrent signal to the auxiliary path 102 in a first data transmission phase, and transmits and outputs valid data in the photocurrent signal in a second data transmission phase; in the first data transmission phase, the mode selection module 103 outputs a first control signal and a second control signal according to the preamble; the first gain adjustment module 108 switches the gain mode according to the first control signal; different gain modes correspond to different gain ranges of the first gain adjustment module 108; the second gain adjustment module 109 performs gain adjustment within the gain range corresponding to the gain mode of the first gain adjustment module according to the second control signal.

[0044] Here, the photocurrent signal includes a preamble portion and a data portion. The preamble portion includes the preamble but not the valid data, while the data portion contains the valid data. The preamble arrives at the optical receiver 100 before the valid data in terms of timing. Specifically, the preamble arrives at the optical receiver 100 in the first data transmission phase, and the valid data arrives at the optical receiver 100 in the second data transmission phase. The first data transmission phase is located before the second data transmission phase in terms of timing. In one example, the preamble can be a periodic signal such as "0101."

[0045] In the embodiment of the present disclosure, the main path 101 includes a first gain adjustment module 108 and a second gain adjustment module 109. The main path 101 transmits the leading code in the photocurrent signal to the auxiliary path 102 in the first data transmission phase, and the main path 101 transmits and outputs the valid data in the photocurrent signal in the second data transmission phase. In the first data transmission phase, the mode selection module 103 can output the first control signal and the second control signal according to the received leading code. Here, the first gain adjustment module can switch the gain mode according to the first control signal, and different gain modes correspond to different gain ranges of the first gain adjustment module. The second gain adjustment module can perform gain adjustment within the gain range corresponding to the gain mode of the first gain adjustment module according to the second control signal. Thereby, the gain within the response frequency band of the main path 101 can be continuously adjusted within a high dynamic range.

[0046] In the embodiment of the present disclosure, the optical receiver may be a high-speed burst mode optical receiver to meet the high dynamic range response of the main channel of the receiver in the high-speed PON system.

[0047] In an embodiment of the present disclosure, the first gain adjustment module includes a transimpedance amplifier and a first continuous-time linear equalizer connected in series; wherein the transimpedance amplifier is located at the input end of the main path.

[0048] In the embodiment of the present disclosure, the second gain adjustment module includes a variable gain amplifier.

[0049] like Figure 1 As shown, the first gain adjustment module 108 includes a transimpedance amplifier 110 and a first continuous-time linear equalizer 111 , and the second gain adjustment module 109 includes a variable gain amplifier 112 . Figure 1In the embodiment, the transimpedance amplifier 110 is located at the input 113 of the main path 101. That is, the input of the transimpedance amplifier 110 is the input 113 of the main path 101. The output 114 of the transimpedance amplifier 110 is coupled to the input 115 of the variable gain amplifier 112, and the output 116 of the variable gain amplifier 112 is coupled to the input 117 of the first continuous time linear equalizer 111. Here, the number of stages of the variable gain amplifier 112 in the main path 101 and the number of stages of the first continuous time linear equalizer 111 can be arbitrary. Moreover, the connection positions of the variable gain amplifier 112 and the first continuous time linear equalizer 111 can be interchanged. Specifically, in another embodiment of the present disclosure, the output 114 of the transimpedance amplifier 110 is coupled to the input 117 of the first continuous time linear equalizer 111, and the output 118 of the first continuous time linear equalizer 111 is coupled to the input 115 of the variable gain amplifier 112.

[0050] Continue to refer Figure 1 In the embodiment of the present disclosure, the auxiliary path 102 is coupled to the main path 101 . Specifically, the input end 104 of the auxiliary path 102 is coupled to the output end 118 of the first continuous time linear equalizer 111 in the main path 101 .

[0051] The mode selection module 103 has three output terminals 107: a first output terminal 107a, a second output terminal 107b, and a third output terminal 107c. The first output terminal 107a is coupled to a transimpedance amplifier 110, the second output terminal 107b is coupled to a variable gain amplifier 112, and the third output terminal 107c is coupled to a first continuous-time linear equalizer 111. During the first data transmission phase, the mode selection module 103 outputs a first control signal from the first output terminal 107a and the third output terminal 107c, and outputs a second control signal from the second output terminal 107b, based on the preamble.

[0052] Figure 2 This is a design framework diagram of another optical receiver provided in an embodiment of the present disclosure. Figure 2As shown, optical receiver 200 includes a main path 101, an auxiliary path 102, and a mode selection module 103. Main path 101 includes a first gain adjustment module 108 and a second gain adjustment module 109. First gain adjustment module 108 includes a transimpedance amplifier 110 and a first continuous-time linear equalizer 111. Second gain adjustment module 109 includes a variable gain amplifier 112. An output 114 of transimpedance amplifier 110 is coupled to an input 115 of variable gain amplifier 112, and an output 116 of variable gain amplifier 112 is coupled to an input 117 of first continuous-time linear equalizer 111. Input 104 of auxiliary path 102 is coupled to main path 101. Specifically, input 104 of auxiliary path 102 is coupled to output 116 of variable gain amplifier 112 in main path 101. The input terminal 106 of the mode selection module 103 is coupled to the output terminal 105 of the auxiliary path 102, and the output terminal 107 of the mode selection module 103 is coupled to the main path 101. Here, the description of the first gain adjustment module 108, the second gain adjustment module 109 and the mode selection module 103 can be referred to. Figure 1 , I will not go into details here.

[0053] Figure 3 Schematic diagram of the frequency response of the optical receiver with high dynamic range provided by the embodiment of the present disclosure. Figure 3 As shown, the response frequency band of the transimpedance amplifier 110 is the low-frequency part in the response frequency band of the main path 101, that is, the transimpedance amplifier 110 can adjust the low-frequency part of multiple gain modes. The response frequency band of the first continuous-time linear equalizer 111 is the high-frequency part in the response frequency band of the main path 101, that is, the first continuous-time linear equalizer 111 can adjust the high-frequency part of multiple gain modes. In this way, the transimpedance amplifier 110 and the first continuous-time linear equalizer 111 can jointly implement switching gain modes according to the first control signal output by the mode selection module 103. Different gain modes correspond to different gain ranges of the first gain adjustment module 108. In other words, different gain modes correspond to different gain ranges of the main path 101. For example, Figure 3 In the example, the gain range corresponding to gain mode 1 is shown in the shaded area.

[0054] In one embodiment, when switching the gain mode, the switching step size can be one step, for example, the transimpedance amplifier 110 and the first continuous-time linear equalizer 111 jointly switch the gain mode from gain mode 1 to gain mode 2, or, alternatively, switch the gain mode from gain mode 2 to gain mode 1. In another embodiment, when switching the gain mode, the switching step size can be multiple steps, for example, the transimpedance amplifier 110 and the first continuous-time linear equalizer 111 jointly switch the gain mode from gain mode 1 to gain mode N (N is an integer greater than 2), or, alternatively, switch the gain mode from gain mode N to gain mode 1. In yet another embodiment, when switching the gain mode, the switching step size can be adaptive. The variable gain amplifier 112 can perform gain adjustment within the gain range corresponding to the gain mode in which the first gain adjustment module 108 is located (i.e., the gain mode in which the main path 101 is located).

[0055] In one specific embodiment, the gain range corresponding to gain mode 1 is 10dB to 20dB, the gain range corresponding to gain mode 2 is 20dB to 30dB, and the first gain adjustment module is currently in gain mode 2. To adjust the gain of the main path to 15dB, the gain mode can be switched from gain mode 2 to gain mode 1. Specifically, after switching the gain mode to gain mode 1, the gain of the main path is at the lower limit of the gain range of gain mode 1, i.e., 10dB. Subsequently, a variable gain amplifier is used to adjust the gain of the main path from 10dB to 15dB. This ensures that the gain of the main path 101 is continuously adjustable within the gain range of the currently described gain modes.

[0056] In the disclosed embodiment, the low-frequency gain of the transimpedance amplifier 110 and the high-frequency gain of the subsequent first continuous-time linear equalizer 111 can jointly construct a two-stage or more gain mode. Furthermore, the variable gain amplifier 112 can adjust the gain within the gain range corresponding to the gain mode in which the first gain adjustment module 108 is located, thereby achieving continuous gain adjustment between the aforementioned gain modes.

[0057] In the embodiment of the present disclosure, the circuit structure of the main path 101 can be diverse. For example, the number of stages of the transimpedance amplifier 110 and the number of stages of the first continuous-time linear equalizer 111 can be arbitrary. Figure 3 The circuit structures with the frequency responses shown all fall within the protection scope of the embodiments of the present disclosure.

[0058] Figure 4 The circuit diagram of the optical receiver provided by the embodiment of the present disclosure is shown in FIG. Figure 4As shown, the optical receiver 400 includes a main path 401, an auxiliary path 402, and a mode selection module 403. The main path 401 includes a transimpedance amplifier 404, a variable gain amplifier 405, and a first continuous-time linear equalizer 406. The transimpedance amplifier 404 is located at the input end of the main path 401, and the output end of the transimpedance amplifier 404 is coupled to the input end of the variable gain amplifier 405. The transimpedance amplifier 404 can receive a photocurrent signal from an external device, convert it into a voltage signal, and amplify it. The amplified voltage signal is output from the output end of the transimpedance amplifier 404. The main path 401 also includes a replica transimpedance amplifier 407, which has only one output end, which is coupled to the input end of the variable gain amplifier 405. The replica transimpedance amplifier 407 is used to provide a DC level identical to that of the transimpedance amplifier 404 to provide a pseudo-differential voltage signal, which is output from the output end of the replica transimpedance amplifier 407. In this way, the conversion of a single-ended signal to a more stable differential signal is achieved. In other words, the transimpedance amplifier 404 and the replica transimpedance amplifier 407 jointly convert one input photocurrent signal into two output differential voltage signals. Here, the two differential voltage signals output by the transimpedance amplifier 404 and the replica transimpedance amplifier 407 can be recorded as a first differential signal. The variable gain amplifier 405 can amplify the first differential signal and output a second differential signal at its output. The output of the variable gain amplifier 405 is coupled to the input of the first continuous-time linear equalizer 406. Thus, the first continuous-time linear equalizer 406 can amplify the second differential signal and output a third differential signal at its output.

[0059] It is understood that in the first data transmission phase, the first differential signal, the second differential signal, and the third differential signal include the preamble in the photocurrent signal. In the second data transmission phase, the first differential signal, the second differential signal, and the third differential signal include valid data in the photocurrent signal.

[0060] It's important to note that while main path 401 can amplify the differential signal passing through it, this amplification effect only occurs during the second data transmission phase, meaning it amplifies only the valid data in the photocurrent signal. During the first data transmission phase, the preamble in the photocurrent signal has a transmission frequency higher than the response frequency band of main path 401. Therefore, the preamble output from main path 401 to auxiliary path 402 is significantly attenuated during this phase.

[0061] In the embodiment of the present disclosure, the main path further includes a buffer, which is located at the output end of the main path.

[0062] like Figure 4As shown, the main path 401 further includes a buffer 408, the input of which is coupled to the output of the first continuous-time linear equalizer 406, and the buffer 408 is located at the output of the main path 401. Here, the buffer 408 may be an output buffer. The buffer 408 can be used to match the optical receiver 400 with subsequent circuits.

[0063] In the embodiment of the present disclosure, the auxiliary path includes a second continuous time linear equalizer, and the response frequency band of the second continuous time linear equalizer is higher than the response frequency band of the first continuous time linear equalizer.

[0064] like Figure 4 As shown, the input of auxiliary path 402 is coupled to the output of first continuous-time linear equalizer 406, that is, the input of auxiliary path 402 is coupled to the input of buffer 408. The output of auxiliary path 402 is coupled to the input of mode selection module 403. During the first data transmission phase, auxiliary path 402 can amplify the third differential signal and output a fourth differential signal at its output. The fourth differential signal here is the preamble.

[0065] In the embodiment of the present disclosure, the auxiliary path 402 includes a second continuous time linear equalizer 409, which includes an amplifier and four inductors. Figure 4 Since the response frequency band of the second continuous time linear equalizer 409 is higher than the response frequency band of the first continuous time linear equalizer 406, the second continuous time linear equalizer 409 can extract the preamble from the main path 401 and amplify the preamble so that the preamble can meet the requirements of the subsequent processing.

[0066] In the embodiment of the present disclosure, the number of stages of the second continuous-time linear equalizer 409 in the auxiliary path 402 can be arbitrary.

[0067] Figure 5 The response spectrum diagram of the main path and auxiliary path corresponding to the embodiment of the present disclosure is provided. In the embodiment of the present disclosure, since the response frequency band of the second continuous time linear equalizer 409 is higher than the response frequency band of the first continuous time linear equalizer 406, the gain of the auxiliary path 402 can be extended beyond a frequency point or a frequency band outside the bandwidth of the main path 401, such as Figure 5 Here, it should be noted that the larger the bandwidth of the main channel 401, the more noise will be introduced. In the embodiment of the present disclosure, the auxiliary channel 402 is used to extend the frequency points or frequency bands outside the bandwidth of the main channel 401, which can effectively avoid the introduction of additional noise into the main channel 401.

[0068] Figure 5Figure 4 illustrates two possible responses of auxiliary path 402, namely response 1 and response 2. For example, when second continuous-time linear equalizer 409 is narrow, or the number of stages of second continuous-time linear equalizer 409 is one, the response of second continuous-time linear equalizer 409 is response 1. In this case, second continuous-time linear equalizer 409 expands the gain of a frequency point outside the bandwidth of main path 401. When second continuous-time linear equalizer 409 is wide, or the number of stages of second continuous-time linear equalizer 409 is multiple, the response of second continuous-time linear equalizer 409 is response 2. In this case, second continuous-time linear equalizer 409 expands the gain of a frequency band outside the bandwidth of main path 401.

[0069] In an embodiment of the present disclosure, the mode selection module includes a peak extraction module and a selection module; the input end of the peak extraction module is coupled to the output end of the auxiliary path, and the output end of the peak extraction module is coupled to the input end of the selection module and the main path respectively; the output end of the selection module is coupled to the main path; wherein, the peak extraction module is used to output a second control signal according to the preamble code, and the selection module is used to output a first control signal according to the second control signal.

[0070] Figure 6 FIG. 1 is a partial architecture diagram of the peak extraction module in the embodiment of the present disclosure. Figure 6 As shown, the peak extraction module 601 includes two basic peak detectors 602 and an offset canceller 603. The input of the offset canceller 603 is coupled to the output of the two basic peak detectors 602. The two basic peak detectors 602 are located at the input of the peak extraction module 601 and are configured to receive the fourth differential signal (i.e., the preamble) output by the auxiliary path and extract the peak signal from the fourth differential signal. It should be noted that the auxiliary path amplifies the third differential signal and outputs it as the fourth differential signal. At this point, the fourth differential signal will have a certain degree of offset. In other words, the fourth differential signal will contain offset information. Therefore, the peak signal output by the basic peak detector 602 contains both the peak information and the offset information from the fourth differential signal. The offset canceller 603 can eliminate the offset information from the peak signal while retaining the peak information from the peak signal.

[0071] Specifically, such as Figure 4As shown, the mode selection module 403 includes a peak extraction module 410 and a selection module 411. The peak extraction module 410 includes two basic peak detectors 412, an offset eliminator 413 and a first broadband amplifier 414. Among them, the first basic peak detector 412 includes a transistor M1, a current source I1 and a capacitor C1. The second basic peak detector 412 includes a transistor M2, a current source I2 and a capacitor C2. The structures of the two basic peak detectors 412 are the same. Below, the first basic peak detector 412 is taken as an example for explanation. Specifically, the transistor M1 can be an NMOS transistor. The gate of the transistor M1 is coupled to the input end of the peak extraction module 410, and the source of the transistor M1 is coupled to one end of the current source I1, one end of the capacitor C1 and the input end of the selection module 411 respectively. The drain of the transistor M1 is connected to the power supply voltage V DD The other end of the current source I1 and the other end of the capacitor C1 are grounded. In the embodiment of the present disclosure, the transistor M1 can be in,n and voltage V in,p When present, it acts as a rectifier forward bias diode and transfers charge to capacitor C1 to obtain a rectified positive voltage. Here, the voltage V in,n and voltage V in,p To achieve bidirectional charge transfer of capacitor C1, current source I1 is used as a constant current sink so that the basic peak detector 412 can detect the voltage V in,n and voltage V in,p Respond.

[0072] The offset canceller 413 includes cross-coupled transistors M3, M4, M5, and M6, all of which are PMOS transistors. The offset canceller 413 also includes current sources I3 and I4, resistors R1, and R2. The gates of transistors M4 and M5 are connected to the two input terminals of the offset canceller 413, respectively. Specifically, the gate of transistor M4 is connected to the source of transistor M1, and the gate of transistor M5 is connected to the source of transistor M2. The source of transistor M4 is connected to one end of current source I3, and the source of transistor M5 is connected to one end of current source I4. The drain of transistor M4 and the drain of transistor M5 are both connected to one end of resistor R1. The gates of transistor M3 and M6 are connected to a reference voltage V0. The source of transistor M3 is connected to one end of current source I3, and the source of transistor M6 is connected to one end of current source I4. The drain of the transistor M3 and the drain of the transistor M6 are connected to one end of the resistor R2. The other end of the current source I3 and the other end of the current source I4 are connected to the power supply voltage V DD, the other end of the resistor R1 and the other end of the resistor R2 are grounded. Here, the current source I3 and the current source I4 can provide constant current, that is, the sum of the current flowing through the transistor M3 and the current flowing through the transistor M4 remains constant, and the sum of the current flowing through the transistor M5 and the current flowing through the transistor M6 remains constant. Therefore, the voltage V loaded on the resistor R1 out,n and the voltage V loaded on resistor R2 out,p Two differential voltages can be formed.

[0073] It should be noted that the offset information in the differential voltage output by the basic peak detector 412 can be converted into a differential current with opposite phases after passing through the transistor M4 and the transistor M5. Moreover, the differential currents with opposite phases can be superimposed on the resistor R1 and cancel each other out, so that the output voltage V out,n and voltage V out,p The offset information is no longer included. Meanwhile, the peak information in the differential voltage output by the basic peak detector 412 can be converted into currents with the same phase after passing through transistors M4 and M5, respectively. These currents with the same phase can be superimposed on resistor R1 and reinforce each other, thereby amplifying the peak information.

[0074] The first broadband amplifier 414 includes two input terminals and one output terminal. out,n and voltage V out,p , output the second control signal. Specifically, the first broadband amplifier can out,n and voltage V out,p The difference is then multiplied by the amplification factor of the first broadband amplifier to output a second control signal.

[0075] The selection module 411 includes a first comparator 415, a second comparator 416, a transistor M7, and a transistor M8. The transistor M7 is a PMOS transistor, and the transistor M8 is an NMOS transistor. The first comparator 415 includes two input terminals and an output terminal, wherein one input terminal of the first comparator 415 is connected to the second control signal, and the other input terminal of the first comparator 415 is connected to the first threshold voltage V vgathhigh The output terminal of the first comparator 415 is connected to the gate of the transistor M7. The second comparator 416 includes two input terminals and one output terminal, wherein one input terminal of the second comparator 416 is connected to the second control signal, and the other input terminal of the second comparator 416 is connected to the second threshold voltage V vgathlow The output terminal of the second comparator 416 is connected to the gate of the transistor M8. Here, the first threshold voltage V vgathhigh The value is greater than the second threshold voltage V vgathlow value, and the first threshold voltage Vvgathhigh The value of the second threshold voltage V vgathlow The value of is related to the gain range corresponding to the gain mode. The drain of transistor M7 and the drain of transistor M8 are connected to the same node, which is located at the output end of the selection module 411, and the output end of the selection module 411 is coupled to the transimpedance amplifier 404 and the first continuous time linear equalizer 406 respectively. The source of transistor M7 is connected to the power supply voltage V DD The source of transistor M8 is connected to ground.

[0076] In the embodiment of the present disclosure, when the second control signal is less than the second threshold voltage V vgathlow When the second comparator 416 outputs a high level, the transistor M8 is turned on, and outputs a low first control signal, thereby switching the gain mode of the main path 401 from a low gain mode to a high gain mode. When the second control signal is greater than the first threshold voltage V vgathhigh When the second control signal is less than the first threshold voltage V vgathhigh and is greater than the second threshold voltage V vgathlow When , the output of the second comparator 416 is low, and the output of the first comparator 415 is high, turning off transistors M7 and M8, maintaining the first control signal unchanged, and not changing the gain mode of the main path 401. At this time, the variable gain amplifier 405 can be used to adjust the gain within the gain range corresponding to the current gain mode.

[0077] like Figure 4 As shown, the mode selection module 403 also includes a sampling and holding capacitor C3 and a switch S1. During the first data transmission phase, switch S1 is closed, and the sampling and holding capacitor C3 can quickly adjust to changes in the second control signal, and the second control signal can be loaded on the sampling and holding capacitor C3. During the second data transmission phase, switch S1 is open, and the sampling and holding capacitor C3 can provide a stable second control signal to the main path 401 and the selection module 411.

[0078] In an embodiment of the present disclosure, a transimpedance amplifier includes a first switch and multiple feedback resistors, and a first continuous-time linear equalizer includes a second switch and multiple inductors; wherein the first switch is used to switch the number of feedback resistors connected in the transimpedance amplifier to adjust the total resistance of the connected feedback resistors; the second switch is used to switch the number of inductors connected in the first continuous-time linear equalizer to adjust the total inductance of the connected inductors; different total resistance values ​​of the feedback resistors and total inductance values ​​of the inductors correspond to different gain modes.

[0079] like Figure 4As shown, the transimpedance amplifier 404 includes a first switch and two feedback resistors. The first switch is switch S2, and the two feedback resistors are resistor R3 and resistor R4, respectively. Among them, switch S2 is connected in series with resistor R3. The closing and closing of switch S2 are controlled by a first control signal. When switch S2 is closed, resistor R3 is connected to the transimpedance amplifier 404. At this time, the total resistance of the feedback resistors in the transimpedance amplifier 404 is the resistance of resistors R3 and R4 in parallel. When switch S2 is disconnected, resistor R3 is not connected to the transimpedance amplifier 404. At this time, the total resistance of the feedback resistors in the transimpedance amplifier 404 is the resistance of resistor R4. In this way, the first switch realizes the switching of the number of feedback resistors connected in the transimpedance amplifier 404, and based on this, realizes the switching of the total resistance of the feedback resistors.

[0080] Here, when resistor R3 and resistor R4 are connected in parallel, the total resistance of the feedback resistor is small. When only resistor R4 is connected to the transimpedance amplifier 404, the total resistance of the feedback resistor is large. Since the gain of the transimpedance amplifier 404 is positively correlated with the total resistance of the feedback resistor, when the first switch is closed, the gain of the transimpedance amplifier 404 is small, which reduces the low-frequency gain of the first gain adjustment module. When the first switch is disconnected, the gain of the transimpedance amplifier 404 is large, which increases the low-frequency gain of the first gain adjustment module. In other words, by switching the first switch on and off, the low-frequency gain of the first gain adjustment module can be adjusted.

[0081] The first continuous-time linear equalizer 406 includes four second switches and four inductors. The four second switches are switch S3, switch S4, switch S5, and switch S6. The four inductors are inductor L1, inductor L2, inductor L3, and inductor L4. Switch S3 is connected in parallel with inductor L1, switch S4 is connected in parallel with inductor L2, switch S5 is connected in parallel with inductor L3, and switch S6 is connected in parallel with inductor L4. Switches S3, S4, S5, and S6 can be closed or closed simultaneously, and the closing and closing of switches S3, S4, S5, and S6 are controlled by a first control signal. When switches S3, S4, S5, and S6 are closed simultaneously, inductor L1, inductor L2, inductor L3, and inductor L4 are all connected to the first continuous-time linear equalizer 406. When switches S3, S4, S5, and S6 are closed simultaneously, no inductor is connected to the first continuous-time linear equalizer 406. Thus, the second switch switches the number of inductors connected to the first continuous-time linear equalizer 406, and thereby switches the total inductance of the inductors.

[0082] Here, when the second switch is closed, all inductors are short-circuited, and the total inductance of the inductors connected to the first continuous-time linear equalizer 406 is small (or zero). When the second switch is open, all inductors are connected to the first continuous-time linear equalizer 406, and the total inductance of the inductors connected to the first continuous-time linear equalizer 406 is large. Because the gain of the first continuous-time linear equalizer 406 is positively correlated with the total inductance of the inductors, when the second switch is closed, the gain of the first continuous-time linear equalizer 406 is small, reducing the high-frequency gain of the first gain adjustment module. When the second switch is open, the gain of the first continuous-time linear equalizer 406 is large, increasing the high-frequency gain of the first gain adjustment module. In other words, by switching the second switch on and off, the high-frequency gain of the first gain adjustment module can be adjusted. Because different gain modes correspond to different gain ranges of the first gain adjustment module, the gain mode of the first gain adjustment module can be switched by simultaneously controlling the closing or opening of the first and second switches using the first control signal.

[0083] In an embodiment of the present disclosure, the transimpedance amplifier also includes a third switch and multiple first amplifiers, and the first continuous-time linear equalizer also includes a fourth switch and multiple second amplifiers; wherein the third switch is used to switch the number of first amplifiers connected in the transimpedance amplifier to adjust the bandwidth of the transimpedance amplifier; the fourth switch is used to switch the number of second amplifiers connected in the first continuous-time linear equalizer to adjust the bandwidth of the first continuous-time linear equalizer.

[0084] like Figure 4 As shown, the transimpedance amplifier 404 also includes a third switch and two first amplifiers. The third switch is switch S7, and the two first amplifiers are amplifier M and amplifier N, respectively. Switch S7 is connected in series with amplifier N. The opening and closing of switch S7 are controlled by a first control signal. When switch S7 is closed, both amplifiers M and N are connected to the transimpedance amplifier. When switch S7 is open, only amplifier M is connected to the transimpedance amplifier. In this way, the third switch switches the number of amplifiers connected to the transimpedance amplifier 404.

[0085] Here, because the bandwidth of the transimpedance amplifier 404 is positively correlated with the number of connected amplifiers, when the third switch is closed, the bandwidth of the transimpedance amplifier 404 is large. When the third switch is open, the bandwidth of the transimpedance amplifier 404 is small. In other words, by switching the third switch on and off, the bandwidth of the transimpedance amplifier 404 can be adjusted.

[0086] The first continuous-time linear equalizer 406 also includes a fourth switch and two second amplifiers. The fourth switch is switch S8, and the two second amplifiers are amplifier P and amplifier Q. The opening and closing of switch S8 are controlled by a first control signal. When switch S8 is closed, both amplifier P and amplifier Q are connected to the first continuous-time linear equalizer 406. When switch S8 is open, only amplifier P is connected to the first continuous-time linear equalizer 406. In this way, the fourth switch switches the number of amplifiers connected to the first continuous-time linear equalizer 406.

[0087] Here, because the bandwidth of the first continuous-time linear equalizer 406 is positively correlated with the number of connected amplifiers, when the fourth switch is closed, the bandwidth of the first continuous-time linear equalizer 406 is larger. When the fourth switch is open, the bandwidth of the first continuous-time linear equalizer 406 is smaller. In other words, by switching the fourth switch on and off, the bandwidth of the first continuous-time linear equalizer 406 can be adjusted.

[0088] In an embodiment of the present disclosure, the first gain adjustment module outputs an offset signal carrying offset information; the optical receiver also includes: an offset elimination module, the input end of the offset elimination module is coupled to the output end of the first gain adjustment module, and the output end of the offset elimination module is coupled to the input end of the first gain adjustment module; the offset elimination module outputs an offset elimination signal based on the offset signal, and the offset elimination signal is used to eliminate the offset information in the offset signal.

[0089] Combine Figure 1 and Figure 4 The first gain adjustment module 108 can output an offset signal carrying offset information based on the photocurrent signal. Specifically, the transimpedance amplifier 404 can output an offset signal carrying offset information based on the photocurrent signal, i.e., the first differential signal. The first continuous-time linear equalizer 406 can output an offset signal carrying offset information based on the photocurrent signal, i.e., the third differential signal.

[0090] The optical receiver 400 also includes an offset cancellation module 417. Specifically, the optical receiver 400 includes a first offset cancellation module 418 and a second offset cancellation module 419. The first offset cancellation module 418 includes a second broadband amplifier 420 and a transistor M9. Here, the transistor M9 is an NMOS transistor. In other embodiments, the transistor M9 may also be a PMOS transistor. The input of the second broadband amplifier 420 is coupled to the input of the first offset cancellation module 418, and the output of the second broadband amplifier 420 is coupled to the gate of the transistor M9. The source of the transistor M9 is grounded, and the drain of the transistor M9 is coupled to the output of the first offset cancellation module 418. The input of the first offset cancellation module 418 is coupled to the output of the transimpedance amplifier 404, and the output of the first offset cancellation module 418 is coupled to the input of the transimpedance amplifier 404.

[0091] The first offset cancellation module 418 can output a first offset cancellation signal according to the first differential signal. The first offset cancellation signal is used to eliminate the DC offset in the photocurrent signal so that the subsequent variable gain amplifier 405 can work normally.

[0092] The second offset cancellation module 419 includes a third broadband amplifier 421, a transistor M 10 and transistor M 11 Here, transistor M 10 and transistor M 11 are all NMOS transistors. In other embodiments, transistor M 10 and transistor M 11 The input end of the third broadband amplifier 421 is coupled to the input end of the second offset elimination module 419, and the two output ends of the third broadband amplifier 421 are respectively coupled to the transistors M 10 The gate and transistor M 11 The gate of transistor M is coupled. 10 The source of transistor M is grounded. 11 The source of transistor M is grounded. 10 The drain of transistor M 11 The drains of the first offset cancellation module 419 are respectively coupled to the two output terminals of the second offset cancellation module 419. The input terminal of the second offset cancellation module 419 is coupled to the output terminal of the first continuous time linear equalizer 406, and the output terminal of the second offset cancellation module 419 is coupled to the input terminal of the first continuous time linear equalizer 406.

[0093] The second offset cancellation module 419 may output a second offset cancellation signal according to the third differential signal, where the second offset cancellation signal is used to cancel the offset information in the third differential signal.

[0094] In another embodiment of the present disclosure, the main path 401 includes a transimpedance amplifier 404, a variable gain amplifier 405, and a first continuous-time linear equalizer 406, which are connected in sequence. The input of a second offset cancellation module 419 can be coupled to the output of the first continuous-time linear equalizer 406, and the output of the second offset cancellation module 419 can be coupled to the input of the variable gain amplifier 405. The second offset cancellation module 419 can also eliminate offset information in the third differential signal to prevent differential offset in the third differential signal.

[0095] In an embodiment of the present disclosure, the offset cancellation module includes a sampling and holding capacitor; in a first data transmission phase, the offset cancellation module is used to output an offset cancellation signal based on the offset signal and load the offset cancellation signal to the sampling and holding capacitor; in a second data transmission phase, the offset cancellation module is used to output the offset cancellation signal through the sampling and holding capacitor.

[0096] like Figure 4 As shown, the first offset cancellation module 418 also includes a sampling and holding capacitor C4 and a switch S9. One end of the sampling and holding capacitor C4 is connected to the gate of the transistor M9, and the other end of the sampling and holding capacitor C4 is grounded. The switch S9 is connected between the output end of the second broadband amplifier 420 and the gate of the transistor M9. In the first data transmission phase, the switch S9 is closed to form a conductive feedback loop in the first offset cancellation module 418. The first offset cancellation module 418 can output a first offset cancellation signal based on the offset signal (i.e., the first differential signal) and load the first offset cancellation signal to the sampling and holding capacitor C4. In the second data transmission phase, the switch S9 is opened to disconnect the feedback loop formed in the first offset cancellation module 418. The first offset cancellation module 418 is configured to output the first offset cancellation signal through the holding capacitor C4.

[0097] The second offset elimination module 419 further includes a sampling and holding capacitor C5, a sampling and holding capacitor C6, a switch S 10 and switch S 11 One end of the sampling and holding capacitor C5 is connected to the transistor M 10 The other end of the sampling and holding capacitor C5 is grounded. One end of the sampling and holding capacitor C6 is connected to the gate of the transistor M. 11 The gate of the switch S is connected, and the other end of the sampling and holding capacitor C6 is grounded. 10 Connected to an output terminal of the third broadband amplifier 421 and the transistor M 10 Between the gates, switch S 11 The other output terminal of the third broadband amplifier 421 is connected to the transistor M 11 In the first data transmission phase, the switch S 10 and switch S 11The second offset cancellation module 419 can output a second offset cancellation signal according to the offset signal (i.e., the third differential signal), and load the second offset cancellation signal to the sampling and holding capacitors C5 and C6. 10 and switch S 11 The second offset cancellation module 419 is disconnected to disconnect the feedback loop formed in the second offset cancellation module 419. The second offset cancellation module 419 outputs a second offset cancellation signal through the sampling and holding capacitors C5 and C6.

[0098] In the disclosed embodiment, offset cancellation module 417 can effectively eliminate offset information in the differential signal transmitted in main path 401, thereby preventing differential signal detuning. Furthermore, because offset cancellation module 417 includes a sample-and-hold capacitor, it can quickly eliminate offset information in the differential signal.

[0099] The following describes in detail the application of the optical receiver according to the embodiment of the present disclosure under the 50G PON standard as an example.

[0100] Figure 7 This is a response spectrum diagram of the auxiliary channel output point under the 50G PON standard provided by the embodiment of the present disclosure. Figure 7 As shown in FIG, when the optical receiver receives the preamble under the 50G PON standard, the base frequency of the preamble is 50 GHz.

[0101] like Figure 4 As shown, in the first data transmission phase, the main path 401 receives the photocurrent signal from the outside and transmits the preamble in the photocurrent signal to the auxiliary path 402. At this time, the switch S1 in the mode selection module 403, the switch S9 in the first offset elimination module 418, and the switch S 10 and switch S 11 The first offset elimination module 418 and the second offset elimination module 419 are automatically adjusted and stabilized after a period of time, so that the transistors M9 and M 10 and transistor M 11 An accurate discharge current (i.e., an offset cancellation signal) is generated in the output of the first broadband amplifier 414, thereby eliminating the offset information in the offset signal. At this time, the voltage output by the first broadband amplifier 414 (i.e., the second control signal) is applied to the sampling and holding capacitor C3. The voltage output by the second broadband amplifier 420 is applied to the sampling and holding capacitor C4. The two voltages output by the third broadband amplifier 421 are applied to the sampling and holding capacitors C5 and C6, respectively.

[0102] After the main path 401 receives the photocurrent signal, the transimpedance amplifier 404 can convert the photocurrent signal into a voltage signal. The voltage signal is output from the output end of the transimpedance amplifier 404 and transmitted to the first continuous time linear equalizer 406 through the variable gain amplifier 405. The first continuous time linear equalizer 406 can compensate for part of the bandwidth of the main path 401. Here, due to the insufficient bandwidth of the main path 401, the leading code entering the auxiliary path 402 is severely attenuated. Therefore, the second continuous time linear equalizer 409 in the auxiliary path 402 needs to amplify the leading code to meet the requirements of the subsequent processing. Combined with Figure 4 、 Figure 5 and Figure 7 In the response spectrum of the output point of the auxiliary path 402, it has the same frequency response as the main path 401 at low frequencies, but it has a sufficiently high gain at the 50 GHz frequency to meet the requirement of receiving the 50 GHz pilot code.

[0103] After receiving the preamble, the auxiliary path 402 outputs a differential signal with a differential offset and enters the mode selection module 403. The mode selection module 403 includes two basic peak detectors 412. When the switch S1 is closed, the two basic peak detectors 412 can extract the peak information in the high-frequency signal (i.e., the preamble) output by the auxiliary path 402 to output a peak signal. It should be noted that at this time, the peak signal output by the basic peak detector 412 contains both peak information and offset information. The offset eliminator 413 can eliminate the offset information in the peak signal, while retaining the peak information in the peak signal, and output a differential signal with peak information, i.e., the voltage V out,n and voltage V out,p . The first broadband amplifier 414 outputs a second control signal based on the input differential signal with peak information. The second control signal is loaded on the sampling and holding capacitor C3. The selection module 411 outputs a first control signal based on the input second control signal. Here, it should be noted that at the start of the first data transmission phase, the first broadband amplifier 414 can quickly output a second control signal, and the selection module 411 can output a first control signal based on the second control signal. The first control signal and the second control signal can be used together to adjust the gain of the main path 401.

[0104] It is understandable that at the start of the first data transmission phase, the second control signal output by the first broadband amplifier 414 and the first control signal output by the selection module 411 may not be able to directly adjust the gain of the main path 401 to meet the design requirements. Therefore, the mode selection module 403 needs to perform a series of feedback adjustments on the main path 401 to ensure that the output first control signal and the second control signal meet the design requirements. Specifically, when the value of the second control signal is less than the second threshold voltage Vvgathlow When the value of the second control signal is greater than the first threshold voltage V vgathhigh When the value of the second control signal is less than the first threshold voltage V, the second control signal controls the gain of the variable gain amplifier 405 to be maximum, and the first control signal output by the selection module is high. At this time, the first control signal switches the gain mode of the main path 401 from a higher gain mode to a lower gain mode. When the value of the second control signal is less than the first threshold voltage V vgathhigh and is greater than the second threshold voltage V vgathlow When the value of , the first control signal output by the selection module 411 remains unchanged, and the gain mode of the main path 401 is not changed. That is, when the first control signal and the second control signal output by the mode selection module 403 are finally stable, the value of the second control signal will be less than the first threshold voltage V vgathhigh and is greater than the second threshold voltage V vgathlow At this time, the variable gain amplifier 405 can adjust the gain within the gain range corresponding to the current gain mode according to the second control signal connected thereto.

[0105] Here, in the higher gain mode, the first control signal controls switch S2 in the transimpedance amplifier 404 to open and switch S7 in the transimpedance amplifier 404 to close. The first control signal controls switches S3, S4, S5, and S6 in the first continuous-time linear equalizer 406 to open and switches S8 in the first continuous-time linear equalizer 406 to close. At this time, amplifiers M, N, and R4 are connected to the transimpedance amplifier 404. The transimpedance amplifier 404 provides a higher low-frequency gain for the main path 401. Amplifiers P, Q, inductors L1, L2, L3, and L4 are connected to the first continuous-time linear equalizer 406. The first continuous-time linear equalizer 406 provides a higher high-frequency gain for the main path 401.

[0106] In the lower gain mode, the first control signal controls switch S2 in the transimpedance amplifier 404 to close and switch S7 in the transimpedance amplifier 404 to open. The first control signal controls switches S3, S4, S5, and S6 in the first continuous-time linear equalizer 406 to close and switches S8 in the first continuous-time linear equalizer 406 to open. In this mode, amplifier M, resistors R3, and R4 are connected to the transimpedance amplifier 404. The transimpedance amplifier 404 provides a lower low-frequency gain for the main path 401. Amplifier P is connected to the first continuous-time linear equalizer 406. The first continuous-time linear equalizer 406 provides a lower high-frequency gain for the main path 401.

[0107] In the second data transmission phase, the main path 401 receives the photocurrent signal from the outside, transmits the valid data in the photocurrent signal and outputs it. At this time, the switch S1 in the mode selection module 403, the switch S9 in the first offset elimination module 418, and the switch S1 in the second offset elimination module 419 are all in the same state. 10 and switch S 11 The voltage stored on the sampling and holding capacitor C4, the sampling and holding capacitor C5 and the sampling and holding capacitor C6 can maintain the transistor M9 and the transistor M 10 and transistor M 11 The discharge current remains unchanged. The voltage stored on the sampling and holding capacitor C3 can maintain the magnitude of the second control signal unchanged, further controlling the gain of the variable gain amplifier 405 to remain unchanged. In this way, the gain mode of the main path 401 remains unchanged.

[0108] An embodiment of the present disclosure provides an optical receiver. The optical receiver includes: a main path, the main path includes a first gain adjustment module and a second gain adjustment module; an auxiliary path, the auxiliary path is coupled to the main path; a mode selection module, the input end of the mode selection module is coupled to the auxiliary path, and the output end of the mode selection module is coupled to the main path; wherein the main path is used to receive a photocurrent signal, the main path transmits the preamble in the photocurrent signal to the auxiliary path in the first data transmission phase, and the main path transmits and outputs the valid data in the photocurrent signal in the second data transmission phase; in the first data transmission phase, the mode selection module outputs a first control signal and a second control signal according to the preamble; the first gain adjustment module switches the gain mode according to the first control signal; different gain modes correspond to different gain ranges of the first gain adjustment module; the second gain adjustment module performs gain adjustment within the gain range corresponding to the gain mode of the first gain adjustment module according to the second control signal. In the embodiment of the present disclosure, in the first data transmission phase, the mode selection module outputs the first control signal and the second control signal according to the preamble. Among them, the first gain adjustment module switches the gain mode according to the first control signal, and the second gain adjustment module performs gain adjustment within the gain range corresponding to the gain mode of the first gain adjustment module according to the second control signal, thereby achieving continuous adjustment of the gain within the main path response frequency band within a high dynamic range.

[0109] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0110] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. An optical receiver, characterized in that: include: A main path, the main path comprising a first gain adjustment module and a second gain adjustment module; an auxiliary path coupled to the main path; a mode selection module, wherein an input terminal of the mode selection module is coupled to the auxiliary path, and an output terminal of the mode selection module is coupled to the main path; In which, the main path is used to receive a photocurrent signal, and the main path transmits the preamble code in the photocurrent signal to the auxiliary path in the first data transmission stage, and the main path transmits and outputs the valid data in the photocurrent signal in the second data transmission stage; in the first data transmission stage, the mode selection module outputs a first control signal and a second control signal according to the preamble code; the first gain adjustment module switches the gain mode according to the first control signal; different gain modes correspond to different gain ranges of the first gain adjustment module; the second gain adjustment module performs gain adjustment within the gain range corresponding to the gain mode of the first gain adjustment module according to the second control signal.

2. The optical receiver according to claim 1, wherein The first gain adjustment module includes a transimpedance amplifier and a first continuous-time linear equalizer connected in series; wherein the transimpedance amplifier is located at the input end of the main path.

3. The optical receiver according to claim 2, wherein: The transimpedance amplifier includes a first switch and a plurality of feedback resistors, and the first continuous-time linear equalizer includes a second switch and a plurality of inductors; The first switch is used to switch the number of feedback resistors connected in the transimpedance amplifier to adjust the total resistance of the connected feedback resistors; the second switch is used to switch the number of inductors connected in the first continuous-time linear equalizer to adjust the total inductance of the connected inductors; different total resistances of the feedback resistors and total inductances of the inductors correspond to different gain modes.

4. The optical receiver according to claim 3, wherein: The transimpedance amplifier further includes a third switch and a plurality of first amplifiers, and the first continuous-time linear equalizer further includes a fourth switch and a plurality of second amplifiers; The third switch is used to switch the number of accesses of the first amplifier in the transimpedance amplifier to adjust the bandwidth of the transimpedance amplifier; the fourth switch is used to switch the number of accesses of the second amplifier in the first continuous-time linear equalizer to adjust the bandwidth of the first continuous-time linear equalizer.

5. The optical receiver according to claim 2, wherein: The auxiliary path includes a second continuous time linear equalizer, and the response frequency band of the second continuous time linear equalizer is higher than the response frequency band of the first continuous time linear equalizer.

6. The optical receiver according to claim 1, wherein: The mode selection module includes a peak extraction module and a selection module; the input end of the peak extraction module is coupled to the output end of the auxiliary path, and the output end of the peak extraction module is coupled to the input end of the selection module and the main path respectively; the output end of the selection module is coupled to the main path; The peak extraction module is used to output the second control signal according to the preamble code, and the selection module is used to output the first control signal according to the second control signal.

7. The optical receiver according to claim 1, wherein: The first gain adjustment module outputs an offset signal carrying offset information; The optical receiver further includes: An offset elimination module, wherein the input end of the offset elimination module is coupled to the output end of the first gain adjustment module, and the output end of the offset elimination module is coupled to the input end of the first gain adjustment module; the offset elimination module outputs an offset elimination signal according to the offset signal, and the offset elimination signal is used to eliminate the offset information in the offset signal.

8. The optical receiver according to claim 7, wherein: The offset cancellation module includes a sample-and-hold capacitor; In the first data transmission phase, the offset cancellation module is used to output the offset cancellation signal according to the offset signal, and load the offset cancellation signal to the sampling and holding capacitor; In the second data transmission phase, the offset cancellation module is configured to output the offset cancellation signal through the sampling and holding capacitor.

9. The optical receiver according to claim 1, wherein: The main path further includes a buffer located at an output end of the main path.

10. The optical receiver according to claim 1, wherein: The second gain adjustment module includes a variable gain amplifier.

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